2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
40 #include <linux/bootmem.h>
41 #include <linux/dmar.h>
42 #include <linux/hpet.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
54 #include <asm/msidef.h>
55 #include <asm/hypertransport.h>
56 #include <asm/setup.h>
57 #include <asm/irq_remapping.h>
59 #include <asm/hw_irq.h>
63 #define __apicdebuginit(type) static type __init
65 #define for_each_irq_pin(entry, head) \
66 for (entry = head; entry; entry = entry->next)
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
72 int sis_apic_bug = -1;
74 static DEFINE_RAW_SPINLOCK(ioapic_lock);
75 static DEFINE_RAW_SPINLOCK(vector_lock);
77 static struct ioapic {
79 * # of IRQ routing registers
83 * Saved state during suspend/resume, or while enabling intr-remap.
85 struct IO_APIC_route_entry *saved_registers;
87 struct mpc_ioapic mp_config;
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi gsi_config;
90 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
91 } ioapics[MAX_IO_APICS];
93 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
95 int mpc_ioapic_id(int ioapic_idx)
97 return ioapics[ioapic_idx].mp_config.apicid;
100 unsigned int mpc_ioapic_addr(int ioapic_idx)
102 return ioapics[ioapic_idx].mp_config.apicaddr;
105 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
107 return &ioapics[ioapic_idx].gsi_config;
112 /* The one past the highest gsi number used */
115 /* MP IRQ source entries */
116 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
118 /* # of MP IRQ source entries */
122 int mp_bus_id_to_type[MAX_MP_BUSSES];
125 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
127 int skip_ioapic_setup;
130 * disable_ioapic_support() - disables ioapic support at runtime
132 void disable_ioapic_support(void)
136 noioapicreroute = -1;
138 skip_ioapic_setup = 1;
141 static int __init parse_noapic(char *str)
143 /* disable IO-APIC */
144 disable_ioapic_support();
147 early_param("noapic", parse_noapic);
149 static int io_apic_setup_irq_pin(unsigned int irq, int node,
150 struct io_apic_irq_attr *attr);
152 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
153 void mp_save_irq(struct mpc_intsrc *m)
157 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
158 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
159 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
160 m->srcbusirq, m->dstapic, m->dstirq);
162 for (i = 0; i < mp_irq_entries; i++) {
163 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
167 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
168 if (++mp_irq_entries == MAX_IRQ_SOURCES)
169 panic("Max # of irq sources exceeded!!\n");
172 struct irq_pin_list {
174 struct irq_pin_list *next;
177 static struct irq_pin_list *alloc_irq_pin_list(int node)
179 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
183 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
184 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
186 int __init arch_early_irq_init(void)
191 if (!legacy_pic->nr_legacy_irqs)
194 for (i = 0; i < nr_ioapics; i++) {
195 ioapics[i].saved_registers =
196 kzalloc(sizeof(struct IO_APIC_route_entry) *
197 ioapics[i].nr_registers, GFP_KERNEL);
198 if (!ioapics[i].saved_registers)
199 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
203 count = ARRAY_SIZE(irq_cfgx);
204 node = cpu_to_node(0);
206 for (i = 0; i < count; i++) {
207 irq_set_chip_data(i, &cfg[i]);
208 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
209 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
211 * For legacy IRQ's, start with assigning irq0 to irq15 to
212 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
214 if (i < legacy_pic->nr_legacy_irqs) {
215 cfg[i].vector = IRQ0_VECTOR + i;
216 cpumask_setall(cfg[i].domain);
223 static struct irq_cfg *irq_cfg(unsigned int irq)
225 return irq_get_chip_data(irq);
228 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
232 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
235 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
237 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
241 free_cpumask_var(cfg->domain);
247 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
251 irq_set_chip_data(at, NULL);
252 free_cpumask_var(cfg->domain);
253 free_cpumask_var(cfg->old_domain);
257 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
259 int res = irq_alloc_desc_at(at, node);
265 cfg = irq_get_chip_data(at);
270 cfg = alloc_irq_cfg(at, node);
272 irq_set_chip_data(at, cfg);
280 unsigned int unused[3];
282 unsigned int unused2[11];
286 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
288 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
289 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
292 void io_apic_eoi(unsigned int apic, unsigned int vector)
294 struct io_apic __iomem *io_apic = io_apic_base(apic);
295 writel(vector, &io_apic->eoi);
298 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
300 struct io_apic __iomem *io_apic = io_apic_base(apic);
301 writel(reg, &io_apic->index);
302 return readl(&io_apic->data);
305 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
307 struct io_apic __iomem *io_apic = io_apic_base(apic);
309 writel(reg, &io_apic->index);
310 writel(value, &io_apic->data);
314 * Re-write a value: to be used for read-modify-write
315 * cycles where the read already set up the index register.
317 * Older SiS APIC requires we rewrite the index register
319 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
321 struct io_apic __iomem *io_apic = io_apic_base(apic);
324 writel(reg, &io_apic->index);
325 writel(value, &io_apic->data);
329 struct { u32 w1, w2; };
330 struct IO_APIC_route_entry entry;
333 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
335 union entry_union eu;
337 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
338 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
343 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
345 union entry_union eu;
348 raw_spin_lock_irqsave(&ioapic_lock, flags);
349 eu.entry = __ioapic_read_entry(apic, pin);
350 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
356 * When we write a new IO APIC routing entry, we need to write the high
357 * word first! If the mask bit in the low word is clear, we will enable
358 * the interrupt, and we need to make sure the entry is fully populated
359 * before that happens.
361 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
363 union entry_union eu = {{0, 0}};
366 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
367 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
370 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
374 raw_spin_lock_irqsave(&ioapic_lock, flags);
375 __ioapic_write_entry(apic, pin, e);
376 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
380 * When we mask an IO APIC routing entry, we need to write the low
381 * word first, in order to set the mask bit before we change the
384 static void ioapic_mask_entry(int apic, int pin)
387 union entry_union eu = { .entry.mask = 1 };
389 raw_spin_lock_irqsave(&ioapic_lock, flags);
390 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
391 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
392 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
396 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
397 * shared ISA-space IRQs, so we have to support them. We are super
398 * fast in the common case, and fast for shared ISA-space IRQs.
400 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
402 struct irq_pin_list **last, *entry;
404 /* don't allow duplicates */
405 last = &cfg->irq_2_pin;
406 for_each_irq_pin(entry, cfg->irq_2_pin) {
407 if (entry->apic == apic && entry->pin == pin)
412 entry = alloc_irq_pin_list(node);
414 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
425 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
427 if (__add_pin_to_irq_node(cfg, node, apic, pin))
428 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
432 * Reroute an IRQ to a different pin.
434 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
435 int oldapic, int oldpin,
436 int newapic, int newpin)
438 struct irq_pin_list *entry;
440 for_each_irq_pin(entry, cfg->irq_2_pin) {
441 if (entry->apic == oldapic && entry->pin == oldpin) {
442 entry->apic = newapic;
444 /* every one is different, right? */
449 /* old apic/pin didn't exist, so just add new ones */
450 add_pin_to_irq_node(cfg, node, newapic, newpin);
453 static void __io_apic_modify_irq(struct irq_pin_list *entry,
454 int mask_and, int mask_or,
455 void (*final)(struct irq_pin_list *entry))
457 unsigned int reg, pin;
460 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
463 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
468 static void io_apic_modify_irq(struct irq_cfg *cfg,
469 int mask_and, int mask_or,
470 void (*final)(struct irq_pin_list *entry))
472 struct irq_pin_list *entry;
474 for_each_irq_pin(entry, cfg->irq_2_pin)
475 __io_apic_modify_irq(entry, mask_and, mask_or, final);
478 static void io_apic_sync(struct irq_pin_list *entry)
481 * Synchronize the IO-APIC and the CPU by doing
482 * a dummy read from the IO-APIC
484 struct io_apic __iomem *io_apic;
486 io_apic = io_apic_base(entry->apic);
487 readl(&io_apic->data);
490 static void mask_ioapic(struct irq_cfg *cfg)
494 raw_spin_lock_irqsave(&ioapic_lock, flags);
495 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
496 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
499 static void mask_ioapic_irq(struct irq_data *data)
501 mask_ioapic(data->chip_data);
504 static void __unmask_ioapic(struct irq_cfg *cfg)
506 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
509 static void unmask_ioapic(struct irq_cfg *cfg)
513 raw_spin_lock_irqsave(&ioapic_lock, flags);
514 __unmask_ioapic(cfg);
515 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
518 static void unmask_ioapic_irq(struct irq_data *data)
520 unmask_ioapic(data->chip_data);
524 * IO-APIC versions below 0x20 don't support EOI register.
525 * For the record, here is the information about various versions:
527 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
528 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
531 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
532 * version as 0x2. This is an error with documentation and these ICH chips
533 * use io-apic's of version 0x20.
535 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
536 * Otherwise, we simulate the EOI message manually by changing the trigger
537 * mode to edge and then back to level, with RTE being masked during this.
539 void native_eoi_ioapic_pin(int apic, int pin, int vector)
541 if (mpc_ioapic_ver(apic) >= 0x20) {
542 io_apic_eoi(apic, vector);
544 struct IO_APIC_route_entry entry, entry1;
546 entry = entry1 = __ioapic_read_entry(apic, pin);
549 * Mask the entry and change the trigger mode to edge.
552 entry1.trigger = IOAPIC_EDGE;
554 __ioapic_write_entry(apic, pin, entry1);
557 * Restore the previous level triggered entry.
559 __ioapic_write_entry(apic, pin, entry);
563 void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
565 struct irq_pin_list *entry;
568 raw_spin_lock_irqsave(&ioapic_lock, flags);
569 for_each_irq_pin(entry, cfg->irq_2_pin)
570 x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
572 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
575 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
577 struct IO_APIC_route_entry entry;
579 /* Check delivery_mode to be sure we're not clearing an SMI pin */
580 entry = ioapic_read_entry(apic, pin);
581 if (entry.delivery_mode == dest_SMI)
585 * Make sure the entry is masked and re-read the contents to check
586 * if it is a level triggered pin and if the remote-IRR is set.
590 ioapic_write_entry(apic, pin, entry);
591 entry = ioapic_read_entry(apic, pin);
598 * Make sure the trigger mode is set to level. Explicit EOI
599 * doesn't clear the remote-IRR if the trigger mode is not
602 if (!entry.trigger) {
603 entry.trigger = IOAPIC_LEVEL;
604 ioapic_write_entry(apic, pin, entry);
607 raw_spin_lock_irqsave(&ioapic_lock, flags);
608 x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector);
609 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
613 * Clear the rest of the bits in the IO-APIC RTE except for the mask
616 ioapic_mask_entry(apic, pin);
617 entry = ioapic_read_entry(apic, pin);
619 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
620 mpc_ioapic_id(apic), pin);
623 static void clear_IO_APIC (void)
627 for (apic = 0; apic < nr_ioapics; apic++)
628 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
629 clear_IO_APIC_pin(apic, pin);
634 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
635 * specific CPU-side IRQs.
639 static int pirq_entries[MAX_PIRQS] = {
640 [0 ... MAX_PIRQS - 1] = -1
643 static int __init ioapic_pirq_setup(char *str)
646 int ints[MAX_PIRQS+1];
648 get_options(str, ARRAY_SIZE(ints), ints);
650 apic_printk(APIC_VERBOSE, KERN_INFO
651 "PIRQ redirection, working around broken MP-BIOS.\n");
653 if (ints[0] < MAX_PIRQS)
656 for (i = 0; i < max; i++) {
657 apic_printk(APIC_VERBOSE, KERN_DEBUG
658 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
660 * PIRQs are mapped upside down, usually.
662 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
667 __setup("pirq=", ioapic_pirq_setup);
668 #endif /* CONFIG_X86_32 */
671 * Saves all the IO-APIC RTE's
673 int save_ioapic_entries(void)
678 for (apic = 0; apic < nr_ioapics; apic++) {
679 if (!ioapics[apic].saved_registers) {
684 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
685 ioapics[apic].saved_registers[pin] =
686 ioapic_read_entry(apic, pin);
693 * Mask all IO APIC entries.
695 void mask_ioapic_entries(void)
699 for (apic = 0; apic < nr_ioapics; apic++) {
700 if (!ioapics[apic].saved_registers)
703 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
704 struct IO_APIC_route_entry entry;
706 entry = ioapics[apic].saved_registers[pin];
709 ioapic_write_entry(apic, pin, entry);
716 * Restore IO APIC entries which was saved in the ioapic structure.
718 int restore_ioapic_entries(void)
722 for (apic = 0; apic < nr_ioapics; apic++) {
723 if (!ioapics[apic].saved_registers)
726 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
727 ioapic_write_entry(apic, pin,
728 ioapics[apic].saved_registers[pin]);
734 * Find the IRQ entry number of a certain pin.
736 static int find_irq_entry(int ioapic_idx, int pin, int type)
740 for (i = 0; i < mp_irq_entries; i++)
741 if (mp_irqs[i].irqtype == type &&
742 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
743 mp_irqs[i].dstapic == MP_APIC_ALL) &&
744 mp_irqs[i].dstirq == pin)
751 * Find the pin to which IRQ[irq] (ISA) is connected
753 static int __init find_isa_irq_pin(int irq, int type)
757 for (i = 0; i < mp_irq_entries; i++) {
758 int lbus = mp_irqs[i].srcbus;
760 if (test_bit(lbus, mp_bus_not_pci) &&
761 (mp_irqs[i].irqtype == type) &&
762 (mp_irqs[i].srcbusirq == irq))
764 return mp_irqs[i].dstirq;
769 static int __init find_isa_irq_apic(int irq, int type)
773 for (i = 0; i < mp_irq_entries; i++) {
774 int lbus = mp_irqs[i].srcbus;
776 if (test_bit(lbus, mp_bus_not_pci) &&
777 (mp_irqs[i].irqtype == type) &&
778 (mp_irqs[i].srcbusirq == irq))
782 if (i < mp_irq_entries) {
785 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
786 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
795 * EISA Edge/Level control register, ELCR
797 static int EISA_ELCR(unsigned int irq)
799 if (irq < legacy_pic->nr_legacy_irqs) {
800 unsigned int port = 0x4d0 + (irq >> 3);
801 return (inb(port) >> (irq & 7)) & 1;
803 apic_printk(APIC_VERBOSE, KERN_INFO
804 "Broken MPtable reports ISA irq %d\n", irq);
810 /* ISA interrupts are always polarity zero edge triggered,
811 * when listed as conforming in the MP table. */
813 #define default_ISA_trigger(idx) (0)
814 #define default_ISA_polarity(idx) (0)
816 /* EISA interrupts are always polarity zero and can be edge or level
817 * trigger depending on the ELCR value. If an interrupt is listed as
818 * EISA conforming in the MP table, that means its trigger type must
819 * be read in from the ELCR */
821 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
822 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
824 /* PCI interrupts are always polarity one level triggered,
825 * when listed as conforming in the MP table. */
827 #define default_PCI_trigger(idx) (1)
828 #define default_PCI_polarity(idx) (1)
830 static int irq_polarity(int idx)
832 int bus = mp_irqs[idx].srcbus;
836 * Determine IRQ line polarity (high active or low active):
838 switch (mp_irqs[idx].irqflag & 3)
840 case 0: /* conforms, ie. bus-type dependent polarity */
841 if (test_bit(bus, mp_bus_not_pci))
842 polarity = default_ISA_polarity(idx);
844 polarity = default_PCI_polarity(idx);
846 case 1: /* high active */
851 case 2: /* reserved */
853 pr_warn("broken BIOS!!\n");
857 case 3: /* low active */
862 default: /* invalid */
864 pr_warn("broken BIOS!!\n");
872 static int irq_trigger(int idx)
874 int bus = mp_irqs[idx].srcbus;
878 * Determine IRQ trigger mode (edge or level sensitive):
880 switch ((mp_irqs[idx].irqflag>>2) & 3)
882 case 0: /* conforms, ie. bus-type dependent */
883 if (test_bit(bus, mp_bus_not_pci))
884 trigger = default_ISA_trigger(idx);
886 trigger = default_PCI_trigger(idx);
888 switch (mp_bus_id_to_type[bus]) {
889 case MP_BUS_ISA: /* ISA pin */
891 /* set before the switch */
894 case MP_BUS_EISA: /* EISA pin */
896 trigger = default_EISA_trigger(idx);
899 case MP_BUS_PCI: /* PCI pin */
901 /* set before the switch */
906 pr_warn("broken BIOS!!\n");
918 case 2: /* reserved */
920 pr_warn("broken BIOS!!\n");
929 default: /* invalid */
931 pr_warn("broken BIOS!!\n");
939 static int pin_2_irq(int idx, int apic, int pin)
942 int bus = mp_irqs[idx].srcbus;
943 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
946 * Debugging check, we are in big trouble if this message pops up!
948 if (mp_irqs[idx].dstirq != pin)
949 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
951 if (test_bit(bus, mp_bus_not_pci)) {
952 irq = mp_irqs[idx].srcbusirq;
954 u32 gsi = gsi_cfg->gsi_base + pin;
956 if (gsi >= NR_IRQS_LEGACY)
964 * PCI IRQ command line redirection. Yes, limits are hardcoded.
966 if ((pin >= 16) && (pin <= 23)) {
967 if (pirq_entries[pin-16] != -1) {
968 if (!pirq_entries[pin-16]) {
969 apic_printk(APIC_VERBOSE, KERN_DEBUG
970 "disabling PIRQ%d\n", pin-16);
972 irq = pirq_entries[pin-16];
973 apic_printk(APIC_VERBOSE, KERN_DEBUG
974 "using PIRQ%d -> IRQ %d\n",
985 * Find a specific PCI IRQ entry.
986 * Not an __init, possibly needed by modules
988 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
989 struct io_apic_irq_attr *irq_attr)
991 int ioapic_idx, i, best_guess = -1;
993 apic_printk(APIC_DEBUG,
994 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
996 if (test_bit(bus, mp_bus_not_pci)) {
997 apic_printk(APIC_VERBOSE,
998 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1001 for (i = 0; i < mp_irq_entries; i++) {
1002 int lbus = mp_irqs[i].srcbus;
1004 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1005 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1006 mp_irqs[i].dstapic == MP_APIC_ALL)
1009 if (!test_bit(lbus, mp_bus_not_pci) &&
1010 mp_irqs[i].irqtype == mp_INT &&
1012 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1013 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1015 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1018 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1019 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1026 * Use the first all-but-pin matching entry as a
1027 * best-guess fuzzy result for broken mptables.
1029 if (best_guess < 0) {
1030 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1040 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1042 void lock_vector_lock(void)
1044 /* Used to the online set of cpus does not change
1045 * during assign_irq_vector.
1047 raw_spin_lock(&vector_lock);
1050 void unlock_vector_lock(void)
1052 raw_spin_unlock(&vector_lock);
1056 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1059 * NOTE! The local APIC isn't very good at handling
1060 * multiple interrupts at the same interrupt level.
1061 * As the interrupt level is determined by taking the
1062 * vector number and shifting that right by 4, we
1063 * want to spread these out a bit so that they don't
1064 * all fall in the same interrupt level.
1066 * Also, we've got to be careful not to trash gate
1067 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1069 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1070 static int current_offset = VECTOR_OFFSET_START % 16;
1072 cpumask_var_t tmp_mask;
1074 if (cfg->move_in_progress)
1077 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1080 /* Only try and allocate irqs on cpus that are present */
1082 cpumask_clear(cfg->old_domain);
1083 cpu = cpumask_first_and(mask, cpu_online_mask);
1084 while (cpu < nr_cpu_ids) {
1085 int new_cpu, vector, offset;
1087 apic->vector_allocation_domain(cpu, tmp_mask, mask);
1089 if (cpumask_subset(tmp_mask, cfg->domain)) {
1091 if (cpumask_equal(tmp_mask, cfg->domain))
1094 * New cpumask using the vector is a proper subset of
1095 * the current in use mask. So cleanup the vector
1096 * allocation for the members that are not used anymore.
1098 cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
1099 cfg->move_in_progress =
1100 cpumask_intersects(cfg->old_domain, cpu_online_mask);
1101 cpumask_and(cfg->domain, cfg->domain, tmp_mask);
1105 vector = current_vector;
1106 offset = current_offset;
1109 if (vector >= first_system_vector) {
1110 offset = (offset + 1) % 16;
1111 vector = FIRST_EXTERNAL_VECTOR + offset;
1114 if (unlikely(current_vector == vector)) {
1115 cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
1116 cpumask_andnot(tmp_mask, mask, cfg->old_domain);
1117 cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
1121 if (test_bit(vector, used_vectors))
1124 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) {
1125 if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED)
1129 current_vector = vector;
1130 current_offset = offset;
1132 cpumask_copy(cfg->old_domain, cfg->domain);
1133 cfg->move_in_progress =
1134 cpumask_intersects(cfg->old_domain, cpu_online_mask);
1136 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1137 per_cpu(vector_irq, new_cpu)[vector] = irq;
1138 cfg->vector = vector;
1139 cpumask_copy(cfg->domain, tmp_mask);
1143 free_cpumask_var(tmp_mask);
1147 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1150 unsigned long flags;
1152 raw_spin_lock_irqsave(&vector_lock, flags);
1153 err = __assign_irq_vector(irq, cfg, mask);
1154 raw_spin_unlock_irqrestore(&vector_lock, flags);
1158 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1162 BUG_ON(!cfg->vector);
1164 vector = cfg->vector;
1165 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1166 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1169 cpumask_clear(cfg->domain);
1171 if (likely(!cfg->move_in_progress))
1173 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1174 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1175 if (per_cpu(vector_irq, cpu)[vector] != irq)
1177 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1181 cfg->move_in_progress = 0;
1184 void __setup_vector_irq(int cpu)
1186 /* Initialize vector_irq on a new cpu */
1188 struct irq_cfg *cfg;
1191 * vector_lock will make sure that we don't run into irq vector
1192 * assignments that might be happening on another cpu in parallel,
1193 * while we setup our initial vector to irq mappings.
1195 raw_spin_lock(&vector_lock);
1196 /* Mark the inuse vectors */
1197 for_each_active_irq(irq) {
1198 cfg = irq_get_chip_data(irq);
1202 if (!cpumask_test_cpu(cpu, cfg->domain))
1204 vector = cfg->vector;
1205 per_cpu(vector_irq, cpu)[vector] = irq;
1207 /* Mark the free vectors */
1208 for (vector = 0; vector < NR_VECTORS; ++vector) {
1209 irq = per_cpu(vector_irq, cpu)[vector];
1210 if (irq <= VECTOR_UNDEFINED)
1214 if (!cpumask_test_cpu(cpu, cfg->domain))
1215 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1217 raw_spin_unlock(&vector_lock);
1220 static struct irq_chip ioapic_chip;
1222 #ifdef CONFIG_X86_32
1223 static inline int IO_APIC_irq_trigger(int irq)
1227 for (apic = 0; apic < nr_ioapics; apic++) {
1228 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1229 idx = find_irq_entry(apic, pin, mp_INT);
1230 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1231 return irq_trigger(idx);
1235 * nonexistent IRQs are edge default
1240 static inline int IO_APIC_irq_trigger(int irq)
1246 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1247 unsigned long trigger)
1249 struct irq_chip *chip = &ioapic_chip;
1250 irq_flow_handler_t hdl;
1253 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1254 trigger == IOAPIC_LEVEL) {
1255 irq_set_status_flags(irq, IRQ_LEVEL);
1258 irq_clear_status_flags(irq, IRQ_LEVEL);
1262 if (setup_remapped_irq(irq, cfg, chip))
1263 fasteoi = trigger != 0;
1265 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1266 irq_set_chip_and_handler_name(irq, chip, hdl,
1267 fasteoi ? "fasteoi" : "edge");
1270 int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1271 unsigned int destination, int vector,
1272 struct io_apic_irq_attr *attr)
1274 memset(entry, 0, sizeof(*entry));
1276 entry->delivery_mode = apic->irq_delivery_mode;
1277 entry->dest_mode = apic->irq_dest_mode;
1278 entry->dest = destination;
1279 entry->vector = vector;
1280 entry->mask = 0; /* enable IRQ */
1281 entry->trigger = attr->trigger;
1282 entry->polarity = attr->polarity;
1285 * Mask level triggered irqs.
1286 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1294 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1295 struct io_apic_irq_attr *attr)
1297 struct IO_APIC_route_entry entry;
1300 if (!IO_APIC_IRQ(irq))
1303 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1306 if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
1308 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1309 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1310 __clear_irq_vector(irq, cfg);
1315 apic_printk(APIC_VERBOSE,KERN_DEBUG
1316 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1317 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1318 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1319 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1321 if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
1322 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1323 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1324 __clear_irq_vector(irq, cfg);
1329 ioapic_register_intr(irq, cfg, attr->trigger);
1330 if (irq < legacy_pic->nr_legacy_irqs)
1331 legacy_pic->mask(irq);
1333 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1336 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1341 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1342 mpc_ioapic_id(ioapic_idx), pin);
1346 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1348 int idx, node = cpu_to_node(0);
1349 struct io_apic_irq_attr attr;
1350 unsigned int pin, irq;
1352 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1353 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1354 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1357 irq = pin_2_irq(idx, ioapic_idx, pin);
1359 if ((ioapic_idx > 0) && (irq > NR_IRQS_LEGACY))
1363 * Skip the timer IRQ if there's a quirk handler
1364 * installed and if it returns 1:
1366 if (apic->multi_timer_check &&
1367 apic->multi_timer_check(ioapic_idx, irq))
1370 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1373 io_apic_setup_irq_pin(irq, node, &attr);
1377 static void __init setup_IO_APIC_irqs(void)
1379 unsigned int ioapic_idx;
1381 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1383 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1384 __io_apic_setup_irqs(ioapic_idx);
1388 * for the gsi that is not in first ioapic
1389 * but could not use acpi_register_gsi()
1390 * like some special sci in IBM x3330
1392 void setup_IO_APIC_irq_extra(u32 gsi)
1394 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1395 struct io_apic_irq_attr attr;
1398 * Convert 'gsi' to 'ioapic.pin'.
1400 ioapic_idx = mp_find_ioapic(gsi);
1404 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1405 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1409 irq = pin_2_irq(idx, ioapic_idx, pin);
1411 /* Only handle the non legacy irqs on secondary ioapics */
1412 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1415 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1418 io_apic_setup_irq_pin_once(irq, node, &attr);
1422 * Set up the timer pin, possibly with the 8259A-master behind.
1424 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1425 unsigned int pin, int vector)
1427 struct IO_APIC_route_entry entry;
1430 memset(&entry, 0, sizeof(entry));
1433 * We use logical delivery to get the timer IRQ
1436 if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
1437 apic->target_cpus(), &dest)))
1440 entry.dest_mode = apic->irq_dest_mode;
1441 entry.mask = 0; /* don't mask IRQ for edge */
1443 entry.delivery_mode = apic->irq_delivery_mode;
1446 entry.vector = vector;
1449 * The timer IRQ doesn't have to know that behind the
1450 * scene we may have a 8259A-master in AEOI mode ...
1452 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1456 * Add it to the IO-APIC irq-routing table:
1458 ioapic_write_entry(ioapic_idx, pin, entry);
1461 void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1465 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1467 for (i = 0; i <= nr_entries; i++) {
1468 struct IO_APIC_route_entry entry;
1470 entry = ioapic_read_entry(apic, i);
1472 pr_debug(" %02x %02X ", i, entry.dest);
1473 pr_cont("%1d %1d %1d %1d %1d "
1479 entry.delivery_status,
1481 entry.delivery_mode,
1486 void intel_ir_io_apic_print_entries(unsigned int apic,
1487 unsigned int nr_entries)
1491 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1493 for (i = 0; i <= nr_entries; i++) {
1494 struct IR_IO_APIC_route_entry *ir_entry;
1495 struct IO_APIC_route_entry entry;
1497 entry = ioapic_read_entry(apic, i);
1499 ir_entry = (struct IR_IO_APIC_route_entry *)&entry;
1501 pr_debug(" %02x %04X ", i, ir_entry->index);
1502 pr_cont("%1d %1d %1d %1d %1d "
1503 "%1d %1d %X %02X\n",
1509 ir_entry->delivery_status,
1516 void ioapic_zap_locks(void)
1518 raw_spin_lock_init(&ioapic_lock);
1521 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1523 union IO_APIC_reg_00 reg_00;
1524 union IO_APIC_reg_01 reg_01;
1525 union IO_APIC_reg_02 reg_02;
1526 union IO_APIC_reg_03 reg_03;
1527 unsigned long flags;
1529 raw_spin_lock_irqsave(&ioapic_lock, flags);
1530 reg_00.raw = io_apic_read(ioapic_idx, 0);
1531 reg_01.raw = io_apic_read(ioapic_idx, 1);
1532 if (reg_01.bits.version >= 0x10)
1533 reg_02.raw = io_apic_read(ioapic_idx, 2);
1534 if (reg_01.bits.version >= 0x20)
1535 reg_03.raw = io_apic_read(ioapic_idx, 3);
1536 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1538 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1539 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1540 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1541 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1542 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1544 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1545 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1546 reg_01.bits.entries);
1548 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1549 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1550 reg_01.bits.version);
1553 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1554 * but the value of reg_02 is read as the previous read register
1555 * value, so ignore it if reg_02 == reg_01.
1557 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1558 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1559 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1563 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1564 * or reg_03, but the value of reg_0[23] is read as the previous read
1565 * register value, so ignore it if reg_03 == reg_0[12].
1567 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1568 reg_03.raw != reg_01.raw) {
1569 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1570 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1573 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1575 x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries);
1578 __apicdebuginit(void) print_IO_APICs(void)
1581 struct irq_cfg *cfg;
1583 struct irq_chip *chip;
1585 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1586 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1587 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1588 mpc_ioapic_id(ioapic_idx),
1589 ioapics[ioapic_idx].nr_registers);
1592 * We are a bit conservative about what we expect. We have to
1593 * know about every hardware change ASAP.
1595 printk(KERN_INFO "testing the IO APIC.......................\n");
1597 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1598 print_IO_APIC(ioapic_idx);
1600 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1601 for_each_active_irq(irq) {
1602 struct irq_pin_list *entry;
1604 chip = irq_get_chip(irq);
1605 if (chip != &ioapic_chip)
1608 cfg = irq_get_chip_data(irq);
1611 entry = cfg->irq_2_pin;
1614 printk(KERN_DEBUG "IRQ%d ", irq);
1615 for_each_irq_pin(entry, cfg->irq_2_pin)
1616 pr_cont("-> %d:%d", entry->apic, entry->pin);
1620 printk(KERN_INFO ".................................... done.\n");
1623 __apicdebuginit(void) print_APIC_field(int base)
1629 for (i = 0; i < 8; i++)
1630 pr_cont("%08x", apic_read(base + i*0x10));
1635 __apicdebuginit(void) print_local_APIC(void *dummy)
1637 unsigned int i, v, ver, maxlvt;
1640 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1641 smp_processor_id(), hard_smp_processor_id());
1642 v = apic_read(APIC_ID);
1643 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1644 v = apic_read(APIC_LVR);
1645 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1646 ver = GET_APIC_VERSION(v);
1647 maxlvt = lapic_get_maxlvt();
1649 v = apic_read(APIC_TASKPRI);
1650 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1652 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1653 if (!APIC_XAPIC(ver)) {
1654 v = apic_read(APIC_ARBPRI);
1655 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1656 v & APIC_ARBPRI_MASK);
1658 v = apic_read(APIC_PROCPRI);
1659 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1663 * Remote read supported only in the 82489DX and local APIC for
1664 * Pentium processors.
1666 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1667 v = apic_read(APIC_RRR);
1668 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1671 v = apic_read(APIC_LDR);
1672 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1673 if (!x2apic_enabled()) {
1674 v = apic_read(APIC_DFR);
1675 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1677 v = apic_read(APIC_SPIV);
1678 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1680 printk(KERN_DEBUG "... APIC ISR field:\n");
1681 print_APIC_field(APIC_ISR);
1682 printk(KERN_DEBUG "... APIC TMR field:\n");
1683 print_APIC_field(APIC_TMR);
1684 printk(KERN_DEBUG "... APIC IRR field:\n");
1685 print_APIC_field(APIC_IRR);
1687 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1688 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1689 apic_write(APIC_ESR, 0);
1691 v = apic_read(APIC_ESR);
1692 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1695 icr = apic_icr_read();
1696 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1697 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1699 v = apic_read(APIC_LVTT);
1700 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1702 if (maxlvt > 3) { /* PC is LVT#4. */
1703 v = apic_read(APIC_LVTPC);
1704 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1706 v = apic_read(APIC_LVT0);
1707 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1708 v = apic_read(APIC_LVT1);
1709 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1711 if (maxlvt > 2) { /* ERR is LVT#3. */
1712 v = apic_read(APIC_LVTERR);
1713 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1716 v = apic_read(APIC_TMICT);
1717 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1718 v = apic_read(APIC_TMCCT);
1719 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1720 v = apic_read(APIC_TDCR);
1721 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1723 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1724 v = apic_read(APIC_EFEAT);
1725 maxlvt = (v >> 16) & 0xff;
1726 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1727 v = apic_read(APIC_ECTRL);
1728 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1729 for (i = 0; i < maxlvt; i++) {
1730 v = apic_read(APIC_EILVTn(i));
1731 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1737 __apicdebuginit(void) print_local_APICs(int maxcpu)
1745 for_each_online_cpu(cpu) {
1748 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1753 __apicdebuginit(void) print_PIC(void)
1756 unsigned long flags;
1758 if (!legacy_pic->nr_legacy_irqs)
1761 printk(KERN_DEBUG "\nprinting PIC contents\n");
1763 raw_spin_lock_irqsave(&i8259A_lock, flags);
1765 v = inb(0xa1) << 8 | inb(0x21);
1766 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1768 v = inb(0xa0) << 8 | inb(0x20);
1769 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1773 v = inb(0xa0) << 8 | inb(0x20);
1777 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1779 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1781 v = inb(0x4d1) << 8 | inb(0x4d0);
1782 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1785 static int __initdata show_lapic = 1;
1786 static __init int setup_show_lapic(char *arg)
1790 if (strcmp(arg, "all") == 0) {
1791 show_lapic = CONFIG_NR_CPUS;
1793 get_option(&arg, &num);
1800 __setup("show_lapic=", setup_show_lapic);
1802 __apicdebuginit(int) print_ICs(void)
1804 if (apic_verbosity == APIC_QUIET)
1809 /* don't print out if apic is not there */
1810 if (!cpu_has_apic && !apic_from_smp_config())
1813 print_local_APICs(show_lapic);
1819 late_initcall(print_ICs);
1822 /* Where if anywhere is the i8259 connect in external int mode */
1823 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1825 void __init enable_IO_APIC(void)
1827 int i8259_apic, i8259_pin;
1830 if (!legacy_pic->nr_legacy_irqs)
1833 for(apic = 0; apic < nr_ioapics; apic++) {
1835 /* See if any of the pins is in ExtINT mode */
1836 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1837 struct IO_APIC_route_entry entry;
1838 entry = ioapic_read_entry(apic, pin);
1840 /* If the interrupt line is enabled and in ExtInt mode
1841 * I have found the pin where the i8259 is connected.
1843 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1844 ioapic_i8259.apic = apic;
1845 ioapic_i8259.pin = pin;
1851 /* Look to see what if the MP table has reported the ExtINT */
1852 /* If we could not find the appropriate pin by looking at the ioapic
1853 * the i8259 probably is not connected the ioapic but give the
1854 * mptable a chance anyway.
1856 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1857 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1858 /* Trust the MP table if nothing is setup in the hardware */
1859 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1860 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1861 ioapic_i8259.pin = i8259_pin;
1862 ioapic_i8259.apic = i8259_apic;
1864 /* Complain if the MP table and the hardware disagree */
1865 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1866 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1868 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1872 * Do not trust the IO-APIC being empty at bootup
1877 void native_disable_io_apic(void)
1880 * If the i8259 is routed through an IOAPIC
1881 * Put that IOAPIC in virtual wire mode
1882 * so legacy interrupts can be delivered.
1884 if (ioapic_i8259.pin != -1) {
1885 struct IO_APIC_route_entry entry;
1887 memset(&entry, 0, sizeof(entry));
1888 entry.mask = 0; /* Enabled */
1889 entry.trigger = 0; /* Edge */
1891 entry.polarity = 0; /* High */
1892 entry.delivery_status = 0;
1893 entry.dest_mode = 0; /* Physical */
1894 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1896 entry.dest = read_apic_id();
1899 * Add it to the IO-APIC irq-routing table:
1901 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1904 if (cpu_has_apic || apic_from_smp_config())
1905 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1910 * Not an __init, needed by the reboot code
1912 void disable_IO_APIC(void)
1915 * Clear the IO-APIC before rebooting:
1919 if (!legacy_pic->nr_legacy_irqs)
1922 x86_io_apic_ops.disable();
1925 #ifdef CONFIG_X86_32
1927 * function to set the IO-APIC physical IDs based on the
1928 * values stored in the MPC table.
1930 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1932 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1934 union IO_APIC_reg_00 reg_00;
1935 physid_mask_t phys_id_present_map;
1938 unsigned char old_id;
1939 unsigned long flags;
1942 * This is broken; anything with a real cpu count has to
1943 * circumvent this idiocy regardless.
1945 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1948 * Set the IOAPIC ID to the value stored in the MPC table.
1950 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1951 /* Read the register 0 value */
1952 raw_spin_lock_irqsave(&ioapic_lock, flags);
1953 reg_00.raw = io_apic_read(ioapic_idx, 0);
1954 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1956 old_id = mpc_ioapic_id(ioapic_idx);
1958 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1959 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1960 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1961 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1963 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1967 * Sanity check, is the ID really free? Every APIC in a
1968 * system must have a unique ID or we get lots of nice
1969 * 'stuck on smp_invalidate_needed IPI wait' messages.
1971 if (apic->check_apicid_used(&phys_id_present_map,
1972 mpc_ioapic_id(ioapic_idx))) {
1973 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1974 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1975 for (i = 0; i < get_physical_broadcast(); i++)
1976 if (!physid_isset(i, phys_id_present_map))
1978 if (i >= get_physical_broadcast())
1979 panic("Max APIC ID exceeded!\n");
1980 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1982 physid_set(i, phys_id_present_map);
1983 ioapics[ioapic_idx].mp_config.apicid = i;
1986 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1988 apic_printk(APIC_VERBOSE, "Setting %d in the "
1989 "phys_id_present_map\n",
1990 mpc_ioapic_id(ioapic_idx));
1991 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1995 * We need to adjust the IRQ routing table
1996 * if the ID changed.
1998 if (old_id != mpc_ioapic_id(ioapic_idx))
1999 for (i = 0; i < mp_irq_entries; i++)
2000 if (mp_irqs[i].dstapic == old_id)
2002 = mpc_ioapic_id(ioapic_idx);
2005 * Update the ID register according to the right value
2006 * from the MPC table if they are different.
2008 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2011 apic_printk(APIC_VERBOSE, KERN_INFO
2012 "...changing IO-APIC physical APIC ID to %d ...",
2013 mpc_ioapic_id(ioapic_idx));
2015 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2016 raw_spin_lock_irqsave(&ioapic_lock, flags);
2017 io_apic_write(ioapic_idx, 0, reg_00.raw);
2018 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2023 raw_spin_lock_irqsave(&ioapic_lock, flags);
2024 reg_00.raw = io_apic_read(ioapic_idx, 0);
2025 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2026 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2027 pr_cont("could not set ID!\n");
2029 apic_printk(APIC_VERBOSE, " ok.\n");
2033 void __init setup_ioapic_ids_from_mpc(void)
2039 * Don't check I/O APIC IDs for xAPIC systems. They have
2040 * no meaning without the serial APIC bus.
2042 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2043 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2045 setup_ioapic_ids_from_mpc_nocheck();
2049 int no_timer_check __initdata;
2051 static int __init notimercheck(char *s)
2056 __setup("no_timer_check", notimercheck);
2059 * There is a nasty bug in some older SMP boards, their mptable lies
2060 * about the timer IRQ. We do the following to work around the situation:
2062 * - timer IRQ defaults to IO-APIC IRQ
2063 * - if this function detects that timer IRQs are defunct, then we fall
2064 * back to ISA timer IRQs
2066 static int __init timer_irq_works(void)
2068 unsigned long t1 = jiffies;
2069 unsigned long flags;
2074 local_save_flags(flags);
2076 /* Let ten ticks pass... */
2077 mdelay((10 * 1000) / HZ);
2078 local_irq_restore(flags);
2081 * Expect a few ticks at least, to be sure some possible
2082 * glue logic does not lock up after one or two first
2083 * ticks in a non-ExtINT mode. Also the local APIC
2084 * might have cached one ExtINT interrupt. Finally, at
2085 * least one tick may be lost due to delays.
2089 if (time_after(jiffies, t1 + 4))
2095 * In the SMP+IOAPIC case it might happen that there are an unspecified
2096 * number of pending IRQ events unhandled. These cases are very rare,
2097 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2098 * better to do it this way as thus we do not have to be aware of
2099 * 'pending' interrupts in the IRQ path, except at this point.
2102 * Edge triggered needs to resend any interrupt
2103 * that was delayed but this is now handled in the device
2108 * Starting up a edge-triggered IO-APIC interrupt is
2109 * nasty - we need to make sure that we get the edge.
2110 * If it is already asserted for some reason, we need
2111 * return 1 to indicate that is was pending.
2113 * This is not complete - we should be able to fake
2114 * an edge even if it isn't on the 8259A...
2117 static unsigned int startup_ioapic_irq(struct irq_data *data)
2119 int was_pending = 0, irq = data->irq;
2120 unsigned long flags;
2122 raw_spin_lock_irqsave(&ioapic_lock, flags);
2123 if (irq < legacy_pic->nr_legacy_irqs) {
2124 legacy_pic->mask(irq);
2125 if (legacy_pic->irq_pending(irq))
2128 __unmask_ioapic(data->chip_data);
2129 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2134 static int ioapic_retrigger_irq(struct irq_data *data)
2136 struct irq_cfg *cfg = data->chip_data;
2137 unsigned long flags;
2140 raw_spin_lock_irqsave(&vector_lock, flags);
2141 cpu = cpumask_first_and(cfg->domain, cpu_online_mask);
2142 apic->send_IPI_mask(cpumask_of(cpu), cfg->vector);
2143 raw_spin_unlock_irqrestore(&vector_lock, flags);
2149 * Level and edge triggered IO-APIC interrupts need different handling,
2150 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2151 * handled with the level-triggered descriptor, but that one has slightly
2152 * more overhead. Level-triggered interrupts cannot be handled with the
2153 * edge-triggered handler, without risking IRQ storms and other ugly
2158 void send_cleanup_vector(struct irq_cfg *cfg)
2160 cpumask_var_t cleanup_mask;
2162 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2164 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2165 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2167 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2168 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2169 free_cpumask_var(cleanup_mask);
2171 cfg->move_in_progress = 0;
2174 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
2176 unsigned vector, me;
2182 me = smp_processor_id();
2183 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2186 struct irq_desc *desc;
2187 struct irq_cfg *cfg;
2188 irq = __this_cpu_read(vector_irq[vector]);
2190 if (irq <= VECTOR_UNDEFINED)
2193 desc = irq_to_desc(irq);
2201 raw_spin_lock(&desc->lock);
2204 * Check if the irq migration is in progress. If so, we
2205 * haven't received the cleanup request yet for this irq.
2207 if (cfg->move_in_progress)
2210 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2213 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2215 * Check if the vector that needs to be cleanedup is
2216 * registered at the cpu's IRR. If so, then this is not
2217 * the best time to clean it up. Lets clean it up in the
2218 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2221 if (irr & (1 << (vector % 32))) {
2222 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2225 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
2227 raw_spin_unlock(&desc->lock);
2233 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2237 if (likely(!cfg->move_in_progress))
2240 me = smp_processor_id();
2242 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2243 send_cleanup_vector(cfg);
2246 static void irq_complete_move(struct irq_cfg *cfg)
2248 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2251 void irq_force_complete_move(int irq)
2253 struct irq_cfg *cfg = irq_get_chip_data(irq);
2258 __irq_complete_move(cfg, cfg->vector);
2261 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2264 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2267 struct irq_pin_list *entry;
2268 u8 vector = cfg->vector;
2270 for_each_irq_pin(entry, cfg->irq_2_pin) {
2276 io_apic_write(apic, 0x11 + pin*2, dest);
2277 reg = io_apic_read(apic, 0x10 + pin*2);
2278 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2280 io_apic_modify(apic, 0x10 + pin*2, reg);
2285 * Either sets data->affinity to a valid value, and returns
2286 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2287 * leaves data->affinity untouched.
2289 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2290 unsigned int *dest_id)
2292 struct irq_cfg *cfg = data->chip_data;
2293 unsigned int irq = data->irq;
2296 if (!config_enabled(CONFIG_SMP))
2299 if (!cpumask_intersects(mask, cpu_online_mask))
2302 err = assign_irq_vector(irq, cfg, mask);
2306 err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
2308 if (assign_irq_vector(irq, cfg, data->affinity))
2309 pr_err("Failed to recover vector for irq %d\n", irq);
2313 cpumask_copy(data->affinity, mask);
2319 int native_ioapic_set_affinity(struct irq_data *data,
2320 const struct cpumask *mask,
2323 unsigned int dest, irq = data->irq;
2324 unsigned long flags;
2327 if (!config_enabled(CONFIG_SMP))
2330 raw_spin_lock_irqsave(&ioapic_lock, flags);
2331 ret = __ioapic_set_affinity(data, mask, &dest);
2333 /* Only the high 8 bits are valid. */
2334 dest = SET_APIC_LOGICAL_ID(dest);
2335 __target_IO_APIC_irq(irq, dest, data->chip_data);
2336 ret = IRQ_SET_MASK_OK_NOCOPY;
2338 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2342 static void ack_apic_edge(struct irq_data *data)
2344 irq_complete_move(data->chip_data);
2349 atomic_t irq_mis_count;
2351 #ifdef CONFIG_GENERIC_PENDING_IRQ
2352 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2354 struct irq_pin_list *entry;
2355 unsigned long flags;
2357 raw_spin_lock_irqsave(&ioapic_lock, flags);
2358 for_each_irq_pin(entry, cfg->irq_2_pin) {
2363 reg = io_apic_read(entry->apic, 0x10 + pin*2);
2364 /* Is the remote IRR bit set? */
2365 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2366 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2370 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2375 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2377 /* If we are moving the irq we need to mask it */
2378 if (unlikely(irqd_is_setaffinity_pending(data))) {
2385 static inline void ioapic_irqd_unmask(struct irq_data *data,
2386 struct irq_cfg *cfg, bool masked)
2388 if (unlikely(masked)) {
2389 /* Only migrate the irq if the ack has been received.
2391 * On rare occasions the broadcast level triggered ack gets
2392 * delayed going to ioapics, and if we reprogram the
2393 * vector while Remote IRR is still set the irq will never
2396 * To prevent this scenario we read the Remote IRR bit
2397 * of the ioapic. This has two effects.
2398 * - On any sane system the read of the ioapic will
2399 * flush writes (and acks) going to the ioapic from
2401 * - We get to see if the ACK has actually been delivered.
2403 * Based on failed experiments of reprogramming the
2404 * ioapic entry from outside of irq context starting
2405 * with masking the ioapic entry and then polling until
2406 * Remote IRR was clear before reprogramming the
2407 * ioapic I don't trust the Remote IRR bit to be
2408 * completey accurate.
2410 * However there appears to be no other way to plug
2411 * this race, so if the Remote IRR bit is not
2412 * accurate and is causing problems then it is a hardware bug
2413 * and you can go talk to the chipset vendor about it.
2415 if (!io_apic_level_ack_pending(cfg))
2416 irq_move_masked_irq(data);
2421 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2425 static inline void ioapic_irqd_unmask(struct irq_data *data,
2426 struct irq_cfg *cfg, bool masked)
2431 static void ack_apic_level(struct irq_data *data)
2433 struct irq_cfg *cfg = data->chip_data;
2434 int i, irq = data->irq;
2438 irq_complete_move(cfg);
2439 masked = ioapic_irqd_mask(data, cfg);
2442 * It appears there is an erratum which affects at least version 0x11
2443 * of I/O APIC (that's the 82093AA and cores integrated into various
2444 * chipsets). Under certain conditions a level-triggered interrupt is
2445 * erroneously delivered as edge-triggered one but the respective IRR
2446 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2447 * message but it will never arrive and further interrupts are blocked
2448 * from the source. The exact reason is so far unknown, but the
2449 * phenomenon was observed when two consecutive interrupt requests
2450 * from a given source get delivered to the same CPU and the source is
2451 * temporarily disabled in between.
2453 * A workaround is to simulate an EOI message manually. We achieve it
2454 * by setting the trigger mode to edge and then to level when the edge
2455 * trigger mode gets detected in the TMR of a local APIC for a
2456 * level-triggered interrupt. We mask the source for the time of the
2457 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2458 * The idea is from Manfred Spraul. --macro
2460 * Also in the case when cpu goes offline, fixup_irqs() will forward
2461 * any unhandled interrupt on the offlined cpu to the new cpu
2462 * destination that is handling the corresponding interrupt. This
2463 * interrupt forwarding is done via IPI's. Hence, in this case also
2464 * level-triggered io-apic interrupt will be seen as an edge
2465 * interrupt in the IRR. And we can't rely on the cpu's EOI
2466 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2467 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2468 * supporting EOI register, we do an explicit EOI to clear the
2469 * remote IRR and on IO-APIC's which don't have an EOI register,
2470 * we use the above logic (mask+edge followed by unmask+level) from
2471 * Manfred Spraul to clear the remote IRR.
2474 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2477 * We must acknowledge the irq before we move it or the acknowledge will
2478 * not propagate properly.
2483 * Tail end of clearing remote IRR bit (either by delivering the EOI
2484 * message via io-apic EOI register write or simulating it using
2485 * mask+edge followed by unnask+level logic) manually when the
2486 * level triggered interrupt is seen as the edge triggered interrupt
2489 if (!(v & (1 << (i & 0x1f)))) {
2490 atomic_inc(&irq_mis_count);
2492 eoi_ioapic_irq(irq, cfg);
2495 ioapic_irqd_unmask(data, cfg, masked);
2498 static struct irq_chip ioapic_chip __read_mostly = {
2500 .irq_startup = startup_ioapic_irq,
2501 .irq_mask = mask_ioapic_irq,
2502 .irq_unmask = unmask_ioapic_irq,
2503 .irq_ack = ack_apic_edge,
2504 .irq_eoi = ack_apic_level,
2505 .irq_set_affinity = native_ioapic_set_affinity,
2506 .irq_retrigger = ioapic_retrigger_irq,
2509 static inline void init_IO_APIC_traps(void)
2511 struct irq_cfg *cfg;
2514 for_each_active_irq(irq) {
2515 cfg = irq_get_chip_data(irq);
2516 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2518 * Hmm.. We don't have an entry for this,
2519 * so default to an old-fashioned 8259
2520 * interrupt if we can..
2522 if (irq < legacy_pic->nr_legacy_irqs)
2523 legacy_pic->make_irq(irq);
2525 /* Strange. Oh, well.. */
2526 irq_set_chip(irq, &no_irq_chip);
2532 * The local APIC irq-chip implementation:
2535 static void mask_lapic_irq(struct irq_data *data)
2539 v = apic_read(APIC_LVT0);
2540 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2543 static void unmask_lapic_irq(struct irq_data *data)
2547 v = apic_read(APIC_LVT0);
2548 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2551 static void ack_lapic_irq(struct irq_data *data)
2556 static struct irq_chip lapic_chip __read_mostly = {
2557 .name = "local-APIC",
2558 .irq_mask = mask_lapic_irq,
2559 .irq_unmask = unmask_lapic_irq,
2560 .irq_ack = ack_lapic_irq,
2563 static void lapic_register_intr(int irq)
2565 irq_clear_status_flags(irq, IRQ_LEVEL);
2566 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2571 * This looks a bit hackish but it's about the only one way of sending
2572 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2573 * not support the ExtINT mode, unfortunately. We need to send these
2574 * cycles as some i82489DX-based boards have glue logic that keeps the
2575 * 8259A interrupt line asserted until INTA. --macro
2577 static inline void __init unlock_ExtINT_logic(void)
2580 struct IO_APIC_route_entry entry0, entry1;
2581 unsigned char save_control, save_freq_select;
2583 pin = find_isa_irq_pin(8, mp_INT);
2588 apic = find_isa_irq_apic(8, mp_INT);
2594 entry0 = ioapic_read_entry(apic, pin);
2595 clear_IO_APIC_pin(apic, pin);
2597 memset(&entry1, 0, sizeof(entry1));
2599 entry1.dest_mode = 0; /* physical delivery */
2600 entry1.mask = 0; /* unmask IRQ now */
2601 entry1.dest = hard_smp_processor_id();
2602 entry1.delivery_mode = dest_ExtINT;
2603 entry1.polarity = entry0.polarity;
2607 ioapic_write_entry(apic, pin, entry1);
2609 save_control = CMOS_READ(RTC_CONTROL);
2610 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2611 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2613 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2618 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2622 CMOS_WRITE(save_control, RTC_CONTROL);
2623 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2624 clear_IO_APIC_pin(apic, pin);
2626 ioapic_write_entry(apic, pin, entry0);
2629 static int disable_timer_pin_1 __initdata;
2630 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2631 static int __init disable_timer_pin_setup(char *arg)
2633 disable_timer_pin_1 = 1;
2636 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2639 * This code may look a bit paranoid, but it's supposed to cooperate with
2640 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2641 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2642 * fanatically on his truly buggy board.
2644 * FIXME: really need to revamp this for all platforms.
2646 static inline void __init check_timer(void)
2648 struct irq_cfg *cfg = irq_get_chip_data(0);
2649 int node = cpu_to_node(0);
2650 int apic1, pin1, apic2, pin2;
2651 unsigned long flags;
2654 local_irq_save(flags);
2657 * get/set the timer IRQ vector:
2659 legacy_pic->mask(0);
2660 assign_irq_vector(0, cfg, apic->target_cpus());
2663 * As IRQ0 is to be enabled in the 8259A, the virtual
2664 * wire has to be disabled in the local APIC. Also
2665 * timer interrupts need to be acknowledged manually in
2666 * the 8259A for the i82489DX when using the NMI
2667 * watchdog as that APIC treats NMIs as level-triggered.
2668 * The AEOI mode will finish them in the 8259A
2671 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2672 legacy_pic->init(1);
2674 pin1 = find_isa_irq_pin(0, mp_INT);
2675 apic1 = find_isa_irq_apic(0, mp_INT);
2676 pin2 = ioapic_i8259.pin;
2677 apic2 = ioapic_i8259.apic;
2679 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2680 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2681 cfg->vector, apic1, pin1, apic2, pin2);
2684 * Some BIOS writers are clueless and report the ExtINTA
2685 * I/O APIC input from the cascaded 8259A as the timer
2686 * interrupt input. So just in case, if only one pin
2687 * was found above, try it both directly and through the
2691 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2695 } else if (pin2 == -1) {
2702 * Ok, does IRQ0 through the IOAPIC work?
2705 add_pin_to_irq_node(cfg, node, apic1, pin1);
2706 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2708 /* for edge trigger, setup_ioapic_irq already
2709 * leave it unmasked.
2710 * so only need to unmask if it is level-trigger
2711 * do we really have level trigger timer?
2714 idx = find_irq_entry(apic1, pin1, mp_INT);
2715 if (idx != -1 && irq_trigger(idx))
2718 if (timer_irq_works()) {
2719 if (disable_timer_pin_1 > 0)
2720 clear_IO_APIC_pin(0, pin1);
2723 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2724 local_irq_disable();
2725 clear_IO_APIC_pin(apic1, pin1);
2727 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2728 "8254 timer not connected to IO-APIC\n");
2730 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2731 "(IRQ0) through the 8259A ...\n");
2732 apic_printk(APIC_QUIET, KERN_INFO
2733 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2735 * legacy devices should be connected to IO APIC #0
2737 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2738 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2739 legacy_pic->unmask(0);
2740 if (timer_irq_works()) {
2741 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2745 * Cleanup, just in case ...
2747 local_irq_disable();
2748 legacy_pic->mask(0);
2749 clear_IO_APIC_pin(apic2, pin2);
2750 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2753 apic_printk(APIC_QUIET, KERN_INFO
2754 "...trying to set up timer as Virtual Wire IRQ...\n");
2756 lapic_register_intr(0);
2757 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2758 legacy_pic->unmask(0);
2760 if (timer_irq_works()) {
2761 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2764 local_irq_disable();
2765 legacy_pic->mask(0);
2766 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2767 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2769 apic_printk(APIC_QUIET, KERN_INFO
2770 "...trying to set up timer as ExtINT IRQ...\n");
2772 legacy_pic->init(0);
2773 legacy_pic->make_irq(0);
2774 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2776 unlock_ExtINT_logic();
2778 if (timer_irq_works()) {
2779 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2782 local_irq_disable();
2783 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2784 if (x2apic_preenabled)
2785 apic_printk(APIC_QUIET, KERN_INFO
2786 "Perhaps problem with the pre-enabled x2apic mode\n"
2787 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2788 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2789 "report. Then try booting with the 'noapic' option.\n");
2791 local_irq_restore(flags);
2795 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2796 * to devices. However there may be an I/O APIC pin available for
2797 * this interrupt regardless. The pin may be left unconnected, but
2798 * typically it will be reused as an ExtINT cascade interrupt for
2799 * the master 8259A. In the MPS case such a pin will normally be
2800 * reported as an ExtINT interrupt in the MP table. With ACPI
2801 * there is no provision for ExtINT interrupts, and in the absence
2802 * of an override it would be treated as an ordinary ISA I/O APIC
2803 * interrupt, that is edge-triggered and unmasked by default. We
2804 * used to do this, but it caused problems on some systems because
2805 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2806 * the same ExtINT cascade interrupt to drive the local APIC of the
2807 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2808 * the I/O APIC in all cases now. No actual device should request
2809 * it anyway. --macro
2811 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2813 void __init setup_IO_APIC(void)
2817 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2819 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2821 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2823 * Set up IO-APIC IRQ routing.
2825 x86_init.mpparse.setup_ioapic_ids();
2828 setup_IO_APIC_irqs();
2829 init_IO_APIC_traps();
2830 if (legacy_pic->nr_legacy_irqs)
2835 * Called after all the initialization is done. If we didn't find any
2836 * APIC bugs then we can allow the modify fast path
2839 static int __init io_apic_bug_finalize(void)
2841 if (sis_apic_bug == -1)
2846 late_initcall(io_apic_bug_finalize);
2848 static void resume_ioapic_id(int ioapic_idx)
2850 unsigned long flags;
2851 union IO_APIC_reg_00 reg_00;
2853 raw_spin_lock_irqsave(&ioapic_lock, flags);
2854 reg_00.raw = io_apic_read(ioapic_idx, 0);
2855 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2856 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2857 io_apic_write(ioapic_idx, 0, reg_00.raw);
2859 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2862 static void ioapic_resume(void)
2866 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2867 resume_ioapic_id(ioapic_idx);
2869 restore_ioapic_entries();
2872 static struct syscore_ops ioapic_syscore_ops = {
2873 .suspend = save_ioapic_entries,
2874 .resume = ioapic_resume,
2877 static int __init ioapic_init_ops(void)
2879 register_syscore_ops(&ioapic_syscore_ops);
2884 device_initcall(ioapic_init_ops);
2887 * Dynamic irq allocate and deallocation. Should be replaced by irq domains!
2889 int arch_setup_hwirq(unsigned int irq, int node)
2891 struct irq_cfg *cfg;
2892 unsigned long flags;
2895 cfg = alloc_irq_cfg(irq, node);
2899 raw_spin_lock_irqsave(&vector_lock, flags);
2900 ret = __assign_irq_vector(irq, cfg, apic->target_cpus());
2901 raw_spin_unlock_irqrestore(&vector_lock, flags);
2904 irq_set_chip_data(irq, cfg);
2906 free_irq_cfg(irq, cfg);
2910 void arch_teardown_hwirq(unsigned int irq)
2912 struct irq_cfg *cfg = irq_get_chip_data(irq);
2913 unsigned long flags;
2915 free_remapped_irq(irq);
2916 raw_spin_lock_irqsave(&vector_lock, flags);
2917 __clear_irq_vector(irq, cfg);
2918 raw_spin_unlock_irqrestore(&vector_lock, flags);
2919 free_irq_cfg(irq, cfg);
2923 * MSI message composition
2925 void native_compose_msi_msg(struct pci_dev *pdev,
2926 unsigned int irq, unsigned int dest,
2927 struct msi_msg *msg, u8 hpet_id)
2929 struct irq_cfg *cfg = irq_cfg(irq);
2931 msg->address_hi = MSI_ADDR_BASE_HI;
2933 if (x2apic_enabled())
2934 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
2938 ((apic->irq_dest_mode == 0) ?
2939 MSI_ADDR_DEST_MODE_PHYSICAL:
2940 MSI_ADDR_DEST_MODE_LOGICAL) |
2941 ((apic->irq_delivery_mode != dest_LowestPrio) ?
2942 MSI_ADDR_REDIRECTION_CPU:
2943 MSI_ADDR_REDIRECTION_LOWPRI) |
2944 MSI_ADDR_DEST_ID(dest);
2947 MSI_DATA_TRIGGER_EDGE |
2948 MSI_DATA_LEVEL_ASSERT |
2949 ((apic->irq_delivery_mode != dest_LowestPrio) ?
2950 MSI_DATA_DELIVERY_FIXED:
2951 MSI_DATA_DELIVERY_LOWPRI) |
2952 MSI_DATA_VECTOR(cfg->vector);
2955 #ifdef CONFIG_PCI_MSI
2956 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
2957 struct msi_msg *msg, u8 hpet_id)
2959 struct irq_cfg *cfg;
2967 err = assign_irq_vector(irq, cfg, apic->target_cpus());
2971 err = apic->cpu_mask_to_apicid_and(cfg->domain,
2972 apic->target_cpus(), &dest);
2976 x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
2982 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
2984 struct irq_cfg *cfg = data->chip_data;
2989 ret = __ioapic_set_affinity(data, mask, &dest);
2993 __get_cached_msi_msg(data->msi_desc, &msg);
2995 msg.data &= ~MSI_DATA_VECTOR_MASK;
2996 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2997 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2998 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3000 __write_msi_msg(data->msi_desc, &msg);
3002 return IRQ_SET_MASK_OK_NOCOPY;
3006 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3007 * which implement the MSI or MSI-X Capability Structure.
3009 static struct irq_chip msi_chip = {
3011 .irq_unmask = unmask_msi_irq,
3012 .irq_mask = mask_msi_irq,
3013 .irq_ack = ack_apic_edge,
3014 .irq_set_affinity = msi_set_affinity,
3015 .irq_retrigger = ioapic_retrigger_irq,
3018 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
3019 unsigned int irq_base, unsigned int irq_offset)
3021 struct irq_chip *chip = &msi_chip;
3023 unsigned int irq = irq_base + irq_offset;
3026 ret = msi_compose_msg(dev, irq, &msg, -1);
3030 irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
3033 * MSI-X message is written per-IRQ, the offset is always 0.
3034 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
3037 write_msi_msg(irq, &msg);
3039 setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
3041 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3043 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3048 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3050 struct msi_desc *msidesc;
3054 /* Multiple MSI vectors only supported with interrupt remapping */
3055 if (type == PCI_CAP_ID_MSI && nvec > 1)
3058 node = dev_to_node(&dev->dev);
3060 list_for_each_entry(msidesc, &dev->msi_list, list) {
3061 irq = irq_alloc_hwirq(node);
3065 ret = setup_msi_irq(dev, msidesc, irq, 0);
3067 irq_free_hwirq(irq);
3075 void native_teardown_msi_irq(unsigned int irq)
3077 irq_free_hwirq(irq);
3080 #ifdef CONFIG_DMAR_TABLE
3082 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3085 struct irq_cfg *cfg = data->chip_data;
3086 unsigned int dest, irq = data->irq;
3090 ret = __ioapic_set_affinity(data, mask, &dest);
3094 dmar_msi_read(irq, &msg);
3096 msg.data &= ~MSI_DATA_VECTOR_MASK;
3097 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3098 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3099 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3100 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3102 dmar_msi_write(irq, &msg);
3104 return IRQ_SET_MASK_OK_NOCOPY;
3107 static struct irq_chip dmar_msi_type = {
3109 .irq_unmask = dmar_msi_unmask,
3110 .irq_mask = dmar_msi_mask,
3111 .irq_ack = ack_apic_edge,
3112 .irq_set_affinity = dmar_msi_set_affinity,
3113 .irq_retrigger = ioapic_retrigger_irq,
3116 int arch_setup_dmar_msi(unsigned int irq)
3121 ret = msi_compose_msg(NULL, irq, &msg, -1);
3124 dmar_msi_write(irq, &msg);
3125 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3131 #ifdef CONFIG_HPET_TIMER
3133 static int hpet_msi_set_affinity(struct irq_data *data,
3134 const struct cpumask *mask, bool force)
3136 struct irq_cfg *cfg = data->chip_data;
3141 ret = __ioapic_set_affinity(data, mask, &dest);
3145 hpet_msi_read(data->handler_data, &msg);
3147 msg.data &= ~MSI_DATA_VECTOR_MASK;
3148 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3149 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3150 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3152 hpet_msi_write(data->handler_data, &msg);
3154 return IRQ_SET_MASK_OK_NOCOPY;
3157 static struct irq_chip hpet_msi_type = {
3159 .irq_unmask = hpet_msi_unmask,
3160 .irq_mask = hpet_msi_mask,
3161 .irq_ack = ack_apic_edge,
3162 .irq_set_affinity = hpet_msi_set_affinity,
3163 .irq_retrigger = ioapic_retrigger_irq,
3166 int default_setup_hpet_msi(unsigned int irq, unsigned int id)
3168 struct irq_chip *chip = &hpet_msi_type;
3172 ret = msi_compose_msg(NULL, irq, &msg, id);
3176 hpet_msi_write(irq_get_handler_data(irq), &msg);
3177 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3178 setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
3180 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3185 #endif /* CONFIG_PCI_MSI */
3187 * Hypertransport interrupt support
3189 #ifdef CONFIG_HT_IRQ
3191 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3193 struct ht_irq_msg msg;
3194 fetch_ht_irq_msg(irq, &msg);
3196 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3197 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3199 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3200 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3202 write_ht_irq_msg(irq, &msg);
3206 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3208 struct irq_cfg *cfg = data->chip_data;
3212 ret = __ioapic_set_affinity(data, mask, &dest);
3216 target_ht_irq(data->irq, dest, cfg->vector);
3217 return IRQ_SET_MASK_OK_NOCOPY;
3220 static struct irq_chip ht_irq_chip = {
3222 .irq_mask = mask_ht_irq,
3223 .irq_unmask = unmask_ht_irq,
3224 .irq_ack = ack_apic_edge,
3225 .irq_set_affinity = ht_set_affinity,
3226 .irq_retrigger = ioapic_retrigger_irq,
3229 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3231 struct irq_cfg *cfg;
3232 struct ht_irq_msg msg;
3240 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3244 err = apic->cpu_mask_to_apicid_and(cfg->domain,
3245 apic->target_cpus(), &dest);
3249 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3253 HT_IRQ_LOW_DEST_ID(dest) |
3254 HT_IRQ_LOW_VECTOR(cfg->vector) |
3255 ((apic->irq_dest_mode == 0) ?
3256 HT_IRQ_LOW_DM_PHYSICAL :
3257 HT_IRQ_LOW_DM_LOGICAL) |
3258 HT_IRQ_LOW_RQEOI_EDGE |
3259 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3260 HT_IRQ_LOW_MT_FIXED :
3261 HT_IRQ_LOW_MT_ARBITRATED) |
3262 HT_IRQ_LOW_IRQ_MASKED;
3264 write_ht_irq_msg(irq, &msg);
3266 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3267 handle_edge_irq, "edge");
3269 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3273 #endif /* CONFIG_HT_IRQ */
3276 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3278 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3283 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3285 setup_ioapic_irq(irq, cfg, attr);
3289 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3290 struct io_apic_irq_attr *attr)
3292 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3294 struct IO_APIC_route_entry orig_entry;
3296 /* Avoid redundant programming */
3297 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3298 pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin);
3299 orig_entry = ioapic_read_entry(attr->ioapic, pin);
3300 if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity)
3304 ret = io_apic_setup_irq_pin(irq, node, attr);
3306 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3310 static int __init io_apic_get_redir_entries(int ioapic)
3312 union IO_APIC_reg_01 reg_01;
3313 unsigned long flags;
3315 raw_spin_lock_irqsave(&ioapic_lock, flags);
3316 reg_01.raw = io_apic_read(ioapic, 1);
3317 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3319 /* The register returns the maximum index redir index
3320 * supported, which is one less than the total number of redir
3323 return reg_01.bits.entries + 1;
3326 unsigned int arch_dynirq_lower_bound(unsigned int from)
3328 unsigned int min = gsi_top + NR_IRQS_LEGACY;
3330 return from < min ? min : from;
3333 int __init arch_probe_nr_irqs(void)
3337 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3338 nr_irqs = NR_VECTORS * nr_cpu_ids;
3340 nr = (gsi_top + NR_IRQS_LEGACY) + 8 * nr_cpu_ids;
3341 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3343 * for MSI and HT dyn irq
3345 nr += (gsi_top + NR_IRQS_LEGACY) * 16;
3350 return NR_IRQS_LEGACY;
3353 int io_apic_set_pci_routing(struct device *dev, int irq,
3354 struct io_apic_irq_attr *irq_attr)
3358 if (!IO_APIC_IRQ(irq)) {
3359 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3364 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3366 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3369 #ifdef CONFIG_X86_32
3370 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3372 union IO_APIC_reg_00 reg_00;
3373 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3375 unsigned long flags;
3379 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3380 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3381 * supports up to 16 on one shared APIC bus.
3383 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3384 * advantage of new APIC bus architecture.
3387 if (physids_empty(apic_id_map))
3388 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3390 raw_spin_lock_irqsave(&ioapic_lock, flags);
3391 reg_00.raw = io_apic_read(ioapic, 0);
3392 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3394 if (apic_id >= get_physical_broadcast()) {
3395 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3396 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3397 apic_id = reg_00.bits.ID;
3401 * Every APIC in a system must have a unique ID or we get lots of nice
3402 * 'stuck on smp_invalidate_needed IPI wait' messages.
3404 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3406 for (i = 0; i < get_physical_broadcast(); i++) {
3407 if (!apic->check_apicid_used(&apic_id_map, i))
3411 if (i == get_physical_broadcast())
3412 panic("Max apic_id exceeded!\n");
3414 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3415 "trying %d\n", ioapic, apic_id, i);
3420 apic->apicid_to_cpu_present(apic_id, &tmp);
3421 physids_or(apic_id_map, apic_id_map, tmp);
3423 if (reg_00.bits.ID != apic_id) {
3424 reg_00.bits.ID = apic_id;
3426 raw_spin_lock_irqsave(&ioapic_lock, flags);
3427 io_apic_write(ioapic, 0, reg_00.raw);
3428 reg_00.raw = io_apic_read(ioapic, 0);
3429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3432 if (reg_00.bits.ID != apic_id) {
3433 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3439 apic_printk(APIC_VERBOSE, KERN_INFO
3440 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3445 static u8 __init io_apic_unique_id(u8 id)
3447 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3448 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3449 return io_apic_get_unique_id(nr_ioapics, id);
3454 static u8 __init io_apic_unique_id(u8 id)
3457 DECLARE_BITMAP(used, 256);
3459 bitmap_zero(used, 256);
3460 for (i = 0; i < nr_ioapics; i++) {
3461 __set_bit(mpc_ioapic_id(i), used);
3463 if (!test_bit(id, used))
3465 return find_first_zero_bit(used, 256);
3469 static int __init io_apic_get_version(int ioapic)
3471 union IO_APIC_reg_01 reg_01;
3472 unsigned long flags;
3474 raw_spin_lock_irqsave(&ioapic_lock, flags);
3475 reg_01.raw = io_apic_read(ioapic, 1);
3476 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3478 return reg_01.bits.version;
3481 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3483 int ioapic, pin, idx;
3485 if (skip_ioapic_setup)
3488 ioapic = mp_find_ioapic(gsi);
3492 pin = mp_find_ioapic_pin(ioapic, gsi);
3496 idx = find_irq_entry(ioapic, pin, mp_INT);
3500 *trigger = irq_trigger(idx);
3501 *polarity = irq_polarity(idx);
3506 * This function currently is only a helper for the i386 smp boot process where
3507 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3508 * so mask in all cases should simply be apic->target_cpus()
3511 void __init setup_ioapic_dest(void)
3513 int pin, ioapic, irq, irq_entry;
3514 const struct cpumask *mask;
3515 struct irq_data *idata;
3517 if (skip_ioapic_setup == 1)
3520 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3521 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3522 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3523 if (irq_entry == -1)
3525 irq = pin_2_irq(irq_entry, ioapic, pin);
3527 if ((ioapic > 0) && (irq > NR_IRQS_LEGACY))
3530 idata = irq_get_irq_data(irq);
3533 * Honour affinities which have been set in early boot
3535 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3536 mask = idata->affinity;
3538 mask = apic->target_cpus();
3540 x86_io_apic_ops.set_affinity(idata, mask, false);
3546 #define IOAPIC_RESOURCE_NAME_SIZE 11
3548 static struct resource *ioapic_resources;
3550 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3553 struct resource *res;
3557 if (nr_ioapics <= 0)
3560 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3563 mem = alloc_bootmem(n);
3566 mem += sizeof(struct resource) * nr_ioapics;
3568 for (i = 0; i < nr_ioapics; i++) {
3570 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3571 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3572 mem += IOAPIC_RESOURCE_NAME_SIZE;
3575 ioapic_resources = res;
3580 void __init native_io_apic_init_mappings(void)
3582 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3583 struct resource *ioapic_res;
3586 ioapic_res = ioapic_setup_resources(nr_ioapics);
3587 for (i = 0; i < nr_ioapics; i++) {
3588 if (smp_found_config) {
3589 ioapic_phys = mpc_ioapic_addr(i);
3590 #ifdef CONFIG_X86_32
3593 "WARNING: bogus zero IO-APIC "
3594 "address found in MPTABLE, "
3595 "disabling IO/APIC support!\n");
3596 smp_found_config = 0;
3597 skip_ioapic_setup = 1;
3598 goto fake_ioapic_page;
3602 #ifdef CONFIG_X86_32
3605 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3606 ioapic_phys = __pa(ioapic_phys);
3608 set_fixmap_nocache(idx, ioapic_phys);
3609 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3610 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3614 ioapic_res->start = ioapic_phys;
3615 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3620 void __init ioapic_insert_resources(void)
3623 struct resource *r = ioapic_resources;
3628 "IO APIC resources couldn't be allocated.\n");
3632 for (i = 0; i < nr_ioapics; i++) {
3633 insert_resource(&iomem_resource, r);
3638 int mp_find_ioapic(u32 gsi)
3642 if (nr_ioapics == 0)
3645 /* Find the IOAPIC that manages this GSI. */
3646 for (i = 0; i < nr_ioapics; i++) {
3647 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3648 if ((gsi >= gsi_cfg->gsi_base)
3649 && (gsi <= gsi_cfg->gsi_end))
3653 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3657 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3659 struct mp_ioapic_gsi *gsi_cfg;
3661 if (WARN_ON(ioapic == -1))
3664 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3665 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3668 return gsi - gsi_cfg->gsi_base;
3671 static __init int bad_ioapic(unsigned long address)
3673 if (nr_ioapics >= MAX_IO_APICS) {
3674 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3675 MAX_IO_APICS, nr_ioapics);
3679 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3685 static __init int bad_ioapic_register(int idx)
3687 union IO_APIC_reg_00 reg_00;
3688 union IO_APIC_reg_01 reg_01;
3689 union IO_APIC_reg_02 reg_02;
3691 reg_00.raw = io_apic_read(idx, 0);
3692 reg_01.raw = io_apic_read(idx, 1);
3693 reg_02.raw = io_apic_read(idx, 2);
3695 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3696 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3697 mpc_ioapic_addr(idx));
3704 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3708 struct mp_ioapic_gsi *gsi_cfg;
3710 if (bad_ioapic(address))
3715 ioapics[idx].mp_config.type = MP_IOAPIC;
3716 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3717 ioapics[idx].mp_config.apicaddr = address;
3719 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3721 if (bad_ioapic_register(idx)) {
3722 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3726 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3727 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3730 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3731 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3733 entries = io_apic_get_redir_entries(idx);
3734 gsi_cfg = mp_ioapic_gsi_routing(idx);
3735 gsi_cfg->gsi_base = gsi_base;
3736 gsi_cfg->gsi_end = gsi_base + entries - 1;
3739 * The number of IO-APIC IRQ registers (== #pins):
3741 ioapics[idx].nr_registers = entries;
3743 if (gsi_cfg->gsi_end >= gsi_top)
3744 gsi_top = gsi_cfg->gsi_end + 1;
3746 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3747 idx, mpc_ioapic_id(idx),
3748 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3749 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3754 /* Enable IOAPIC early just for system timer */
3755 void __init pre_init_apic_IRQ0(void)
3757 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3759 printk(KERN_INFO "Early APIC setup for system timer0\n");
3761 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3762 &phys_cpu_present_map);
3766 io_apic_setup_irq_pin(0, 0, &attr);
3767 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,