2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
97 /* Number of legacy interrupts */
98 static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY;
100 static int nr_irqs_gsi = NR_IRQS_LEGACY;
102 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
103 int mp_bus_id_to_type[MAX_MP_BUSSES];
106 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
108 int skip_ioapic_setup;
110 void arch_disable_smp_support(void)
114 noioapicreroute = -1;
116 skip_ioapic_setup = 1;
119 static int __init parse_noapic(char *str)
121 /* disable IO-APIC */
122 arch_disable_smp_support();
125 early_param("noapic", parse_noapic);
127 struct irq_pin_list {
129 struct irq_pin_list *next;
132 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
134 struct irq_pin_list *pin;
136 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
141 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
142 #ifdef CONFIG_SPARSE_IRQ
143 static struct irq_cfg irq_cfgx[] = {
145 static struct irq_cfg irq_cfgx[NR_IRQS] = {
147 [0] = { .vector = IRQ0_VECTOR, },
148 [1] = { .vector = IRQ1_VECTOR, },
149 [2] = { .vector = IRQ2_VECTOR, },
150 [3] = { .vector = IRQ3_VECTOR, },
151 [4] = { .vector = IRQ4_VECTOR, },
152 [5] = { .vector = IRQ5_VECTOR, },
153 [6] = { .vector = IRQ6_VECTOR, },
154 [7] = { .vector = IRQ7_VECTOR, },
155 [8] = { .vector = IRQ8_VECTOR, },
156 [9] = { .vector = IRQ9_VECTOR, },
157 [10] = { .vector = IRQ10_VECTOR, },
158 [11] = { .vector = IRQ11_VECTOR, },
159 [12] = { .vector = IRQ12_VECTOR, },
160 [13] = { .vector = IRQ13_VECTOR, },
161 [14] = { .vector = IRQ14_VECTOR, },
162 [15] = { .vector = IRQ15_VECTOR, },
165 void __init io_apic_disable_legacy(void)
171 int __init arch_early_irq_init(void)
174 struct irq_desc *desc;
180 count = ARRAY_SIZE(irq_cfgx);
181 node= cpu_to_node(boot_cpu_id);
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
187 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
188 if (i < nr_legacy_irqs)
189 cpumask_setall(cfg[i].domain);
195 #ifdef CONFIG_SPARSE_IRQ
196 struct irq_cfg *irq_cfg(unsigned int irq)
198 struct irq_cfg *cfg = NULL;
199 struct irq_desc *desc;
201 desc = irq_to_desc(irq);
203 cfg = desc->chip_data;
208 static struct irq_cfg *get_one_free_irq_cfg(int node)
212 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
214 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
217 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
219 free_cpumask_var(cfg->domain);
228 int arch_init_chip_data(struct irq_desc *desc, int node)
232 cfg = desc->chip_data;
234 desc->chip_data = get_one_free_irq_cfg(node);
235 if (!desc->chip_data) {
236 printk(KERN_ERR "can not alloc irq_cfg\n");
244 /* for move_irq_desc */
246 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
248 struct irq_pin_list *old_entry, *head, *tail, *entry;
250 cfg->irq_2_pin = NULL;
251 old_entry = old_cfg->irq_2_pin;
255 entry = get_one_free_irq_2_pin(node);
259 entry->apic = old_entry->apic;
260 entry->pin = old_entry->pin;
263 old_entry = old_entry->next;
265 entry = get_one_free_irq_2_pin(node);
273 /* still use the old one */
276 entry->apic = old_entry->apic;
277 entry->pin = old_entry->pin;
280 old_entry = old_entry->next;
284 cfg->irq_2_pin = head;
287 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
289 struct irq_pin_list *entry, *next;
291 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
294 entry = old_cfg->irq_2_pin;
301 old_cfg->irq_2_pin = NULL;
304 void arch_init_copy_chip_data(struct irq_desc *old_desc,
305 struct irq_desc *desc, int node)
308 struct irq_cfg *old_cfg;
310 cfg = get_one_free_irq_cfg(node);
315 desc->chip_data = cfg;
317 old_cfg = old_desc->chip_data;
319 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
321 init_copy_irq_2_pin(old_cfg, cfg, node);
324 static void free_irq_cfg(struct irq_cfg *old_cfg)
329 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
331 struct irq_cfg *old_cfg, *cfg;
333 old_cfg = old_desc->chip_data;
334 cfg = desc->chip_data;
340 free_irq_2_pin(old_cfg, cfg);
341 free_irq_cfg(old_cfg);
342 old_desc->chip_data = NULL;
345 /* end for move_irq_desc */
348 struct irq_cfg *irq_cfg(unsigned int irq)
350 return irq < nr_irqs ? irq_cfgx + irq : NULL;
357 unsigned int unused[3];
359 unsigned int unused2[11];
363 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
365 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
366 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
369 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
371 struct io_apic __iomem *io_apic = io_apic_base(apic);
372 writel(vector, &io_apic->eoi);
375 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
377 struct io_apic __iomem *io_apic = io_apic_base(apic);
378 writel(reg, &io_apic->index);
379 return readl(&io_apic->data);
382 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 writel(value, &io_apic->data);
390 * Re-write a value: to be used for read-modify-write
391 * cycles where the read already set up the index register.
393 * Older SiS APIC requires we rewrite the index register
395 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
397 struct io_apic __iomem *io_apic = io_apic_base(apic);
400 writel(reg, &io_apic->index);
401 writel(value, &io_apic->data);
404 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
406 struct irq_pin_list *entry;
409 spin_lock_irqsave(&ioapic_lock, flags);
410 for_each_irq_pin(entry, cfg->irq_2_pin) {
415 reg = io_apic_read(entry->apic, 0x10 + pin*2);
416 /* Is the remote IRR bit set? */
417 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
418 spin_unlock_irqrestore(&ioapic_lock, flags);
422 spin_unlock_irqrestore(&ioapic_lock, flags);
428 struct { u32 w1, w2; };
429 struct IO_APIC_route_entry entry;
432 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
434 union entry_union eu;
436 spin_lock_irqsave(&ioapic_lock, flags);
437 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
438 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
439 spin_unlock_irqrestore(&ioapic_lock, flags);
444 * When we write a new IO APIC routing entry, we need to write the high
445 * word first! If the mask bit in the low word is clear, we will enable
446 * the interrupt, and we need to make sure the entry is fully populated
447 * before that happens.
450 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
452 union entry_union eu = {{0, 0}};
455 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
456 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
459 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
462 spin_lock_irqsave(&ioapic_lock, flags);
463 __ioapic_write_entry(apic, pin, e);
464 spin_unlock_irqrestore(&ioapic_lock, flags);
468 * When we mask an IO APIC routing entry, we need to write the low
469 * word first, in order to set the mask bit before we change the
472 static void ioapic_mask_entry(int apic, int pin)
475 union entry_union eu = { .entry.mask = 1 };
477 spin_lock_irqsave(&ioapic_lock, flags);
478 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
479 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
480 spin_unlock_irqrestore(&ioapic_lock, flags);
484 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
485 * shared ISA-space IRQs, so we have to support them. We are super
486 * fast in the common case, and fast for shared ISA-space IRQs.
489 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
491 struct irq_pin_list **last, *entry;
493 /* don't allow duplicates */
494 last = &cfg->irq_2_pin;
495 for_each_irq_pin(entry, cfg->irq_2_pin) {
496 if (entry->apic == apic && entry->pin == pin)
501 entry = get_one_free_irq_2_pin(node);
503 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
514 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
516 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
517 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
521 * Reroute an IRQ to a different pin.
523 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
524 int oldapic, int oldpin,
525 int newapic, int newpin)
527 struct irq_pin_list *entry;
529 for_each_irq_pin(entry, cfg->irq_2_pin) {
530 if (entry->apic == oldapic && entry->pin == oldpin) {
531 entry->apic = newapic;
533 /* every one is different, right? */
538 /* old apic/pin didn't exist, so just add new ones */
539 add_pin_to_irq_node(cfg, node, newapic, newpin);
542 static void __io_apic_modify_irq(struct irq_pin_list *entry,
543 int mask_and, int mask_or,
544 void (*final)(struct irq_pin_list *entry))
546 unsigned int reg, pin;
549 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
552 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
557 static void io_apic_modify_irq(struct irq_cfg *cfg,
558 int mask_and, int mask_or,
559 void (*final)(struct irq_pin_list *entry))
561 struct irq_pin_list *entry;
563 for_each_irq_pin(entry, cfg->irq_2_pin)
564 __io_apic_modify_irq(entry, mask_and, mask_or, final);
567 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
569 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
570 IO_APIC_REDIR_MASKED, NULL);
573 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
575 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
576 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
579 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
581 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
584 static void io_apic_sync(struct irq_pin_list *entry)
587 * Synchronize the IO-APIC and the CPU by doing
588 * a dummy read from the IO-APIC
590 struct io_apic __iomem *io_apic;
591 io_apic = io_apic_base(entry->apic);
592 readl(&io_apic->data);
595 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
597 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
600 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
602 struct irq_cfg *cfg = desc->chip_data;
607 spin_lock_irqsave(&ioapic_lock, flags);
608 __mask_IO_APIC_irq(cfg);
609 spin_unlock_irqrestore(&ioapic_lock, flags);
612 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
614 struct irq_cfg *cfg = desc->chip_data;
617 spin_lock_irqsave(&ioapic_lock, flags);
618 __unmask_IO_APIC_irq(cfg);
619 spin_unlock_irqrestore(&ioapic_lock, flags);
622 static void mask_IO_APIC_irq(unsigned int irq)
624 struct irq_desc *desc = irq_to_desc(irq);
626 mask_IO_APIC_irq_desc(desc);
628 static void unmask_IO_APIC_irq(unsigned int irq)
630 struct irq_desc *desc = irq_to_desc(irq);
632 unmask_IO_APIC_irq_desc(desc);
635 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
637 struct IO_APIC_route_entry entry;
639 /* Check delivery_mode to be sure we're not clearing an SMI pin */
640 entry = ioapic_read_entry(apic, pin);
641 if (entry.delivery_mode == dest_SMI)
644 * Disable it in the IO-APIC irq-routing table:
646 ioapic_mask_entry(apic, pin);
649 static void clear_IO_APIC (void)
653 for (apic = 0; apic < nr_ioapics; apic++)
654 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
655 clear_IO_APIC_pin(apic, pin);
660 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
661 * specific CPU-side IRQs.
665 static int pirq_entries[MAX_PIRQS] = {
666 [0 ... MAX_PIRQS - 1] = -1
669 static int __init ioapic_pirq_setup(char *str)
672 int ints[MAX_PIRQS+1];
674 get_options(str, ARRAY_SIZE(ints), ints);
676 apic_printk(APIC_VERBOSE, KERN_INFO
677 "PIRQ redirection, working around broken MP-BIOS.\n");
679 if (ints[0] < MAX_PIRQS)
682 for (i = 0; i < max; i++) {
683 apic_printk(APIC_VERBOSE, KERN_DEBUG
684 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
686 * PIRQs are mapped upside down, usually.
688 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
693 __setup("pirq=", ioapic_pirq_setup);
694 #endif /* CONFIG_X86_32 */
696 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
699 struct IO_APIC_route_entry **ioapic_entries;
701 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
706 for (apic = 0; apic < nr_ioapics; apic++) {
707 ioapic_entries[apic] =
708 kzalloc(sizeof(struct IO_APIC_route_entry) *
709 nr_ioapic_registers[apic], GFP_ATOMIC);
710 if (!ioapic_entries[apic])
714 return ioapic_entries;
718 kfree(ioapic_entries[apic]);
719 kfree(ioapic_entries);
725 * Saves all the IO-APIC RTE's
727 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
734 for (apic = 0; apic < nr_ioapics; apic++) {
735 if (!ioapic_entries[apic])
738 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
739 ioapic_entries[apic][pin] =
740 ioapic_read_entry(apic, pin);
747 * Mask all IO APIC entries.
749 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
756 for (apic = 0; apic < nr_ioapics; apic++) {
757 if (!ioapic_entries[apic])
760 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
761 struct IO_APIC_route_entry entry;
763 entry = ioapic_entries[apic][pin];
766 ioapic_write_entry(apic, pin, entry);
773 * Restore IO APIC entries which was saved in ioapic_entries.
775 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
782 for (apic = 0; apic < nr_ioapics; apic++) {
783 if (!ioapic_entries[apic])
786 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
787 ioapic_write_entry(apic, pin,
788 ioapic_entries[apic][pin]);
793 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
797 for (apic = 0; apic < nr_ioapics; apic++)
798 kfree(ioapic_entries[apic]);
800 kfree(ioapic_entries);
804 * Find the IRQ entry number of a certain pin.
806 static int find_irq_entry(int apic, int pin, int type)
810 for (i = 0; i < mp_irq_entries; i++)
811 if (mp_irqs[i].irqtype == type &&
812 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
813 mp_irqs[i].dstapic == MP_APIC_ALL) &&
814 mp_irqs[i].dstirq == pin)
821 * Find the pin to which IRQ[irq] (ISA) is connected
823 static int __init find_isa_irq_pin(int irq, int type)
827 for (i = 0; i < mp_irq_entries; i++) {
828 int lbus = mp_irqs[i].srcbus;
830 if (test_bit(lbus, mp_bus_not_pci) &&
831 (mp_irqs[i].irqtype == type) &&
832 (mp_irqs[i].srcbusirq == irq))
834 return mp_irqs[i].dstirq;
839 static int __init find_isa_irq_apic(int irq, int type)
843 for (i = 0; i < mp_irq_entries; i++) {
844 int lbus = mp_irqs[i].srcbus;
846 if (test_bit(lbus, mp_bus_not_pci) &&
847 (mp_irqs[i].irqtype == type) &&
848 (mp_irqs[i].srcbusirq == irq))
851 if (i < mp_irq_entries) {
853 for(apic = 0; apic < nr_ioapics; apic++) {
854 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
862 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
864 * EISA Edge/Level control register, ELCR
866 static int EISA_ELCR(unsigned int irq)
868 if (irq < nr_legacy_irqs) {
869 unsigned int port = 0x4d0 + (irq >> 3);
870 return (inb(port) >> (irq & 7)) & 1;
872 apic_printk(APIC_VERBOSE, KERN_INFO
873 "Broken MPtable reports ISA irq %d\n", irq);
879 /* ISA interrupts are always polarity zero edge triggered,
880 * when listed as conforming in the MP table. */
882 #define default_ISA_trigger(idx) (0)
883 #define default_ISA_polarity(idx) (0)
885 /* EISA interrupts are always polarity zero and can be edge or level
886 * trigger depending on the ELCR value. If an interrupt is listed as
887 * EISA conforming in the MP table, that means its trigger type must
888 * be read in from the ELCR */
890 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
891 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
893 /* PCI interrupts are always polarity one level triggered,
894 * when listed as conforming in the MP table. */
896 #define default_PCI_trigger(idx) (1)
897 #define default_PCI_polarity(idx) (1)
899 /* MCA interrupts are always polarity zero level triggered,
900 * when listed as conforming in the MP table. */
902 #define default_MCA_trigger(idx) (1)
903 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
905 static int MPBIOS_polarity(int idx)
907 int bus = mp_irqs[idx].srcbus;
911 * Determine IRQ line polarity (high active or low active):
913 switch (mp_irqs[idx].irqflag & 3)
915 case 0: /* conforms, ie. bus-type dependent polarity */
916 if (test_bit(bus, mp_bus_not_pci))
917 polarity = default_ISA_polarity(idx);
919 polarity = default_PCI_polarity(idx);
921 case 1: /* high active */
926 case 2: /* reserved */
928 printk(KERN_WARNING "broken BIOS!!\n");
932 case 3: /* low active */
937 default: /* invalid */
939 printk(KERN_WARNING "broken BIOS!!\n");
947 static int MPBIOS_trigger(int idx)
949 int bus = mp_irqs[idx].srcbus;
953 * Determine IRQ trigger mode (edge or level sensitive):
955 switch ((mp_irqs[idx].irqflag>>2) & 3)
957 case 0: /* conforms, ie. bus-type dependent */
958 if (test_bit(bus, mp_bus_not_pci))
959 trigger = default_ISA_trigger(idx);
961 trigger = default_PCI_trigger(idx);
962 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
963 switch (mp_bus_id_to_type[bus]) {
964 case MP_BUS_ISA: /* ISA pin */
966 /* set before the switch */
969 case MP_BUS_EISA: /* EISA pin */
971 trigger = default_EISA_trigger(idx);
974 case MP_BUS_PCI: /* PCI pin */
976 /* set before the switch */
979 case MP_BUS_MCA: /* MCA pin */
981 trigger = default_MCA_trigger(idx);
986 printk(KERN_WARNING "broken BIOS!!\n");
998 case 2: /* reserved */
1000 printk(KERN_WARNING "broken BIOS!!\n");
1009 default: /* invalid */
1011 printk(KERN_WARNING "broken BIOS!!\n");
1019 static inline int irq_polarity(int idx)
1021 return MPBIOS_polarity(idx);
1024 static inline int irq_trigger(int idx)
1026 return MPBIOS_trigger(idx);
1029 int (*ioapic_renumber_irq)(int ioapic, int irq);
1030 static int pin_2_irq(int idx, int apic, int pin)
1033 int bus = mp_irqs[idx].srcbus;
1036 * Debugging check, we are in big trouble if this message pops up!
1038 if (mp_irqs[idx].dstirq != pin)
1039 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1041 if (test_bit(bus, mp_bus_not_pci)) {
1042 irq = mp_irqs[idx].srcbusirq;
1045 * PCI IRQs are mapped in order
1049 irq += nr_ioapic_registers[i++];
1052 * For MPS mode, so far only needed by ES7000 platform
1054 if (ioapic_renumber_irq)
1055 irq = ioapic_renumber_irq(apic, irq);
1058 #ifdef CONFIG_X86_32
1060 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1062 if ((pin >= 16) && (pin <= 23)) {
1063 if (pirq_entries[pin-16] != -1) {
1064 if (!pirq_entries[pin-16]) {
1065 apic_printk(APIC_VERBOSE, KERN_DEBUG
1066 "disabling PIRQ%d\n", pin-16);
1068 irq = pirq_entries[pin-16];
1069 apic_printk(APIC_VERBOSE, KERN_DEBUG
1070 "using PIRQ%d -> IRQ %d\n",
1081 * Find a specific PCI IRQ entry.
1082 * Not an __init, possibly needed by modules
1084 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1085 struct io_apic_irq_attr *irq_attr)
1087 int apic, i, best_guess = -1;
1089 apic_printk(APIC_DEBUG,
1090 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1092 if (test_bit(bus, mp_bus_not_pci)) {
1093 apic_printk(APIC_VERBOSE,
1094 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1097 for (i = 0; i < mp_irq_entries; i++) {
1098 int lbus = mp_irqs[i].srcbus;
1100 for (apic = 0; apic < nr_ioapics; apic++)
1101 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1102 mp_irqs[i].dstapic == MP_APIC_ALL)
1105 if (!test_bit(lbus, mp_bus_not_pci) &&
1106 !mp_irqs[i].irqtype &&
1108 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1109 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1111 if (!(apic || IO_APIC_IRQ(irq)))
1114 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1115 set_io_apic_irq_attr(irq_attr, apic,
1122 * Use the first all-but-pin matching entry as a
1123 * best-guess fuzzy result for broken mptables.
1125 if (best_guess < 0) {
1126 set_io_apic_irq_attr(irq_attr, apic,
1136 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1138 void lock_vector_lock(void)
1140 /* Used to the online set of cpus does not change
1141 * during assign_irq_vector.
1143 spin_lock(&vector_lock);
1146 void unlock_vector_lock(void)
1148 spin_unlock(&vector_lock);
1152 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1155 * NOTE! The local APIC isn't very good at handling
1156 * multiple interrupts at the same interrupt level.
1157 * As the interrupt level is determined by taking the
1158 * vector number and shifting that right by 4, we
1159 * want to spread these out a bit so that they don't
1160 * all fall in the same interrupt level.
1162 * Also, we've got to be careful not to trash gate
1163 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1165 static int current_vector = FIRST_DEVICE_VECTOR + VECTOR_OFFSET_START;
1166 static int current_offset = VECTOR_OFFSET_START % 8;
1167 unsigned int old_vector;
1169 cpumask_var_t tmp_mask;
1171 if (cfg->move_in_progress)
1174 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1177 old_vector = cfg->vector;
1179 cpumask_and(tmp_mask, mask, cpu_online_mask);
1180 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1181 if (!cpumask_empty(tmp_mask)) {
1182 free_cpumask_var(tmp_mask);
1187 /* Only try and allocate irqs on cpus that are present */
1189 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1193 apic->vector_allocation_domain(cpu, tmp_mask);
1195 vector = current_vector;
1196 offset = current_offset;
1199 if (vector >= first_system_vector) {
1200 /* If out of vectors on large boxen, must share them. */
1201 offset = (offset + 1) % 8;
1202 vector = FIRST_DEVICE_VECTOR + offset;
1204 if (unlikely(current_vector == vector))
1207 if (test_bit(vector, used_vectors))
1210 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1211 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1214 current_vector = vector;
1215 current_offset = offset;
1217 cfg->move_in_progress = 1;
1218 cpumask_copy(cfg->old_domain, cfg->domain);
1220 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1221 per_cpu(vector_irq, new_cpu)[vector] = irq;
1222 cfg->vector = vector;
1223 cpumask_copy(cfg->domain, tmp_mask);
1227 free_cpumask_var(tmp_mask);
1231 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1234 unsigned long flags;
1236 spin_lock_irqsave(&vector_lock, flags);
1237 err = __assign_irq_vector(irq, cfg, mask);
1238 spin_unlock_irqrestore(&vector_lock, flags);
1242 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1246 BUG_ON(!cfg->vector);
1248 vector = cfg->vector;
1249 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1250 per_cpu(vector_irq, cpu)[vector] = -1;
1253 cpumask_clear(cfg->domain);
1255 if (likely(!cfg->move_in_progress))
1257 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1258 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1260 if (per_cpu(vector_irq, cpu)[vector] != irq)
1262 per_cpu(vector_irq, cpu)[vector] = -1;
1266 cfg->move_in_progress = 0;
1269 void __setup_vector_irq(int cpu)
1271 /* Initialize vector_irq on a new cpu */
1272 /* This function must be called with vector_lock held */
1274 struct irq_cfg *cfg;
1275 struct irq_desc *desc;
1277 /* Mark the inuse vectors */
1278 for_each_irq_desc(irq, desc) {
1279 cfg = desc->chip_data;
1280 if (!cpumask_test_cpu(cpu, cfg->domain))
1282 vector = cfg->vector;
1283 per_cpu(vector_irq, cpu)[vector] = irq;
1285 /* Mark the free vectors */
1286 for (vector = 0; vector < NR_VECTORS; ++vector) {
1287 irq = per_cpu(vector_irq, cpu)[vector];
1292 if (!cpumask_test_cpu(cpu, cfg->domain))
1293 per_cpu(vector_irq, cpu)[vector] = -1;
1297 static struct irq_chip ioapic_chip;
1298 static struct irq_chip ir_ioapic_chip;
1300 #define IOAPIC_AUTO -1
1301 #define IOAPIC_EDGE 0
1302 #define IOAPIC_LEVEL 1
1304 #ifdef CONFIG_X86_32
1305 static inline int IO_APIC_irq_trigger(int irq)
1309 for (apic = 0; apic < nr_ioapics; apic++) {
1310 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1311 idx = find_irq_entry(apic, pin, mp_INT);
1312 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1313 return irq_trigger(idx);
1317 * nonexistent IRQs are edge default
1322 static inline int IO_APIC_irq_trigger(int irq)
1328 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1331 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1332 trigger == IOAPIC_LEVEL)
1333 desc->status |= IRQ_LEVEL;
1335 desc->status &= ~IRQ_LEVEL;
1337 if (irq_remapped(irq)) {
1338 desc->status |= IRQ_MOVE_PCNTXT;
1340 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1344 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1345 handle_edge_irq, "edge");
1349 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1350 trigger == IOAPIC_LEVEL)
1351 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1355 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1356 handle_edge_irq, "edge");
1359 int setup_ioapic_entry(int apic_id, int irq,
1360 struct IO_APIC_route_entry *entry,
1361 unsigned int destination, int trigger,
1362 int polarity, int vector, int pin)
1365 * add it to the IO-APIC irq-routing table:
1367 memset(entry,0,sizeof(*entry));
1369 if (intr_remapping_enabled) {
1370 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1372 struct IR_IO_APIC_route_entry *ir_entry =
1373 (struct IR_IO_APIC_route_entry *) entry;
1377 panic("No mapping iommu for ioapic %d\n", apic_id);
1379 index = alloc_irte(iommu, irq, 1);
1381 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1383 memset(&irte, 0, sizeof(irte));
1386 irte.dst_mode = apic->irq_dest_mode;
1388 * Trigger mode in the IRTE will always be edge, and the
1389 * actual level or edge trigger will be setup in the IO-APIC
1390 * RTE. This will help simplify level triggered irq migration.
1391 * For more details, see the comments above explainig IO-APIC
1392 * irq migration in the presence of interrupt-remapping.
1394 irte.trigger_mode = 0;
1395 irte.dlvry_mode = apic->irq_delivery_mode;
1396 irte.vector = vector;
1397 irte.dest_id = IRTE_DEST(destination);
1399 /* Set source-id of interrupt request */
1400 set_ioapic_sid(&irte, apic_id);
1402 modify_irte(irq, &irte);
1404 ir_entry->index2 = (index >> 15) & 0x1;
1406 ir_entry->format = 1;
1407 ir_entry->index = (index & 0x7fff);
1409 * IO-APIC RTE will be configured with virtual vector.
1410 * irq handler will do the explicit EOI to the io-apic.
1412 ir_entry->vector = pin;
1414 entry->delivery_mode = apic->irq_delivery_mode;
1415 entry->dest_mode = apic->irq_dest_mode;
1416 entry->dest = destination;
1417 entry->vector = vector;
1420 entry->mask = 0; /* enable IRQ */
1421 entry->trigger = trigger;
1422 entry->polarity = polarity;
1424 /* Mask level triggered irqs.
1425 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1432 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1433 int trigger, int polarity)
1435 struct irq_cfg *cfg;
1436 struct IO_APIC_route_entry entry;
1439 if (!IO_APIC_IRQ(irq))
1442 cfg = desc->chip_data;
1444 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1447 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1449 apic_printk(APIC_VERBOSE,KERN_DEBUG
1450 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1451 "IRQ %d Mode:%i Active:%i)\n",
1452 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1453 irq, trigger, polarity);
1456 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1457 dest, trigger, polarity, cfg->vector, pin)) {
1458 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1459 mp_ioapics[apic_id].apicid, pin);
1460 __clear_irq_vector(irq, cfg);
1464 ioapic_register_intr(irq, desc, trigger);
1465 if (irq < nr_legacy_irqs)
1466 disable_8259A_irq(irq);
1468 ioapic_write_entry(apic_id, pin, entry);
1472 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1473 } mp_ioapic_routing[MAX_IO_APICS];
1475 static void __init setup_IO_APIC_irqs(void)
1477 int apic_id = 0, pin, idx, irq;
1479 struct irq_desc *desc;
1480 struct irq_cfg *cfg;
1481 int node = cpu_to_node(boot_cpu_id);
1483 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1486 if (!acpi_disabled && acpi_ioapic) {
1487 apic_id = mp_find_ioapic(0);
1493 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1494 idx = find_irq_entry(apic_id, pin, mp_INT);
1498 apic_printk(APIC_VERBOSE,
1499 KERN_DEBUG " %d-%d",
1500 mp_ioapics[apic_id].apicid, pin);
1502 apic_printk(APIC_VERBOSE, " %d-%d",
1503 mp_ioapics[apic_id].apicid, pin);
1507 apic_printk(APIC_VERBOSE,
1508 " (apicid-pin) not connected\n");
1512 irq = pin_2_irq(idx, apic_id, pin);
1515 * Skip the timer IRQ if there's a quirk handler
1516 * installed and if it returns 1:
1518 if (apic->multi_timer_check &&
1519 apic->multi_timer_check(apic_id, irq))
1522 desc = irq_to_desc_alloc_node(irq, node);
1524 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1527 cfg = desc->chip_data;
1528 add_pin_to_irq_node(cfg, node, apic_id, pin);
1530 * don't mark it in pin_programmed, so later acpi could
1531 * set it correctly when irq < 16
1533 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1534 irq_trigger(idx), irq_polarity(idx));
1538 apic_printk(APIC_VERBOSE,
1539 " (apicid-pin) not connected\n");
1543 * Set up the timer pin, possibly with the 8259A-master behind.
1545 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1548 struct IO_APIC_route_entry entry;
1550 if (intr_remapping_enabled)
1553 memset(&entry, 0, sizeof(entry));
1556 * We use logical delivery to get the timer IRQ
1559 entry.dest_mode = apic->irq_dest_mode;
1560 entry.mask = 0; /* don't mask IRQ for edge */
1561 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1562 entry.delivery_mode = apic->irq_delivery_mode;
1565 entry.vector = vector;
1568 * The timer IRQ doesn't have to know that behind the
1569 * scene we may have a 8259A-master in AEOI mode ...
1571 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1574 * Add it to the IO-APIC irq-routing table:
1576 ioapic_write_entry(apic_id, pin, entry);
1580 __apicdebuginit(void) print_IO_APIC(void)
1583 union IO_APIC_reg_00 reg_00;
1584 union IO_APIC_reg_01 reg_01;
1585 union IO_APIC_reg_02 reg_02;
1586 union IO_APIC_reg_03 reg_03;
1587 unsigned long flags;
1588 struct irq_cfg *cfg;
1589 struct irq_desc *desc;
1592 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1593 for (i = 0; i < nr_ioapics; i++)
1594 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1595 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1598 * We are a bit conservative about what we expect. We have to
1599 * know about every hardware change ASAP.
1601 printk(KERN_INFO "testing the IO APIC.......................\n");
1603 for (apic = 0; apic < nr_ioapics; apic++) {
1605 spin_lock_irqsave(&ioapic_lock, flags);
1606 reg_00.raw = io_apic_read(apic, 0);
1607 reg_01.raw = io_apic_read(apic, 1);
1608 if (reg_01.bits.version >= 0x10)
1609 reg_02.raw = io_apic_read(apic, 2);
1610 if (reg_01.bits.version >= 0x20)
1611 reg_03.raw = io_apic_read(apic, 3);
1612 spin_unlock_irqrestore(&ioapic_lock, flags);
1615 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1616 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1617 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1618 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1619 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1621 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1622 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1624 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1625 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1628 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1629 * but the value of reg_02 is read as the previous read register
1630 * value, so ignore it if reg_02 == reg_01.
1632 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1633 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1634 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1638 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1639 * or reg_03, but the value of reg_0[23] is read as the previous read
1640 * register value, so ignore it if reg_03 == reg_0[12].
1642 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1643 reg_03.raw != reg_01.raw) {
1644 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1645 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1648 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1650 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1651 " Stat Dmod Deli Vect: \n");
1653 for (i = 0; i <= reg_01.bits.entries; i++) {
1654 struct IO_APIC_route_entry entry;
1656 entry = ioapic_read_entry(apic, i);
1658 printk(KERN_DEBUG " %02x %03X ",
1663 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1668 entry.delivery_status,
1670 entry.delivery_mode,
1675 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1676 for_each_irq_desc(irq, desc) {
1677 struct irq_pin_list *entry;
1679 cfg = desc->chip_data;
1680 entry = cfg->irq_2_pin;
1683 printk(KERN_DEBUG "IRQ%d ", irq);
1684 for_each_irq_pin(entry, cfg->irq_2_pin)
1685 printk("-> %d:%d", entry->apic, entry->pin);
1689 printk(KERN_INFO ".................................... done.\n");
1694 __apicdebuginit(void) print_APIC_field(int base)
1700 for (i = 0; i < 8; i++)
1701 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1703 printk(KERN_CONT "\n");
1706 __apicdebuginit(void) print_local_APIC(void *dummy)
1708 unsigned int i, v, ver, maxlvt;
1711 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1712 smp_processor_id(), hard_smp_processor_id());
1713 v = apic_read(APIC_ID);
1714 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1715 v = apic_read(APIC_LVR);
1716 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1717 ver = GET_APIC_VERSION(v);
1718 maxlvt = lapic_get_maxlvt();
1720 v = apic_read(APIC_TASKPRI);
1721 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1723 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1724 if (!APIC_XAPIC(ver)) {
1725 v = apic_read(APIC_ARBPRI);
1726 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1727 v & APIC_ARBPRI_MASK);
1729 v = apic_read(APIC_PROCPRI);
1730 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1734 * Remote read supported only in the 82489DX and local APIC for
1735 * Pentium processors.
1737 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1738 v = apic_read(APIC_RRR);
1739 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1742 v = apic_read(APIC_LDR);
1743 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1744 if (!x2apic_enabled()) {
1745 v = apic_read(APIC_DFR);
1746 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1748 v = apic_read(APIC_SPIV);
1749 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1751 printk(KERN_DEBUG "... APIC ISR field:\n");
1752 print_APIC_field(APIC_ISR);
1753 printk(KERN_DEBUG "... APIC TMR field:\n");
1754 print_APIC_field(APIC_TMR);
1755 printk(KERN_DEBUG "... APIC IRR field:\n");
1756 print_APIC_field(APIC_IRR);
1758 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1759 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1760 apic_write(APIC_ESR, 0);
1762 v = apic_read(APIC_ESR);
1763 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1766 icr = apic_icr_read();
1767 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1768 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1770 v = apic_read(APIC_LVTT);
1771 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1773 if (maxlvt > 3) { /* PC is LVT#4. */
1774 v = apic_read(APIC_LVTPC);
1775 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1777 v = apic_read(APIC_LVT0);
1778 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1779 v = apic_read(APIC_LVT1);
1780 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1782 if (maxlvt > 2) { /* ERR is LVT#3. */
1783 v = apic_read(APIC_LVTERR);
1784 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1787 v = apic_read(APIC_TMICT);
1788 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1789 v = apic_read(APIC_TMCCT);
1790 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1791 v = apic_read(APIC_TDCR);
1792 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1794 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1795 v = apic_read(APIC_EFEAT);
1796 maxlvt = (v >> 16) & 0xff;
1797 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1798 v = apic_read(APIC_ECTRL);
1799 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1800 for (i = 0; i < maxlvt; i++) {
1801 v = apic_read(APIC_EILVTn(i));
1802 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1808 __apicdebuginit(void) print_local_APICs(int maxcpu)
1816 for_each_online_cpu(cpu) {
1819 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1824 __apicdebuginit(void) print_PIC(void)
1827 unsigned long flags;
1829 if (!nr_legacy_irqs)
1832 printk(KERN_DEBUG "\nprinting PIC contents\n");
1834 spin_lock_irqsave(&i8259A_lock, flags);
1836 v = inb(0xa1) << 8 | inb(0x21);
1837 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1839 v = inb(0xa0) << 8 | inb(0x20);
1840 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1844 v = inb(0xa0) << 8 | inb(0x20);
1848 spin_unlock_irqrestore(&i8259A_lock, flags);
1850 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1852 v = inb(0x4d1) << 8 | inb(0x4d0);
1853 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1856 static int __initdata show_lapic = 1;
1857 static __init int setup_show_lapic(char *arg)
1861 if (strcmp(arg, "all") == 0) {
1862 show_lapic = CONFIG_NR_CPUS;
1864 get_option(&arg, &num);
1871 __setup("show_lapic=", setup_show_lapic);
1873 __apicdebuginit(int) print_ICs(void)
1875 if (apic_verbosity == APIC_QUIET)
1880 /* don't print out if apic is not there */
1881 if (!cpu_has_apic && !apic_from_smp_config())
1884 print_local_APICs(show_lapic);
1890 fs_initcall(print_ICs);
1893 /* Where if anywhere is the i8259 connect in external int mode */
1894 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1896 void __init enable_IO_APIC(void)
1898 union IO_APIC_reg_01 reg_01;
1899 int i8259_apic, i8259_pin;
1901 unsigned long flags;
1904 * The number of IO-APIC IRQ registers (== #pins):
1906 for (apic = 0; apic < nr_ioapics; apic++) {
1907 spin_lock_irqsave(&ioapic_lock, flags);
1908 reg_01.raw = io_apic_read(apic, 1);
1909 spin_unlock_irqrestore(&ioapic_lock, flags);
1910 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1913 if (!nr_legacy_irqs)
1916 for(apic = 0; apic < nr_ioapics; apic++) {
1918 /* See if any of the pins is in ExtINT mode */
1919 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1920 struct IO_APIC_route_entry entry;
1921 entry = ioapic_read_entry(apic, pin);
1923 /* If the interrupt line is enabled and in ExtInt mode
1924 * I have found the pin where the i8259 is connected.
1926 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1927 ioapic_i8259.apic = apic;
1928 ioapic_i8259.pin = pin;
1934 /* Look to see what if the MP table has reported the ExtINT */
1935 /* If we could not find the appropriate pin by looking at the ioapic
1936 * the i8259 probably is not connected the ioapic but give the
1937 * mptable a chance anyway.
1939 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1940 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1941 /* Trust the MP table if nothing is setup in the hardware */
1942 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1943 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1944 ioapic_i8259.pin = i8259_pin;
1945 ioapic_i8259.apic = i8259_apic;
1947 /* Complain if the MP table and the hardware disagree */
1948 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1949 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1951 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1955 * Do not trust the IO-APIC being empty at bootup
1961 * Not an __init, needed by the reboot code
1963 void disable_IO_APIC(void)
1966 * Clear the IO-APIC before rebooting:
1970 if (!nr_legacy_irqs)
1974 * If the i8259 is routed through an IOAPIC
1975 * Put that IOAPIC in virtual wire mode
1976 * so legacy interrupts can be delivered.
1978 * With interrupt-remapping, for now we will use virtual wire A mode,
1979 * as virtual wire B is little complex (need to configure both
1980 * IOAPIC RTE aswell as interrupt-remapping table entry).
1981 * As this gets called during crash dump, keep this simple for now.
1983 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1984 struct IO_APIC_route_entry entry;
1986 memset(&entry, 0, sizeof(entry));
1987 entry.mask = 0; /* Enabled */
1988 entry.trigger = 0; /* Edge */
1990 entry.polarity = 0; /* High */
1991 entry.delivery_status = 0;
1992 entry.dest_mode = 0; /* Physical */
1993 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1995 entry.dest = read_apic_id();
1998 * Add it to the IO-APIC irq-routing table:
2000 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2004 * Use virtual wire A mode when interrupt remapping is enabled.
2006 if (cpu_has_apic || apic_from_smp_config())
2007 disconnect_bsp_APIC(!intr_remapping_enabled &&
2008 ioapic_i8259.pin != -1);
2011 #ifdef CONFIG_X86_32
2013 * function to set the IO-APIC physical IDs based on the
2014 * values stored in the MPC table.
2016 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2019 void __init setup_ioapic_ids_from_mpc(void)
2021 union IO_APIC_reg_00 reg_00;
2022 physid_mask_t phys_id_present_map;
2025 unsigned char old_id;
2026 unsigned long flags;
2031 * Don't check I/O APIC IDs for xAPIC systems. They have
2032 * no meaning without the serial APIC bus.
2034 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2035 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2038 * This is broken; anything with a real cpu count has to
2039 * circumvent this idiocy regardless.
2041 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2044 * Set the IOAPIC ID to the value stored in the MPC table.
2046 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2048 /* Read the register 0 value */
2049 spin_lock_irqsave(&ioapic_lock, flags);
2050 reg_00.raw = io_apic_read(apic_id, 0);
2051 spin_unlock_irqrestore(&ioapic_lock, flags);
2053 old_id = mp_ioapics[apic_id].apicid;
2055 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2056 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2057 apic_id, mp_ioapics[apic_id].apicid);
2058 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2060 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2064 * Sanity check, is the ID really free? Every APIC in a
2065 * system must have a unique ID or we get lots of nice
2066 * 'stuck on smp_invalidate_needed IPI wait' messages.
2068 if (apic->check_apicid_used(&phys_id_present_map,
2069 mp_ioapics[apic_id].apicid)) {
2070 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2071 apic_id, mp_ioapics[apic_id].apicid);
2072 for (i = 0; i < get_physical_broadcast(); i++)
2073 if (!physid_isset(i, phys_id_present_map))
2075 if (i >= get_physical_broadcast())
2076 panic("Max APIC ID exceeded!\n");
2077 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2079 physid_set(i, phys_id_present_map);
2080 mp_ioapics[apic_id].apicid = i;
2083 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2084 apic_printk(APIC_VERBOSE, "Setting %d in the "
2085 "phys_id_present_map\n",
2086 mp_ioapics[apic_id].apicid);
2087 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2092 * We need to adjust the IRQ routing table
2093 * if the ID changed.
2095 if (old_id != mp_ioapics[apic_id].apicid)
2096 for (i = 0; i < mp_irq_entries; i++)
2097 if (mp_irqs[i].dstapic == old_id)
2099 = mp_ioapics[apic_id].apicid;
2102 * Read the right value from the MPC table and
2103 * write it into the ID register.
2105 apic_printk(APIC_VERBOSE, KERN_INFO
2106 "...changing IO-APIC physical APIC ID to %d ...",
2107 mp_ioapics[apic_id].apicid);
2109 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2110 spin_lock_irqsave(&ioapic_lock, flags);
2111 io_apic_write(apic_id, 0, reg_00.raw);
2112 spin_unlock_irqrestore(&ioapic_lock, flags);
2117 spin_lock_irqsave(&ioapic_lock, flags);
2118 reg_00.raw = io_apic_read(apic_id, 0);
2119 spin_unlock_irqrestore(&ioapic_lock, flags);
2120 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2121 printk("could not set ID!\n");
2123 apic_printk(APIC_VERBOSE, " ok.\n");
2128 int no_timer_check __initdata;
2130 static int __init notimercheck(char *s)
2135 __setup("no_timer_check", notimercheck);
2138 * There is a nasty bug in some older SMP boards, their mptable lies
2139 * about the timer IRQ. We do the following to work around the situation:
2141 * - timer IRQ defaults to IO-APIC IRQ
2142 * - if this function detects that timer IRQs are defunct, then we fall
2143 * back to ISA timer IRQs
2145 static int __init timer_irq_works(void)
2147 unsigned long t1 = jiffies;
2148 unsigned long flags;
2153 local_save_flags(flags);
2155 /* Let ten ticks pass... */
2156 mdelay((10 * 1000) / HZ);
2157 local_irq_restore(flags);
2160 * Expect a few ticks at least, to be sure some possible
2161 * glue logic does not lock up after one or two first
2162 * ticks in a non-ExtINT mode. Also the local APIC
2163 * might have cached one ExtINT interrupt. Finally, at
2164 * least one tick may be lost due to delays.
2168 if (time_after(jiffies, t1 + 4))
2174 * In the SMP+IOAPIC case it might happen that there are an unspecified
2175 * number of pending IRQ events unhandled. These cases are very rare,
2176 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2177 * better to do it this way as thus we do not have to be aware of
2178 * 'pending' interrupts in the IRQ path, except at this point.
2181 * Edge triggered needs to resend any interrupt
2182 * that was delayed but this is now handled in the device
2187 * Starting up a edge-triggered IO-APIC interrupt is
2188 * nasty - we need to make sure that we get the edge.
2189 * If it is already asserted for some reason, we need
2190 * return 1 to indicate that is was pending.
2192 * This is not complete - we should be able to fake
2193 * an edge even if it isn't on the 8259A...
2196 static unsigned int startup_ioapic_irq(unsigned int irq)
2198 int was_pending = 0;
2199 unsigned long flags;
2200 struct irq_cfg *cfg;
2202 spin_lock_irqsave(&ioapic_lock, flags);
2203 if (irq < nr_legacy_irqs) {
2204 disable_8259A_irq(irq);
2205 if (i8259A_irq_pending(irq))
2209 __unmask_IO_APIC_irq(cfg);
2210 spin_unlock_irqrestore(&ioapic_lock, flags);
2215 static int ioapic_retrigger_irq(unsigned int irq)
2218 struct irq_cfg *cfg = irq_cfg(irq);
2219 unsigned long flags;
2221 spin_lock_irqsave(&vector_lock, flags);
2222 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2223 spin_unlock_irqrestore(&vector_lock, flags);
2229 * Level and edge triggered IO-APIC interrupts need different handling,
2230 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2231 * handled with the level-triggered descriptor, but that one has slightly
2232 * more overhead. Level-triggered interrupts cannot be handled with the
2233 * edge-triggered handler, without risking IRQ storms and other ugly
2238 void send_cleanup_vector(struct irq_cfg *cfg)
2240 cpumask_var_t cleanup_mask;
2242 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2244 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2245 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2247 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2248 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2249 free_cpumask_var(cleanup_mask);
2251 cfg->move_in_progress = 0;
2254 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2257 struct irq_pin_list *entry;
2258 u8 vector = cfg->vector;
2260 for_each_irq_pin(entry, cfg->irq_2_pin) {
2266 * With interrupt-remapping, destination information comes
2267 * from interrupt-remapping table entry.
2269 if (!irq_remapped(irq))
2270 io_apic_write(apic, 0x11 + pin*2, dest);
2271 reg = io_apic_read(apic, 0x10 + pin*2);
2272 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2274 io_apic_modify(apic, 0x10 + pin*2, reg);
2279 * Either sets desc->affinity to a valid value, and returns
2280 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2281 * leaves desc->affinity untouched.
2284 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2285 unsigned int *dest_id)
2287 struct irq_cfg *cfg;
2290 if (!cpumask_intersects(mask, cpu_online_mask))
2294 cfg = desc->chip_data;
2295 if (assign_irq_vector(irq, cfg, mask))
2298 cpumask_copy(desc->affinity, mask);
2300 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2305 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2307 struct irq_cfg *cfg;
2308 unsigned long flags;
2314 cfg = desc->chip_data;
2316 spin_lock_irqsave(&ioapic_lock, flags);
2317 ret = set_desc_affinity(desc, mask, &dest);
2319 /* Only the high 8 bits are valid. */
2320 dest = SET_APIC_LOGICAL_ID(dest);
2321 __target_IO_APIC_irq(irq, dest, cfg);
2323 spin_unlock_irqrestore(&ioapic_lock, flags);
2329 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2331 struct irq_desc *desc;
2333 desc = irq_to_desc(irq);
2335 return set_ioapic_affinity_irq_desc(desc, mask);
2338 #ifdef CONFIG_INTR_REMAP
2341 * Migrate the IO-APIC irq in the presence of intr-remapping.
2343 * For both level and edge triggered, irq migration is a simple atomic
2344 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2346 * For level triggered, we eliminate the io-apic RTE modification (with the
2347 * updated vector information), by using a virtual vector (io-apic pin number).
2348 * Real vector that is used for interrupting cpu will be coming from
2349 * the interrupt-remapping table entry.
2352 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2354 struct irq_cfg *cfg;
2360 if (!cpumask_intersects(mask, cpu_online_mask))
2364 if (get_irte(irq, &irte))
2367 cfg = desc->chip_data;
2368 if (assign_irq_vector(irq, cfg, mask))
2371 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2373 irte.vector = cfg->vector;
2374 irte.dest_id = IRTE_DEST(dest);
2377 * Modified the IRTE and flushes the Interrupt entry cache.
2379 modify_irte(irq, &irte);
2381 if (cfg->move_in_progress)
2382 send_cleanup_vector(cfg);
2384 cpumask_copy(desc->affinity, mask);
2390 * Migrates the IRQ destination in the process context.
2392 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2393 const struct cpumask *mask)
2395 return migrate_ioapic_irq_desc(desc, mask);
2397 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2398 const struct cpumask *mask)
2400 struct irq_desc *desc = irq_to_desc(irq);
2402 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2405 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2406 const struct cpumask *mask)
2412 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2414 unsigned vector, me;
2420 me = smp_processor_id();
2421 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2424 struct irq_desc *desc;
2425 struct irq_cfg *cfg;
2426 irq = __get_cpu_var(vector_irq)[vector];
2431 desc = irq_to_desc(irq);
2436 raw_spin_lock(&desc->lock);
2438 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2441 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2443 * Check if the vector that needs to be cleanedup is
2444 * registered at the cpu's IRR. If so, then this is not
2445 * the best time to clean it up. Lets clean it up in the
2446 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2449 if (irr & (1 << (vector % 32))) {
2450 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2453 __get_cpu_var(vector_irq)[vector] = -1;
2455 raw_spin_unlock(&desc->lock);
2461 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2463 struct irq_desc *desc = *descp;
2464 struct irq_cfg *cfg = desc->chip_data;
2467 if (likely(!cfg->move_in_progress))
2470 me = smp_processor_id();
2472 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2473 send_cleanup_vector(cfg);
2476 static void irq_complete_move(struct irq_desc **descp)
2478 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2481 void irq_force_complete_move(int irq)
2483 struct irq_desc *desc = irq_to_desc(irq);
2484 struct irq_cfg *cfg = desc->chip_data;
2486 __irq_complete_move(&desc, cfg->vector);
2489 static inline void irq_complete_move(struct irq_desc **descp) {}
2492 static void ack_apic_edge(unsigned int irq)
2494 struct irq_desc *desc = irq_to_desc(irq);
2496 irq_complete_move(&desc);
2497 move_native_irq(irq);
2501 atomic_t irq_mis_count;
2504 * IO-APIC versions below 0x20 don't support EOI register.
2505 * For the record, here is the information about various versions:
2507 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2508 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2511 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2512 * version as 0x2. This is an error with documentation and these ICH chips
2513 * use io-apic's of version 0x20.
2515 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2516 * Otherwise, we simulate the EOI message manually by changing the trigger
2517 * mode to edge and then back to level, with RTE being masked during this.
2519 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2521 struct irq_pin_list *entry;
2523 for_each_irq_pin(entry, cfg->irq_2_pin) {
2524 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2526 * Intr-remapping uses pin number as the virtual vector
2527 * in the RTE. Actual vector is programmed in
2528 * intr-remapping table entry. Hence for the io-apic
2529 * EOI we use the pin number.
2531 if (irq_remapped(irq))
2532 io_apic_eoi(entry->apic, entry->pin);
2534 io_apic_eoi(entry->apic, cfg->vector);
2536 __mask_and_edge_IO_APIC_irq(entry);
2537 __unmask_and_level_IO_APIC_irq(entry);
2542 static void eoi_ioapic_irq(struct irq_desc *desc)
2544 struct irq_cfg *cfg;
2545 unsigned long flags;
2549 cfg = desc->chip_data;
2551 spin_lock_irqsave(&ioapic_lock, flags);
2552 __eoi_ioapic_irq(irq, cfg);
2553 spin_unlock_irqrestore(&ioapic_lock, flags);
2556 static void ack_apic_level(unsigned int irq)
2558 struct irq_desc *desc = irq_to_desc(irq);
2561 struct irq_cfg *cfg;
2562 int do_unmask_irq = 0;
2564 irq_complete_move(&desc);
2565 #ifdef CONFIG_GENERIC_PENDING_IRQ
2566 /* If we are moving the irq we need to mask it */
2567 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2569 mask_IO_APIC_irq_desc(desc);
2574 * It appears there is an erratum which affects at least version 0x11
2575 * of I/O APIC (that's the 82093AA and cores integrated into various
2576 * chipsets). Under certain conditions a level-triggered interrupt is
2577 * erroneously delivered as edge-triggered one but the respective IRR
2578 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2579 * message but it will never arrive and further interrupts are blocked
2580 * from the source. The exact reason is so far unknown, but the
2581 * phenomenon was observed when two consecutive interrupt requests
2582 * from a given source get delivered to the same CPU and the source is
2583 * temporarily disabled in between.
2585 * A workaround is to simulate an EOI message manually. We achieve it
2586 * by setting the trigger mode to edge and then to level when the edge
2587 * trigger mode gets detected in the TMR of a local APIC for a
2588 * level-triggered interrupt. We mask the source for the time of the
2589 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2590 * The idea is from Manfred Spraul. --macro
2592 * Also in the case when cpu goes offline, fixup_irqs() will forward
2593 * any unhandled interrupt on the offlined cpu to the new cpu
2594 * destination that is handling the corresponding interrupt. This
2595 * interrupt forwarding is done via IPI's. Hence, in this case also
2596 * level-triggered io-apic interrupt will be seen as an edge
2597 * interrupt in the IRR. And we can't rely on the cpu's EOI
2598 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2599 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2600 * supporting EOI register, we do an explicit EOI to clear the
2601 * remote IRR and on IO-APIC's which don't have an EOI register,
2602 * we use the above logic (mask+edge followed by unmask+level) from
2603 * Manfred Spraul to clear the remote IRR.
2605 cfg = desc->chip_data;
2607 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2610 * We must acknowledge the irq before we move it or the acknowledge will
2611 * not propagate properly.
2616 * Tail end of clearing remote IRR bit (either by delivering the EOI
2617 * message via io-apic EOI register write or simulating it using
2618 * mask+edge followed by unnask+level logic) manually when the
2619 * level triggered interrupt is seen as the edge triggered interrupt
2622 if (!(v & (1 << (i & 0x1f)))) {
2623 atomic_inc(&irq_mis_count);
2625 eoi_ioapic_irq(desc);
2628 /* Now we can move and renable the irq */
2629 if (unlikely(do_unmask_irq)) {
2630 /* Only migrate the irq if the ack has been received.
2632 * On rare occasions the broadcast level triggered ack gets
2633 * delayed going to ioapics, and if we reprogram the
2634 * vector while Remote IRR is still set the irq will never
2637 * To prevent this scenario we read the Remote IRR bit
2638 * of the ioapic. This has two effects.
2639 * - On any sane system the read of the ioapic will
2640 * flush writes (and acks) going to the ioapic from
2642 * - We get to see if the ACK has actually been delivered.
2644 * Based on failed experiments of reprogramming the
2645 * ioapic entry from outside of irq context starting
2646 * with masking the ioapic entry and then polling until
2647 * Remote IRR was clear before reprogramming the
2648 * ioapic I don't trust the Remote IRR bit to be
2649 * completey accurate.
2651 * However there appears to be no other way to plug
2652 * this race, so if the Remote IRR bit is not
2653 * accurate and is causing problems then it is a hardware bug
2654 * and you can go talk to the chipset vendor about it.
2656 cfg = desc->chip_data;
2657 if (!io_apic_level_ack_pending(cfg))
2658 move_masked_irq(irq);
2659 unmask_IO_APIC_irq_desc(desc);
2663 #ifdef CONFIG_INTR_REMAP
2664 static void ir_ack_apic_edge(unsigned int irq)
2669 static void ir_ack_apic_level(unsigned int irq)
2671 struct irq_desc *desc = irq_to_desc(irq);
2674 eoi_ioapic_irq(desc);
2676 #endif /* CONFIG_INTR_REMAP */
2678 static struct irq_chip ioapic_chip __read_mostly = {
2680 .startup = startup_ioapic_irq,
2681 .mask = mask_IO_APIC_irq,
2682 .unmask = unmask_IO_APIC_irq,
2683 .ack = ack_apic_edge,
2684 .eoi = ack_apic_level,
2686 .set_affinity = set_ioapic_affinity_irq,
2688 .retrigger = ioapic_retrigger_irq,
2691 static struct irq_chip ir_ioapic_chip __read_mostly = {
2692 .name = "IR-IO-APIC",
2693 .startup = startup_ioapic_irq,
2694 .mask = mask_IO_APIC_irq,
2695 .unmask = unmask_IO_APIC_irq,
2696 #ifdef CONFIG_INTR_REMAP
2697 .ack = ir_ack_apic_edge,
2698 .eoi = ir_ack_apic_level,
2700 .set_affinity = set_ir_ioapic_affinity_irq,
2703 .retrigger = ioapic_retrigger_irq,
2706 static inline void init_IO_APIC_traps(void)
2709 struct irq_desc *desc;
2710 struct irq_cfg *cfg;
2713 * NOTE! The local APIC isn't very good at handling
2714 * multiple interrupts at the same interrupt level.
2715 * As the interrupt level is determined by taking the
2716 * vector number and shifting that right by 4, we
2717 * want to spread these out a bit so that they don't
2718 * all fall in the same interrupt level.
2720 * Also, we've got to be careful not to trash gate
2721 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2723 for_each_irq_desc(irq, desc) {
2724 cfg = desc->chip_data;
2725 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2727 * Hmm.. We don't have an entry for this,
2728 * so default to an old-fashioned 8259
2729 * interrupt if we can..
2731 if (irq < nr_legacy_irqs)
2732 make_8259A_irq(irq);
2734 /* Strange. Oh, well.. */
2735 desc->chip = &no_irq_chip;
2741 * The local APIC irq-chip implementation:
2744 static void mask_lapic_irq(unsigned int irq)
2748 v = apic_read(APIC_LVT0);
2749 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2752 static void unmask_lapic_irq(unsigned int irq)
2756 v = apic_read(APIC_LVT0);
2757 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2760 static void ack_lapic_irq(unsigned int irq)
2765 static struct irq_chip lapic_chip __read_mostly = {
2766 .name = "local-APIC",
2767 .mask = mask_lapic_irq,
2768 .unmask = unmask_lapic_irq,
2769 .ack = ack_lapic_irq,
2772 static void lapic_register_intr(int irq, struct irq_desc *desc)
2774 desc->status &= ~IRQ_LEVEL;
2775 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2779 static void __init setup_nmi(void)
2782 * Dirty trick to enable the NMI watchdog ...
2783 * We put the 8259A master into AEOI mode and
2784 * unmask on all local APICs LVT0 as NMI.
2786 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2787 * is from Maciej W. Rozycki - so we do not have to EOI from
2788 * the NMI handler or the timer interrupt.
2790 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2792 enable_NMI_through_LVT0();
2794 apic_printk(APIC_VERBOSE, " done.\n");
2798 * This looks a bit hackish but it's about the only one way of sending
2799 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2800 * not support the ExtINT mode, unfortunately. We need to send these
2801 * cycles as some i82489DX-based boards have glue logic that keeps the
2802 * 8259A interrupt line asserted until INTA. --macro
2804 static inline void __init unlock_ExtINT_logic(void)
2807 struct IO_APIC_route_entry entry0, entry1;
2808 unsigned char save_control, save_freq_select;
2810 pin = find_isa_irq_pin(8, mp_INT);
2815 apic = find_isa_irq_apic(8, mp_INT);
2821 entry0 = ioapic_read_entry(apic, pin);
2822 clear_IO_APIC_pin(apic, pin);
2824 memset(&entry1, 0, sizeof(entry1));
2826 entry1.dest_mode = 0; /* physical delivery */
2827 entry1.mask = 0; /* unmask IRQ now */
2828 entry1.dest = hard_smp_processor_id();
2829 entry1.delivery_mode = dest_ExtINT;
2830 entry1.polarity = entry0.polarity;
2834 ioapic_write_entry(apic, pin, entry1);
2836 save_control = CMOS_READ(RTC_CONTROL);
2837 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2838 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2840 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2845 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2849 CMOS_WRITE(save_control, RTC_CONTROL);
2850 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2851 clear_IO_APIC_pin(apic, pin);
2853 ioapic_write_entry(apic, pin, entry0);
2856 static int disable_timer_pin_1 __initdata;
2857 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2858 static int __init disable_timer_pin_setup(char *arg)
2860 disable_timer_pin_1 = 1;
2863 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2865 int timer_through_8259 __initdata;
2868 * This code may look a bit paranoid, but it's supposed to cooperate with
2869 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2870 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2871 * fanatically on his truly buggy board.
2873 * FIXME: really need to revamp this for all platforms.
2875 static inline void __init check_timer(void)
2877 struct irq_desc *desc = irq_to_desc(0);
2878 struct irq_cfg *cfg = desc->chip_data;
2879 int node = cpu_to_node(boot_cpu_id);
2880 int apic1, pin1, apic2, pin2;
2881 unsigned long flags;
2884 local_irq_save(flags);
2887 * get/set the timer IRQ vector:
2889 disable_8259A_irq(0);
2890 assign_irq_vector(0, cfg, apic->target_cpus());
2893 * As IRQ0 is to be enabled in the 8259A, the virtual
2894 * wire has to be disabled in the local APIC. Also
2895 * timer interrupts need to be acknowledged manually in
2896 * the 8259A for the i82489DX when using the NMI
2897 * watchdog as that APIC treats NMIs as level-triggered.
2898 * The AEOI mode will finish them in the 8259A
2901 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2903 #ifdef CONFIG_X86_32
2907 ver = apic_read(APIC_LVR);
2908 ver = GET_APIC_VERSION(ver);
2909 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2913 pin1 = find_isa_irq_pin(0, mp_INT);
2914 apic1 = find_isa_irq_apic(0, mp_INT);
2915 pin2 = ioapic_i8259.pin;
2916 apic2 = ioapic_i8259.apic;
2918 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2919 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2920 cfg->vector, apic1, pin1, apic2, pin2);
2923 * Some BIOS writers are clueless and report the ExtINTA
2924 * I/O APIC input from the cascaded 8259A as the timer
2925 * interrupt input. So just in case, if only one pin
2926 * was found above, try it both directly and through the
2930 if (intr_remapping_enabled)
2931 panic("BIOS bug: timer not connected to IO-APIC");
2935 } else if (pin2 == -1) {
2942 * Ok, does IRQ0 through the IOAPIC work?
2945 add_pin_to_irq_node(cfg, node, apic1, pin1);
2946 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2948 /* for edge trigger, setup_IO_APIC_irq already
2949 * leave it unmasked.
2950 * so only need to unmask if it is level-trigger
2951 * do we really have level trigger timer?
2954 idx = find_irq_entry(apic1, pin1, mp_INT);
2955 if (idx != -1 && irq_trigger(idx))
2956 unmask_IO_APIC_irq_desc(desc);
2958 if (timer_irq_works()) {
2959 if (nmi_watchdog == NMI_IO_APIC) {
2961 enable_8259A_irq(0);
2963 if (disable_timer_pin_1 > 0)
2964 clear_IO_APIC_pin(0, pin1);
2967 if (intr_remapping_enabled)
2968 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2969 local_irq_disable();
2970 clear_IO_APIC_pin(apic1, pin1);
2972 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2973 "8254 timer not connected to IO-APIC\n");
2975 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2976 "(IRQ0) through the 8259A ...\n");
2977 apic_printk(APIC_QUIET, KERN_INFO
2978 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2980 * legacy devices should be connected to IO APIC #0
2982 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2983 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2984 enable_8259A_irq(0);
2985 if (timer_irq_works()) {
2986 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2987 timer_through_8259 = 1;
2988 if (nmi_watchdog == NMI_IO_APIC) {
2989 disable_8259A_irq(0);
2991 enable_8259A_irq(0);
2996 * Cleanup, just in case ...
2998 local_irq_disable();
2999 disable_8259A_irq(0);
3000 clear_IO_APIC_pin(apic2, pin2);
3001 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3004 if (nmi_watchdog == NMI_IO_APIC) {
3005 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3006 "through the IO-APIC - disabling NMI Watchdog!\n");
3007 nmi_watchdog = NMI_NONE;
3009 #ifdef CONFIG_X86_32
3013 apic_printk(APIC_QUIET, KERN_INFO
3014 "...trying to set up timer as Virtual Wire IRQ...\n");
3016 lapic_register_intr(0, desc);
3017 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3018 enable_8259A_irq(0);
3020 if (timer_irq_works()) {
3021 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3024 local_irq_disable();
3025 disable_8259A_irq(0);
3026 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3027 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3029 apic_printk(APIC_QUIET, KERN_INFO
3030 "...trying to set up timer as ExtINT IRQ...\n");
3034 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3036 unlock_ExtINT_logic();
3038 if (timer_irq_works()) {
3039 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3042 local_irq_disable();
3043 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3044 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3045 "report. Then try booting with the 'noapic' option.\n");
3047 local_irq_restore(flags);
3051 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3052 * to devices. However there may be an I/O APIC pin available for
3053 * this interrupt regardless. The pin may be left unconnected, but
3054 * typically it will be reused as an ExtINT cascade interrupt for
3055 * the master 8259A. In the MPS case such a pin will normally be
3056 * reported as an ExtINT interrupt in the MP table. With ACPI
3057 * there is no provision for ExtINT interrupts, and in the absence
3058 * of an override it would be treated as an ordinary ISA I/O APIC
3059 * interrupt, that is edge-triggered and unmasked by default. We
3060 * used to do this, but it caused problems on some systems because
3061 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3062 * the same ExtINT cascade interrupt to drive the local APIC of the
3063 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3064 * the I/O APIC in all cases now. No actual device should request
3065 * it anyway. --macro
3067 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3069 void __init setup_IO_APIC(void)
3073 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3075 io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3077 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3079 * Set up IO-APIC IRQ routing.
3081 x86_init.mpparse.setup_ioapic_ids();
3084 setup_IO_APIC_irqs();
3085 init_IO_APIC_traps();
3091 * Called after all the initialization is done. If we didnt find any
3092 * APIC bugs then we can allow the modify fast path
3095 static int __init io_apic_bug_finalize(void)
3097 if (sis_apic_bug == -1)
3102 late_initcall(io_apic_bug_finalize);
3104 struct sysfs_ioapic_data {
3105 struct sys_device dev;
3106 struct IO_APIC_route_entry entry[0];
3108 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3110 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3112 struct IO_APIC_route_entry *entry;
3113 struct sysfs_ioapic_data *data;
3116 data = container_of(dev, struct sysfs_ioapic_data, dev);
3117 entry = data->entry;
3118 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3119 *entry = ioapic_read_entry(dev->id, i);
3124 static int ioapic_resume(struct sys_device *dev)
3126 struct IO_APIC_route_entry *entry;
3127 struct sysfs_ioapic_data *data;
3128 unsigned long flags;
3129 union IO_APIC_reg_00 reg_00;
3132 data = container_of(dev, struct sysfs_ioapic_data, dev);
3133 entry = data->entry;
3135 spin_lock_irqsave(&ioapic_lock, flags);
3136 reg_00.raw = io_apic_read(dev->id, 0);
3137 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3138 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3139 io_apic_write(dev->id, 0, reg_00.raw);
3141 spin_unlock_irqrestore(&ioapic_lock, flags);
3142 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3143 ioapic_write_entry(dev->id, i, entry[i]);
3148 static struct sysdev_class ioapic_sysdev_class = {
3150 .suspend = ioapic_suspend,
3151 .resume = ioapic_resume,
3154 static int __init ioapic_init_sysfs(void)
3156 struct sys_device * dev;
3159 error = sysdev_class_register(&ioapic_sysdev_class);
3163 for (i = 0; i < nr_ioapics; i++ ) {
3164 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3165 * sizeof(struct IO_APIC_route_entry);
3166 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3167 if (!mp_ioapic_data[i]) {
3168 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3171 dev = &mp_ioapic_data[i]->dev;
3173 dev->cls = &ioapic_sysdev_class;
3174 error = sysdev_register(dev);
3176 kfree(mp_ioapic_data[i]);
3177 mp_ioapic_data[i] = NULL;
3178 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3186 device_initcall(ioapic_init_sysfs);
3189 * Dynamic irq allocate and deallocation
3191 unsigned int create_irq_nr(unsigned int irq_want, int node)
3193 /* Allocate an unused irq */
3196 unsigned long flags;
3197 struct irq_cfg *cfg_new = NULL;
3198 struct irq_desc *desc_new = NULL;
3201 if (irq_want < nr_irqs_gsi)
3202 irq_want = nr_irqs_gsi;
3204 spin_lock_irqsave(&vector_lock, flags);
3205 for (new = irq_want; new < nr_irqs; new++) {
3206 desc_new = irq_to_desc_alloc_node(new, node);
3208 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3211 cfg_new = desc_new->chip_data;
3213 if (cfg_new->vector != 0)
3216 desc_new = move_irq_desc(desc_new, node);
3217 cfg_new = desc_new->chip_data;
3219 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3223 spin_unlock_irqrestore(&vector_lock, flags);
3226 dynamic_irq_init(irq);
3227 /* restore it, in case dynamic_irq_init clear it */
3229 desc_new->chip_data = cfg_new;
3234 int create_irq(void)
3236 int node = cpu_to_node(boot_cpu_id);
3237 unsigned int irq_want;
3240 irq_want = nr_irqs_gsi;
3241 irq = create_irq_nr(irq_want, node);
3249 void destroy_irq(unsigned int irq)
3251 unsigned long flags;
3252 struct irq_cfg *cfg;
3253 struct irq_desc *desc;
3255 /* store it, in case dynamic_irq_cleanup clear it */
3256 desc = irq_to_desc(irq);
3257 cfg = desc->chip_data;
3258 dynamic_irq_cleanup(irq);
3259 /* connect back irq_cfg */
3260 desc->chip_data = cfg;
3263 spin_lock_irqsave(&vector_lock, flags);
3264 __clear_irq_vector(irq, cfg);
3265 spin_unlock_irqrestore(&vector_lock, flags);
3269 * MSI message composition
3271 #ifdef CONFIG_PCI_MSI
3272 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3273 struct msi_msg *msg, u8 hpet_id)
3275 struct irq_cfg *cfg;
3283 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3287 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3289 if (irq_remapped(irq)) {
3294 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3295 BUG_ON(ir_index == -1);
3297 memset (&irte, 0, sizeof(irte));
3300 irte.dst_mode = apic->irq_dest_mode;
3301 irte.trigger_mode = 0; /* edge */
3302 irte.dlvry_mode = apic->irq_delivery_mode;
3303 irte.vector = cfg->vector;
3304 irte.dest_id = IRTE_DEST(dest);
3306 /* Set source-id of interrupt request */
3308 set_msi_sid(&irte, pdev);
3310 set_hpet_sid(&irte, hpet_id);
3312 modify_irte(irq, &irte);
3314 msg->address_hi = MSI_ADDR_BASE_HI;
3315 msg->data = sub_handle;
3316 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3318 MSI_ADDR_IR_INDEX1(ir_index) |
3319 MSI_ADDR_IR_INDEX2(ir_index);
3321 if (x2apic_enabled())
3322 msg->address_hi = MSI_ADDR_BASE_HI |
3323 MSI_ADDR_EXT_DEST_ID(dest);
3325 msg->address_hi = MSI_ADDR_BASE_HI;
3329 ((apic->irq_dest_mode == 0) ?
3330 MSI_ADDR_DEST_MODE_PHYSICAL:
3331 MSI_ADDR_DEST_MODE_LOGICAL) |
3332 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3333 MSI_ADDR_REDIRECTION_CPU:
3334 MSI_ADDR_REDIRECTION_LOWPRI) |
3335 MSI_ADDR_DEST_ID(dest);
3338 MSI_DATA_TRIGGER_EDGE |
3339 MSI_DATA_LEVEL_ASSERT |
3340 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3341 MSI_DATA_DELIVERY_FIXED:
3342 MSI_DATA_DELIVERY_LOWPRI) |
3343 MSI_DATA_VECTOR(cfg->vector);
3349 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3351 struct irq_desc *desc = irq_to_desc(irq);
3352 struct irq_cfg *cfg;
3356 if (set_desc_affinity(desc, mask, &dest))
3359 cfg = desc->chip_data;
3361 read_msi_msg_desc(desc, &msg);
3363 msg.data &= ~MSI_DATA_VECTOR_MASK;
3364 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3365 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3366 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3368 write_msi_msg_desc(desc, &msg);
3372 #ifdef CONFIG_INTR_REMAP
3374 * Migrate the MSI irq to another cpumask. This migration is
3375 * done in the process context using interrupt-remapping hardware.
3378 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3380 struct irq_desc *desc = irq_to_desc(irq);
3381 struct irq_cfg *cfg = desc->chip_data;
3385 if (get_irte(irq, &irte))
3388 if (set_desc_affinity(desc, mask, &dest))
3391 irte.vector = cfg->vector;
3392 irte.dest_id = IRTE_DEST(dest);
3395 * atomically update the IRTE with the new destination and vector.
3397 modify_irte(irq, &irte);
3400 * After this point, all the interrupts will start arriving
3401 * at the new destination. So, time to cleanup the previous
3402 * vector allocation.
3404 if (cfg->move_in_progress)
3405 send_cleanup_vector(cfg);
3411 #endif /* CONFIG_SMP */
3414 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3415 * which implement the MSI or MSI-X Capability Structure.
3417 static struct irq_chip msi_chip = {
3419 .unmask = unmask_msi_irq,
3420 .mask = mask_msi_irq,
3421 .ack = ack_apic_edge,
3423 .set_affinity = set_msi_irq_affinity,
3425 .retrigger = ioapic_retrigger_irq,
3428 static struct irq_chip msi_ir_chip = {
3429 .name = "IR-PCI-MSI",
3430 .unmask = unmask_msi_irq,
3431 .mask = mask_msi_irq,
3432 #ifdef CONFIG_INTR_REMAP
3433 .ack = ir_ack_apic_edge,
3435 .set_affinity = ir_set_msi_irq_affinity,
3438 .retrigger = ioapic_retrigger_irq,
3442 * Map the PCI dev to the corresponding remapping hardware unit
3443 * and allocate 'nvec' consecutive interrupt-remapping table entries
3446 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3448 struct intel_iommu *iommu;
3451 iommu = map_dev_to_ir(dev);
3454 "Unable to map PCI %s to iommu\n", pci_name(dev));
3458 index = alloc_irte(iommu, irq, nvec);
3461 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3468 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3473 ret = msi_compose_msg(dev, irq, &msg, -1);
3477 set_irq_msi(irq, msidesc);
3478 write_msi_msg(irq, &msg);
3480 if (irq_remapped(irq)) {
3481 struct irq_desc *desc = irq_to_desc(irq);
3483 * irq migration in process context
3485 desc->status |= IRQ_MOVE_PCNTXT;
3486 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3488 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3490 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3495 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3498 int ret, sub_handle;
3499 struct msi_desc *msidesc;
3500 unsigned int irq_want;
3501 struct intel_iommu *iommu = NULL;
3505 /* x86 doesn't support multiple MSI yet */
3506 if (type == PCI_CAP_ID_MSI && nvec > 1)
3509 node = dev_to_node(&dev->dev);
3510 irq_want = nr_irqs_gsi;
3512 list_for_each_entry(msidesc, &dev->msi_list, list) {
3513 irq = create_irq_nr(irq_want, node);
3517 if (!intr_remapping_enabled)
3522 * allocate the consecutive block of IRTE's
3525 index = msi_alloc_irte(dev, irq, nvec);
3531 iommu = map_dev_to_ir(dev);
3537 * setup the mapping between the irq and the IRTE
3538 * base index, the sub_handle pointing to the
3539 * appropriate interrupt remap table entry.
3541 set_irte_irq(irq, iommu, index, sub_handle);
3544 ret = setup_msi_irq(dev, msidesc, irq);
3556 void arch_teardown_msi_irq(unsigned int irq)
3561 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3563 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3565 struct irq_desc *desc = irq_to_desc(irq);
3566 struct irq_cfg *cfg;
3570 if (set_desc_affinity(desc, mask, &dest))
3573 cfg = desc->chip_data;
3575 dmar_msi_read(irq, &msg);
3577 msg.data &= ~MSI_DATA_VECTOR_MASK;
3578 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3579 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3580 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3582 dmar_msi_write(irq, &msg);
3587 #endif /* CONFIG_SMP */
3589 static struct irq_chip dmar_msi_type = {
3591 .unmask = dmar_msi_unmask,
3592 .mask = dmar_msi_mask,
3593 .ack = ack_apic_edge,
3595 .set_affinity = dmar_msi_set_affinity,
3597 .retrigger = ioapic_retrigger_irq,
3600 int arch_setup_dmar_msi(unsigned int irq)
3605 ret = msi_compose_msg(NULL, irq, &msg, -1);
3608 dmar_msi_write(irq, &msg);
3609 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3615 #ifdef CONFIG_HPET_TIMER
3618 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3620 struct irq_desc *desc = irq_to_desc(irq);
3621 struct irq_cfg *cfg;
3625 if (set_desc_affinity(desc, mask, &dest))
3628 cfg = desc->chip_data;
3630 hpet_msi_read(irq, &msg);
3632 msg.data &= ~MSI_DATA_VECTOR_MASK;
3633 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3634 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3635 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3637 hpet_msi_write(irq, &msg);
3642 #endif /* CONFIG_SMP */
3644 static struct irq_chip ir_hpet_msi_type = {
3645 .name = "IR-HPET_MSI",
3646 .unmask = hpet_msi_unmask,
3647 .mask = hpet_msi_mask,
3648 #ifdef CONFIG_INTR_REMAP
3649 .ack = ir_ack_apic_edge,
3651 .set_affinity = ir_set_msi_irq_affinity,
3654 .retrigger = ioapic_retrigger_irq,
3657 static struct irq_chip hpet_msi_type = {
3659 .unmask = hpet_msi_unmask,
3660 .mask = hpet_msi_mask,
3661 .ack = ack_apic_edge,
3663 .set_affinity = hpet_msi_set_affinity,
3665 .retrigger = ioapic_retrigger_irq,
3668 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3672 struct irq_desc *desc = irq_to_desc(irq);
3674 if (intr_remapping_enabled) {
3675 struct intel_iommu *iommu = map_hpet_to_ir(id);
3681 index = alloc_irte(iommu, irq, 1);
3686 ret = msi_compose_msg(NULL, irq, &msg, id);
3690 hpet_msi_write(irq, &msg);
3691 desc->status |= IRQ_MOVE_PCNTXT;
3692 if (irq_remapped(irq))
3693 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3694 handle_edge_irq, "edge");
3696 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3697 handle_edge_irq, "edge");
3703 #endif /* CONFIG_PCI_MSI */
3705 * Hypertransport interrupt support
3707 #ifdef CONFIG_HT_IRQ
3711 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3713 struct ht_irq_msg msg;
3714 fetch_ht_irq_msg(irq, &msg);
3716 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3717 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3719 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3720 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3722 write_ht_irq_msg(irq, &msg);
3725 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3727 struct irq_desc *desc = irq_to_desc(irq);
3728 struct irq_cfg *cfg;
3731 if (set_desc_affinity(desc, mask, &dest))
3734 cfg = desc->chip_data;
3736 target_ht_irq(irq, dest, cfg->vector);
3743 static struct irq_chip ht_irq_chip = {
3745 .mask = mask_ht_irq,
3746 .unmask = unmask_ht_irq,
3747 .ack = ack_apic_edge,
3749 .set_affinity = set_ht_irq_affinity,
3751 .retrigger = ioapic_retrigger_irq,
3754 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3756 struct irq_cfg *cfg;
3763 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3765 struct ht_irq_msg msg;
3768 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3769 apic->target_cpus());
3771 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3775 HT_IRQ_LOW_DEST_ID(dest) |
3776 HT_IRQ_LOW_VECTOR(cfg->vector) |
3777 ((apic->irq_dest_mode == 0) ?
3778 HT_IRQ_LOW_DM_PHYSICAL :
3779 HT_IRQ_LOW_DM_LOGICAL) |
3780 HT_IRQ_LOW_RQEOI_EDGE |
3781 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3782 HT_IRQ_LOW_MT_FIXED :
3783 HT_IRQ_LOW_MT_ARBITRATED) |
3784 HT_IRQ_LOW_IRQ_MASKED;
3786 write_ht_irq_msg(irq, &msg);
3788 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3789 handle_edge_irq, "edge");
3791 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3795 #endif /* CONFIG_HT_IRQ */
3797 int __init io_apic_get_redir_entries (int ioapic)
3799 union IO_APIC_reg_01 reg_01;
3800 unsigned long flags;
3802 spin_lock_irqsave(&ioapic_lock, flags);
3803 reg_01.raw = io_apic_read(ioapic, 1);
3804 spin_unlock_irqrestore(&ioapic_lock, flags);
3806 return reg_01.bits.entries;
3809 void __init probe_nr_irqs_gsi(void)
3813 nr = acpi_probe_gsi();
3814 if (nr > nr_irqs_gsi) {
3817 /* for acpi=off or acpi is not compiled in */
3821 for (idx = 0; idx < nr_ioapics; idx++)
3822 nr += io_apic_get_redir_entries(idx) + 1;
3824 if (nr > nr_irqs_gsi)
3828 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3831 #ifdef CONFIG_SPARSE_IRQ
3832 int __init arch_probe_nr_irqs(void)
3836 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3837 nr_irqs = NR_VECTORS * nr_cpu_ids;
3839 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3840 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3842 * for MSI and HT dyn irq
3844 nr += nr_irqs_gsi * 64;
3853 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3854 struct io_apic_irq_attr *irq_attr)
3856 struct irq_desc *desc;
3857 struct irq_cfg *cfg;
3860 int trigger, polarity;
3862 ioapic = irq_attr->ioapic;
3863 if (!IO_APIC_IRQ(irq)) {
3864 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3870 node = dev_to_node(dev);
3872 node = cpu_to_node(boot_cpu_id);
3874 desc = irq_to_desc_alloc_node(irq, node);
3876 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3880 pin = irq_attr->ioapic_pin;
3881 trigger = irq_attr->trigger;
3882 polarity = irq_attr->polarity;
3885 * IRQs < 16 are already in the irq_2_pin[] map
3887 if (irq >= nr_legacy_irqs) {
3888 cfg = desc->chip_data;
3889 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3890 printk(KERN_INFO "can not add pin %d for irq %d\n",
3896 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3901 int io_apic_set_pci_routing(struct device *dev, int irq,
3902 struct io_apic_irq_attr *irq_attr)
3906 * Avoid pin reprogramming. PRTs typically include entries
3907 * with redundant pin->gsi mappings (but unique PCI devices);
3908 * we only program the IOAPIC on the first.
3910 ioapic = irq_attr->ioapic;
3911 pin = irq_attr->ioapic_pin;
3912 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3913 pr_debug("Pin %d-%d already programmed\n",
3914 mp_ioapics[ioapic].apicid, pin);
3917 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3919 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3922 u8 __init io_apic_unique_id(u8 id)
3924 #ifdef CONFIG_X86_32
3925 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3926 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3927 return io_apic_get_unique_id(nr_ioapics, id);
3932 DECLARE_BITMAP(used, 256);
3934 bitmap_zero(used, 256);
3935 for (i = 0; i < nr_ioapics; i++) {
3936 struct mpc_ioapic *ia = &mp_ioapics[i];
3937 __set_bit(ia->apicid, used);
3939 if (!test_bit(id, used))
3941 return find_first_zero_bit(used, 256);
3945 #ifdef CONFIG_X86_32
3946 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3948 union IO_APIC_reg_00 reg_00;
3949 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3951 unsigned long flags;
3955 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3956 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3957 * supports up to 16 on one shared APIC bus.
3959 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3960 * advantage of new APIC bus architecture.
3963 if (physids_empty(apic_id_map))
3964 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3966 spin_lock_irqsave(&ioapic_lock, flags);
3967 reg_00.raw = io_apic_read(ioapic, 0);
3968 spin_unlock_irqrestore(&ioapic_lock, flags);
3970 if (apic_id >= get_physical_broadcast()) {
3971 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3972 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3973 apic_id = reg_00.bits.ID;
3977 * Every APIC in a system must have a unique ID or we get lots of nice
3978 * 'stuck on smp_invalidate_needed IPI wait' messages.
3980 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3982 for (i = 0; i < get_physical_broadcast(); i++) {
3983 if (!apic->check_apicid_used(&apic_id_map, i))
3987 if (i == get_physical_broadcast())
3988 panic("Max apic_id exceeded!\n");
3990 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3991 "trying %d\n", ioapic, apic_id, i);
3996 apic->apicid_to_cpu_present(apic_id, &tmp);
3997 physids_or(apic_id_map, apic_id_map, tmp);
3999 if (reg_00.bits.ID != apic_id) {
4000 reg_00.bits.ID = apic_id;
4002 spin_lock_irqsave(&ioapic_lock, flags);
4003 io_apic_write(ioapic, 0, reg_00.raw);
4004 reg_00.raw = io_apic_read(ioapic, 0);
4005 spin_unlock_irqrestore(&ioapic_lock, flags);
4008 if (reg_00.bits.ID != apic_id) {
4009 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4014 apic_printk(APIC_VERBOSE, KERN_INFO
4015 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4021 int __init io_apic_get_version(int ioapic)
4023 union IO_APIC_reg_01 reg_01;
4024 unsigned long flags;
4026 spin_lock_irqsave(&ioapic_lock, flags);
4027 reg_01.raw = io_apic_read(ioapic, 1);
4028 spin_unlock_irqrestore(&ioapic_lock, flags);
4030 return reg_01.bits.version;
4033 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4037 if (skip_ioapic_setup)
4040 for (i = 0; i < mp_irq_entries; i++)
4041 if (mp_irqs[i].irqtype == mp_INT &&
4042 mp_irqs[i].srcbusirq == bus_irq)
4044 if (i >= mp_irq_entries)
4047 *trigger = irq_trigger(i);
4048 *polarity = irq_polarity(i);
4053 * This function currently is only a helper for the i386 smp boot process where
4054 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4055 * so mask in all cases should simply be apic->target_cpus()
4058 void __init setup_ioapic_dest(void)
4060 int pin, ioapic = 0, irq, irq_entry;
4061 struct irq_desc *desc;
4062 const struct cpumask *mask;
4064 if (skip_ioapic_setup == 1)
4068 if (!acpi_disabled && acpi_ioapic) {
4069 ioapic = mp_find_ioapic(0);
4075 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4076 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4077 if (irq_entry == -1)
4079 irq = pin_2_irq(irq_entry, ioapic, pin);
4081 desc = irq_to_desc(irq);
4084 * Honour affinities which have been set in early boot
4087 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4088 mask = desc->affinity;
4090 mask = apic->target_cpus();
4092 if (intr_remapping_enabled)
4093 set_ir_ioapic_affinity_irq_desc(desc, mask);
4095 set_ioapic_affinity_irq_desc(desc, mask);
4101 #define IOAPIC_RESOURCE_NAME_SIZE 11
4103 static struct resource *ioapic_resources;
4105 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4108 struct resource *res;
4112 if (nr_ioapics <= 0)
4115 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4118 mem = alloc_bootmem(n);
4121 mem += sizeof(struct resource) * nr_ioapics;
4123 for (i = 0; i < nr_ioapics; i++) {
4125 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4126 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4127 mem += IOAPIC_RESOURCE_NAME_SIZE;
4130 ioapic_resources = res;
4135 void __init ioapic_init_mappings(void)
4137 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4138 struct resource *ioapic_res;
4141 ioapic_res = ioapic_setup_resources(nr_ioapics);
4142 for (i = 0; i < nr_ioapics; i++) {
4143 if (smp_found_config) {
4144 ioapic_phys = mp_ioapics[i].apicaddr;
4145 #ifdef CONFIG_X86_32
4148 "WARNING: bogus zero IO-APIC "
4149 "address found in MPTABLE, "
4150 "disabling IO/APIC support!\n");
4151 smp_found_config = 0;
4152 skip_ioapic_setup = 1;
4153 goto fake_ioapic_page;
4157 #ifdef CONFIG_X86_32
4160 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4161 ioapic_phys = __pa(ioapic_phys);
4163 set_fixmap_nocache(idx, ioapic_phys);
4164 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4165 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4169 ioapic_res->start = ioapic_phys;
4170 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4175 void __init ioapic_insert_resources(void)
4178 struct resource *r = ioapic_resources;
4183 "IO APIC resources couldn't be allocated.\n");
4187 for (i = 0; i < nr_ioapics; i++) {
4188 insert_resource(&iomem_resource, r);
4193 int mp_find_ioapic(int gsi)
4197 /* Find the IOAPIC that manages this GSI. */
4198 for (i = 0; i < nr_ioapics; i++) {
4199 if ((gsi >= mp_gsi_routing[i].gsi_base)
4200 && (gsi <= mp_gsi_routing[i].gsi_end))
4204 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4208 int mp_find_ioapic_pin(int ioapic, int gsi)
4210 if (WARN_ON(ioapic == -1))
4212 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4215 return gsi - mp_gsi_routing[ioapic].gsi_base;
4218 static int bad_ioapic(unsigned long address)
4220 if (nr_ioapics >= MAX_IO_APICS) {
4221 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4222 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4226 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4227 " found in table, skipping!\n");
4233 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4237 if (bad_ioapic(address))
4242 mp_ioapics[idx].type = MP_IOAPIC;
4243 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4244 mp_ioapics[idx].apicaddr = address;
4246 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4247 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4248 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4251 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4252 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4254 mp_gsi_routing[idx].gsi_base = gsi_base;
4255 mp_gsi_routing[idx].gsi_end = gsi_base +
4256 io_apic_get_redir_entries(idx);
4258 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4259 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4260 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4261 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);