2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
98 static int nr_irqs_gsi = NR_IRQS_LEGACY;
100 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
101 int mp_bus_id_to_type[MAX_MP_BUSSES];
104 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
106 int skip_ioapic_setup;
108 void arch_disable_smp_support(void)
112 noioapicreroute = -1;
114 skip_ioapic_setup = 1;
117 static int __init parse_noapic(char *str)
119 /* disable IO-APIC */
120 arch_disable_smp_support();
123 early_param("noapic", parse_noapic);
125 struct irq_pin_list {
127 struct irq_pin_list *next;
130 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
132 struct irq_pin_list *pin;
134 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
143 static struct irq_cfg irq_cfgx[NR_IRQS];
146 void __init io_apic_disable_legacy(void)
152 int __init arch_early_irq_init(void)
155 struct irq_desc *desc;
161 count = ARRAY_SIZE(irq_cfgx);
162 node= cpu_to_node(boot_cpu_id);
164 for (i = 0; i < count; i++) {
165 desc = irq_to_desc(i);
166 desc->chip_data = &cfg[i];
167 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
168 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
170 * For legacy IRQ's, start with assigning irq0 to irq15 to
171 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
173 if (i < nr_legacy_irqs) {
174 cfg[i].vector = IRQ0_VECTOR + i;
175 cpumask_set_cpu(0, cfg[i].domain);
182 #ifdef CONFIG_SPARSE_IRQ
183 struct irq_cfg *irq_cfg(unsigned int irq)
185 struct irq_cfg *cfg = NULL;
186 struct irq_desc *desc;
188 desc = irq_to_desc(irq);
190 cfg = desc->chip_data;
195 static struct irq_cfg *get_one_free_irq_cfg(int node)
199 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
201 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
204 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
206 free_cpumask_var(cfg->domain);
215 int arch_init_chip_data(struct irq_desc *desc, int node)
219 cfg = desc->chip_data;
221 desc->chip_data = get_one_free_irq_cfg(node);
222 if (!desc->chip_data) {
223 printk(KERN_ERR "can not alloc irq_cfg\n");
231 /* for move_irq_desc */
233 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
235 struct irq_pin_list *old_entry, *head, *tail, *entry;
237 cfg->irq_2_pin = NULL;
238 old_entry = old_cfg->irq_2_pin;
242 entry = get_one_free_irq_2_pin(node);
246 entry->apic = old_entry->apic;
247 entry->pin = old_entry->pin;
250 old_entry = old_entry->next;
252 entry = get_one_free_irq_2_pin(node);
260 /* still use the old one */
263 entry->apic = old_entry->apic;
264 entry->pin = old_entry->pin;
267 old_entry = old_entry->next;
271 cfg->irq_2_pin = head;
274 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
276 struct irq_pin_list *entry, *next;
278 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
281 entry = old_cfg->irq_2_pin;
288 old_cfg->irq_2_pin = NULL;
291 void arch_init_copy_chip_data(struct irq_desc *old_desc,
292 struct irq_desc *desc, int node)
295 struct irq_cfg *old_cfg;
297 cfg = get_one_free_irq_cfg(node);
302 desc->chip_data = cfg;
304 old_cfg = old_desc->chip_data;
306 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
308 init_copy_irq_2_pin(old_cfg, cfg, node);
311 static void free_irq_cfg(struct irq_cfg *old_cfg)
316 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
318 struct irq_cfg *old_cfg, *cfg;
320 old_cfg = old_desc->chip_data;
321 cfg = desc->chip_data;
327 free_irq_2_pin(old_cfg, cfg);
328 free_irq_cfg(old_cfg);
329 old_desc->chip_data = NULL;
332 /* end for move_irq_desc */
335 struct irq_cfg *irq_cfg(unsigned int irq)
337 return irq < nr_irqs ? irq_cfgx + irq : NULL;
344 unsigned int unused[3];
346 unsigned int unused2[11];
350 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
352 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
353 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
356 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
358 struct io_apic __iomem *io_apic = io_apic_base(apic);
359 writel(vector, &io_apic->eoi);
362 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
364 struct io_apic __iomem *io_apic = io_apic_base(apic);
365 writel(reg, &io_apic->index);
366 return readl(&io_apic->data);
369 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
371 struct io_apic __iomem *io_apic = io_apic_base(apic);
372 writel(reg, &io_apic->index);
373 writel(value, &io_apic->data);
377 * Re-write a value: to be used for read-modify-write
378 * cycles where the read already set up the index register.
380 * Older SiS APIC requires we rewrite the index register
382 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
387 writel(reg, &io_apic->index);
388 writel(value, &io_apic->data);
391 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
393 struct irq_pin_list *entry;
396 raw_spin_lock_irqsave(&ioapic_lock, flags);
397 for_each_irq_pin(entry, cfg->irq_2_pin) {
402 reg = io_apic_read(entry->apic, 0x10 + pin*2);
403 /* Is the remote IRR bit set? */
404 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
405 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
409 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
415 struct { u32 w1, w2; };
416 struct IO_APIC_route_entry entry;
419 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
421 union entry_union eu;
423 raw_spin_lock_irqsave(&ioapic_lock, flags);
424 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
425 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
426 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
431 * When we write a new IO APIC routing entry, we need to write the high
432 * word first! If the mask bit in the low word is clear, we will enable
433 * the interrupt, and we need to make sure the entry is fully populated
434 * before that happens.
437 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
439 union entry_union eu = {{0, 0}};
442 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
443 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
446 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
449 raw_spin_lock_irqsave(&ioapic_lock, flags);
450 __ioapic_write_entry(apic, pin, e);
451 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
455 * When we mask an IO APIC routing entry, we need to write the low
456 * word first, in order to set the mask bit before we change the
459 static void ioapic_mask_entry(int apic, int pin)
462 union entry_union eu = { .entry.mask = 1 };
464 raw_spin_lock_irqsave(&ioapic_lock, flags);
465 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
466 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
467 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
471 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
472 * shared ISA-space IRQs, so we have to support them. We are super
473 * fast in the common case, and fast for shared ISA-space IRQs.
476 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
478 struct irq_pin_list **last, *entry;
480 /* don't allow duplicates */
481 last = &cfg->irq_2_pin;
482 for_each_irq_pin(entry, cfg->irq_2_pin) {
483 if (entry->apic == apic && entry->pin == pin)
488 entry = get_one_free_irq_2_pin(node);
490 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
501 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
503 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
504 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
508 * Reroute an IRQ to a different pin.
510 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
511 int oldapic, int oldpin,
512 int newapic, int newpin)
514 struct irq_pin_list *entry;
516 for_each_irq_pin(entry, cfg->irq_2_pin) {
517 if (entry->apic == oldapic && entry->pin == oldpin) {
518 entry->apic = newapic;
520 /* every one is different, right? */
525 /* old apic/pin didn't exist, so just add new ones */
526 add_pin_to_irq_node(cfg, node, newapic, newpin);
529 static void __io_apic_modify_irq(struct irq_pin_list *entry,
530 int mask_and, int mask_or,
531 void (*final)(struct irq_pin_list *entry))
533 unsigned int reg, pin;
536 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
539 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
544 static void io_apic_modify_irq(struct irq_cfg *cfg,
545 int mask_and, int mask_or,
546 void (*final)(struct irq_pin_list *entry))
548 struct irq_pin_list *entry;
550 for_each_irq_pin(entry, cfg->irq_2_pin)
551 __io_apic_modify_irq(entry, mask_and, mask_or, final);
554 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
556 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
557 IO_APIC_REDIR_MASKED, NULL);
560 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
562 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
563 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
566 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
568 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
571 static void io_apic_sync(struct irq_pin_list *entry)
574 * Synchronize the IO-APIC and the CPU by doing
575 * a dummy read from the IO-APIC
577 struct io_apic __iomem *io_apic;
578 io_apic = io_apic_base(entry->apic);
579 readl(&io_apic->data);
582 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
584 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
587 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
589 struct irq_cfg *cfg = desc->chip_data;
594 raw_spin_lock_irqsave(&ioapic_lock, flags);
595 __mask_IO_APIC_irq(cfg);
596 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
599 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
601 struct irq_cfg *cfg = desc->chip_data;
604 raw_spin_lock_irqsave(&ioapic_lock, flags);
605 __unmask_IO_APIC_irq(cfg);
606 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
609 static void mask_IO_APIC_irq(unsigned int irq)
611 struct irq_desc *desc = irq_to_desc(irq);
613 mask_IO_APIC_irq_desc(desc);
615 static void unmask_IO_APIC_irq(unsigned int irq)
617 struct irq_desc *desc = irq_to_desc(irq);
619 unmask_IO_APIC_irq_desc(desc);
622 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
624 struct IO_APIC_route_entry entry;
626 /* Check delivery_mode to be sure we're not clearing an SMI pin */
627 entry = ioapic_read_entry(apic, pin);
628 if (entry.delivery_mode == dest_SMI)
631 * Disable it in the IO-APIC irq-routing table:
633 ioapic_mask_entry(apic, pin);
636 static void clear_IO_APIC (void)
640 for (apic = 0; apic < nr_ioapics; apic++)
641 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
642 clear_IO_APIC_pin(apic, pin);
647 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
648 * specific CPU-side IRQs.
652 static int pirq_entries[MAX_PIRQS] = {
653 [0 ... MAX_PIRQS - 1] = -1
656 static int __init ioapic_pirq_setup(char *str)
659 int ints[MAX_PIRQS+1];
661 get_options(str, ARRAY_SIZE(ints), ints);
663 apic_printk(APIC_VERBOSE, KERN_INFO
664 "PIRQ redirection, working around broken MP-BIOS.\n");
666 if (ints[0] < MAX_PIRQS)
669 for (i = 0; i < max; i++) {
670 apic_printk(APIC_VERBOSE, KERN_DEBUG
671 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
673 * PIRQs are mapped upside down, usually.
675 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
680 __setup("pirq=", ioapic_pirq_setup);
681 #endif /* CONFIG_X86_32 */
683 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
686 struct IO_APIC_route_entry **ioapic_entries;
688 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
693 for (apic = 0; apic < nr_ioapics; apic++) {
694 ioapic_entries[apic] =
695 kzalloc(sizeof(struct IO_APIC_route_entry) *
696 nr_ioapic_registers[apic], GFP_ATOMIC);
697 if (!ioapic_entries[apic])
701 return ioapic_entries;
705 kfree(ioapic_entries[apic]);
706 kfree(ioapic_entries);
712 * Saves all the IO-APIC RTE's
714 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
721 for (apic = 0; apic < nr_ioapics; apic++) {
722 if (!ioapic_entries[apic])
725 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
726 ioapic_entries[apic][pin] =
727 ioapic_read_entry(apic, pin);
734 * Mask all IO APIC entries.
736 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
743 for (apic = 0; apic < nr_ioapics; apic++) {
744 if (!ioapic_entries[apic])
747 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
748 struct IO_APIC_route_entry entry;
750 entry = ioapic_entries[apic][pin];
753 ioapic_write_entry(apic, pin, entry);
760 * Restore IO APIC entries which was saved in ioapic_entries.
762 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
769 for (apic = 0; apic < nr_ioapics; apic++) {
770 if (!ioapic_entries[apic])
773 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
774 ioapic_write_entry(apic, pin,
775 ioapic_entries[apic][pin]);
780 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
784 for (apic = 0; apic < nr_ioapics; apic++)
785 kfree(ioapic_entries[apic]);
787 kfree(ioapic_entries);
791 * Find the IRQ entry number of a certain pin.
793 static int find_irq_entry(int apic, int pin, int type)
797 for (i = 0; i < mp_irq_entries; i++)
798 if (mp_irqs[i].irqtype == type &&
799 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
800 mp_irqs[i].dstapic == MP_APIC_ALL) &&
801 mp_irqs[i].dstirq == pin)
808 * Find the pin to which IRQ[irq] (ISA) is connected
810 static int __init find_isa_irq_pin(int irq, int type)
814 for (i = 0; i < mp_irq_entries; i++) {
815 int lbus = mp_irqs[i].srcbus;
817 if (test_bit(lbus, mp_bus_not_pci) &&
818 (mp_irqs[i].irqtype == type) &&
819 (mp_irqs[i].srcbusirq == irq))
821 return mp_irqs[i].dstirq;
826 static int __init find_isa_irq_apic(int irq, int type)
830 for (i = 0; i < mp_irq_entries; i++) {
831 int lbus = mp_irqs[i].srcbus;
833 if (test_bit(lbus, mp_bus_not_pci) &&
834 (mp_irqs[i].irqtype == type) &&
835 (mp_irqs[i].srcbusirq == irq))
838 if (i < mp_irq_entries) {
840 for(apic = 0; apic < nr_ioapics; apic++) {
841 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
849 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
851 * EISA Edge/Level control register, ELCR
853 static int EISA_ELCR(unsigned int irq)
855 if (irq < nr_legacy_irqs) {
856 unsigned int port = 0x4d0 + (irq >> 3);
857 return (inb(port) >> (irq & 7)) & 1;
859 apic_printk(APIC_VERBOSE, KERN_INFO
860 "Broken MPtable reports ISA irq %d\n", irq);
866 /* ISA interrupts are always polarity zero edge triggered,
867 * when listed as conforming in the MP table. */
869 #define default_ISA_trigger(idx) (0)
870 #define default_ISA_polarity(idx) (0)
872 /* EISA interrupts are always polarity zero and can be edge or level
873 * trigger depending on the ELCR value. If an interrupt is listed as
874 * EISA conforming in the MP table, that means its trigger type must
875 * be read in from the ELCR */
877 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
878 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
880 /* PCI interrupts are always polarity one level triggered,
881 * when listed as conforming in the MP table. */
883 #define default_PCI_trigger(idx) (1)
884 #define default_PCI_polarity(idx) (1)
886 /* MCA interrupts are always polarity zero level triggered,
887 * when listed as conforming in the MP table. */
889 #define default_MCA_trigger(idx) (1)
890 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
892 static int MPBIOS_polarity(int idx)
894 int bus = mp_irqs[idx].srcbus;
898 * Determine IRQ line polarity (high active or low active):
900 switch (mp_irqs[idx].irqflag & 3)
902 case 0: /* conforms, ie. bus-type dependent polarity */
903 if (test_bit(bus, mp_bus_not_pci))
904 polarity = default_ISA_polarity(idx);
906 polarity = default_PCI_polarity(idx);
908 case 1: /* high active */
913 case 2: /* reserved */
915 printk(KERN_WARNING "broken BIOS!!\n");
919 case 3: /* low active */
924 default: /* invalid */
926 printk(KERN_WARNING "broken BIOS!!\n");
934 static int MPBIOS_trigger(int idx)
936 int bus = mp_irqs[idx].srcbus;
940 * Determine IRQ trigger mode (edge or level sensitive):
942 switch ((mp_irqs[idx].irqflag>>2) & 3)
944 case 0: /* conforms, ie. bus-type dependent */
945 if (test_bit(bus, mp_bus_not_pci))
946 trigger = default_ISA_trigger(idx);
948 trigger = default_PCI_trigger(idx);
949 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
950 switch (mp_bus_id_to_type[bus]) {
951 case MP_BUS_ISA: /* ISA pin */
953 /* set before the switch */
956 case MP_BUS_EISA: /* EISA pin */
958 trigger = default_EISA_trigger(idx);
961 case MP_BUS_PCI: /* PCI pin */
963 /* set before the switch */
966 case MP_BUS_MCA: /* MCA pin */
968 trigger = default_MCA_trigger(idx);
973 printk(KERN_WARNING "broken BIOS!!\n");
985 case 2: /* reserved */
987 printk(KERN_WARNING "broken BIOS!!\n");
996 default: /* invalid */
998 printk(KERN_WARNING "broken BIOS!!\n");
1006 static inline int irq_polarity(int idx)
1008 return MPBIOS_polarity(idx);
1011 static inline int irq_trigger(int idx)
1013 return MPBIOS_trigger(idx);
1016 int (*ioapic_renumber_irq)(int ioapic, int irq);
1017 static int pin_2_irq(int idx, int apic, int pin)
1020 int bus = mp_irqs[idx].srcbus;
1023 * Debugging check, we are in big trouble if this message pops up!
1025 if (mp_irqs[idx].dstirq != pin)
1026 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1028 if (test_bit(bus, mp_bus_not_pci)) {
1029 irq = mp_irqs[idx].srcbusirq;
1032 * PCI IRQs are mapped in order
1036 irq += nr_ioapic_registers[i++];
1039 * For MPS mode, so far only needed by ES7000 platform
1041 if (ioapic_renumber_irq)
1042 irq = ioapic_renumber_irq(apic, irq);
1045 #ifdef CONFIG_X86_32
1047 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1049 if ((pin >= 16) && (pin <= 23)) {
1050 if (pirq_entries[pin-16] != -1) {
1051 if (!pirq_entries[pin-16]) {
1052 apic_printk(APIC_VERBOSE, KERN_DEBUG
1053 "disabling PIRQ%d\n", pin-16);
1055 irq = pirq_entries[pin-16];
1056 apic_printk(APIC_VERBOSE, KERN_DEBUG
1057 "using PIRQ%d -> IRQ %d\n",
1068 * Find a specific PCI IRQ entry.
1069 * Not an __init, possibly needed by modules
1071 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1072 struct io_apic_irq_attr *irq_attr)
1074 int apic, i, best_guess = -1;
1076 apic_printk(APIC_DEBUG,
1077 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1079 if (test_bit(bus, mp_bus_not_pci)) {
1080 apic_printk(APIC_VERBOSE,
1081 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1084 for (i = 0; i < mp_irq_entries; i++) {
1085 int lbus = mp_irqs[i].srcbus;
1087 for (apic = 0; apic < nr_ioapics; apic++)
1088 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1089 mp_irqs[i].dstapic == MP_APIC_ALL)
1092 if (!test_bit(lbus, mp_bus_not_pci) &&
1093 !mp_irqs[i].irqtype &&
1095 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1096 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1098 if (!(apic || IO_APIC_IRQ(irq)))
1101 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1102 set_io_apic_irq_attr(irq_attr, apic,
1109 * Use the first all-but-pin matching entry as a
1110 * best-guess fuzzy result for broken mptables.
1112 if (best_guess < 0) {
1113 set_io_apic_irq_attr(irq_attr, apic,
1123 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1125 void lock_vector_lock(void)
1127 /* Used to the online set of cpus does not change
1128 * during assign_irq_vector.
1130 raw_spin_lock(&vector_lock);
1133 void unlock_vector_lock(void)
1135 raw_spin_unlock(&vector_lock);
1139 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1142 * NOTE! The local APIC isn't very good at handling
1143 * multiple interrupts at the same interrupt level.
1144 * As the interrupt level is determined by taking the
1145 * vector number and shifting that right by 4, we
1146 * want to spread these out a bit so that they don't
1147 * all fall in the same interrupt level.
1149 * Also, we've got to be careful not to trash gate
1150 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1152 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1153 static int current_offset = VECTOR_OFFSET_START % 8;
1154 unsigned int old_vector;
1156 cpumask_var_t tmp_mask;
1158 if (cfg->move_in_progress)
1161 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1164 old_vector = cfg->vector;
1166 cpumask_and(tmp_mask, mask, cpu_online_mask);
1167 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1168 if (!cpumask_empty(tmp_mask)) {
1169 free_cpumask_var(tmp_mask);
1174 /* Only try and allocate irqs on cpus that are present */
1176 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1180 apic->vector_allocation_domain(cpu, tmp_mask);
1182 vector = current_vector;
1183 offset = current_offset;
1186 if (vector >= first_system_vector) {
1187 /* If out of vectors on large boxen, must share them. */
1188 offset = (offset + 1) % 8;
1189 vector = FIRST_EXTERNAL_VECTOR + offset;
1191 if (unlikely(current_vector == vector))
1194 if (test_bit(vector, used_vectors))
1197 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1198 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1201 current_vector = vector;
1202 current_offset = offset;
1204 cfg->move_in_progress = 1;
1205 cpumask_copy(cfg->old_domain, cfg->domain);
1207 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1208 per_cpu(vector_irq, new_cpu)[vector] = irq;
1209 cfg->vector = vector;
1210 cpumask_copy(cfg->domain, tmp_mask);
1214 free_cpumask_var(tmp_mask);
1218 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1221 unsigned long flags;
1223 raw_spin_lock_irqsave(&vector_lock, flags);
1224 err = __assign_irq_vector(irq, cfg, mask);
1225 raw_spin_unlock_irqrestore(&vector_lock, flags);
1229 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1233 BUG_ON(!cfg->vector);
1235 vector = cfg->vector;
1236 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1237 per_cpu(vector_irq, cpu)[vector] = -1;
1240 cpumask_clear(cfg->domain);
1242 if (likely(!cfg->move_in_progress))
1244 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1245 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1247 if (per_cpu(vector_irq, cpu)[vector] != irq)
1249 per_cpu(vector_irq, cpu)[vector] = -1;
1253 cfg->move_in_progress = 0;
1256 void __setup_vector_irq(int cpu)
1258 /* Initialize vector_irq on a new cpu */
1260 struct irq_cfg *cfg;
1261 struct irq_desc *desc;
1264 * vector_lock will make sure that we don't run into irq vector
1265 * assignments that might be happening on another cpu in parallel,
1266 * while we setup our initial vector to irq mappings.
1268 raw_spin_lock(&vector_lock);
1269 /* Mark the inuse vectors */
1270 for_each_irq_desc(irq, desc) {
1271 cfg = desc->chip_data;
1272 if (!cpumask_test_cpu(cpu, cfg->domain))
1274 vector = cfg->vector;
1275 per_cpu(vector_irq, cpu)[vector] = irq;
1277 /* Mark the free vectors */
1278 for (vector = 0; vector < NR_VECTORS; ++vector) {
1279 irq = per_cpu(vector_irq, cpu)[vector];
1284 if (!cpumask_test_cpu(cpu, cfg->domain))
1285 per_cpu(vector_irq, cpu)[vector] = -1;
1287 raw_spin_unlock(&vector_lock);
1290 static struct irq_chip ioapic_chip;
1291 static struct irq_chip ir_ioapic_chip;
1293 #define IOAPIC_AUTO -1
1294 #define IOAPIC_EDGE 0
1295 #define IOAPIC_LEVEL 1
1297 #ifdef CONFIG_X86_32
1298 static inline int IO_APIC_irq_trigger(int irq)
1302 for (apic = 0; apic < nr_ioapics; apic++) {
1303 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1304 idx = find_irq_entry(apic, pin, mp_INT);
1305 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1306 return irq_trigger(idx);
1310 * nonexistent IRQs are edge default
1315 static inline int IO_APIC_irq_trigger(int irq)
1321 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1324 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1325 trigger == IOAPIC_LEVEL)
1326 desc->status |= IRQ_LEVEL;
1328 desc->status &= ~IRQ_LEVEL;
1330 if (irq_remapped(irq)) {
1331 desc->status |= IRQ_MOVE_PCNTXT;
1333 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1337 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1338 handle_edge_irq, "edge");
1342 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1343 trigger == IOAPIC_LEVEL)
1344 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1348 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1349 handle_edge_irq, "edge");
1352 int setup_ioapic_entry(int apic_id, int irq,
1353 struct IO_APIC_route_entry *entry,
1354 unsigned int destination, int trigger,
1355 int polarity, int vector, int pin)
1358 * add it to the IO-APIC irq-routing table:
1360 memset(entry,0,sizeof(*entry));
1362 if (intr_remapping_enabled) {
1363 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1365 struct IR_IO_APIC_route_entry *ir_entry =
1366 (struct IR_IO_APIC_route_entry *) entry;
1370 panic("No mapping iommu for ioapic %d\n", apic_id);
1372 index = alloc_irte(iommu, irq, 1);
1374 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1376 memset(&irte, 0, sizeof(irte));
1379 irte.dst_mode = apic->irq_dest_mode;
1381 * Trigger mode in the IRTE will always be edge, and the
1382 * actual level or edge trigger will be setup in the IO-APIC
1383 * RTE. This will help simplify level triggered irq migration.
1384 * For more details, see the comments above explainig IO-APIC
1385 * irq migration in the presence of interrupt-remapping.
1387 irte.trigger_mode = 0;
1388 irte.dlvry_mode = apic->irq_delivery_mode;
1389 irte.vector = vector;
1390 irte.dest_id = IRTE_DEST(destination);
1392 /* Set source-id of interrupt request */
1393 set_ioapic_sid(&irte, apic_id);
1395 modify_irte(irq, &irte);
1397 ir_entry->index2 = (index >> 15) & 0x1;
1399 ir_entry->format = 1;
1400 ir_entry->index = (index & 0x7fff);
1402 * IO-APIC RTE will be configured with virtual vector.
1403 * irq handler will do the explicit EOI to the io-apic.
1405 ir_entry->vector = pin;
1407 entry->delivery_mode = apic->irq_delivery_mode;
1408 entry->dest_mode = apic->irq_dest_mode;
1409 entry->dest = destination;
1410 entry->vector = vector;
1413 entry->mask = 0; /* enable IRQ */
1414 entry->trigger = trigger;
1415 entry->polarity = polarity;
1417 /* Mask level triggered irqs.
1418 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1425 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1426 int trigger, int polarity)
1428 struct irq_cfg *cfg;
1429 struct IO_APIC_route_entry entry;
1432 if (!IO_APIC_IRQ(irq))
1435 cfg = desc->chip_data;
1438 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1439 * controllers like 8259. Now that IO-APIC can handle this irq, update
1442 if (irq < nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1443 apic->vector_allocation_domain(0, cfg->domain);
1445 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1448 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1450 apic_printk(APIC_VERBOSE,KERN_DEBUG
1451 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1452 "IRQ %d Mode:%i Active:%i)\n",
1453 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1454 irq, trigger, polarity);
1457 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1458 dest, trigger, polarity, cfg->vector, pin)) {
1459 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1460 mp_ioapics[apic_id].apicid, pin);
1461 __clear_irq_vector(irq, cfg);
1465 ioapic_register_intr(irq, desc, trigger);
1466 if (irq < nr_legacy_irqs)
1467 disable_8259A_irq(irq);
1469 ioapic_write_entry(apic_id, pin, entry);
1473 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1474 } mp_ioapic_routing[MAX_IO_APICS];
1476 static void __init setup_IO_APIC_irqs(void)
1478 int apic_id = 0, pin, idx, irq;
1480 struct irq_desc *desc;
1481 struct irq_cfg *cfg;
1482 int node = cpu_to_node(boot_cpu_id);
1484 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1487 if (!acpi_disabled && acpi_ioapic) {
1488 apic_id = mp_find_ioapic(0);
1494 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1495 idx = find_irq_entry(apic_id, pin, mp_INT);
1499 apic_printk(APIC_VERBOSE,
1500 KERN_DEBUG " %d-%d",
1501 mp_ioapics[apic_id].apicid, pin);
1503 apic_printk(APIC_VERBOSE, " %d-%d",
1504 mp_ioapics[apic_id].apicid, pin);
1508 apic_printk(APIC_VERBOSE,
1509 " (apicid-pin) not connected\n");
1513 irq = pin_2_irq(idx, apic_id, pin);
1516 * Skip the timer IRQ if there's a quirk handler
1517 * installed and if it returns 1:
1519 if (apic->multi_timer_check &&
1520 apic->multi_timer_check(apic_id, irq))
1523 desc = irq_to_desc_alloc_node(irq, node);
1525 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1528 cfg = desc->chip_data;
1529 add_pin_to_irq_node(cfg, node, apic_id, pin);
1531 * don't mark it in pin_programmed, so later acpi could
1532 * set it correctly when irq < 16
1534 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1535 irq_trigger(idx), irq_polarity(idx));
1539 apic_printk(APIC_VERBOSE,
1540 " (apicid-pin) not connected\n");
1544 * for the gsit that is not in first ioapic
1545 * but could not use acpi_register_gsi()
1546 * like some special sci in IBM x3330
1548 void setup_IO_APIC_irq_extra(u32 gsi)
1550 int apic_id = 0, pin, idx, irq;
1551 int node = cpu_to_node(boot_cpu_id);
1552 struct irq_desc *desc;
1553 struct irq_cfg *cfg;
1556 * Convert 'gsi' to 'ioapic.pin'.
1558 apic_id = mp_find_ioapic(gsi);
1562 pin = mp_find_ioapic_pin(apic_id, gsi);
1563 idx = find_irq_entry(apic_id, pin, mp_INT);
1567 irq = pin_2_irq(idx, apic_id, pin);
1568 #ifdef CONFIG_SPARSE_IRQ
1569 desc = irq_to_desc(irq);
1573 desc = irq_to_desc_alloc_node(irq, node);
1575 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1579 cfg = desc->chip_data;
1580 add_pin_to_irq_node(cfg, node, apic_id, pin);
1582 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1583 pr_debug("Pin %d-%d already programmed\n",
1584 mp_ioapics[apic_id].apicid, pin);
1587 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1589 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1590 irq_trigger(idx), irq_polarity(idx));
1594 * Set up the timer pin, possibly with the 8259A-master behind.
1596 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1599 struct IO_APIC_route_entry entry;
1601 if (intr_remapping_enabled)
1604 memset(&entry, 0, sizeof(entry));
1607 * We use logical delivery to get the timer IRQ
1610 entry.dest_mode = apic->irq_dest_mode;
1611 entry.mask = 0; /* don't mask IRQ for edge */
1612 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1613 entry.delivery_mode = apic->irq_delivery_mode;
1616 entry.vector = vector;
1619 * The timer IRQ doesn't have to know that behind the
1620 * scene we may have a 8259A-master in AEOI mode ...
1622 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1625 * Add it to the IO-APIC irq-routing table:
1627 ioapic_write_entry(apic_id, pin, entry);
1631 __apicdebuginit(void) print_IO_APIC(void)
1634 union IO_APIC_reg_00 reg_00;
1635 union IO_APIC_reg_01 reg_01;
1636 union IO_APIC_reg_02 reg_02;
1637 union IO_APIC_reg_03 reg_03;
1638 unsigned long flags;
1639 struct irq_cfg *cfg;
1640 struct irq_desc *desc;
1643 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1644 for (i = 0; i < nr_ioapics; i++)
1645 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1646 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1649 * We are a bit conservative about what we expect. We have to
1650 * know about every hardware change ASAP.
1652 printk(KERN_INFO "testing the IO APIC.......................\n");
1654 for (apic = 0; apic < nr_ioapics; apic++) {
1656 raw_spin_lock_irqsave(&ioapic_lock, flags);
1657 reg_00.raw = io_apic_read(apic, 0);
1658 reg_01.raw = io_apic_read(apic, 1);
1659 if (reg_01.bits.version >= 0x10)
1660 reg_02.raw = io_apic_read(apic, 2);
1661 if (reg_01.bits.version >= 0x20)
1662 reg_03.raw = io_apic_read(apic, 3);
1663 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1666 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1667 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1668 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1669 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1670 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1672 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1673 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1675 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1676 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1679 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1680 * but the value of reg_02 is read as the previous read register
1681 * value, so ignore it if reg_02 == reg_01.
1683 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1684 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1685 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1689 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1690 * or reg_03, but the value of reg_0[23] is read as the previous read
1691 * register value, so ignore it if reg_03 == reg_0[12].
1693 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1694 reg_03.raw != reg_01.raw) {
1695 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1696 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1699 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1701 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1702 " Stat Dmod Deli Vect: \n");
1704 for (i = 0; i <= reg_01.bits.entries; i++) {
1705 struct IO_APIC_route_entry entry;
1707 entry = ioapic_read_entry(apic, i);
1709 printk(KERN_DEBUG " %02x %03X ",
1714 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1719 entry.delivery_status,
1721 entry.delivery_mode,
1726 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1727 for_each_irq_desc(irq, desc) {
1728 struct irq_pin_list *entry;
1730 cfg = desc->chip_data;
1731 entry = cfg->irq_2_pin;
1734 printk(KERN_DEBUG "IRQ%d ", irq);
1735 for_each_irq_pin(entry, cfg->irq_2_pin)
1736 printk("-> %d:%d", entry->apic, entry->pin);
1740 printk(KERN_INFO ".................................... done.\n");
1745 __apicdebuginit(void) print_APIC_field(int base)
1751 for (i = 0; i < 8; i++)
1752 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1754 printk(KERN_CONT "\n");
1757 __apicdebuginit(void) print_local_APIC(void *dummy)
1759 unsigned int i, v, ver, maxlvt;
1762 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1763 smp_processor_id(), hard_smp_processor_id());
1764 v = apic_read(APIC_ID);
1765 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1766 v = apic_read(APIC_LVR);
1767 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1768 ver = GET_APIC_VERSION(v);
1769 maxlvt = lapic_get_maxlvt();
1771 v = apic_read(APIC_TASKPRI);
1772 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1774 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1775 if (!APIC_XAPIC(ver)) {
1776 v = apic_read(APIC_ARBPRI);
1777 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1778 v & APIC_ARBPRI_MASK);
1780 v = apic_read(APIC_PROCPRI);
1781 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1785 * Remote read supported only in the 82489DX and local APIC for
1786 * Pentium processors.
1788 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1789 v = apic_read(APIC_RRR);
1790 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1793 v = apic_read(APIC_LDR);
1794 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1795 if (!x2apic_enabled()) {
1796 v = apic_read(APIC_DFR);
1797 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1799 v = apic_read(APIC_SPIV);
1800 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1802 printk(KERN_DEBUG "... APIC ISR field:\n");
1803 print_APIC_field(APIC_ISR);
1804 printk(KERN_DEBUG "... APIC TMR field:\n");
1805 print_APIC_field(APIC_TMR);
1806 printk(KERN_DEBUG "... APIC IRR field:\n");
1807 print_APIC_field(APIC_IRR);
1809 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1810 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1811 apic_write(APIC_ESR, 0);
1813 v = apic_read(APIC_ESR);
1814 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1817 icr = apic_icr_read();
1818 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1819 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1821 v = apic_read(APIC_LVTT);
1822 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1824 if (maxlvt > 3) { /* PC is LVT#4. */
1825 v = apic_read(APIC_LVTPC);
1826 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1828 v = apic_read(APIC_LVT0);
1829 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1830 v = apic_read(APIC_LVT1);
1831 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1833 if (maxlvt > 2) { /* ERR is LVT#3. */
1834 v = apic_read(APIC_LVTERR);
1835 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1838 v = apic_read(APIC_TMICT);
1839 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1840 v = apic_read(APIC_TMCCT);
1841 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1842 v = apic_read(APIC_TDCR);
1843 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1845 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1846 v = apic_read(APIC_EFEAT);
1847 maxlvt = (v >> 16) & 0xff;
1848 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1849 v = apic_read(APIC_ECTRL);
1850 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1851 for (i = 0; i < maxlvt; i++) {
1852 v = apic_read(APIC_EILVTn(i));
1853 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1859 __apicdebuginit(void) print_local_APICs(int maxcpu)
1867 for_each_online_cpu(cpu) {
1870 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1875 __apicdebuginit(void) print_PIC(void)
1878 unsigned long flags;
1880 if (!nr_legacy_irqs)
1883 printk(KERN_DEBUG "\nprinting PIC contents\n");
1885 raw_spin_lock_irqsave(&i8259A_lock, flags);
1887 v = inb(0xa1) << 8 | inb(0x21);
1888 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1890 v = inb(0xa0) << 8 | inb(0x20);
1891 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1895 v = inb(0xa0) << 8 | inb(0x20);
1899 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1901 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1903 v = inb(0x4d1) << 8 | inb(0x4d0);
1904 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1907 static int __initdata show_lapic = 1;
1908 static __init int setup_show_lapic(char *arg)
1912 if (strcmp(arg, "all") == 0) {
1913 show_lapic = CONFIG_NR_CPUS;
1915 get_option(&arg, &num);
1922 __setup("show_lapic=", setup_show_lapic);
1924 __apicdebuginit(int) print_ICs(void)
1926 if (apic_verbosity == APIC_QUIET)
1931 /* don't print out if apic is not there */
1932 if (!cpu_has_apic && !apic_from_smp_config())
1935 print_local_APICs(show_lapic);
1941 fs_initcall(print_ICs);
1944 /* Where if anywhere is the i8259 connect in external int mode */
1945 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1947 void __init enable_IO_APIC(void)
1949 union IO_APIC_reg_01 reg_01;
1950 int i8259_apic, i8259_pin;
1952 unsigned long flags;
1955 * The number of IO-APIC IRQ registers (== #pins):
1957 for (apic = 0; apic < nr_ioapics; apic++) {
1958 raw_spin_lock_irqsave(&ioapic_lock, flags);
1959 reg_01.raw = io_apic_read(apic, 1);
1960 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1961 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1964 if (!nr_legacy_irqs)
1967 for(apic = 0; apic < nr_ioapics; apic++) {
1969 /* See if any of the pins is in ExtINT mode */
1970 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1971 struct IO_APIC_route_entry entry;
1972 entry = ioapic_read_entry(apic, pin);
1974 /* If the interrupt line is enabled and in ExtInt mode
1975 * I have found the pin where the i8259 is connected.
1977 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1978 ioapic_i8259.apic = apic;
1979 ioapic_i8259.pin = pin;
1985 /* Look to see what if the MP table has reported the ExtINT */
1986 /* If we could not find the appropriate pin by looking at the ioapic
1987 * the i8259 probably is not connected the ioapic but give the
1988 * mptable a chance anyway.
1990 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1991 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1992 /* Trust the MP table if nothing is setup in the hardware */
1993 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1994 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1995 ioapic_i8259.pin = i8259_pin;
1996 ioapic_i8259.apic = i8259_apic;
1998 /* Complain if the MP table and the hardware disagree */
1999 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2000 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2002 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2006 * Do not trust the IO-APIC being empty at bootup
2012 * Not an __init, needed by the reboot code
2014 void disable_IO_APIC(void)
2017 * Clear the IO-APIC before rebooting:
2021 if (!nr_legacy_irqs)
2025 * If the i8259 is routed through an IOAPIC
2026 * Put that IOAPIC in virtual wire mode
2027 * so legacy interrupts can be delivered.
2029 * With interrupt-remapping, for now we will use virtual wire A mode,
2030 * as virtual wire B is little complex (need to configure both
2031 * IOAPIC RTE aswell as interrupt-remapping table entry).
2032 * As this gets called during crash dump, keep this simple for now.
2034 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2035 struct IO_APIC_route_entry entry;
2037 memset(&entry, 0, sizeof(entry));
2038 entry.mask = 0; /* Enabled */
2039 entry.trigger = 0; /* Edge */
2041 entry.polarity = 0; /* High */
2042 entry.delivery_status = 0;
2043 entry.dest_mode = 0; /* Physical */
2044 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2046 entry.dest = read_apic_id();
2049 * Add it to the IO-APIC irq-routing table:
2051 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2055 * Use virtual wire A mode when interrupt remapping is enabled.
2057 if (cpu_has_apic || apic_from_smp_config())
2058 disconnect_bsp_APIC(!intr_remapping_enabled &&
2059 ioapic_i8259.pin != -1);
2062 #ifdef CONFIG_X86_32
2064 * function to set the IO-APIC physical IDs based on the
2065 * values stored in the MPC table.
2067 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2070 void __init setup_ioapic_ids_from_mpc(void)
2072 union IO_APIC_reg_00 reg_00;
2073 physid_mask_t phys_id_present_map;
2076 unsigned char old_id;
2077 unsigned long flags;
2082 * Don't check I/O APIC IDs for xAPIC systems. They have
2083 * no meaning without the serial APIC bus.
2085 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2086 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2089 * This is broken; anything with a real cpu count has to
2090 * circumvent this idiocy regardless.
2092 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2095 * Set the IOAPIC ID to the value stored in the MPC table.
2097 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2099 /* Read the register 0 value */
2100 raw_spin_lock_irqsave(&ioapic_lock, flags);
2101 reg_00.raw = io_apic_read(apic_id, 0);
2102 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2104 old_id = mp_ioapics[apic_id].apicid;
2106 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2107 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2108 apic_id, mp_ioapics[apic_id].apicid);
2109 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2111 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2115 * Sanity check, is the ID really free? Every APIC in a
2116 * system must have a unique ID or we get lots of nice
2117 * 'stuck on smp_invalidate_needed IPI wait' messages.
2119 if (apic->check_apicid_used(&phys_id_present_map,
2120 mp_ioapics[apic_id].apicid)) {
2121 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2122 apic_id, mp_ioapics[apic_id].apicid);
2123 for (i = 0; i < get_physical_broadcast(); i++)
2124 if (!physid_isset(i, phys_id_present_map))
2126 if (i >= get_physical_broadcast())
2127 panic("Max APIC ID exceeded!\n");
2128 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2130 physid_set(i, phys_id_present_map);
2131 mp_ioapics[apic_id].apicid = i;
2134 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2135 apic_printk(APIC_VERBOSE, "Setting %d in the "
2136 "phys_id_present_map\n",
2137 mp_ioapics[apic_id].apicid);
2138 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2143 * We need to adjust the IRQ routing table
2144 * if the ID changed.
2146 if (old_id != mp_ioapics[apic_id].apicid)
2147 for (i = 0; i < mp_irq_entries; i++)
2148 if (mp_irqs[i].dstapic == old_id)
2150 = mp_ioapics[apic_id].apicid;
2153 * Read the right value from the MPC table and
2154 * write it into the ID register.
2156 apic_printk(APIC_VERBOSE, KERN_INFO
2157 "...changing IO-APIC physical APIC ID to %d ...",
2158 mp_ioapics[apic_id].apicid);
2160 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2161 raw_spin_lock_irqsave(&ioapic_lock, flags);
2162 io_apic_write(apic_id, 0, reg_00.raw);
2163 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2168 raw_spin_lock_irqsave(&ioapic_lock, flags);
2169 reg_00.raw = io_apic_read(apic_id, 0);
2170 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2171 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2172 printk("could not set ID!\n");
2174 apic_printk(APIC_VERBOSE, " ok.\n");
2179 int no_timer_check __initdata;
2181 static int __init notimercheck(char *s)
2186 __setup("no_timer_check", notimercheck);
2189 * There is a nasty bug in some older SMP boards, their mptable lies
2190 * about the timer IRQ. We do the following to work around the situation:
2192 * - timer IRQ defaults to IO-APIC IRQ
2193 * - if this function detects that timer IRQs are defunct, then we fall
2194 * back to ISA timer IRQs
2196 static int __init timer_irq_works(void)
2198 unsigned long t1 = jiffies;
2199 unsigned long flags;
2204 local_save_flags(flags);
2206 /* Let ten ticks pass... */
2207 mdelay((10 * 1000) / HZ);
2208 local_irq_restore(flags);
2211 * Expect a few ticks at least, to be sure some possible
2212 * glue logic does not lock up after one or two first
2213 * ticks in a non-ExtINT mode. Also the local APIC
2214 * might have cached one ExtINT interrupt. Finally, at
2215 * least one tick may be lost due to delays.
2219 if (time_after(jiffies, t1 + 4))
2225 * In the SMP+IOAPIC case it might happen that there are an unspecified
2226 * number of pending IRQ events unhandled. These cases are very rare,
2227 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2228 * better to do it this way as thus we do not have to be aware of
2229 * 'pending' interrupts in the IRQ path, except at this point.
2232 * Edge triggered needs to resend any interrupt
2233 * that was delayed but this is now handled in the device
2238 * Starting up a edge-triggered IO-APIC interrupt is
2239 * nasty - we need to make sure that we get the edge.
2240 * If it is already asserted for some reason, we need
2241 * return 1 to indicate that is was pending.
2243 * This is not complete - we should be able to fake
2244 * an edge even if it isn't on the 8259A...
2247 static unsigned int startup_ioapic_irq(unsigned int irq)
2249 int was_pending = 0;
2250 unsigned long flags;
2251 struct irq_cfg *cfg;
2253 raw_spin_lock_irqsave(&ioapic_lock, flags);
2254 if (irq < nr_legacy_irqs) {
2255 disable_8259A_irq(irq);
2256 if (i8259A_irq_pending(irq))
2260 __unmask_IO_APIC_irq(cfg);
2261 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2266 static int ioapic_retrigger_irq(unsigned int irq)
2269 struct irq_cfg *cfg = irq_cfg(irq);
2270 unsigned long flags;
2272 raw_spin_lock_irqsave(&vector_lock, flags);
2273 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2274 raw_spin_unlock_irqrestore(&vector_lock, flags);
2280 * Level and edge triggered IO-APIC interrupts need different handling,
2281 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2282 * handled with the level-triggered descriptor, but that one has slightly
2283 * more overhead. Level-triggered interrupts cannot be handled with the
2284 * edge-triggered handler, without risking IRQ storms and other ugly
2289 void send_cleanup_vector(struct irq_cfg *cfg)
2291 cpumask_var_t cleanup_mask;
2293 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2295 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2296 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2298 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2299 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2300 free_cpumask_var(cleanup_mask);
2302 cfg->move_in_progress = 0;
2305 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2308 struct irq_pin_list *entry;
2309 u8 vector = cfg->vector;
2311 for_each_irq_pin(entry, cfg->irq_2_pin) {
2317 * With interrupt-remapping, destination information comes
2318 * from interrupt-remapping table entry.
2320 if (!irq_remapped(irq))
2321 io_apic_write(apic, 0x11 + pin*2, dest);
2322 reg = io_apic_read(apic, 0x10 + pin*2);
2323 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2325 io_apic_modify(apic, 0x10 + pin*2, reg);
2330 * Either sets desc->affinity to a valid value, and returns
2331 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2332 * leaves desc->affinity untouched.
2335 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2336 unsigned int *dest_id)
2338 struct irq_cfg *cfg;
2341 if (!cpumask_intersects(mask, cpu_online_mask))
2345 cfg = desc->chip_data;
2346 if (assign_irq_vector(irq, cfg, mask))
2349 cpumask_copy(desc->affinity, mask);
2351 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2356 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2358 struct irq_cfg *cfg;
2359 unsigned long flags;
2365 cfg = desc->chip_data;
2367 raw_spin_lock_irqsave(&ioapic_lock, flags);
2368 ret = set_desc_affinity(desc, mask, &dest);
2370 /* Only the high 8 bits are valid. */
2371 dest = SET_APIC_LOGICAL_ID(dest);
2372 __target_IO_APIC_irq(irq, dest, cfg);
2374 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2380 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2382 struct irq_desc *desc;
2384 desc = irq_to_desc(irq);
2386 return set_ioapic_affinity_irq_desc(desc, mask);
2389 #ifdef CONFIG_INTR_REMAP
2392 * Migrate the IO-APIC irq in the presence of intr-remapping.
2394 * For both level and edge triggered, irq migration is a simple atomic
2395 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2397 * For level triggered, we eliminate the io-apic RTE modification (with the
2398 * updated vector information), by using a virtual vector (io-apic pin number).
2399 * Real vector that is used for interrupting cpu will be coming from
2400 * the interrupt-remapping table entry.
2403 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2405 struct irq_cfg *cfg;
2411 if (!cpumask_intersects(mask, cpu_online_mask))
2415 if (get_irte(irq, &irte))
2418 cfg = desc->chip_data;
2419 if (assign_irq_vector(irq, cfg, mask))
2422 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2424 irte.vector = cfg->vector;
2425 irte.dest_id = IRTE_DEST(dest);
2428 * Modified the IRTE and flushes the Interrupt entry cache.
2430 modify_irte(irq, &irte);
2432 if (cfg->move_in_progress)
2433 send_cleanup_vector(cfg);
2435 cpumask_copy(desc->affinity, mask);
2441 * Migrates the IRQ destination in the process context.
2443 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2444 const struct cpumask *mask)
2446 return migrate_ioapic_irq_desc(desc, mask);
2448 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2449 const struct cpumask *mask)
2451 struct irq_desc *desc = irq_to_desc(irq);
2453 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2456 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2457 const struct cpumask *mask)
2463 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2465 unsigned vector, me;
2471 me = smp_processor_id();
2472 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2475 struct irq_desc *desc;
2476 struct irq_cfg *cfg;
2477 irq = __get_cpu_var(vector_irq)[vector];
2482 desc = irq_to_desc(irq);
2487 raw_spin_lock(&desc->lock);
2490 * Check if the irq migration is in progress. If so, we
2491 * haven't received the cleanup request yet for this irq.
2493 if (cfg->move_in_progress)
2496 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2499 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2501 * Check if the vector that needs to be cleanedup is
2502 * registered at the cpu's IRR. If so, then this is not
2503 * the best time to clean it up. Lets clean it up in the
2504 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2507 if (irr & (1 << (vector % 32))) {
2508 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2511 __get_cpu_var(vector_irq)[vector] = -1;
2513 raw_spin_unlock(&desc->lock);
2519 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2521 struct irq_desc *desc = *descp;
2522 struct irq_cfg *cfg = desc->chip_data;
2525 if (likely(!cfg->move_in_progress))
2528 me = smp_processor_id();
2530 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2531 send_cleanup_vector(cfg);
2534 static void irq_complete_move(struct irq_desc **descp)
2536 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2539 void irq_force_complete_move(int irq)
2541 struct irq_desc *desc = irq_to_desc(irq);
2542 struct irq_cfg *cfg = desc->chip_data;
2544 __irq_complete_move(&desc, cfg->vector);
2547 static inline void irq_complete_move(struct irq_desc **descp) {}
2550 static void ack_apic_edge(unsigned int irq)
2552 struct irq_desc *desc = irq_to_desc(irq);
2554 irq_complete_move(&desc);
2555 move_native_irq(irq);
2559 atomic_t irq_mis_count;
2562 * IO-APIC versions below 0x20 don't support EOI register.
2563 * For the record, here is the information about various versions:
2565 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2566 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2569 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2570 * version as 0x2. This is an error with documentation and these ICH chips
2571 * use io-apic's of version 0x20.
2573 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2574 * Otherwise, we simulate the EOI message manually by changing the trigger
2575 * mode to edge and then back to level, with RTE being masked during this.
2577 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2579 struct irq_pin_list *entry;
2581 for_each_irq_pin(entry, cfg->irq_2_pin) {
2582 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2584 * Intr-remapping uses pin number as the virtual vector
2585 * in the RTE. Actual vector is programmed in
2586 * intr-remapping table entry. Hence for the io-apic
2587 * EOI we use the pin number.
2589 if (irq_remapped(irq))
2590 io_apic_eoi(entry->apic, entry->pin);
2592 io_apic_eoi(entry->apic, cfg->vector);
2594 __mask_and_edge_IO_APIC_irq(entry);
2595 __unmask_and_level_IO_APIC_irq(entry);
2600 static void eoi_ioapic_irq(struct irq_desc *desc)
2602 struct irq_cfg *cfg;
2603 unsigned long flags;
2607 cfg = desc->chip_data;
2609 raw_spin_lock_irqsave(&ioapic_lock, flags);
2610 __eoi_ioapic_irq(irq, cfg);
2611 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2614 static void ack_apic_level(unsigned int irq)
2616 struct irq_desc *desc = irq_to_desc(irq);
2619 struct irq_cfg *cfg;
2620 int do_unmask_irq = 0;
2622 irq_complete_move(&desc);
2623 #ifdef CONFIG_GENERIC_PENDING_IRQ
2624 /* If we are moving the irq we need to mask it */
2625 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2627 mask_IO_APIC_irq_desc(desc);
2632 * It appears there is an erratum which affects at least version 0x11
2633 * of I/O APIC (that's the 82093AA and cores integrated into various
2634 * chipsets). Under certain conditions a level-triggered interrupt is
2635 * erroneously delivered as edge-triggered one but the respective IRR
2636 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2637 * message but it will never arrive and further interrupts are blocked
2638 * from the source. The exact reason is so far unknown, but the
2639 * phenomenon was observed when two consecutive interrupt requests
2640 * from a given source get delivered to the same CPU and the source is
2641 * temporarily disabled in between.
2643 * A workaround is to simulate an EOI message manually. We achieve it
2644 * by setting the trigger mode to edge and then to level when the edge
2645 * trigger mode gets detected in the TMR of a local APIC for a
2646 * level-triggered interrupt. We mask the source for the time of the
2647 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2648 * The idea is from Manfred Spraul. --macro
2650 * Also in the case when cpu goes offline, fixup_irqs() will forward
2651 * any unhandled interrupt on the offlined cpu to the new cpu
2652 * destination that is handling the corresponding interrupt. This
2653 * interrupt forwarding is done via IPI's. Hence, in this case also
2654 * level-triggered io-apic interrupt will be seen as an edge
2655 * interrupt in the IRR. And we can't rely on the cpu's EOI
2656 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2657 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2658 * supporting EOI register, we do an explicit EOI to clear the
2659 * remote IRR and on IO-APIC's which don't have an EOI register,
2660 * we use the above logic (mask+edge followed by unmask+level) from
2661 * Manfred Spraul to clear the remote IRR.
2663 cfg = desc->chip_data;
2665 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2668 * We must acknowledge the irq before we move it or the acknowledge will
2669 * not propagate properly.
2674 * Tail end of clearing remote IRR bit (either by delivering the EOI
2675 * message via io-apic EOI register write or simulating it using
2676 * mask+edge followed by unnask+level logic) manually when the
2677 * level triggered interrupt is seen as the edge triggered interrupt
2680 if (!(v & (1 << (i & 0x1f)))) {
2681 atomic_inc(&irq_mis_count);
2683 eoi_ioapic_irq(desc);
2686 /* Now we can move and renable the irq */
2687 if (unlikely(do_unmask_irq)) {
2688 /* Only migrate the irq if the ack has been received.
2690 * On rare occasions the broadcast level triggered ack gets
2691 * delayed going to ioapics, and if we reprogram the
2692 * vector while Remote IRR is still set the irq will never
2695 * To prevent this scenario we read the Remote IRR bit
2696 * of the ioapic. This has two effects.
2697 * - On any sane system the read of the ioapic will
2698 * flush writes (and acks) going to the ioapic from
2700 * - We get to see if the ACK has actually been delivered.
2702 * Based on failed experiments of reprogramming the
2703 * ioapic entry from outside of irq context starting
2704 * with masking the ioapic entry and then polling until
2705 * Remote IRR was clear before reprogramming the
2706 * ioapic I don't trust the Remote IRR bit to be
2707 * completey accurate.
2709 * However there appears to be no other way to plug
2710 * this race, so if the Remote IRR bit is not
2711 * accurate and is causing problems then it is a hardware bug
2712 * and you can go talk to the chipset vendor about it.
2714 cfg = desc->chip_data;
2715 if (!io_apic_level_ack_pending(cfg))
2716 move_masked_irq(irq);
2717 unmask_IO_APIC_irq_desc(desc);
2721 #ifdef CONFIG_INTR_REMAP
2722 static void ir_ack_apic_edge(unsigned int irq)
2727 static void ir_ack_apic_level(unsigned int irq)
2729 struct irq_desc *desc = irq_to_desc(irq);
2732 eoi_ioapic_irq(desc);
2734 #endif /* CONFIG_INTR_REMAP */
2736 static struct irq_chip ioapic_chip __read_mostly = {
2738 .startup = startup_ioapic_irq,
2739 .mask = mask_IO_APIC_irq,
2740 .unmask = unmask_IO_APIC_irq,
2741 .ack = ack_apic_edge,
2742 .eoi = ack_apic_level,
2744 .set_affinity = set_ioapic_affinity_irq,
2746 .retrigger = ioapic_retrigger_irq,
2749 static struct irq_chip ir_ioapic_chip __read_mostly = {
2750 .name = "IR-IO-APIC",
2751 .startup = startup_ioapic_irq,
2752 .mask = mask_IO_APIC_irq,
2753 .unmask = unmask_IO_APIC_irq,
2754 #ifdef CONFIG_INTR_REMAP
2755 .ack = ir_ack_apic_edge,
2756 .eoi = ir_ack_apic_level,
2758 .set_affinity = set_ir_ioapic_affinity_irq,
2761 .retrigger = ioapic_retrigger_irq,
2764 static inline void init_IO_APIC_traps(void)
2767 struct irq_desc *desc;
2768 struct irq_cfg *cfg;
2771 * NOTE! The local APIC isn't very good at handling
2772 * multiple interrupts at the same interrupt level.
2773 * As the interrupt level is determined by taking the
2774 * vector number and shifting that right by 4, we
2775 * want to spread these out a bit so that they don't
2776 * all fall in the same interrupt level.
2778 * Also, we've got to be careful not to trash gate
2779 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2781 for_each_irq_desc(irq, desc) {
2782 cfg = desc->chip_data;
2783 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2785 * Hmm.. We don't have an entry for this,
2786 * so default to an old-fashioned 8259
2787 * interrupt if we can..
2789 if (irq < nr_legacy_irqs)
2790 make_8259A_irq(irq);
2792 /* Strange. Oh, well.. */
2793 desc->chip = &no_irq_chip;
2799 * The local APIC irq-chip implementation:
2802 static void mask_lapic_irq(unsigned int irq)
2806 v = apic_read(APIC_LVT0);
2807 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2810 static void unmask_lapic_irq(unsigned int irq)
2814 v = apic_read(APIC_LVT0);
2815 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2818 static void ack_lapic_irq(unsigned int irq)
2823 static struct irq_chip lapic_chip __read_mostly = {
2824 .name = "local-APIC",
2825 .mask = mask_lapic_irq,
2826 .unmask = unmask_lapic_irq,
2827 .ack = ack_lapic_irq,
2830 static void lapic_register_intr(int irq, struct irq_desc *desc)
2832 desc->status &= ~IRQ_LEVEL;
2833 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2837 static void __init setup_nmi(void)
2840 * Dirty trick to enable the NMI watchdog ...
2841 * We put the 8259A master into AEOI mode and
2842 * unmask on all local APICs LVT0 as NMI.
2844 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2845 * is from Maciej W. Rozycki - so we do not have to EOI from
2846 * the NMI handler or the timer interrupt.
2848 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2850 enable_NMI_through_LVT0();
2852 apic_printk(APIC_VERBOSE, " done.\n");
2856 * This looks a bit hackish but it's about the only one way of sending
2857 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2858 * not support the ExtINT mode, unfortunately. We need to send these
2859 * cycles as some i82489DX-based boards have glue logic that keeps the
2860 * 8259A interrupt line asserted until INTA. --macro
2862 static inline void __init unlock_ExtINT_logic(void)
2865 struct IO_APIC_route_entry entry0, entry1;
2866 unsigned char save_control, save_freq_select;
2868 pin = find_isa_irq_pin(8, mp_INT);
2873 apic = find_isa_irq_apic(8, mp_INT);
2879 entry0 = ioapic_read_entry(apic, pin);
2880 clear_IO_APIC_pin(apic, pin);
2882 memset(&entry1, 0, sizeof(entry1));
2884 entry1.dest_mode = 0; /* physical delivery */
2885 entry1.mask = 0; /* unmask IRQ now */
2886 entry1.dest = hard_smp_processor_id();
2887 entry1.delivery_mode = dest_ExtINT;
2888 entry1.polarity = entry0.polarity;
2892 ioapic_write_entry(apic, pin, entry1);
2894 save_control = CMOS_READ(RTC_CONTROL);
2895 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2896 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2898 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2903 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2907 CMOS_WRITE(save_control, RTC_CONTROL);
2908 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2909 clear_IO_APIC_pin(apic, pin);
2911 ioapic_write_entry(apic, pin, entry0);
2914 static int disable_timer_pin_1 __initdata;
2915 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2916 static int __init disable_timer_pin_setup(char *arg)
2918 disable_timer_pin_1 = 1;
2921 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2923 int timer_through_8259 __initdata;
2926 * This code may look a bit paranoid, but it's supposed to cooperate with
2927 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2928 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2929 * fanatically on his truly buggy board.
2931 * FIXME: really need to revamp this for all platforms.
2933 static inline void __init check_timer(void)
2935 struct irq_desc *desc = irq_to_desc(0);
2936 struct irq_cfg *cfg = desc->chip_data;
2937 int node = cpu_to_node(boot_cpu_id);
2938 int apic1, pin1, apic2, pin2;
2939 unsigned long flags;
2942 local_irq_save(flags);
2945 * get/set the timer IRQ vector:
2947 disable_8259A_irq(0);
2948 assign_irq_vector(0, cfg, apic->target_cpus());
2951 * As IRQ0 is to be enabled in the 8259A, the virtual
2952 * wire has to be disabled in the local APIC. Also
2953 * timer interrupts need to be acknowledged manually in
2954 * the 8259A for the i82489DX when using the NMI
2955 * watchdog as that APIC treats NMIs as level-triggered.
2956 * The AEOI mode will finish them in the 8259A
2959 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2961 #ifdef CONFIG_X86_32
2965 ver = apic_read(APIC_LVR);
2966 ver = GET_APIC_VERSION(ver);
2967 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2971 pin1 = find_isa_irq_pin(0, mp_INT);
2972 apic1 = find_isa_irq_apic(0, mp_INT);
2973 pin2 = ioapic_i8259.pin;
2974 apic2 = ioapic_i8259.apic;
2976 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2977 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2978 cfg->vector, apic1, pin1, apic2, pin2);
2981 * Some BIOS writers are clueless and report the ExtINTA
2982 * I/O APIC input from the cascaded 8259A as the timer
2983 * interrupt input. So just in case, if only one pin
2984 * was found above, try it both directly and through the
2988 if (intr_remapping_enabled)
2989 panic("BIOS bug: timer not connected to IO-APIC");
2993 } else if (pin2 == -1) {
3000 * Ok, does IRQ0 through the IOAPIC work?
3003 add_pin_to_irq_node(cfg, node, apic1, pin1);
3004 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
3006 /* for edge trigger, setup_IO_APIC_irq already
3007 * leave it unmasked.
3008 * so only need to unmask if it is level-trigger
3009 * do we really have level trigger timer?
3012 idx = find_irq_entry(apic1, pin1, mp_INT);
3013 if (idx != -1 && irq_trigger(idx))
3014 unmask_IO_APIC_irq_desc(desc);
3016 if (timer_irq_works()) {
3017 if (nmi_watchdog == NMI_IO_APIC) {
3019 enable_8259A_irq(0);
3021 if (disable_timer_pin_1 > 0)
3022 clear_IO_APIC_pin(0, pin1);
3025 if (intr_remapping_enabled)
3026 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3027 local_irq_disable();
3028 clear_IO_APIC_pin(apic1, pin1);
3030 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3031 "8254 timer not connected to IO-APIC\n");
3033 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3034 "(IRQ0) through the 8259A ...\n");
3035 apic_printk(APIC_QUIET, KERN_INFO
3036 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3038 * legacy devices should be connected to IO APIC #0
3040 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3041 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3042 enable_8259A_irq(0);
3043 if (timer_irq_works()) {
3044 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3045 timer_through_8259 = 1;
3046 if (nmi_watchdog == NMI_IO_APIC) {
3047 disable_8259A_irq(0);
3049 enable_8259A_irq(0);
3054 * Cleanup, just in case ...
3056 local_irq_disable();
3057 disable_8259A_irq(0);
3058 clear_IO_APIC_pin(apic2, pin2);
3059 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3062 if (nmi_watchdog == NMI_IO_APIC) {
3063 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3064 "through the IO-APIC - disabling NMI Watchdog!\n");
3065 nmi_watchdog = NMI_NONE;
3067 #ifdef CONFIG_X86_32
3071 apic_printk(APIC_QUIET, KERN_INFO
3072 "...trying to set up timer as Virtual Wire IRQ...\n");
3074 lapic_register_intr(0, desc);
3075 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3076 enable_8259A_irq(0);
3078 if (timer_irq_works()) {
3079 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3082 local_irq_disable();
3083 disable_8259A_irq(0);
3084 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3085 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3087 apic_printk(APIC_QUIET, KERN_INFO
3088 "...trying to set up timer as ExtINT IRQ...\n");
3092 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3094 unlock_ExtINT_logic();
3096 if (timer_irq_works()) {
3097 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3100 local_irq_disable();
3101 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3102 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3103 "report. Then try booting with the 'noapic' option.\n");
3105 local_irq_restore(flags);
3109 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3110 * to devices. However there may be an I/O APIC pin available for
3111 * this interrupt regardless. The pin may be left unconnected, but
3112 * typically it will be reused as an ExtINT cascade interrupt for
3113 * the master 8259A. In the MPS case such a pin will normally be
3114 * reported as an ExtINT interrupt in the MP table. With ACPI
3115 * there is no provision for ExtINT interrupts, and in the absence
3116 * of an override it would be treated as an ordinary ISA I/O APIC
3117 * interrupt, that is edge-triggered and unmasked by default. We
3118 * used to do this, but it caused problems on some systems because
3119 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3120 * the same ExtINT cascade interrupt to drive the local APIC of the
3121 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3122 * the I/O APIC in all cases now. No actual device should request
3123 * it anyway. --macro
3125 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3127 void __init setup_IO_APIC(void)
3131 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3133 io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3135 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3137 * Set up IO-APIC IRQ routing.
3139 x86_init.mpparse.setup_ioapic_ids();
3142 setup_IO_APIC_irqs();
3143 init_IO_APIC_traps();
3149 * Called after all the initialization is done. If we didnt find any
3150 * APIC bugs then we can allow the modify fast path
3153 static int __init io_apic_bug_finalize(void)
3155 if (sis_apic_bug == -1)
3160 late_initcall(io_apic_bug_finalize);
3162 struct sysfs_ioapic_data {
3163 struct sys_device dev;
3164 struct IO_APIC_route_entry entry[0];
3166 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3168 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3170 struct IO_APIC_route_entry *entry;
3171 struct sysfs_ioapic_data *data;
3174 data = container_of(dev, struct sysfs_ioapic_data, dev);
3175 entry = data->entry;
3176 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3177 *entry = ioapic_read_entry(dev->id, i);
3182 static int ioapic_resume(struct sys_device *dev)
3184 struct IO_APIC_route_entry *entry;
3185 struct sysfs_ioapic_data *data;
3186 unsigned long flags;
3187 union IO_APIC_reg_00 reg_00;
3190 data = container_of(dev, struct sysfs_ioapic_data, dev);
3191 entry = data->entry;
3193 raw_spin_lock_irqsave(&ioapic_lock, flags);
3194 reg_00.raw = io_apic_read(dev->id, 0);
3195 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3196 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3197 io_apic_write(dev->id, 0, reg_00.raw);
3199 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3200 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3201 ioapic_write_entry(dev->id, i, entry[i]);
3206 static struct sysdev_class ioapic_sysdev_class = {
3208 .suspend = ioapic_suspend,
3209 .resume = ioapic_resume,
3212 static int __init ioapic_init_sysfs(void)
3214 struct sys_device * dev;
3217 error = sysdev_class_register(&ioapic_sysdev_class);
3221 for (i = 0; i < nr_ioapics; i++ ) {
3222 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3223 * sizeof(struct IO_APIC_route_entry);
3224 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3225 if (!mp_ioapic_data[i]) {
3226 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3229 dev = &mp_ioapic_data[i]->dev;
3231 dev->cls = &ioapic_sysdev_class;
3232 error = sysdev_register(dev);
3234 kfree(mp_ioapic_data[i]);
3235 mp_ioapic_data[i] = NULL;
3236 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3244 device_initcall(ioapic_init_sysfs);
3247 * Dynamic irq allocate and deallocation
3249 unsigned int create_irq_nr(unsigned int irq_want, int node)
3251 /* Allocate an unused irq */
3254 unsigned long flags;
3255 struct irq_cfg *cfg_new = NULL;
3256 struct irq_desc *desc_new = NULL;
3259 if (irq_want < nr_irqs_gsi)
3260 irq_want = nr_irqs_gsi;
3262 raw_spin_lock_irqsave(&vector_lock, flags);
3263 for (new = irq_want; new < nr_irqs; new++) {
3264 desc_new = irq_to_desc_alloc_node(new, node);
3266 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3269 cfg_new = desc_new->chip_data;
3271 if (cfg_new->vector != 0)
3274 desc_new = move_irq_desc(desc_new, node);
3275 cfg_new = desc_new->chip_data;
3277 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3281 raw_spin_unlock_irqrestore(&vector_lock, flags);
3284 dynamic_irq_init_keep_chip_data(irq);
3289 int create_irq(void)
3291 int node = cpu_to_node(boot_cpu_id);
3292 unsigned int irq_want;
3295 irq_want = nr_irqs_gsi;
3296 irq = create_irq_nr(irq_want, node);
3304 void destroy_irq(unsigned int irq)
3306 unsigned long flags;
3308 dynamic_irq_cleanup_keep_chip_data(irq);
3311 raw_spin_lock_irqsave(&vector_lock, flags);
3312 __clear_irq_vector(irq, get_irq_chip_data(irq));
3313 raw_spin_unlock_irqrestore(&vector_lock, flags);
3317 * MSI message composition
3319 #ifdef CONFIG_PCI_MSI
3320 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3321 struct msi_msg *msg, u8 hpet_id)
3323 struct irq_cfg *cfg;
3331 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3335 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3337 if (irq_remapped(irq)) {
3342 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3343 BUG_ON(ir_index == -1);
3345 memset (&irte, 0, sizeof(irte));
3348 irte.dst_mode = apic->irq_dest_mode;
3349 irte.trigger_mode = 0; /* edge */
3350 irte.dlvry_mode = apic->irq_delivery_mode;
3351 irte.vector = cfg->vector;
3352 irte.dest_id = IRTE_DEST(dest);
3354 /* Set source-id of interrupt request */
3356 set_msi_sid(&irte, pdev);
3358 set_hpet_sid(&irte, hpet_id);
3360 modify_irte(irq, &irte);
3362 msg->address_hi = MSI_ADDR_BASE_HI;
3363 msg->data = sub_handle;
3364 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3366 MSI_ADDR_IR_INDEX1(ir_index) |
3367 MSI_ADDR_IR_INDEX2(ir_index);
3369 if (x2apic_enabled())
3370 msg->address_hi = MSI_ADDR_BASE_HI |
3371 MSI_ADDR_EXT_DEST_ID(dest);
3373 msg->address_hi = MSI_ADDR_BASE_HI;
3377 ((apic->irq_dest_mode == 0) ?
3378 MSI_ADDR_DEST_MODE_PHYSICAL:
3379 MSI_ADDR_DEST_MODE_LOGICAL) |
3380 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3381 MSI_ADDR_REDIRECTION_CPU:
3382 MSI_ADDR_REDIRECTION_LOWPRI) |
3383 MSI_ADDR_DEST_ID(dest);
3386 MSI_DATA_TRIGGER_EDGE |
3387 MSI_DATA_LEVEL_ASSERT |
3388 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3389 MSI_DATA_DELIVERY_FIXED:
3390 MSI_DATA_DELIVERY_LOWPRI) |
3391 MSI_DATA_VECTOR(cfg->vector);
3397 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3399 struct irq_desc *desc = irq_to_desc(irq);
3400 struct irq_cfg *cfg;
3404 if (set_desc_affinity(desc, mask, &dest))
3407 cfg = desc->chip_data;
3409 read_msi_msg_desc(desc, &msg);
3411 msg.data &= ~MSI_DATA_VECTOR_MASK;
3412 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3413 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3414 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3416 write_msi_msg_desc(desc, &msg);
3420 #ifdef CONFIG_INTR_REMAP
3422 * Migrate the MSI irq to another cpumask. This migration is
3423 * done in the process context using interrupt-remapping hardware.
3426 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3428 struct irq_desc *desc = irq_to_desc(irq);
3429 struct irq_cfg *cfg = desc->chip_data;
3433 if (get_irte(irq, &irte))
3436 if (set_desc_affinity(desc, mask, &dest))
3439 irte.vector = cfg->vector;
3440 irte.dest_id = IRTE_DEST(dest);
3443 * atomically update the IRTE with the new destination and vector.
3445 modify_irte(irq, &irte);
3448 * After this point, all the interrupts will start arriving
3449 * at the new destination. So, time to cleanup the previous
3450 * vector allocation.
3452 if (cfg->move_in_progress)
3453 send_cleanup_vector(cfg);
3459 #endif /* CONFIG_SMP */
3462 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3463 * which implement the MSI or MSI-X Capability Structure.
3465 static struct irq_chip msi_chip = {
3467 .unmask = unmask_msi_irq,
3468 .mask = mask_msi_irq,
3469 .ack = ack_apic_edge,
3471 .set_affinity = set_msi_irq_affinity,
3473 .retrigger = ioapic_retrigger_irq,
3476 static struct irq_chip msi_ir_chip = {
3477 .name = "IR-PCI-MSI",
3478 .unmask = unmask_msi_irq,
3479 .mask = mask_msi_irq,
3480 #ifdef CONFIG_INTR_REMAP
3481 .ack = ir_ack_apic_edge,
3483 .set_affinity = ir_set_msi_irq_affinity,
3486 .retrigger = ioapic_retrigger_irq,
3490 * Map the PCI dev to the corresponding remapping hardware unit
3491 * and allocate 'nvec' consecutive interrupt-remapping table entries
3494 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3496 struct intel_iommu *iommu;
3499 iommu = map_dev_to_ir(dev);
3502 "Unable to map PCI %s to iommu\n", pci_name(dev));
3506 index = alloc_irte(iommu, irq, nvec);
3509 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3516 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3521 ret = msi_compose_msg(dev, irq, &msg, -1);
3525 set_irq_msi(irq, msidesc);
3526 write_msi_msg(irq, &msg);
3528 if (irq_remapped(irq)) {
3529 struct irq_desc *desc = irq_to_desc(irq);
3531 * irq migration in process context
3533 desc->status |= IRQ_MOVE_PCNTXT;
3534 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3536 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3538 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3543 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3546 int ret, sub_handle;
3547 struct msi_desc *msidesc;
3548 unsigned int irq_want;
3549 struct intel_iommu *iommu = NULL;
3553 /* x86 doesn't support multiple MSI yet */
3554 if (type == PCI_CAP_ID_MSI && nvec > 1)
3557 node = dev_to_node(&dev->dev);
3558 irq_want = nr_irqs_gsi;
3560 list_for_each_entry(msidesc, &dev->msi_list, list) {
3561 irq = create_irq_nr(irq_want, node);
3565 if (!intr_remapping_enabled)
3570 * allocate the consecutive block of IRTE's
3573 index = msi_alloc_irte(dev, irq, nvec);
3579 iommu = map_dev_to_ir(dev);
3585 * setup the mapping between the irq and the IRTE
3586 * base index, the sub_handle pointing to the
3587 * appropriate interrupt remap table entry.
3589 set_irte_irq(irq, iommu, index, sub_handle);
3592 ret = setup_msi_irq(dev, msidesc, irq);
3604 void arch_teardown_msi_irq(unsigned int irq)
3609 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3611 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3613 struct irq_desc *desc = irq_to_desc(irq);
3614 struct irq_cfg *cfg;
3618 if (set_desc_affinity(desc, mask, &dest))
3621 cfg = desc->chip_data;
3623 dmar_msi_read(irq, &msg);
3625 msg.data &= ~MSI_DATA_VECTOR_MASK;
3626 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3627 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3628 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3630 dmar_msi_write(irq, &msg);
3635 #endif /* CONFIG_SMP */
3637 static struct irq_chip dmar_msi_type = {
3639 .unmask = dmar_msi_unmask,
3640 .mask = dmar_msi_mask,
3641 .ack = ack_apic_edge,
3643 .set_affinity = dmar_msi_set_affinity,
3645 .retrigger = ioapic_retrigger_irq,
3648 int arch_setup_dmar_msi(unsigned int irq)
3653 ret = msi_compose_msg(NULL, irq, &msg, -1);
3656 dmar_msi_write(irq, &msg);
3657 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3663 #ifdef CONFIG_HPET_TIMER
3666 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3668 struct irq_desc *desc = irq_to_desc(irq);
3669 struct irq_cfg *cfg;
3673 if (set_desc_affinity(desc, mask, &dest))
3676 cfg = desc->chip_data;
3678 hpet_msi_read(irq, &msg);
3680 msg.data &= ~MSI_DATA_VECTOR_MASK;
3681 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3682 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3683 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3685 hpet_msi_write(irq, &msg);
3690 #endif /* CONFIG_SMP */
3692 static struct irq_chip ir_hpet_msi_type = {
3693 .name = "IR-HPET_MSI",
3694 .unmask = hpet_msi_unmask,
3695 .mask = hpet_msi_mask,
3696 #ifdef CONFIG_INTR_REMAP
3697 .ack = ir_ack_apic_edge,
3699 .set_affinity = ir_set_msi_irq_affinity,
3702 .retrigger = ioapic_retrigger_irq,
3705 static struct irq_chip hpet_msi_type = {
3707 .unmask = hpet_msi_unmask,
3708 .mask = hpet_msi_mask,
3709 .ack = ack_apic_edge,
3711 .set_affinity = hpet_msi_set_affinity,
3713 .retrigger = ioapic_retrigger_irq,
3716 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3720 struct irq_desc *desc = irq_to_desc(irq);
3722 if (intr_remapping_enabled) {
3723 struct intel_iommu *iommu = map_hpet_to_ir(id);
3729 index = alloc_irte(iommu, irq, 1);
3734 ret = msi_compose_msg(NULL, irq, &msg, id);
3738 hpet_msi_write(irq, &msg);
3739 desc->status |= IRQ_MOVE_PCNTXT;
3740 if (irq_remapped(irq))
3741 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3742 handle_edge_irq, "edge");
3744 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3745 handle_edge_irq, "edge");
3751 #endif /* CONFIG_PCI_MSI */
3753 * Hypertransport interrupt support
3755 #ifdef CONFIG_HT_IRQ
3759 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3761 struct ht_irq_msg msg;
3762 fetch_ht_irq_msg(irq, &msg);
3764 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3765 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3767 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3768 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3770 write_ht_irq_msg(irq, &msg);
3773 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3775 struct irq_desc *desc = irq_to_desc(irq);
3776 struct irq_cfg *cfg;
3779 if (set_desc_affinity(desc, mask, &dest))
3782 cfg = desc->chip_data;
3784 target_ht_irq(irq, dest, cfg->vector);
3791 static struct irq_chip ht_irq_chip = {
3793 .mask = mask_ht_irq,
3794 .unmask = unmask_ht_irq,
3795 .ack = ack_apic_edge,
3797 .set_affinity = set_ht_irq_affinity,
3799 .retrigger = ioapic_retrigger_irq,
3802 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3804 struct irq_cfg *cfg;
3811 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3813 struct ht_irq_msg msg;
3816 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3817 apic->target_cpus());
3819 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3823 HT_IRQ_LOW_DEST_ID(dest) |
3824 HT_IRQ_LOW_VECTOR(cfg->vector) |
3825 ((apic->irq_dest_mode == 0) ?
3826 HT_IRQ_LOW_DM_PHYSICAL :
3827 HT_IRQ_LOW_DM_LOGICAL) |
3828 HT_IRQ_LOW_RQEOI_EDGE |
3829 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3830 HT_IRQ_LOW_MT_FIXED :
3831 HT_IRQ_LOW_MT_ARBITRATED) |
3832 HT_IRQ_LOW_IRQ_MASKED;
3834 write_ht_irq_msg(irq, &msg);
3836 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3837 handle_edge_irq, "edge");
3839 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3843 #endif /* CONFIG_HT_IRQ */
3845 int __init io_apic_get_redir_entries (int ioapic)
3847 union IO_APIC_reg_01 reg_01;
3848 unsigned long flags;
3850 raw_spin_lock_irqsave(&ioapic_lock, flags);
3851 reg_01.raw = io_apic_read(ioapic, 1);
3852 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3854 return reg_01.bits.entries;
3857 void __init probe_nr_irqs_gsi(void)
3861 nr = acpi_probe_gsi();
3862 if (nr > nr_irqs_gsi) {
3865 /* for acpi=off or acpi is not compiled in */
3869 for (idx = 0; idx < nr_ioapics; idx++)
3870 nr += io_apic_get_redir_entries(idx) + 1;
3872 if (nr > nr_irqs_gsi)
3876 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3879 #ifdef CONFIG_SPARSE_IRQ
3880 int __init arch_probe_nr_irqs(void)
3884 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3885 nr_irqs = NR_VECTORS * nr_cpu_ids;
3887 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3888 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3890 * for MSI and HT dyn irq
3892 nr += nr_irqs_gsi * 16;
3901 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3902 struct io_apic_irq_attr *irq_attr)
3904 struct irq_desc *desc;
3905 struct irq_cfg *cfg;
3908 int trigger, polarity;
3910 ioapic = irq_attr->ioapic;
3911 if (!IO_APIC_IRQ(irq)) {
3912 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3918 node = dev_to_node(dev);
3920 node = cpu_to_node(boot_cpu_id);
3922 desc = irq_to_desc_alloc_node(irq, node);
3924 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3928 pin = irq_attr->ioapic_pin;
3929 trigger = irq_attr->trigger;
3930 polarity = irq_attr->polarity;
3933 * IRQs < 16 are already in the irq_2_pin[] map
3935 if (irq >= nr_legacy_irqs) {
3936 cfg = desc->chip_data;
3937 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3938 printk(KERN_INFO "can not add pin %d for irq %d\n",
3944 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3949 int io_apic_set_pci_routing(struct device *dev, int irq,
3950 struct io_apic_irq_attr *irq_attr)
3954 * Avoid pin reprogramming. PRTs typically include entries
3955 * with redundant pin->gsi mappings (but unique PCI devices);
3956 * we only program the IOAPIC on the first.
3958 ioapic = irq_attr->ioapic;
3959 pin = irq_attr->ioapic_pin;
3960 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3961 pr_debug("Pin %d-%d already programmed\n",
3962 mp_ioapics[ioapic].apicid, pin);
3965 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3967 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3970 u8 __init io_apic_unique_id(u8 id)
3972 #ifdef CONFIG_X86_32
3973 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3974 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3975 return io_apic_get_unique_id(nr_ioapics, id);
3980 DECLARE_BITMAP(used, 256);
3982 bitmap_zero(used, 256);
3983 for (i = 0; i < nr_ioapics; i++) {
3984 struct mpc_ioapic *ia = &mp_ioapics[i];
3985 __set_bit(ia->apicid, used);
3987 if (!test_bit(id, used))
3989 return find_first_zero_bit(used, 256);
3993 #ifdef CONFIG_X86_32
3994 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3996 union IO_APIC_reg_00 reg_00;
3997 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3999 unsigned long flags;
4003 * The P4 platform supports up to 256 APIC IDs on two separate APIC
4004 * buses (one for LAPICs, one for IOAPICs), where predecessors only
4005 * supports up to 16 on one shared APIC bus.
4007 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
4008 * advantage of new APIC bus architecture.
4011 if (physids_empty(apic_id_map))
4012 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
4014 raw_spin_lock_irqsave(&ioapic_lock, flags);
4015 reg_00.raw = io_apic_read(ioapic, 0);
4016 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4018 if (apic_id >= get_physical_broadcast()) {
4019 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
4020 "%d\n", ioapic, apic_id, reg_00.bits.ID);
4021 apic_id = reg_00.bits.ID;
4025 * Every APIC in a system must have a unique ID or we get lots of nice
4026 * 'stuck on smp_invalidate_needed IPI wait' messages.
4028 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
4030 for (i = 0; i < get_physical_broadcast(); i++) {
4031 if (!apic->check_apicid_used(&apic_id_map, i))
4035 if (i == get_physical_broadcast())
4036 panic("Max apic_id exceeded!\n");
4038 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4039 "trying %d\n", ioapic, apic_id, i);
4044 apic->apicid_to_cpu_present(apic_id, &tmp);
4045 physids_or(apic_id_map, apic_id_map, tmp);
4047 if (reg_00.bits.ID != apic_id) {
4048 reg_00.bits.ID = apic_id;
4050 raw_spin_lock_irqsave(&ioapic_lock, flags);
4051 io_apic_write(ioapic, 0, reg_00.raw);
4052 reg_00.raw = io_apic_read(ioapic, 0);
4053 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4056 if (reg_00.bits.ID != apic_id) {
4057 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4062 apic_printk(APIC_VERBOSE, KERN_INFO
4063 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4069 int __init io_apic_get_version(int ioapic)
4071 union IO_APIC_reg_01 reg_01;
4072 unsigned long flags;
4074 raw_spin_lock_irqsave(&ioapic_lock, flags);
4075 reg_01.raw = io_apic_read(ioapic, 1);
4076 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4078 return reg_01.bits.version;
4081 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4085 if (skip_ioapic_setup)
4088 for (i = 0; i < mp_irq_entries; i++)
4089 if (mp_irqs[i].irqtype == mp_INT &&
4090 mp_irqs[i].srcbusirq == bus_irq)
4092 if (i >= mp_irq_entries)
4095 *trigger = irq_trigger(i);
4096 *polarity = irq_polarity(i);
4101 * This function currently is only a helper for the i386 smp boot process where
4102 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4103 * so mask in all cases should simply be apic->target_cpus()
4106 void __init setup_ioapic_dest(void)
4108 int pin, ioapic = 0, irq, irq_entry;
4109 struct irq_desc *desc;
4110 const struct cpumask *mask;
4112 if (skip_ioapic_setup == 1)
4116 if (!acpi_disabled && acpi_ioapic) {
4117 ioapic = mp_find_ioapic(0);
4123 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4124 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4125 if (irq_entry == -1)
4127 irq = pin_2_irq(irq_entry, ioapic, pin);
4129 desc = irq_to_desc(irq);
4132 * Honour affinities which have been set in early boot
4135 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4136 mask = desc->affinity;
4138 mask = apic->target_cpus();
4140 if (intr_remapping_enabled)
4141 set_ir_ioapic_affinity_irq_desc(desc, mask);
4143 set_ioapic_affinity_irq_desc(desc, mask);
4149 #define IOAPIC_RESOURCE_NAME_SIZE 11
4151 static struct resource *ioapic_resources;
4153 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4156 struct resource *res;
4160 if (nr_ioapics <= 0)
4163 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4166 mem = alloc_bootmem(n);
4169 mem += sizeof(struct resource) * nr_ioapics;
4171 for (i = 0; i < nr_ioapics; i++) {
4173 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4174 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4175 mem += IOAPIC_RESOURCE_NAME_SIZE;
4178 ioapic_resources = res;
4183 void __init ioapic_init_mappings(void)
4185 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4186 struct resource *ioapic_res;
4189 ioapic_res = ioapic_setup_resources(nr_ioapics);
4190 for (i = 0; i < nr_ioapics; i++) {
4191 if (smp_found_config) {
4192 ioapic_phys = mp_ioapics[i].apicaddr;
4193 #ifdef CONFIG_X86_32
4196 "WARNING: bogus zero IO-APIC "
4197 "address found in MPTABLE, "
4198 "disabling IO/APIC support!\n");
4199 smp_found_config = 0;
4200 skip_ioapic_setup = 1;
4201 goto fake_ioapic_page;
4205 #ifdef CONFIG_X86_32
4208 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4209 ioapic_phys = __pa(ioapic_phys);
4211 set_fixmap_nocache(idx, ioapic_phys);
4212 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4213 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4217 ioapic_res->start = ioapic_phys;
4218 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4223 void __init ioapic_insert_resources(void)
4226 struct resource *r = ioapic_resources;
4231 "IO APIC resources couldn't be allocated.\n");
4235 for (i = 0; i < nr_ioapics; i++) {
4236 insert_resource(&iomem_resource, r);
4241 int mp_find_ioapic(int gsi)
4245 /* Find the IOAPIC that manages this GSI. */
4246 for (i = 0; i < nr_ioapics; i++) {
4247 if ((gsi >= mp_gsi_routing[i].gsi_base)
4248 && (gsi <= mp_gsi_routing[i].gsi_end))
4252 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4256 int mp_find_ioapic_pin(int ioapic, int gsi)
4258 if (WARN_ON(ioapic == -1))
4260 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4263 return gsi - mp_gsi_routing[ioapic].gsi_base;
4266 static int bad_ioapic(unsigned long address)
4268 if (nr_ioapics >= MAX_IO_APICS) {
4269 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4270 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4274 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4275 " found in table, skipping!\n");
4281 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4285 if (bad_ioapic(address))
4290 mp_ioapics[idx].type = MP_IOAPIC;
4291 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4292 mp_ioapics[idx].apicaddr = address;
4294 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4295 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4296 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4299 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4300 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4302 mp_gsi_routing[idx].gsi_base = gsi_base;
4303 mp_gsi_routing[idx].gsi_end = gsi_base +
4304 io_apic_get_redir_entries(idx);
4306 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4307 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4308 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4309 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);