2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/irqdomain.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
40 #include <linux/slab.h>
41 #include <linux/bootmem.h>
42 #include <linux/dmar.h>
43 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
60 #include <asm/hw_irq.h>
64 #define __apicdebuginit(type) static type __init
66 #define for_each_ioapic(idx) \
67 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
68 #define for_each_ioapic_reverse(idx) \
69 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
70 #define for_each_pin(idx, pin) \
71 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
72 #define for_each_ioapic_pin(idx, pin) \
73 for_each_ioapic((idx)) \
74 for_each_pin((idx), (pin))
76 #define for_each_irq_pin(entry, head) \
77 for (entry = head; entry; entry = entry->next)
80 * Is the SiS APIC rmw bug present ?
81 * -1 = don't know, 0 = no, 1 = yes
83 int sis_apic_bug = -1;
85 static DEFINE_RAW_SPINLOCK(ioapic_lock);
86 static DEFINE_RAW_SPINLOCK(vector_lock);
87 static DEFINE_MUTEX(ioapic_mutex);
88 static unsigned int ioapic_dynirq_base;
89 static int ioapic_initialized;
99 static struct ioapic {
101 * # of IRQ routing registers
105 * Saved state during suspend/resume, or while enabling intr-remap.
107 struct IO_APIC_route_entry *saved_registers;
108 /* I/O APIC config */
109 struct mpc_ioapic mp_config;
110 /* IO APIC gsi routing info */
111 struct mp_ioapic_gsi gsi_config;
112 struct ioapic_domain_cfg irqdomain_cfg;
113 struct irq_domain *irqdomain;
114 struct mp_pin_info *pin_info;
115 } ioapics[MAX_IO_APICS];
117 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
119 int mpc_ioapic_id(int ioapic_idx)
121 return ioapics[ioapic_idx].mp_config.apicid;
124 unsigned int mpc_ioapic_addr(int ioapic_idx)
126 return ioapics[ioapic_idx].mp_config.apicaddr;
129 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
131 return &ioapics[ioapic_idx].gsi_config;
134 static inline int mp_ioapic_pin_count(int ioapic)
136 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
138 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
141 u32 mp_pin_to_gsi(int ioapic, int pin)
143 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
147 * Initialize all legacy IRQs and all pins on the first IOAPIC
148 * if we have legacy interrupt controller. Kernel boot option "pirq="
149 * may rely on non-legacy pins on the first IOAPIC.
151 static inline int mp_init_irq_at_boot(int ioapic, int irq)
153 if (!nr_legacy_irqs())
156 return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs());
159 static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin)
161 return ioapics[ioapic_idx].pin_info + pin;
164 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
166 return ioapics[ioapic].irqdomain;
171 /* The one past the highest gsi number used */
174 /* MP IRQ source entries */
175 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
177 /* # of MP IRQ source entries */
181 int mp_bus_id_to_type[MAX_MP_BUSSES];
184 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
186 int skip_ioapic_setup;
189 * disable_ioapic_support() - disables ioapic support at runtime
191 void disable_ioapic_support(void)
195 noioapicreroute = -1;
197 skip_ioapic_setup = 1;
200 static int __init parse_noapic(char *str)
202 /* disable IO-APIC */
203 disable_ioapic_support();
206 early_param("noapic", parse_noapic);
208 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node);
210 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
211 void mp_save_irq(struct mpc_intsrc *m)
215 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
216 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
217 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
218 m->srcbusirq, m->dstapic, m->dstirq);
220 for (i = 0; i < mp_irq_entries; i++) {
221 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
225 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
226 if (++mp_irq_entries == MAX_IRQ_SOURCES)
227 panic("Max # of irq sources exceeded!!\n");
230 struct irq_pin_list {
232 struct irq_pin_list *next;
235 static struct irq_pin_list *alloc_irq_pin_list(int node)
237 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
240 int __init arch_early_irq_init(void)
243 int i, node = cpu_to_node(0);
245 if (!nr_legacy_irqs())
249 ioapics[i].saved_registers =
250 kzalloc(sizeof(struct IO_APIC_route_entry) *
251 ioapics[i].nr_registers, GFP_KERNEL);
252 if (!ioapics[i].saved_registers)
253 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
257 * For legacy IRQ's, start with assigning irq0 to irq15 to
258 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
260 for (i = 0; i < nr_legacy_irqs(); i++) {
261 cfg = alloc_irq_and_cfg_at(i, node);
262 cfg->vector = IRQ0_VECTOR + i;
263 cpumask_setall(cfg->domain);
269 static inline struct irq_cfg *irq_cfg(unsigned int irq)
271 return irq_get_chip_data(irq);
274 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
278 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
281 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
283 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
287 free_cpumask_var(cfg->domain);
293 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
297 irq_set_chip_data(at, NULL);
298 free_cpumask_var(cfg->domain);
299 free_cpumask_var(cfg->old_domain);
303 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
305 int res = irq_alloc_desc_at(at, node);
316 cfg = alloc_irq_cfg(at, node);
318 irq_set_chip_data(at, cfg);
326 unsigned int unused[3];
328 unsigned int unused2[11];
332 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
334 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
335 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
338 void io_apic_eoi(unsigned int apic, unsigned int vector)
340 struct io_apic __iomem *io_apic = io_apic_base(apic);
341 writel(vector, &io_apic->eoi);
344 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
346 struct io_apic __iomem *io_apic = io_apic_base(apic);
347 writel(reg, &io_apic->index);
348 return readl(&io_apic->data);
351 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
353 struct io_apic __iomem *io_apic = io_apic_base(apic);
355 writel(reg, &io_apic->index);
356 writel(value, &io_apic->data);
360 * Re-write a value: to be used for read-modify-write
361 * cycles where the read already set up the index register.
363 * Older SiS APIC requires we rewrite the index register
365 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
370 writel(reg, &io_apic->index);
371 writel(value, &io_apic->data);
375 struct { u32 w1, w2; };
376 struct IO_APIC_route_entry entry;
379 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
381 union entry_union eu;
383 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
384 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
389 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
391 union entry_union eu;
394 raw_spin_lock_irqsave(&ioapic_lock, flags);
395 eu.entry = __ioapic_read_entry(apic, pin);
396 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
402 * When we write a new IO APIC routing entry, we need to write the high
403 * word first! If the mask bit in the low word is clear, we will enable
404 * the interrupt, and we need to make sure the entry is fully populated
405 * before that happens.
407 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
409 union entry_union eu = {{0, 0}};
412 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
413 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
416 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
420 raw_spin_lock_irqsave(&ioapic_lock, flags);
421 __ioapic_write_entry(apic, pin, e);
422 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
426 * When we mask an IO APIC routing entry, we need to write the low
427 * word first, in order to set the mask bit before we change the
430 static void ioapic_mask_entry(int apic, int pin)
433 union entry_union eu = { .entry.mask = 1 };
435 raw_spin_lock_irqsave(&ioapic_lock, flags);
436 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
437 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
438 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
442 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
443 * shared ISA-space IRQs, so we have to support them. We are super
444 * fast in the common case, and fast for shared ISA-space IRQs.
446 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
448 struct irq_pin_list **last, *entry;
450 /* don't allow duplicates */
451 last = &cfg->irq_2_pin;
452 for_each_irq_pin(entry, cfg->irq_2_pin) {
453 if (entry->apic == apic && entry->pin == pin)
458 entry = alloc_irq_pin_list(node);
460 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
471 static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
473 struct irq_pin_list **last, *entry;
475 last = &cfg->irq_2_pin;
476 for_each_irq_pin(entry, cfg->irq_2_pin)
477 if (entry->apic == apic && entry->pin == pin) {
486 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
488 if (__add_pin_to_irq_node(cfg, node, apic, pin))
489 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
493 * Reroute an IRQ to a different pin.
495 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
496 int oldapic, int oldpin,
497 int newapic, int newpin)
499 struct irq_pin_list *entry;
501 for_each_irq_pin(entry, cfg->irq_2_pin) {
502 if (entry->apic == oldapic && entry->pin == oldpin) {
503 entry->apic = newapic;
505 /* every one is different, right? */
510 /* old apic/pin didn't exist, so just add new ones */
511 add_pin_to_irq_node(cfg, node, newapic, newpin);
514 static void __io_apic_modify_irq(struct irq_pin_list *entry,
515 int mask_and, int mask_or,
516 void (*final)(struct irq_pin_list *entry))
518 unsigned int reg, pin;
521 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
524 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
529 static void io_apic_modify_irq(struct irq_cfg *cfg,
530 int mask_and, int mask_or,
531 void (*final)(struct irq_pin_list *entry))
533 struct irq_pin_list *entry;
535 for_each_irq_pin(entry, cfg->irq_2_pin)
536 __io_apic_modify_irq(entry, mask_and, mask_or, final);
539 static void io_apic_sync(struct irq_pin_list *entry)
542 * Synchronize the IO-APIC and the CPU by doing
543 * a dummy read from the IO-APIC
545 struct io_apic __iomem *io_apic;
547 io_apic = io_apic_base(entry->apic);
548 readl(&io_apic->data);
551 static void mask_ioapic(struct irq_cfg *cfg)
555 raw_spin_lock_irqsave(&ioapic_lock, flags);
556 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
557 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
560 static void mask_ioapic_irq(struct irq_data *data)
562 mask_ioapic(data->chip_data);
565 static void __unmask_ioapic(struct irq_cfg *cfg)
567 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
570 static void unmask_ioapic(struct irq_cfg *cfg)
574 raw_spin_lock_irqsave(&ioapic_lock, flags);
575 __unmask_ioapic(cfg);
576 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
579 static void unmask_ioapic_irq(struct irq_data *data)
581 unmask_ioapic(data->chip_data);
585 * IO-APIC versions below 0x20 don't support EOI register.
586 * For the record, here is the information about various versions:
588 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
589 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
592 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
593 * version as 0x2. This is an error with documentation and these ICH chips
594 * use io-apic's of version 0x20.
596 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
597 * Otherwise, we simulate the EOI message manually by changing the trigger
598 * mode to edge and then back to level, with RTE being masked during this.
600 void native_eoi_ioapic_pin(int apic, int pin, int vector)
602 if (mpc_ioapic_ver(apic) >= 0x20) {
603 io_apic_eoi(apic, vector);
605 struct IO_APIC_route_entry entry, entry1;
607 entry = entry1 = __ioapic_read_entry(apic, pin);
610 * Mask the entry and change the trigger mode to edge.
613 entry1.trigger = IOAPIC_EDGE;
615 __ioapic_write_entry(apic, pin, entry1);
618 * Restore the previous level triggered entry.
620 __ioapic_write_entry(apic, pin, entry);
624 void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
626 struct irq_pin_list *entry;
629 raw_spin_lock_irqsave(&ioapic_lock, flags);
630 for_each_irq_pin(entry, cfg->irq_2_pin)
631 x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
633 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
636 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
638 struct IO_APIC_route_entry entry;
640 /* Check delivery_mode to be sure we're not clearing an SMI pin */
641 entry = ioapic_read_entry(apic, pin);
642 if (entry.delivery_mode == dest_SMI)
646 * Make sure the entry is masked and re-read the contents to check
647 * if it is a level triggered pin and if the remote-IRR is set.
651 ioapic_write_entry(apic, pin, entry);
652 entry = ioapic_read_entry(apic, pin);
659 * Make sure the trigger mode is set to level. Explicit EOI
660 * doesn't clear the remote-IRR if the trigger mode is not
663 if (!entry.trigger) {
664 entry.trigger = IOAPIC_LEVEL;
665 ioapic_write_entry(apic, pin, entry);
668 raw_spin_lock_irqsave(&ioapic_lock, flags);
669 x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector);
670 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
674 * Clear the rest of the bits in the IO-APIC RTE except for the mask
677 ioapic_mask_entry(apic, pin);
678 entry = ioapic_read_entry(apic, pin);
680 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
681 mpc_ioapic_id(apic), pin);
684 static void clear_IO_APIC (void)
688 for_each_ioapic_pin(apic, pin)
689 clear_IO_APIC_pin(apic, pin);
694 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
695 * specific CPU-side IRQs.
699 static int pirq_entries[MAX_PIRQS] = {
700 [0 ... MAX_PIRQS - 1] = -1
703 static int __init ioapic_pirq_setup(char *str)
706 int ints[MAX_PIRQS+1];
708 get_options(str, ARRAY_SIZE(ints), ints);
710 apic_printk(APIC_VERBOSE, KERN_INFO
711 "PIRQ redirection, working around broken MP-BIOS.\n");
713 if (ints[0] < MAX_PIRQS)
716 for (i = 0; i < max; i++) {
717 apic_printk(APIC_VERBOSE, KERN_DEBUG
718 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
720 * PIRQs are mapped upside down, usually.
722 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
727 __setup("pirq=", ioapic_pirq_setup);
728 #endif /* CONFIG_X86_32 */
731 * Saves all the IO-APIC RTE's
733 int save_ioapic_entries(void)
738 for_each_ioapic(apic) {
739 if (!ioapics[apic].saved_registers) {
744 for_each_pin(apic, pin)
745 ioapics[apic].saved_registers[pin] =
746 ioapic_read_entry(apic, pin);
753 * Mask all IO APIC entries.
755 void mask_ioapic_entries(void)
759 for_each_ioapic(apic) {
760 if (!ioapics[apic].saved_registers)
763 for_each_pin(apic, pin) {
764 struct IO_APIC_route_entry entry;
766 entry = ioapics[apic].saved_registers[pin];
769 ioapic_write_entry(apic, pin, entry);
776 * Restore IO APIC entries which was saved in the ioapic structure.
778 int restore_ioapic_entries(void)
782 for_each_ioapic(apic) {
783 if (!ioapics[apic].saved_registers)
786 for_each_pin(apic, pin)
787 ioapic_write_entry(apic, pin,
788 ioapics[apic].saved_registers[pin]);
794 * Find the IRQ entry number of a certain pin.
796 static int find_irq_entry(int ioapic_idx, int pin, int type)
800 for (i = 0; i < mp_irq_entries; i++)
801 if (mp_irqs[i].irqtype == type &&
802 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
803 mp_irqs[i].dstapic == MP_APIC_ALL) &&
804 mp_irqs[i].dstirq == pin)
811 * Find the pin to which IRQ[irq] (ISA) is connected
813 static int __init find_isa_irq_pin(int irq, int type)
817 for (i = 0; i < mp_irq_entries; i++) {
818 int lbus = mp_irqs[i].srcbus;
820 if (test_bit(lbus, mp_bus_not_pci) &&
821 (mp_irqs[i].irqtype == type) &&
822 (mp_irqs[i].srcbusirq == irq))
824 return mp_irqs[i].dstirq;
829 static int __init find_isa_irq_apic(int irq, int type)
833 for (i = 0; i < mp_irq_entries; i++) {
834 int lbus = mp_irqs[i].srcbus;
836 if (test_bit(lbus, mp_bus_not_pci) &&
837 (mp_irqs[i].irqtype == type) &&
838 (mp_irqs[i].srcbusirq == irq))
842 if (i < mp_irq_entries) {
845 for_each_ioapic(ioapic_idx)
846 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
855 * EISA Edge/Level control register, ELCR
857 static int EISA_ELCR(unsigned int irq)
859 if (irq < nr_legacy_irqs()) {
860 unsigned int port = 0x4d0 + (irq >> 3);
861 return (inb(port) >> (irq & 7)) & 1;
863 apic_printk(APIC_VERBOSE, KERN_INFO
864 "Broken MPtable reports ISA irq %d\n", irq);
870 /* ISA interrupts are always polarity zero edge triggered,
871 * when listed as conforming in the MP table. */
873 #define default_ISA_trigger(idx) (0)
874 #define default_ISA_polarity(idx) (0)
876 /* EISA interrupts are always polarity zero and can be edge or level
877 * trigger depending on the ELCR value. If an interrupt is listed as
878 * EISA conforming in the MP table, that means its trigger type must
879 * be read in from the ELCR */
881 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
882 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
884 /* PCI interrupts are always polarity one level triggered,
885 * when listed as conforming in the MP table. */
887 #define default_PCI_trigger(idx) (1)
888 #define default_PCI_polarity(idx) (1)
890 static int irq_polarity(int idx)
892 int bus = mp_irqs[idx].srcbus;
896 * Determine IRQ line polarity (high active or low active):
898 switch (mp_irqs[idx].irqflag & 3)
900 case 0: /* conforms, ie. bus-type dependent polarity */
901 if (test_bit(bus, mp_bus_not_pci))
902 polarity = default_ISA_polarity(idx);
904 polarity = default_PCI_polarity(idx);
906 case 1: /* high active */
911 case 2: /* reserved */
913 pr_warn("broken BIOS!!\n");
917 case 3: /* low active */
922 default: /* invalid */
924 pr_warn("broken BIOS!!\n");
932 static int irq_trigger(int idx)
934 int bus = mp_irqs[idx].srcbus;
938 * Determine IRQ trigger mode (edge or level sensitive):
940 switch ((mp_irqs[idx].irqflag>>2) & 3)
942 case 0: /* conforms, ie. bus-type dependent */
943 if (test_bit(bus, mp_bus_not_pci))
944 trigger = default_ISA_trigger(idx);
946 trigger = default_PCI_trigger(idx);
948 switch (mp_bus_id_to_type[bus]) {
949 case MP_BUS_ISA: /* ISA pin */
951 /* set before the switch */
954 case MP_BUS_EISA: /* EISA pin */
956 trigger = default_EISA_trigger(idx);
959 case MP_BUS_PCI: /* PCI pin */
961 /* set before the switch */
966 pr_warn("broken BIOS!!\n");
978 case 2: /* reserved */
980 pr_warn("broken BIOS!!\n");
989 default: /* invalid */
991 pr_warn("broken BIOS!!\n");
999 static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin)
1002 int ioapic = (int)(long)domain->host_data;
1003 int type = ioapics[ioapic].irqdomain_cfg.type;
1006 case IOAPIC_DOMAIN_LEGACY:
1008 * Dynamically allocate IRQ number for non-ISA IRQs in the first 16
1009 * GSIs on some weird platforms.
1011 if (gsi < nr_legacy_irqs())
1012 irq = irq_create_mapping(domain, pin);
1013 else if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
1016 case IOAPIC_DOMAIN_STRICT:
1017 if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
1020 case IOAPIC_DOMAIN_DYNAMIC:
1021 irq = irq_create_mapping(domain, pin);
1024 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
1028 return irq > 0 ? irq : -1;
1031 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1035 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1036 struct mp_pin_info *info = mp_pin_info(ioapic, pin);
1041 mutex_lock(&ioapic_mutex);
1044 * Don't use irqdomain to manage ISA IRQs because there may be
1045 * multiple IOAPIC pins sharing the same ISA IRQ number and
1046 * irqdomain only supports 1:1 mapping between IOAPIC pin and
1047 * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
1048 * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1049 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
1050 * available, and some BIOSes may use MP Interrupt Source records
1051 * to override IRQ numbers for PIRQs instead of reprogramming
1052 * the interrupt routing logic. Thus there may be multiple pins
1053 * sharing the same legacy IRQ number when ACPI is disabled.
1055 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1056 irq = mp_irqs[idx].srcbusirq;
1057 if (flags & IOAPIC_MAP_ALLOC) {
1058 if (info->count == 0 &&
1059 mp_irqdomain_map(domain, irq, pin) != 0)
1062 /* special handling for timer IRQ0 */
1067 irq = irq_find_mapping(domain, pin);
1068 if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC))
1069 irq = alloc_irq_from_domain(domain, gsi, pin);
1072 if (flags & IOAPIC_MAP_ALLOC) {
1073 /* special handling for legacy IRQs */
1074 if (irq < nr_legacy_irqs() && info->count == 1 &&
1075 mp_irqdomain_map(domain, irq, pin) != 0)
1080 else if (info->count == 0)
1084 mutex_unlock(&ioapic_mutex);
1086 return irq > 0 ? irq : -1;
1089 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1091 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1094 * Debugging check, we are in big trouble if this message pops up!
1096 if (mp_irqs[idx].dstirq != pin)
1097 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1099 #ifdef CONFIG_X86_32
1101 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1103 if ((pin >= 16) && (pin <= 23)) {
1104 if (pirq_entries[pin-16] != -1) {
1105 if (!pirq_entries[pin-16]) {
1106 apic_printk(APIC_VERBOSE, KERN_DEBUG
1107 "disabling PIRQ%d\n", pin-16);
1109 int irq = pirq_entries[pin-16];
1110 apic_printk(APIC_VERBOSE, KERN_DEBUG
1111 "using PIRQ%d -> IRQ %d\n",
1119 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
1122 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags)
1124 int ioapic, pin, idx;
1126 ioapic = mp_find_ioapic(gsi);
1130 pin = mp_find_ioapic_pin(ioapic, gsi);
1131 idx = find_irq_entry(ioapic, pin, mp_INT);
1132 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1135 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
1138 void mp_unmap_irq(int irq)
1140 struct irq_data *data = irq_get_irq_data(irq);
1141 struct mp_pin_info *info;
1144 if (!data || !data->domain)
1147 ioapic = (int)(long)data->domain->host_data;
1148 pin = (int)data->hwirq;
1149 info = mp_pin_info(ioapic, pin);
1151 mutex_lock(&ioapic_mutex);
1152 if (--info->count == 0) {
1154 if (irq < nr_legacy_irqs() &&
1155 ioapics[ioapic].irqdomain_cfg.type == IOAPIC_DOMAIN_LEGACY)
1156 mp_irqdomain_unmap(data->domain, irq);
1158 irq_dispose_mapping(irq);
1160 mutex_unlock(&ioapic_mutex);
1164 * Find a specific PCI IRQ entry.
1165 * Not an __init, possibly needed by modules
1167 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1168 struct io_apic_irq_attr *irq_attr)
1170 int irq, i, best_ioapic = -1, best_idx = -1;
1172 apic_printk(APIC_DEBUG,
1173 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1175 if (test_bit(bus, mp_bus_not_pci)) {
1176 apic_printk(APIC_VERBOSE,
1177 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1181 for (i = 0; i < mp_irq_entries; i++) {
1182 int lbus = mp_irqs[i].srcbus;
1183 int ioapic_idx, found = 0;
1185 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1186 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1189 for_each_ioapic(ioapic_idx)
1190 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1191 mp_irqs[i].dstapic == MP_APIC_ALL) {
1199 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1200 if (irq > 0 && !IO_APIC_IRQ(irq))
1203 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1205 best_ioapic = ioapic_idx;
1210 * Use the first all-but-pin matching entry as a
1211 * best-guess fuzzy result for broken mptables.
1215 best_ioapic = ioapic_idx;
1222 irq = pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1225 set_io_apic_irq_attr(irq_attr, best_ioapic,
1226 mp_irqs[best_idx].dstirq,
1227 irq_trigger(best_idx),
1228 irq_polarity(best_idx));
1231 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1233 void lock_vector_lock(void)
1235 /* Used to the online set of cpus does not change
1236 * during assign_irq_vector.
1238 raw_spin_lock(&vector_lock);
1241 void unlock_vector_lock(void)
1243 raw_spin_unlock(&vector_lock);
1247 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1250 * NOTE! The local APIC isn't very good at handling
1251 * multiple interrupts at the same interrupt level.
1252 * As the interrupt level is determined by taking the
1253 * vector number and shifting that right by 4, we
1254 * want to spread these out a bit so that they don't
1255 * all fall in the same interrupt level.
1257 * Also, we've got to be careful not to trash gate
1258 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1260 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1261 static int current_offset = VECTOR_OFFSET_START % 16;
1263 cpumask_var_t tmp_mask;
1265 if (cfg->move_in_progress)
1268 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1271 /* Only try and allocate irqs on cpus that are present */
1273 cpumask_clear(cfg->old_domain);
1274 cpu = cpumask_first_and(mask, cpu_online_mask);
1275 while (cpu < nr_cpu_ids) {
1276 int new_cpu, vector, offset;
1278 apic->vector_allocation_domain(cpu, tmp_mask, mask);
1280 if (cpumask_subset(tmp_mask, cfg->domain)) {
1282 if (cpumask_equal(tmp_mask, cfg->domain))
1285 * New cpumask using the vector is a proper subset of
1286 * the current in use mask. So cleanup the vector
1287 * allocation for the members that are not used anymore.
1289 cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
1290 cfg->move_in_progress =
1291 cpumask_intersects(cfg->old_domain, cpu_online_mask);
1292 cpumask_and(cfg->domain, cfg->domain, tmp_mask);
1296 vector = current_vector;
1297 offset = current_offset;
1300 if (vector >= first_system_vector) {
1301 offset = (offset + 1) % 16;
1302 vector = FIRST_EXTERNAL_VECTOR + offset;
1305 if (unlikely(current_vector == vector)) {
1306 cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
1307 cpumask_andnot(tmp_mask, mask, cfg->old_domain);
1308 cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
1312 if (test_bit(vector, used_vectors))
1315 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) {
1316 if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED)
1320 current_vector = vector;
1321 current_offset = offset;
1323 cpumask_copy(cfg->old_domain, cfg->domain);
1324 cfg->move_in_progress =
1325 cpumask_intersects(cfg->old_domain, cpu_online_mask);
1327 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1328 per_cpu(vector_irq, new_cpu)[vector] = irq;
1329 cfg->vector = vector;
1330 cpumask_copy(cfg->domain, tmp_mask);
1334 free_cpumask_var(tmp_mask);
1338 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1341 unsigned long flags;
1343 raw_spin_lock_irqsave(&vector_lock, flags);
1344 err = __assign_irq_vector(irq, cfg, mask);
1345 raw_spin_unlock_irqrestore(&vector_lock, flags);
1349 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1353 BUG_ON(!cfg->vector);
1355 vector = cfg->vector;
1356 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1357 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1360 cpumask_clear(cfg->domain);
1362 if (likely(!cfg->move_in_progress))
1364 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1365 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1366 if (per_cpu(vector_irq, cpu)[vector] != irq)
1368 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1372 cfg->move_in_progress = 0;
1375 void __setup_vector_irq(int cpu)
1377 /* Initialize vector_irq on a new cpu */
1379 struct irq_cfg *cfg;
1382 * vector_lock will make sure that we don't run into irq vector
1383 * assignments that might be happening on another cpu in parallel,
1384 * while we setup our initial vector to irq mappings.
1386 raw_spin_lock(&vector_lock);
1387 /* Mark the inuse vectors */
1388 for_each_active_irq(irq) {
1393 if (!cpumask_test_cpu(cpu, cfg->domain))
1395 vector = cfg->vector;
1396 per_cpu(vector_irq, cpu)[vector] = irq;
1398 /* Mark the free vectors */
1399 for (vector = 0; vector < NR_VECTORS; ++vector) {
1400 irq = per_cpu(vector_irq, cpu)[vector];
1401 if (irq <= VECTOR_UNDEFINED)
1405 if (!cpumask_test_cpu(cpu, cfg->domain))
1406 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1408 raw_spin_unlock(&vector_lock);
1411 static struct irq_chip ioapic_chip;
1413 #ifdef CONFIG_X86_32
1414 static inline int IO_APIC_irq_trigger(int irq)
1418 for_each_ioapic_pin(apic, pin) {
1419 idx = find_irq_entry(apic, pin, mp_INT);
1420 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1421 return irq_trigger(idx);
1424 * nonexistent IRQs are edge default
1429 static inline int IO_APIC_irq_trigger(int irq)
1435 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1436 unsigned long trigger)
1438 struct irq_chip *chip = &ioapic_chip;
1439 irq_flow_handler_t hdl;
1442 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1443 trigger == IOAPIC_LEVEL) {
1444 irq_set_status_flags(irq, IRQ_LEVEL);
1447 irq_clear_status_flags(irq, IRQ_LEVEL);
1451 if (setup_remapped_irq(irq, cfg, chip))
1452 fasteoi = trigger != 0;
1454 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1455 irq_set_chip_and_handler_name(irq, chip, hdl,
1456 fasteoi ? "fasteoi" : "edge");
1459 int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1460 unsigned int destination, int vector,
1461 struct io_apic_irq_attr *attr)
1463 memset(entry, 0, sizeof(*entry));
1465 entry->delivery_mode = apic->irq_delivery_mode;
1466 entry->dest_mode = apic->irq_dest_mode;
1467 entry->dest = destination;
1468 entry->vector = vector;
1469 entry->mask = 0; /* enable IRQ */
1470 entry->trigger = attr->trigger;
1471 entry->polarity = attr->polarity;
1474 * Mask level triggered irqs.
1475 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1483 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1484 struct io_apic_irq_attr *attr)
1486 struct IO_APIC_route_entry entry;
1489 if (!IO_APIC_IRQ(irq))
1492 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1495 if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
1497 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1498 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1499 __clear_irq_vector(irq, cfg);
1504 apic_printk(APIC_VERBOSE,KERN_DEBUG
1505 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1506 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1507 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1508 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1510 if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
1511 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1512 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1513 __clear_irq_vector(irq, cfg);
1518 ioapic_register_intr(irq, cfg, attr->trigger);
1519 if (irq < nr_legacy_irqs())
1520 legacy_pic->mask(irq);
1522 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1525 static void __init setup_IO_APIC_irqs(void)
1527 unsigned int ioapic, pin;
1530 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1532 for_each_ioapic_pin(ioapic, pin) {
1533 idx = find_irq_entry(ioapic, pin, mp_INT);
1535 apic_printk(APIC_VERBOSE,
1536 KERN_DEBUG " apic %d pin %d not connected\n",
1537 mpc_ioapic_id(ioapic), pin);
1539 pin_2_irq(idx, ioapic, pin,
1540 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1545 * Set up the timer pin, possibly with the 8259A-master behind.
1547 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1548 unsigned int pin, int vector)
1550 struct IO_APIC_route_entry entry;
1553 memset(&entry, 0, sizeof(entry));
1556 * We use logical delivery to get the timer IRQ
1559 if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
1560 apic->target_cpus(), &dest)))
1563 entry.dest_mode = apic->irq_dest_mode;
1564 entry.mask = 0; /* don't mask IRQ for edge */
1566 entry.delivery_mode = apic->irq_delivery_mode;
1569 entry.vector = vector;
1572 * The timer IRQ doesn't have to know that behind the
1573 * scene we may have a 8259A-master in AEOI mode ...
1575 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1579 * Add it to the IO-APIC irq-routing table:
1581 ioapic_write_entry(ioapic_idx, pin, entry);
1584 void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1588 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1590 for (i = 0; i <= nr_entries; i++) {
1591 struct IO_APIC_route_entry entry;
1593 entry = ioapic_read_entry(apic, i);
1595 pr_debug(" %02x %02X ", i, entry.dest);
1596 pr_cont("%1d %1d %1d %1d %1d "
1602 entry.delivery_status,
1604 entry.delivery_mode,
1609 void intel_ir_io_apic_print_entries(unsigned int apic,
1610 unsigned int nr_entries)
1614 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1616 for (i = 0; i <= nr_entries; i++) {
1617 struct IR_IO_APIC_route_entry *ir_entry;
1618 struct IO_APIC_route_entry entry;
1620 entry = ioapic_read_entry(apic, i);
1622 ir_entry = (struct IR_IO_APIC_route_entry *)&entry;
1624 pr_debug(" %02x %04X ", i, ir_entry->index);
1625 pr_cont("%1d %1d %1d %1d %1d "
1626 "%1d %1d %X %02X\n",
1632 ir_entry->delivery_status,
1639 void ioapic_zap_locks(void)
1641 raw_spin_lock_init(&ioapic_lock);
1644 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1646 union IO_APIC_reg_00 reg_00;
1647 union IO_APIC_reg_01 reg_01;
1648 union IO_APIC_reg_02 reg_02;
1649 union IO_APIC_reg_03 reg_03;
1650 unsigned long flags;
1652 raw_spin_lock_irqsave(&ioapic_lock, flags);
1653 reg_00.raw = io_apic_read(ioapic_idx, 0);
1654 reg_01.raw = io_apic_read(ioapic_idx, 1);
1655 if (reg_01.bits.version >= 0x10)
1656 reg_02.raw = io_apic_read(ioapic_idx, 2);
1657 if (reg_01.bits.version >= 0x20)
1658 reg_03.raw = io_apic_read(ioapic_idx, 3);
1659 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1661 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1662 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1663 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1664 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1665 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1667 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1668 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1669 reg_01.bits.entries);
1671 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1672 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1673 reg_01.bits.version);
1676 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1677 * but the value of reg_02 is read as the previous read register
1678 * value, so ignore it if reg_02 == reg_01.
1680 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1681 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1682 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1686 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1687 * or reg_03, but the value of reg_0[23] is read as the previous read
1688 * register value, so ignore it if reg_03 == reg_0[12].
1690 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1691 reg_03.raw != reg_01.raw) {
1692 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1693 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1696 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1698 x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries);
1701 __apicdebuginit(void) print_IO_APICs(void)
1704 struct irq_cfg *cfg;
1706 struct irq_chip *chip;
1708 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1709 for_each_ioapic(ioapic_idx)
1710 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1711 mpc_ioapic_id(ioapic_idx),
1712 ioapics[ioapic_idx].nr_registers);
1715 * We are a bit conservative about what we expect. We have to
1716 * know about every hardware change ASAP.
1718 printk(KERN_INFO "testing the IO APIC.......................\n");
1720 for_each_ioapic(ioapic_idx)
1721 print_IO_APIC(ioapic_idx);
1723 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1724 for_each_active_irq(irq) {
1725 struct irq_pin_list *entry;
1727 chip = irq_get_chip(irq);
1728 if (chip != &ioapic_chip)
1734 entry = cfg->irq_2_pin;
1737 printk(KERN_DEBUG "IRQ%d ", irq);
1738 for_each_irq_pin(entry, cfg->irq_2_pin)
1739 pr_cont("-> %d:%d", entry->apic, entry->pin);
1743 printk(KERN_INFO ".................................... done.\n");
1746 __apicdebuginit(void) print_APIC_field(int base)
1752 for (i = 0; i < 8; i++)
1753 pr_cont("%08x", apic_read(base + i*0x10));
1758 __apicdebuginit(void) print_local_APIC(void *dummy)
1760 unsigned int i, v, ver, maxlvt;
1763 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1764 smp_processor_id(), hard_smp_processor_id());
1765 v = apic_read(APIC_ID);
1766 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1767 v = apic_read(APIC_LVR);
1768 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1769 ver = GET_APIC_VERSION(v);
1770 maxlvt = lapic_get_maxlvt();
1772 v = apic_read(APIC_TASKPRI);
1773 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1775 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1776 if (!APIC_XAPIC(ver)) {
1777 v = apic_read(APIC_ARBPRI);
1778 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1779 v & APIC_ARBPRI_MASK);
1781 v = apic_read(APIC_PROCPRI);
1782 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1786 * Remote read supported only in the 82489DX and local APIC for
1787 * Pentium processors.
1789 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1790 v = apic_read(APIC_RRR);
1791 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1794 v = apic_read(APIC_LDR);
1795 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1796 if (!x2apic_enabled()) {
1797 v = apic_read(APIC_DFR);
1798 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1800 v = apic_read(APIC_SPIV);
1801 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1803 printk(KERN_DEBUG "... APIC ISR field:\n");
1804 print_APIC_field(APIC_ISR);
1805 printk(KERN_DEBUG "... APIC TMR field:\n");
1806 print_APIC_field(APIC_TMR);
1807 printk(KERN_DEBUG "... APIC IRR field:\n");
1808 print_APIC_field(APIC_IRR);
1810 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1811 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1812 apic_write(APIC_ESR, 0);
1814 v = apic_read(APIC_ESR);
1815 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1818 icr = apic_icr_read();
1819 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1820 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1822 v = apic_read(APIC_LVTT);
1823 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1825 if (maxlvt > 3) { /* PC is LVT#4. */
1826 v = apic_read(APIC_LVTPC);
1827 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1829 v = apic_read(APIC_LVT0);
1830 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1831 v = apic_read(APIC_LVT1);
1832 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1834 if (maxlvt > 2) { /* ERR is LVT#3. */
1835 v = apic_read(APIC_LVTERR);
1836 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1839 v = apic_read(APIC_TMICT);
1840 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1841 v = apic_read(APIC_TMCCT);
1842 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1843 v = apic_read(APIC_TDCR);
1844 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1846 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1847 v = apic_read(APIC_EFEAT);
1848 maxlvt = (v >> 16) & 0xff;
1849 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1850 v = apic_read(APIC_ECTRL);
1851 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1852 for (i = 0; i < maxlvt; i++) {
1853 v = apic_read(APIC_EILVTn(i));
1854 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1860 __apicdebuginit(void) print_local_APICs(int maxcpu)
1868 for_each_online_cpu(cpu) {
1871 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1876 __apicdebuginit(void) print_PIC(void)
1879 unsigned long flags;
1881 if (!nr_legacy_irqs())
1884 printk(KERN_DEBUG "\nprinting PIC contents\n");
1886 raw_spin_lock_irqsave(&i8259A_lock, flags);
1888 v = inb(0xa1) << 8 | inb(0x21);
1889 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1891 v = inb(0xa0) << 8 | inb(0x20);
1892 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1896 v = inb(0xa0) << 8 | inb(0x20);
1900 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1902 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1904 v = inb(0x4d1) << 8 | inb(0x4d0);
1905 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1908 static int __initdata show_lapic = 1;
1909 static __init int setup_show_lapic(char *arg)
1913 if (strcmp(arg, "all") == 0) {
1914 show_lapic = CONFIG_NR_CPUS;
1916 get_option(&arg, &num);
1923 __setup("show_lapic=", setup_show_lapic);
1925 __apicdebuginit(int) print_ICs(void)
1927 if (apic_verbosity == APIC_QUIET)
1932 /* don't print out if apic is not there */
1933 if (!cpu_has_apic && !apic_from_smp_config())
1936 print_local_APICs(show_lapic);
1942 late_initcall(print_ICs);
1945 /* Where if anywhere is the i8259 connect in external int mode */
1946 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1948 void __init enable_IO_APIC(void)
1950 int i8259_apic, i8259_pin;
1953 if (!nr_legacy_irqs())
1956 for_each_ioapic_pin(apic, pin) {
1957 /* See if any of the pins is in ExtINT mode */
1958 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1960 /* If the interrupt line is enabled and in ExtInt mode
1961 * I have found the pin where the i8259 is connected.
1963 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1964 ioapic_i8259.apic = apic;
1965 ioapic_i8259.pin = pin;
1970 /* Look to see what if the MP table has reported the ExtINT */
1971 /* If we could not find the appropriate pin by looking at the ioapic
1972 * the i8259 probably is not connected the ioapic but give the
1973 * mptable a chance anyway.
1975 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1976 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1977 /* Trust the MP table if nothing is setup in the hardware */
1978 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1979 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1980 ioapic_i8259.pin = i8259_pin;
1981 ioapic_i8259.apic = i8259_apic;
1983 /* Complain if the MP table and the hardware disagree */
1984 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1985 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1987 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1991 * Do not trust the IO-APIC being empty at bootup
1996 void native_disable_io_apic(void)
1999 * If the i8259 is routed through an IOAPIC
2000 * Put that IOAPIC in virtual wire mode
2001 * so legacy interrupts can be delivered.
2003 if (ioapic_i8259.pin != -1) {
2004 struct IO_APIC_route_entry entry;
2006 memset(&entry, 0, sizeof(entry));
2007 entry.mask = 0; /* Enabled */
2008 entry.trigger = 0; /* Edge */
2010 entry.polarity = 0; /* High */
2011 entry.delivery_status = 0;
2012 entry.dest_mode = 0; /* Physical */
2013 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2015 entry.dest = read_apic_id();
2018 * Add it to the IO-APIC irq-routing table:
2020 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2023 if (cpu_has_apic || apic_from_smp_config())
2024 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2029 * Not an __init, needed by the reboot code
2031 void disable_IO_APIC(void)
2034 * Clear the IO-APIC before rebooting:
2038 if (!nr_legacy_irqs())
2041 x86_io_apic_ops.disable();
2044 #ifdef CONFIG_X86_32
2046 * function to set the IO-APIC physical IDs based on the
2047 * values stored in the MPC table.
2049 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2051 void __init setup_ioapic_ids_from_mpc_nocheck(void)
2053 union IO_APIC_reg_00 reg_00;
2054 physid_mask_t phys_id_present_map;
2057 unsigned char old_id;
2058 unsigned long flags;
2061 * This is broken; anything with a real cpu count has to
2062 * circumvent this idiocy regardless.
2064 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2067 * Set the IOAPIC ID to the value stored in the MPC table.
2069 for_each_ioapic(ioapic_idx) {
2070 /* Read the register 0 value */
2071 raw_spin_lock_irqsave(&ioapic_lock, flags);
2072 reg_00.raw = io_apic_read(ioapic_idx, 0);
2073 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2075 old_id = mpc_ioapic_id(ioapic_idx);
2077 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2078 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2079 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2080 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2082 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2086 * Sanity check, is the ID really free? Every APIC in a
2087 * system must have a unique ID or we get lots of nice
2088 * 'stuck on smp_invalidate_needed IPI wait' messages.
2090 if (apic->check_apicid_used(&phys_id_present_map,
2091 mpc_ioapic_id(ioapic_idx))) {
2092 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2093 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2094 for (i = 0; i < get_physical_broadcast(); i++)
2095 if (!physid_isset(i, phys_id_present_map))
2097 if (i >= get_physical_broadcast())
2098 panic("Max APIC ID exceeded!\n");
2099 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2101 physid_set(i, phys_id_present_map);
2102 ioapics[ioapic_idx].mp_config.apicid = i;
2105 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2107 apic_printk(APIC_VERBOSE, "Setting %d in the "
2108 "phys_id_present_map\n",
2109 mpc_ioapic_id(ioapic_idx));
2110 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2114 * We need to adjust the IRQ routing table
2115 * if the ID changed.
2117 if (old_id != mpc_ioapic_id(ioapic_idx))
2118 for (i = 0; i < mp_irq_entries; i++)
2119 if (mp_irqs[i].dstapic == old_id)
2121 = mpc_ioapic_id(ioapic_idx);
2124 * Update the ID register according to the right value
2125 * from the MPC table if they are different.
2127 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2130 apic_printk(APIC_VERBOSE, KERN_INFO
2131 "...changing IO-APIC physical APIC ID to %d ...",
2132 mpc_ioapic_id(ioapic_idx));
2134 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2135 raw_spin_lock_irqsave(&ioapic_lock, flags);
2136 io_apic_write(ioapic_idx, 0, reg_00.raw);
2137 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2142 raw_spin_lock_irqsave(&ioapic_lock, flags);
2143 reg_00.raw = io_apic_read(ioapic_idx, 0);
2144 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2145 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2146 pr_cont("could not set ID!\n");
2148 apic_printk(APIC_VERBOSE, " ok.\n");
2152 void __init setup_ioapic_ids_from_mpc(void)
2158 * Don't check I/O APIC IDs for xAPIC systems. They have
2159 * no meaning without the serial APIC bus.
2161 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2162 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2164 setup_ioapic_ids_from_mpc_nocheck();
2168 int no_timer_check __initdata;
2170 static int __init notimercheck(char *s)
2175 __setup("no_timer_check", notimercheck);
2178 * There is a nasty bug in some older SMP boards, their mptable lies
2179 * about the timer IRQ. We do the following to work around the situation:
2181 * - timer IRQ defaults to IO-APIC IRQ
2182 * - if this function detects that timer IRQs are defunct, then we fall
2183 * back to ISA timer IRQs
2185 static int __init timer_irq_works(void)
2187 unsigned long t1 = jiffies;
2188 unsigned long flags;
2193 local_save_flags(flags);
2195 /* Let ten ticks pass... */
2196 mdelay((10 * 1000) / HZ);
2197 local_irq_restore(flags);
2200 * Expect a few ticks at least, to be sure some possible
2201 * glue logic does not lock up after one or two first
2202 * ticks in a non-ExtINT mode. Also the local APIC
2203 * might have cached one ExtINT interrupt. Finally, at
2204 * least one tick may be lost due to delays.
2208 if (time_after(jiffies, t1 + 4))
2214 * In the SMP+IOAPIC case it might happen that there are an unspecified
2215 * number of pending IRQ events unhandled. These cases are very rare,
2216 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2217 * better to do it this way as thus we do not have to be aware of
2218 * 'pending' interrupts in the IRQ path, except at this point.
2221 * Edge triggered needs to resend any interrupt
2222 * that was delayed but this is now handled in the device
2227 * Starting up a edge-triggered IO-APIC interrupt is
2228 * nasty - we need to make sure that we get the edge.
2229 * If it is already asserted for some reason, we need
2230 * return 1 to indicate that is was pending.
2232 * This is not complete - we should be able to fake
2233 * an edge even if it isn't on the 8259A...
2236 static unsigned int startup_ioapic_irq(struct irq_data *data)
2238 int was_pending = 0, irq = data->irq;
2239 unsigned long flags;
2241 raw_spin_lock_irqsave(&ioapic_lock, flags);
2242 if (irq < nr_legacy_irqs()) {
2243 legacy_pic->mask(irq);
2244 if (legacy_pic->irq_pending(irq))
2247 __unmask_ioapic(data->chip_data);
2248 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2253 static int ioapic_retrigger_irq(struct irq_data *data)
2255 struct irq_cfg *cfg = data->chip_data;
2256 unsigned long flags;
2259 raw_spin_lock_irqsave(&vector_lock, flags);
2260 cpu = cpumask_first_and(cfg->domain, cpu_online_mask);
2261 apic->send_IPI_mask(cpumask_of(cpu), cfg->vector);
2262 raw_spin_unlock_irqrestore(&vector_lock, flags);
2268 * Level and edge triggered IO-APIC interrupts need different handling,
2269 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2270 * handled with the level-triggered descriptor, but that one has slightly
2271 * more overhead. Level-triggered interrupts cannot be handled with the
2272 * edge-triggered handler, without risking IRQ storms and other ugly
2277 void send_cleanup_vector(struct irq_cfg *cfg)
2279 cpumask_var_t cleanup_mask;
2281 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2283 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2284 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2286 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2287 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2288 free_cpumask_var(cleanup_mask);
2290 cfg->move_in_progress = 0;
2293 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
2295 unsigned vector, me;
2301 me = smp_processor_id();
2302 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2305 struct irq_desc *desc;
2306 struct irq_cfg *cfg;
2307 irq = __this_cpu_read(vector_irq[vector]);
2309 if (irq <= VECTOR_UNDEFINED)
2312 desc = irq_to_desc(irq);
2320 raw_spin_lock(&desc->lock);
2323 * Check if the irq migration is in progress. If so, we
2324 * haven't received the cleanup request yet for this irq.
2326 if (cfg->move_in_progress)
2329 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2332 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2334 * Check if the vector that needs to be cleanedup is
2335 * registered at the cpu's IRR. If so, then this is not
2336 * the best time to clean it up. Lets clean it up in the
2337 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2340 if (irr & (1 << (vector % 32))) {
2341 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2344 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
2346 raw_spin_unlock(&desc->lock);
2352 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2356 if (likely(!cfg->move_in_progress))
2359 me = smp_processor_id();
2361 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2362 send_cleanup_vector(cfg);
2365 static void irq_complete_move(struct irq_cfg *cfg)
2367 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2370 void irq_force_complete_move(int irq)
2372 struct irq_cfg *cfg = irq_cfg(irq);
2377 __irq_complete_move(cfg, cfg->vector);
2380 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2383 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2386 struct irq_pin_list *entry;
2387 u8 vector = cfg->vector;
2389 for_each_irq_pin(entry, cfg->irq_2_pin) {
2395 io_apic_write(apic, 0x11 + pin*2, dest);
2396 reg = io_apic_read(apic, 0x10 + pin*2);
2397 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2399 io_apic_modify(apic, 0x10 + pin*2, reg);
2404 * Either sets data->affinity to a valid value, and returns
2405 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2406 * leaves data->affinity untouched.
2408 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2409 unsigned int *dest_id)
2411 struct irq_cfg *cfg = data->chip_data;
2412 unsigned int irq = data->irq;
2415 if (!config_enabled(CONFIG_SMP))
2418 if (!cpumask_intersects(mask, cpu_online_mask))
2421 err = assign_irq_vector(irq, cfg, mask);
2425 err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
2427 if (assign_irq_vector(irq, cfg, data->affinity))
2428 pr_err("Failed to recover vector for irq %d\n", irq);
2432 cpumask_copy(data->affinity, mask);
2438 int native_ioapic_set_affinity(struct irq_data *data,
2439 const struct cpumask *mask,
2442 unsigned int dest, irq = data->irq;
2443 unsigned long flags;
2446 if (!config_enabled(CONFIG_SMP))
2449 raw_spin_lock_irqsave(&ioapic_lock, flags);
2450 ret = __ioapic_set_affinity(data, mask, &dest);
2452 /* Only the high 8 bits are valid. */
2453 dest = SET_APIC_LOGICAL_ID(dest);
2454 __target_IO_APIC_irq(irq, dest, data->chip_data);
2455 ret = IRQ_SET_MASK_OK_NOCOPY;
2457 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2461 static void ack_apic_edge(struct irq_data *data)
2463 irq_complete_move(data->chip_data);
2468 atomic_t irq_mis_count;
2470 #ifdef CONFIG_GENERIC_PENDING_IRQ
2471 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2473 struct irq_pin_list *entry;
2474 unsigned long flags;
2476 raw_spin_lock_irqsave(&ioapic_lock, flags);
2477 for_each_irq_pin(entry, cfg->irq_2_pin) {
2482 reg = io_apic_read(entry->apic, 0x10 + pin*2);
2483 /* Is the remote IRR bit set? */
2484 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2485 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2489 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2494 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2496 /* If we are moving the irq we need to mask it */
2497 if (unlikely(irqd_is_setaffinity_pending(data))) {
2504 static inline void ioapic_irqd_unmask(struct irq_data *data,
2505 struct irq_cfg *cfg, bool masked)
2507 if (unlikely(masked)) {
2508 /* Only migrate the irq if the ack has been received.
2510 * On rare occasions the broadcast level triggered ack gets
2511 * delayed going to ioapics, and if we reprogram the
2512 * vector while Remote IRR is still set the irq will never
2515 * To prevent this scenario we read the Remote IRR bit
2516 * of the ioapic. This has two effects.
2517 * - On any sane system the read of the ioapic will
2518 * flush writes (and acks) going to the ioapic from
2520 * - We get to see if the ACK has actually been delivered.
2522 * Based on failed experiments of reprogramming the
2523 * ioapic entry from outside of irq context starting
2524 * with masking the ioapic entry and then polling until
2525 * Remote IRR was clear before reprogramming the
2526 * ioapic I don't trust the Remote IRR bit to be
2527 * completey accurate.
2529 * However there appears to be no other way to plug
2530 * this race, so if the Remote IRR bit is not
2531 * accurate and is causing problems then it is a hardware bug
2532 * and you can go talk to the chipset vendor about it.
2534 if (!io_apic_level_ack_pending(cfg))
2535 irq_move_masked_irq(data);
2540 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2544 static inline void ioapic_irqd_unmask(struct irq_data *data,
2545 struct irq_cfg *cfg, bool masked)
2550 static void ack_apic_level(struct irq_data *data)
2552 struct irq_cfg *cfg = data->chip_data;
2553 int i, irq = data->irq;
2557 irq_complete_move(cfg);
2558 masked = ioapic_irqd_mask(data, cfg);
2561 * It appears there is an erratum which affects at least version 0x11
2562 * of I/O APIC (that's the 82093AA and cores integrated into various
2563 * chipsets). Under certain conditions a level-triggered interrupt is
2564 * erroneously delivered as edge-triggered one but the respective IRR
2565 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2566 * message but it will never arrive and further interrupts are blocked
2567 * from the source. The exact reason is so far unknown, but the
2568 * phenomenon was observed when two consecutive interrupt requests
2569 * from a given source get delivered to the same CPU and the source is
2570 * temporarily disabled in between.
2572 * A workaround is to simulate an EOI message manually. We achieve it
2573 * by setting the trigger mode to edge and then to level when the edge
2574 * trigger mode gets detected in the TMR of a local APIC for a
2575 * level-triggered interrupt. We mask the source for the time of the
2576 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2577 * The idea is from Manfred Spraul. --macro
2579 * Also in the case when cpu goes offline, fixup_irqs() will forward
2580 * any unhandled interrupt on the offlined cpu to the new cpu
2581 * destination that is handling the corresponding interrupt. This
2582 * interrupt forwarding is done via IPI's. Hence, in this case also
2583 * level-triggered io-apic interrupt will be seen as an edge
2584 * interrupt in the IRR. And we can't rely on the cpu's EOI
2585 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2586 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2587 * supporting EOI register, we do an explicit EOI to clear the
2588 * remote IRR and on IO-APIC's which don't have an EOI register,
2589 * we use the above logic (mask+edge followed by unmask+level) from
2590 * Manfred Spraul to clear the remote IRR.
2593 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2596 * We must acknowledge the irq before we move it or the acknowledge will
2597 * not propagate properly.
2602 * Tail end of clearing remote IRR bit (either by delivering the EOI
2603 * message via io-apic EOI register write or simulating it using
2604 * mask+edge followed by unnask+level logic) manually when the
2605 * level triggered interrupt is seen as the edge triggered interrupt
2608 if (!(v & (1 << (i & 0x1f)))) {
2609 atomic_inc(&irq_mis_count);
2611 eoi_ioapic_irq(irq, cfg);
2614 ioapic_irqd_unmask(data, cfg, masked);
2617 static struct irq_chip ioapic_chip __read_mostly = {
2619 .irq_startup = startup_ioapic_irq,
2620 .irq_mask = mask_ioapic_irq,
2621 .irq_unmask = unmask_ioapic_irq,
2622 .irq_ack = ack_apic_edge,
2623 .irq_eoi = ack_apic_level,
2624 .irq_set_affinity = native_ioapic_set_affinity,
2625 .irq_retrigger = ioapic_retrigger_irq,
2626 .flags = IRQCHIP_SKIP_SET_WAKE,
2629 static inline void init_IO_APIC_traps(void)
2631 struct irq_cfg *cfg;
2634 for_each_active_irq(irq) {
2636 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2638 * Hmm.. We don't have an entry for this,
2639 * so default to an old-fashioned 8259
2640 * interrupt if we can..
2642 if (irq < nr_legacy_irqs())
2643 legacy_pic->make_irq(irq);
2645 /* Strange. Oh, well.. */
2646 irq_set_chip(irq, &no_irq_chip);
2652 * The local APIC irq-chip implementation:
2655 static void mask_lapic_irq(struct irq_data *data)
2659 v = apic_read(APIC_LVT0);
2660 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2663 static void unmask_lapic_irq(struct irq_data *data)
2667 v = apic_read(APIC_LVT0);
2668 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2671 static void ack_lapic_irq(struct irq_data *data)
2676 static struct irq_chip lapic_chip __read_mostly = {
2677 .name = "local-APIC",
2678 .irq_mask = mask_lapic_irq,
2679 .irq_unmask = unmask_lapic_irq,
2680 .irq_ack = ack_lapic_irq,
2683 static void lapic_register_intr(int irq)
2685 irq_clear_status_flags(irq, IRQ_LEVEL);
2686 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2691 * This looks a bit hackish but it's about the only one way of sending
2692 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2693 * not support the ExtINT mode, unfortunately. We need to send these
2694 * cycles as some i82489DX-based boards have glue logic that keeps the
2695 * 8259A interrupt line asserted until INTA. --macro
2697 static inline void __init unlock_ExtINT_logic(void)
2700 struct IO_APIC_route_entry entry0, entry1;
2701 unsigned char save_control, save_freq_select;
2703 pin = find_isa_irq_pin(8, mp_INT);
2708 apic = find_isa_irq_apic(8, mp_INT);
2714 entry0 = ioapic_read_entry(apic, pin);
2715 clear_IO_APIC_pin(apic, pin);
2717 memset(&entry1, 0, sizeof(entry1));
2719 entry1.dest_mode = 0; /* physical delivery */
2720 entry1.mask = 0; /* unmask IRQ now */
2721 entry1.dest = hard_smp_processor_id();
2722 entry1.delivery_mode = dest_ExtINT;
2723 entry1.polarity = entry0.polarity;
2727 ioapic_write_entry(apic, pin, entry1);
2729 save_control = CMOS_READ(RTC_CONTROL);
2730 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2731 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2733 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2738 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2742 CMOS_WRITE(save_control, RTC_CONTROL);
2743 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2744 clear_IO_APIC_pin(apic, pin);
2746 ioapic_write_entry(apic, pin, entry0);
2749 static int disable_timer_pin_1 __initdata;
2750 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2751 static int __init disable_timer_pin_setup(char *arg)
2753 disable_timer_pin_1 = 1;
2756 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2759 * This code may look a bit paranoid, but it's supposed to cooperate with
2760 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2761 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2762 * fanatically on his truly buggy board.
2764 * FIXME: really need to revamp this for all platforms.
2766 static inline void __init check_timer(void)
2768 struct irq_cfg *cfg = irq_cfg(0);
2769 int node = cpu_to_node(0);
2770 int apic1, pin1, apic2, pin2;
2771 unsigned long flags;
2774 local_irq_save(flags);
2777 * get/set the timer IRQ vector:
2779 legacy_pic->mask(0);
2780 assign_irq_vector(0, cfg, apic->target_cpus());
2783 * As IRQ0 is to be enabled in the 8259A, the virtual
2784 * wire has to be disabled in the local APIC. Also
2785 * timer interrupts need to be acknowledged manually in
2786 * the 8259A for the i82489DX when using the NMI
2787 * watchdog as that APIC treats NMIs as level-triggered.
2788 * The AEOI mode will finish them in the 8259A
2791 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2792 legacy_pic->init(1);
2794 pin1 = find_isa_irq_pin(0, mp_INT);
2795 apic1 = find_isa_irq_apic(0, mp_INT);
2796 pin2 = ioapic_i8259.pin;
2797 apic2 = ioapic_i8259.apic;
2799 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2800 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2801 cfg->vector, apic1, pin1, apic2, pin2);
2804 * Some BIOS writers are clueless and report the ExtINTA
2805 * I/O APIC input from the cascaded 8259A as the timer
2806 * interrupt input. So just in case, if only one pin
2807 * was found above, try it both directly and through the
2811 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2815 } else if (pin2 == -1) {
2822 * Ok, does IRQ0 through the IOAPIC work?
2825 add_pin_to_irq_node(cfg, node, apic1, pin1);
2826 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2828 /* for edge trigger, setup_ioapic_irq already
2829 * leave it unmasked.
2830 * so only need to unmask if it is level-trigger
2831 * do we really have level trigger timer?
2834 idx = find_irq_entry(apic1, pin1, mp_INT);
2835 if (idx != -1 && irq_trigger(idx))
2838 if (timer_irq_works()) {
2839 if (disable_timer_pin_1 > 0)
2840 clear_IO_APIC_pin(0, pin1);
2843 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2844 local_irq_disable();
2845 clear_IO_APIC_pin(apic1, pin1);
2847 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2848 "8254 timer not connected to IO-APIC\n");
2850 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2851 "(IRQ0) through the 8259A ...\n");
2852 apic_printk(APIC_QUIET, KERN_INFO
2853 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2855 * legacy devices should be connected to IO APIC #0
2857 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2858 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2859 legacy_pic->unmask(0);
2860 if (timer_irq_works()) {
2861 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2865 * Cleanup, just in case ...
2867 local_irq_disable();
2868 legacy_pic->mask(0);
2869 clear_IO_APIC_pin(apic2, pin2);
2870 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2873 apic_printk(APIC_QUIET, KERN_INFO
2874 "...trying to set up timer as Virtual Wire IRQ...\n");
2876 lapic_register_intr(0);
2877 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2878 legacy_pic->unmask(0);
2880 if (timer_irq_works()) {
2881 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2884 local_irq_disable();
2885 legacy_pic->mask(0);
2886 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2887 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2889 apic_printk(APIC_QUIET, KERN_INFO
2890 "...trying to set up timer as ExtINT IRQ...\n");
2892 legacy_pic->init(0);
2893 legacy_pic->make_irq(0);
2894 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2896 unlock_ExtINT_logic();
2898 if (timer_irq_works()) {
2899 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2902 local_irq_disable();
2903 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2904 if (x2apic_preenabled)
2905 apic_printk(APIC_QUIET, KERN_INFO
2906 "Perhaps problem with the pre-enabled x2apic mode\n"
2907 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2908 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2909 "report. Then try booting with the 'noapic' option.\n");
2911 local_irq_restore(flags);
2915 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2916 * to devices. However there may be an I/O APIC pin available for
2917 * this interrupt regardless. The pin may be left unconnected, but
2918 * typically it will be reused as an ExtINT cascade interrupt for
2919 * the master 8259A. In the MPS case such a pin will normally be
2920 * reported as an ExtINT interrupt in the MP table. With ACPI
2921 * there is no provision for ExtINT interrupts, and in the absence
2922 * of an override it would be treated as an ordinary ISA I/O APIC
2923 * interrupt, that is edge-triggered and unmasked by default. We
2924 * used to do this, but it caused problems on some systems because
2925 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2926 * the same ExtINT cascade interrupt to drive the local APIC of the
2927 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2928 * the I/O APIC in all cases now. No actual device should request
2929 * it anyway. --macro
2931 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2933 static int mp_irqdomain_create(int ioapic)
2936 int hwirqs = mp_ioapic_pin_count(ioapic);
2937 struct ioapic *ip = &ioapics[ioapic];
2938 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2939 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2941 size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic);
2942 ip->pin_info = kzalloc(size, GFP_KERNEL);
2946 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2949 ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2950 (void *)(long)ioapic);
2951 if(!ip->irqdomain) {
2952 kfree(ip->pin_info);
2953 ip->pin_info = NULL;
2957 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2958 cfg->type == IOAPIC_DOMAIN_STRICT)
2959 ioapic_dynirq_base = max(ioapic_dynirq_base,
2960 gsi_cfg->gsi_end + 1);
2962 if (gsi_cfg->gsi_base == 0)
2963 irq_set_default_host(ip->irqdomain);
2968 void __init setup_IO_APIC(void)
2973 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2975 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2977 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2978 for_each_ioapic(ioapic)
2979 BUG_ON(mp_irqdomain_create(ioapic));
2982 * Set up IO-APIC IRQ routing.
2984 x86_init.mpparse.setup_ioapic_ids();
2987 setup_IO_APIC_irqs();
2988 init_IO_APIC_traps();
2989 if (nr_legacy_irqs())
2992 ioapic_initialized = 1;
2996 * Called after all the initialization is done. If we didn't find any
2997 * APIC bugs then we can allow the modify fast path
3000 static int __init io_apic_bug_finalize(void)
3002 if (sis_apic_bug == -1)
3007 late_initcall(io_apic_bug_finalize);
3009 static void resume_ioapic_id(int ioapic_idx)
3011 unsigned long flags;
3012 union IO_APIC_reg_00 reg_00;
3014 raw_spin_lock_irqsave(&ioapic_lock, flags);
3015 reg_00.raw = io_apic_read(ioapic_idx, 0);
3016 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
3017 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
3018 io_apic_write(ioapic_idx, 0, reg_00.raw);
3020 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3023 static void ioapic_resume(void)
3027 for_each_ioapic_reverse(ioapic_idx)
3028 resume_ioapic_id(ioapic_idx);
3030 restore_ioapic_entries();
3033 static struct syscore_ops ioapic_syscore_ops = {
3034 .suspend = save_ioapic_entries,
3035 .resume = ioapic_resume,
3038 static int __init ioapic_init_ops(void)
3040 register_syscore_ops(&ioapic_syscore_ops);
3045 device_initcall(ioapic_init_ops);
3048 * Dynamic irq allocate and deallocation. Should be replaced by irq domains!
3050 int arch_setup_hwirq(unsigned int irq, int node)
3052 struct irq_cfg *cfg;
3053 unsigned long flags;
3056 cfg = alloc_irq_cfg(irq, node);
3060 raw_spin_lock_irqsave(&vector_lock, flags);
3061 ret = __assign_irq_vector(irq, cfg, apic->target_cpus());
3062 raw_spin_unlock_irqrestore(&vector_lock, flags);
3065 irq_set_chip_data(irq, cfg);
3067 free_irq_cfg(irq, cfg);
3071 void arch_teardown_hwirq(unsigned int irq)
3073 struct irq_cfg *cfg = irq_cfg(irq);
3074 unsigned long flags;
3076 free_remapped_irq(irq);
3077 raw_spin_lock_irqsave(&vector_lock, flags);
3078 __clear_irq_vector(irq, cfg);
3079 raw_spin_unlock_irqrestore(&vector_lock, flags);
3080 free_irq_cfg(irq, cfg);
3084 * MSI message composition
3086 void native_compose_msi_msg(struct pci_dev *pdev,
3087 unsigned int irq, unsigned int dest,
3088 struct msi_msg *msg, u8 hpet_id)
3090 struct irq_cfg *cfg = irq_cfg(irq);
3092 msg->address_hi = MSI_ADDR_BASE_HI;
3094 if (x2apic_enabled())
3095 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
3099 ((apic->irq_dest_mode == 0) ?
3100 MSI_ADDR_DEST_MODE_PHYSICAL:
3101 MSI_ADDR_DEST_MODE_LOGICAL) |
3102 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3103 MSI_ADDR_REDIRECTION_CPU:
3104 MSI_ADDR_REDIRECTION_LOWPRI) |
3105 MSI_ADDR_DEST_ID(dest);
3108 MSI_DATA_TRIGGER_EDGE |
3109 MSI_DATA_LEVEL_ASSERT |
3110 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3111 MSI_DATA_DELIVERY_FIXED:
3112 MSI_DATA_DELIVERY_LOWPRI) |
3113 MSI_DATA_VECTOR(cfg->vector);
3116 #ifdef CONFIG_PCI_MSI
3117 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3118 struct msi_msg *msg, u8 hpet_id)
3120 struct irq_cfg *cfg;
3128 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3132 err = apic->cpu_mask_to_apicid_and(cfg->domain,
3133 apic->target_cpus(), &dest);
3137 x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
3143 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3145 struct irq_cfg *cfg = data->chip_data;
3150 ret = __ioapic_set_affinity(data, mask, &dest);
3154 __get_cached_msi_msg(data->msi_desc, &msg);
3156 msg.data &= ~MSI_DATA_VECTOR_MASK;
3157 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3158 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3159 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3161 __write_msi_msg(data->msi_desc, &msg);
3163 return IRQ_SET_MASK_OK_NOCOPY;
3167 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3168 * which implement the MSI or MSI-X Capability Structure.
3170 static struct irq_chip msi_chip = {
3172 .irq_unmask = unmask_msi_irq,
3173 .irq_mask = mask_msi_irq,
3174 .irq_ack = ack_apic_edge,
3175 .irq_set_affinity = msi_set_affinity,
3176 .irq_retrigger = ioapic_retrigger_irq,
3177 .flags = IRQCHIP_SKIP_SET_WAKE,
3180 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
3181 unsigned int irq_base, unsigned int irq_offset)
3183 struct irq_chip *chip = &msi_chip;
3185 unsigned int irq = irq_base + irq_offset;
3188 ret = msi_compose_msg(dev, irq, &msg, -1);
3192 irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
3195 * MSI-X message is written per-IRQ, the offset is always 0.
3196 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
3199 write_msi_msg(irq, &msg);
3201 setup_remapped_irq(irq, irq_cfg(irq), chip);
3203 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3205 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3210 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3212 struct msi_desc *msidesc;
3216 /* Multiple MSI vectors only supported with interrupt remapping */
3217 if (type == PCI_CAP_ID_MSI && nvec > 1)
3220 node = dev_to_node(&dev->dev);
3222 list_for_each_entry(msidesc, &dev->msi_list, list) {
3223 irq = irq_alloc_hwirq(node);
3227 ret = setup_msi_irq(dev, msidesc, irq, 0);
3229 irq_free_hwirq(irq);
3237 void native_teardown_msi_irq(unsigned int irq)
3239 irq_free_hwirq(irq);
3242 #ifdef CONFIG_DMAR_TABLE
3244 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3247 struct irq_cfg *cfg = data->chip_data;
3248 unsigned int dest, irq = data->irq;
3252 ret = __ioapic_set_affinity(data, mask, &dest);
3256 dmar_msi_read(irq, &msg);
3258 msg.data &= ~MSI_DATA_VECTOR_MASK;
3259 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3260 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3261 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3262 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3264 dmar_msi_write(irq, &msg);
3266 return IRQ_SET_MASK_OK_NOCOPY;
3269 static struct irq_chip dmar_msi_type = {
3271 .irq_unmask = dmar_msi_unmask,
3272 .irq_mask = dmar_msi_mask,
3273 .irq_ack = ack_apic_edge,
3274 .irq_set_affinity = dmar_msi_set_affinity,
3275 .irq_retrigger = ioapic_retrigger_irq,
3276 .flags = IRQCHIP_SKIP_SET_WAKE,
3279 int arch_setup_dmar_msi(unsigned int irq)
3284 ret = msi_compose_msg(NULL, irq, &msg, -1);
3287 dmar_msi_write(irq, &msg);
3288 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3294 #ifdef CONFIG_HPET_TIMER
3296 static int hpet_msi_set_affinity(struct irq_data *data,
3297 const struct cpumask *mask, bool force)
3299 struct irq_cfg *cfg = data->chip_data;
3304 ret = __ioapic_set_affinity(data, mask, &dest);
3308 hpet_msi_read(data->handler_data, &msg);
3310 msg.data &= ~MSI_DATA_VECTOR_MASK;
3311 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3312 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3313 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3315 hpet_msi_write(data->handler_data, &msg);
3317 return IRQ_SET_MASK_OK_NOCOPY;
3320 static struct irq_chip hpet_msi_type = {
3322 .irq_unmask = hpet_msi_unmask,
3323 .irq_mask = hpet_msi_mask,
3324 .irq_ack = ack_apic_edge,
3325 .irq_set_affinity = hpet_msi_set_affinity,
3326 .irq_retrigger = ioapic_retrigger_irq,
3327 .flags = IRQCHIP_SKIP_SET_WAKE,
3330 int default_setup_hpet_msi(unsigned int irq, unsigned int id)
3332 struct irq_chip *chip = &hpet_msi_type;
3336 ret = msi_compose_msg(NULL, irq, &msg, id);
3340 hpet_msi_write(irq_get_handler_data(irq), &msg);
3341 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3342 setup_remapped_irq(irq, irq_cfg(irq), chip);
3344 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3349 #endif /* CONFIG_PCI_MSI */
3351 * Hypertransport interrupt support
3353 #ifdef CONFIG_HT_IRQ
3355 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3357 struct ht_irq_msg msg;
3358 fetch_ht_irq_msg(irq, &msg);
3360 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3361 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3363 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3364 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3366 write_ht_irq_msg(irq, &msg);
3370 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3372 struct irq_cfg *cfg = data->chip_data;
3376 ret = __ioapic_set_affinity(data, mask, &dest);
3380 target_ht_irq(data->irq, dest, cfg->vector);
3381 return IRQ_SET_MASK_OK_NOCOPY;
3384 static struct irq_chip ht_irq_chip = {
3386 .irq_mask = mask_ht_irq,
3387 .irq_unmask = unmask_ht_irq,
3388 .irq_ack = ack_apic_edge,
3389 .irq_set_affinity = ht_set_affinity,
3390 .irq_retrigger = ioapic_retrigger_irq,
3391 .flags = IRQCHIP_SKIP_SET_WAKE,
3394 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3396 struct irq_cfg *cfg;
3397 struct ht_irq_msg msg;
3405 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3409 err = apic->cpu_mask_to_apicid_and(cfg->domain,
3410 apic->target_cpus(), &dest);
3414 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3418 HT_IRQ_LOW_DEST_ID(dest) |
3419 HT_IRQ_LOW_VECTOR(cfg->vector) |
3420 ((apic->irq_dest_mode == 0) ?
3421 HT_IRQ_LOW_DM_PHYSICAL :
3422 HT_IRQ_LOW_DM_LOGICAL) |
3423 HT_IRQ_LOW_RQEOI_EDGE |
3424 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3425 HT_IRQ_LOW_MT_FIXED :
3426 HT_IRQ_LOW_MT_ARBITRATED) |
3427 HT_IRQ_LOW_IRQ_MASKED;
3429 write_ht_irq_msg(irq, &msg);
3431 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3432 handle_edge_irq, "edge");
3434 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3438 #endif /* CONFIG_HT_IRQ */
3441 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3443 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3448 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3450 setup_ioapic_irq(irq, cfg, attr);
3454 static int __init io_apic_get_redir_entries(int ioapic)
3456 union IO_APIC_reg_01 reg_01;
3457 unsigned long flags;
3459 raw_spin_lock_irqsave(&ioapic_lock, flags);
3460 reg_01.raw = io_apic_read(ioapic, 1);
3461 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3463 /* The register returns the maximum index redir index
3464 * supported, which is one less than the total number of redir
3467 return reg_01.bits.entries + 1;
3470 unsigned int arch_dynirq_lower_bound(unsigned int from)
3473 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
3474 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
3476 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
3479 int __init arch_probe_nr_irqs(void)
3483 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3484 nr_irqs = NR_VECTORS * nr_cpu_ids;
3486 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
3487 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3489 * for MSI and HT dyn irq
3499 #ifdef CONFIG_X86_32
3500 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3502 union IO_APIC_reg_00 reg_00;
3503 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3505 unsigned long flags;
3509 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3510 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3511 * supports up to 16 on one shared APIC bus.
3513 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3514 * advantage of new APIC bus architecture.
3517 if (physids_empty(apic_id_map))
3518 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3520 raw_spin_lock_irqsave(&ioapic_lock, flags);
3521 reg_00.raw = io_apic_read(ioapic, 0);
3522 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3524 if (apic_id >= get_physical_broadcast()) {
3525 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3526 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3527 apic_id = reg_00.bits.ID;
3531 * Every APIC in a system must have a unique ID or we get lots of nice
3532 * 'stuck on smp_invalidate_needed IPI wait' messages.
3534 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3536 for (i = 0; i < get_physical_broadcast(); i++) {
3537 if (!apic->check_apicid_used(&apic_id_map, i))
3541 if (i == get_physical_broadcast())
3542 panic("Max apic_id exceeded!\n");
3544 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3545 "trying %d\n", ioapic, apic_id, i);
3550 apic->apicid_to_cpu_present(apic_id, &tmp);
3551 physids_or(apic_id_map, apic_id_map, tmp);
3553 if (reg_00.bits.ID != apic_id) {
3554 reg_00.bits.ID = apic_id;
3556 raw_spin_lock_irqsave(&ioapic_lock, flags);
3557 io_apic_write(ioapic, 0, reg_00.raw);
3558 reg_00.raw = io_apic_read(ioapic, 0);
3559 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3562 if (reg_00.bits.ID != apic_id) {
3563 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3569 apic_printk(APIC_VERBOSE, KERN_INFO
3570 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3575 static u8 __init io_apic_unique_id(u8 id)
3577 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3578 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3579 return io_apic_get_unique_id(nr_ioapics, id);
3584 static u8 __init io_apic_unique_id(u8 id)
3587 DECLARE_BITMAP(used, 256);
3589 bitmap_zero(used, 256);
3591 __set_bit(mpc_ioapic_id(i), used);
3592 if (!test_bit(id, used))
3594 return find_first_zero_bit(used, 256);
3598 static int __init io_apic_get_version(int ioapic)
3600 union IO_APIC_reg_01 reg_01;
3601 unsigned long flags;
3603 raw_spin_lock_irqsave(&ioapic_lock, flags);
3604 reg_01.raw = io_apic_read(ioapic, 1);
3605 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3607 return reg_01.bits.version;
3610 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3612 int ioapic, pin, idx;
3614 if (skip_ioapic_setup)
3617 ioapic = mp_find_ioapic(gsi);
3621 pin = mp_find_ioapic_pin(ioapic, gsi);
3625 idx = find_irq_entry(ioapic, pin, mp_INT);
3629 *trigger = irq_trigger(idx);
3630 *polarity = irq_polarity(idx);
3635 * This function currently is only a helper for the i386 smp boot process where
3636 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3637 * so mask in all cases should simply be apic->target_cpus()
3640 void __init setup_ioapic_dest(void)
3642 int pin, ioapic, irq, irq_entry;
3643 const struct cpumask *mask;
3644 struct irq_data *idata;
3646 if (skip_ioapic_setup == 1)
3649 for_each_ioapic_pin(ioapic, pin) {
3650 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3651 if (irq_entry == -1)
3654 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
3655 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
3658 idata = irq_get_irq_data(irq);
3661 * Honour affinities which have been set in early boot
3663 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3664 mask = idata->affinity;
3666 mask = apic->target_cpus();
3668 x86_io_apic_ops.set_affinity(idata, mask, false);
3674 #define IOAPIC_RESOURCE_NAME_SIZE 11
3676 static struct resource *ioapic_resources;
3678 static struct resource * __init ioapic_setup_resources(void)
3681 struct resource *res;
3690 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3693 mem = alloc_bootmem(n);
3696 mem += sizeof(struct resource) * num;
3699 for_each_ioapic(i) {
3700 res[num].name = mem;
3701 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3702 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3703 mem += IOAPIC_RESOURCE_NAME_SIZE;
3707 ioapic_resources = res;
3712 void __init native_io_apic_init_mappings(void)
3714 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3715 struct resource *ioapic_res;
3718 ioapic_res = ioapic_setup_resources();
3719 for_each_ioapic(i) {
3720 if (smp_found_config) {
3721 ioapic_phys = mpc_ioapic_addr(i);
3722 #ifdef CONFIG_X86_32
3725 "WARNING: bogus zero IO-APIC "
3726 "address found in MPTABLE, "
3727 "disabling IO/APIC support!\n");
3728 smp_found_config = 0;
3729 skip_ioapic_setup = 1;
3730 goto fake_ioapic_page;
3734 #ifdef CONFIG_X86_32
3737 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3738 ioapic_phys = __pa(ioapic_phys);
3740 set_fixmap_nocache(idx, ioapic_phys);
3741 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3742 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3746 ioapic_res->start = ioapic_phys;
3747 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3752 void __init ioapic_insert_resources(void)
3755 struct resource *r = ioapic_resources;
3760 "IO APIC resources couldn't be allocated.\n");
3764 for_each_ioapic(i) {
3765 insert_resource(&iomem_resource, r);
3770 int mp_find_ioapic(u32 gsi)
3774 if (nr_ioapics == 0)
3777 /* Find the IOAPIC that manages this GSI. */
3778 for_each_ioapic(i) {
3779 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3780 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
3784 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3788 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3790 struct mp_ioapic_gsi *gsi_cfg;
3792 if (WARN_ON(ioapic < 0))
3795 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3796 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3799 return gsi - gsi_cfg->gsi_base;
3802 static __init int bad_ioapic(unsigned long address)
3804 if (nr_ioapics >= MAX_IO_APICS) {
3805 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3806 MAX_IO_APICS, nr_ioapics);
3810 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3816 static __init int bad_ioapic_register(int idx)
3818 union IO_APIC_reg_00 reg_00;
3819 union IO_APIC_reg_01 reg_01;
3820 union IO_APIC_reg_02 reg_02;
3822 reg_00.raw = io_apic_read(idx, 0);
3823 reg_01.raw = io_apic_read(idx, 1);
3824 reg_02.raw = io_apic_read(idx, 2);
3826 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3827 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3828 mpc_ioapic_addr(idx));
3835 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base,
3836 struct ioapic_domain_cfg *cfg)
3840 struct mp_ioapic_gsi *gsi_cfg;
3842 if (bad_ioapic(address))
3847 ioapics[idx].mp_config.type = MP_IOAPIC;
3848 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3849 ioapics[idx].mp_config.apicaddr = address;
3850 ioapics[idx].irqdomain = NULL;
3851 ioapics[idx].irqdomain_cfg = *cfg;
3853 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3855 if (bad_ioapic_register(idx)) {
3856 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3860 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3861 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3864 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3865 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3867 entries = io_apic_get_redir_entries(idx);
3868 gsi_cfg = mp_ioapic_gsi_routing(idx);
3869 gsi_cfg->gsi_base = gsi_base;
3870 gsi_cfg->gsi_end = gsi_base + entries - 1;
3873 * The number of IO-APIC IRQ registers (== #pins):
3875 ioapics[idx].nr_registers = entries;
3877 if (gsi_cfg->gsi_end >= gsi_top)
3878 gsi_top = gsi_cfg->gsi_end + 1;
3880 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3881 idx, mpc_ioapic_id(idx),
3882 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3883 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3888 int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
3889 irq_hw_number_t hwirq)
3891 int ioapic = (int)(long)domain->host_data;
3892 struct mp_pin_info *info = mp_pin_info(ioapic, hwirq);
3893 struct io_apic_irq_attr attr;
3895 /* Get default attribute if not set by caller yet */
3897 u32 gsi = mp_pin_to_gsi(ioapic, hwirq);
3899 if (acpi_get_override_irq(gsi, &info->trigger,
3900 &info->polarity) < 0) {
3902 * PCI interrupts are always polarity one level
3908 info->node = NUMA_NO_NODE;
3911 * setup_IO_APIC_irqs() programs all legacy IRQs with default
3912 * trigger and polarity attributes. Don't set the flag for that
3913 * case so the first legacy IRQ user could reprogram the pin
3914 * with real trigger and polarity attributes.
3916 if (virq >= nr_legacy_irqs() || info->count)
3919 set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
3922 return io_apic_setup_irq_pin(virq, info->node, &attr);
3925 void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq)
3927 struct irq_data *data = irq_get_irq_data(virq);
3928 struct irq_cfg *cfg = irq_cfg(virq);
3929 int ioapic = (int)(long)domain->host_data;
3930 int pin = (int)data->hwirq;
3932 ioapic_mask_entry(ioapic, pin);
3933 __remove_pin_from_irq(cfg, ioapic, pin);
3934 WARN_ON(cfg->irq_2_pin != NULL);
3935 arch_teardown_hwirq(virq);
3938 int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
3942 struct mp_pin_info *info;
3944 ioapic = mp_find_ioapic(gsi);
3948 pin = mp_find_ioapic_pin(ioapic, gsi);
3949 info = mp_pin_info(ioapic, pin);
3950 trigger = trigger ? 1 : 0;
3951 polarity = polarity ? 1 : 0;
3953 mutex_lock(&ioapic_mutex);
3955 info->trigger = trigger;
3956 info->polarity = polarity;
3959 } else if (info->trigger != trigger || info->polarity != polarity) {
3962 mutex_unlock(&ioapic_mutex);
3967 bool mp_should_keep_irq(struct device *dev)
3969 if (dev->power.is_prepared)
3971 #ifdef CONFIG_PM_RUNTIME
3972 if (dev->power.runtime_status == RPM_SUSPENDING)
3979 /* Enable IOAPIC early just for system timer */
3980 void __init pre_init_apic_IRQ0(void)
3982 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3984 printk(KERN_INFO "Early APIC setup for system timer0\n");
3986 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3987 &phys_cpu_present_map);
3991 io_apic_setup_irq_pin(0, 0, &attr);
3992 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,