2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
97 /* Number of legacy interrupts */
98 static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY;
100 static int nr_irqs_gsi = NR_IRQS_LEGACY;
102 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
103 int mp_bus_id_to_type[MAX_MP_BUSSES];
106 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
108 int skip_ioapic_setup;
110 void arch_disable_smp_support(void)
114 noioapicreroute = -1;
116 skip_ioapic_setup = 1;
119 static int __init parse_noapic(char *str)
121 /* disable IO-APIC */
122 arch_disable_smp_support();
125 early_param("noapic", parse_noapic);
127 struct irq_pin_list {
129 struct irq_pin_list *next;
132 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
134 struct irq_pin_list *pin;
136 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
141 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
142 #ifdef CONFIG_SPARSE_IRQ
143 static struct irq_cfg irq_cfgx[] = {
145 static struct irq_cfg irq_cfgx[NR_IRQS] = {
147 [0] = { .vector = IRQ0_VECTOR, },
148 [1] = { .vector = IRQ1_VECTOR, },
149 [2] = { .vector = IRQ2_VECTOR, },
150 [3] = { .vector = IRQ3_VECTOR, },
151 [4] = { .vector = IRQ4_VECTOR, },
152 [5] = { .vector = IRQ5_VECTOR, },
153 [6] = { .vector = IRQ6_VECTOR, },
154 [7] = { .vector = IRQ7_VECTOR, },
155 [8] = { .vector = IRQ8_VECTOR, },
156 [9] = { .vector = IRQ9_VECTOR, },
157 [10] = { .vector = IRQ10_VECTOR, },
158 [11] = { .vector = IRQ11_VECTOR, },
159 [12] = { .vector = IRQ12_VECTOR, },
160 [13] = { .vector = IRQ13_VECTOR, },
161 [14] = { .vector = IRQ14_VECTOR, },
162 [15] = { .vector = IRQ15_VECTOR, },
165 void __init io_apic_disable_legacy(void)
171 int __init arch_early_irq_init(void)
174 struct irq_desc *desc;
180 count = ARRAY_SIZE(irq_cfgx);
181 node= cpu_to_node(boot_cpu_id);
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
187 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
188 if (i < nr_legacy_irqs)
189 cpumask_setall(cfg[i].domain);
195 #ifdef CONFIG_SPARSE_IRQ
196 struct irq_cfg *irq_cfg(unsigned int irq)
198 struct irq_cfg *cfg = NULL;
199 struct irq_desc *desc;
201 desc = irq_to_desc(irq);
203 cfg = desc->chip_data;
208 static struct irq_cfg *get_one_free_irq_cfg(int node)
212 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
214 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
217 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
219 free_cpumask_var(cfg->domain);
228 int arch_init_chip_data(struct irq_desc *desc, int node)
232 cfg = desc->chip_data;
234 desc->chip_data = get_one_free_irq_cfg(node);
235 if (!desc->chip_data) {
236 printk(KERN_ERR "can not alloc irq_cfg\n");
244 /* for move_irq_desc */
246 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
248 struct irq_pin_list *old_entry, *head, *tail, *entry;
250 cfg->irq_2_pin = NULL;
251 old_entry = old_cfg->irq_2_pin;
255 entry = get_one_free_irq_2_pin(node);
259 entry->apic = old_entry->apic;
260 entry->pin = old_entry->pin;
263 old_entry = old_entry->next;
265 entry = get_one_free_irq_2_pin(node);
273 /* still use the old one */
276 entry->apic = old_entry->apic;
277 entry->pin = old_entry->pin;
280 old_entry = old_entry->next;
284 cfg->irq_2_pin = head;
287 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
289 struct irq_pin_list *entry, *next;
291 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
294 entry = old_cfg->irq_2_pin;
301 old_cfg->irq_2_pin = NULL;
304 void arch_init_copy_chip_data(struct irq_desc *old_desc,
305 struct irq_desc *desc, int node)
308 struct irq_cfg *old_cfg;
310 cfg = get_one_free_irq_cfg(node);
315 desc->chip_data = cfg;
317 old_cfg = old_desc->chip_data;
319 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
321 init_copy_irq_2_pin(old_cfg, cfg, node);
324 static void free_irq_cfg(struct irq_cfg *old_cfg)
329 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
331 struct irq_cfg *old_cfg, *cfg;
333 old_cfg = old_desc->chip_data;
334 cfg = desc->chip_data;
340 free_irq_2_pin(old_cfg, cfg);
341 free_irq_cfg(old_cfg);
342 old_desc->chip_data = NULL;
345 /* end for move_irq_desc */
348 struct irq_cfg *irq_cfg(unsigned int irq)
350 return irq < nr_irqs ? irq_cfgx + irq : NULL;
357 unsigned int unused[3];
359 unsigned int unused2[11];
363 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
365 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
366 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
369 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
371 struct io_apic __iomem *io_apic = io_apic_base(apic);
372 writel(vector, &io_apic->eoi);
375 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
377 struct io_apic __iomem *io_apic = io_apic_base(apic);
378 writel(reg, &io_apic->index);
379 return readl(&io_apic->data);
382 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 writel(value, &io_apic->data);
390 * Re-write a value: to be used for read-modify-write
391 * cycles where the read already set up the index register.
393 * Older SiS APIC requires we rewrite the index register
395 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
397 struct io_apic __iomem *io_apic = io_apic_base(apic);
400 writel(reg, &io_apic->index);
401 writel(value, &io_apic->data);
404 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
406 struct irq_pin_list *entry;
409 spin_lock_irqsave(&ioapic_lock, flags);
410 for_each_irq_pin(entry, cfg->irq_2_pin) {
415 reg = io_apic_read(entry->apic, 0x10 + pin*2);
416 /* Is the remote IRR bit set? */
417 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
418 spin_unlock_irqrestore(&ioapic_lock, flags);
422 spin_unlock_irqrestore(&ioapic_lock, flags);
428 struct { u32 w1, w2; };
429 struct IO_APIC_route_entry entry;
432 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
434 union entry_union eu;
436 spin_lock_irqsave(&ioapic_lock, flags);
437 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
438 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
439 spin_unlock_irqrestore(&ioapic_lock, flags);
444 * When we write a new IO APIC routing entry, we need to write the high
445 * word first! If the mask bit in the low word is clear, we will enable
446 * the interrupt, and we need to make sure the entry is fully populated
447 * before that happens.
450 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
452 union entry_union eu = {{0, 0}};
455 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
456 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
459 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
462 spin_lock_irqsave(&ioapic_lock, flags);
463 __ioapic_write_entry(apic, pin, e);
464 spin_unlock_irqrestore(&ioapic_lock, flags);
468 * When we mask an IO APIC routing entry, we need to write the low
469 * word first, in order to set the mask bit before we change the
472 static void ioapic_mask_entry(int apic, int pin)
475 union entry_union eu = { .entry.mask = 1 };
477 spin_lock_irqsave(&ioapic_lock, flags);
478 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
479 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
480 spin_unlock_irqrestore(&ioapic_lock, flags);
484 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
485 * shared ISA-space IRQs, so we have to support them. We are super
486 * fast in the common case, and fast for shared ISA-space IRQs.
489 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
491 struct irq_pin_list **last, *entry;
493 /* don't allow duplicates */
494 last = &cfg->irq_2_pin;
495 for_each_irq_pin(entry, cfg->irq_2_pin) {
496 if (entry->apic == apic && entry->pin == pin)
501 entry = get_one_free_irq_2_pin(node);
503 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
514 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
516 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
517 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
521 * Reroute an IRQ to a different pin.
523 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
524 int oldapic, int oldpin,
525 int newapic, int newpin)
527 struct irq_pin_list *entry;
529 for_each_irq_pin(entry, cfg->irq_2_pin) {
530 if (entry->apic == oldapic && entry->pin == oldpin) {
531 entry->apic = newapic;
533 /* every one is different, right? */
538 /* old apic/pin didn't exist, so just add new ones */
539 add_pin_to_irq_node(cfg, node, newapic, newpin);
542 static void io_apic_modify_irq(struct irq_cfg *cfg,
543 int mask_and, int mask_or,
544 void (*final)(struct irq_pin_list *entry))
547 struct irq_pin_list *entry;
549 for_each_irq_pin(entry, cfg->irq_2_pin) {
552 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
555 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
561 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
563 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
566 static void io_apic_sync(struct irq_pin_list *entry)
569 * Synchronize the IO-APIC and the CPU by doing
570 * a dummy read from the IO-APIC
572 struct io_apic __iomem *io_apic;
573 io_apic = io_apic_base(entry->apic);
574 readl(&io_apic->data);
577 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
579 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
582 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
584 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
585 IO_APIC_REDIR_MASKED, NULL);
588 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
590 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
591 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
594 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
596 struct irq_cfg *cfg = desc->chip_data;
601 spin_lock_irqsave(&ioapic_lock, flags);
602 __mask_IO_APIC_irq(cfg);
603 spin_unlock_irqrestore(&ioapic_lock, flags);
606 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
608 struct irq_cfg *cfg = desc->chip_data;
611 spin_lock_irqsave(&ioapic_lock, flags);
612 __unmask_IO_APIC_irq(cfg);
613 spin_unlock_irqrestore(&ioapic_lock, flags);
616 static void mask_IO_APIC_irq(unsigned int irq)
618 struct irq_desc *desc = irq_to_desc(irq);
620 mask_IO_APIC_irq_desc(desc);
622 static void unmask_IO_APIC_irq(unsigned int irq)
624 struct irq_desc *desc = irq_to_desc(irq);
626 unmask_IO_APIC_irq_desc(desc);
629 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
631 struct IO_APIC_route_entry entry;
633 /* Check delivery_mode to be sure we're not clearing an SMI pin */
634 entry = ioapic_read_entry(apic, pin);
635 if (entry.delivery_mode == dest_SMI)
638 * Disable it in the IO-APIC irq-routing table:
640 ioapic_mask_entry(apic, pin);
643 static void clear_IO_APIC (void)
647 for (apic = 0; apic < nr_ioapics; apic++)
648 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
649 clear_IO_APIC_pin(apic, pin);
654 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
655 * specific CPU-side IRQs.
659 static int pirq_entries[MAX_PIRQS] = {
660 [0 ... MAX_PIRQS - 1] = -1
663 static int __init ioapic_pirq_setup(char *str)
666 int ints[MAX_PIRQS+1];
668 get_options(str, ARRAY_SIZE(ints), ints);
670 apic_printk(APIC_VERBOSE, KERN_INFO
671 "PIRQ redirection, working around broken MP-BIOS.\n");
673 if (ints[0] < MAX_PIRQS)
676 for (i = 0; i < max; i++) {
677 apic_printk(APIC_VERBOSE, KERN_DEBUG
678 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
680 * PIRQs are mapped upside down, usually.
682 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
687 __setup("pirq=", ioapic_pirq_setup);
688 #endif /* CONFIG_X86_32 */
690 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
693 struct IO_APIC_route_entry **ioapic_entries;
695 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
700 for (apic = 0; apic < nr_ioapics; apic++) {
701 ioapic_entries[apic] =
702 kzalloc(sizeof(struct IO_APIC_route_entry) *
703 nr_ioapic_registers[apic], GFP_ATOMIC);
704 if (!ioapic_entries[apic])
708 return ioapic_entries;
712 kfree(ioapic_entries[apic]);
713 kfree(ioapic_entries);
719 * Saves all the IO-APIC RTE's
721 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
728 for (apic = 0; apic < nr_ioapics; apic++) {
729 if (!ioapic_entries[apic])
732 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
733 ioapic_entries[apic][pin] =
734 ioapic_read_entry(apic, pin);
741 * Mask all IO APIC entries.
743 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
750 for (apic = 0; apic < nr_ioapics; apic++) {
751 if (!ioapic_entries[apic])
754 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
755 struct IO_APIC_route_entry entry;
757 entry = ioapic_entries[apic][pin];
760 ioapic_write_entry(apic, pin, entry);
767 * Restore IO APIC entries which was saved in ioapic_entries.
769 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
776 for (apic = 0; apic < nr_ioapics; apic++) {
777 if (!ioapic_entries[apic])
780 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
781 ioapic_write_entry(apic, pin,
782 ioapic_entries[apic][pin]);
787 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
791 for (apic = 0; apic < nr_ioapics; apic++)
792 kfree(ioapic_entries[apic]);
794 kfree(ioapic_entries);
798 * Find the IRQ entry number of a certain pin.
800 static int find_irq_entry(int apic, int pin, int type)
804 for (i = 0; i < mp_irq_entries; i++)
805 if (mp_irqs[i].irqtype == type &&
806 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
807 mp_irqs[i].dstapic == MP_APIC_ALL) &&
808 mp_irqs[i].dstirq == pin)
815 * Find the pin to which IRQ[irq] (ISA) is connected
817 static int __init find_isa_irq_pin(int irq, int type)
821 for (i = 0; i < mp_irq_entries; i++) {
822 int lbus = mp_irqs[i].srcbus;
824 if (test_bit(lbus, mp_bus_not_pci) &&
825 (mp_irqs[i].irqtype == type) &&
826 (mp_irqs[i].srcbusirq == irq))
828 return mp_irqs[i].dstirq;
833 static int __init find_isa_irq_apic(int irq, int type)
837 for (i = 0; i < mp_irq_entries; i++) {
838 int lbus = mp_irqs[i].srcbus;
840 if (test_bit(lbus, mp_bus_not_pci) &&
841 (mp_irqs[i].irqtype == type) &&
842 (mp_irqs[i].srcbusirq == irq))
845 if (i < mp_irq_entries) {
847 for(apic = 0; apic < nr_ioapics; apic++) {
848 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
856 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
858 * EISA Edge/Level control register, ELCR
860 static int EISA_ELCR(unsigned int irq)
862 if (irq < nr_legacy_irqs) {
863 unsigned int port = 0x4d0 + (irq >> 3);
864 return (inb(port) >> (irq & 7)) & 1;
866 apic_printk(APIC_VERBOSE, KERN_INFO
867 "Broken MPtable reports ISA irq %d\n", irq);
873 /* ISA interrupts are always polarity zero edge triggered,
874 * when listed as conforming in the MP table. */
876 #define default_ISA_trigger(idx) (0)
877 #define default_ISA_polarity(idx) (0)
879 /* EISA interrupts are always polarity zero and can be edge or level
880 * trigger depending on the ELCR value. If an interrupt is listed as
881 * EISA conforming in the MP table, that means its trigger type must
882 * be read in from the ELCR */
884 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
885 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
887 /* PCI interrupts are always polarity one level triggered,
888 * when listed as conforming in the MP table. */
890 #define default_PCI_trigger(idx) (1)
891 #define default_PCI_polarity(idx) (1)
893 /* MCA interrupts are always polarity zero level triggered,
894 * when listed as conforming in the MP table. */
896 #define default_MCA_trigger(idx) (1)
897 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
899 static int MPBIOS_polarity(int idx)
901 int bus = mp_irqs[idx].srcbus;
905 * Determine IRQ line polarity (high active or low active):
907 switch (mp_irqs[idx].irqflag & 3)
909 case 0: /* conforms, ie. bus-type dependent polarity */
910 if (test_bit(bus, mp_bus_not_pci))
911 polarity = default_ISA_polarity(idx);
913 polarity = default_PCI_polarity(idx);
915 case 1: /* high active */
920 case 2: /* reserved */
922 printk(KERN_WARNING "broken BIOS!!\n");
926 case 3: /* low active */
931 default: /* invalid */
933 printk(KERN_WARNING "broken BIOS!!\n");
941 static int MPBIOS_trigger(int idx)
943 int bus = mp_irqs[idx].srcbus;
947 * Determine IRQ trigger mode (edge or level sensitive):
949 switch ((mp_irqs[idx].irqflag>>2) & 3)
951 case 0: /* conforms, ie. bus-type dependent */
952 if (test_bit(bus, mp_bus_not_pci))
953 trigger = default_ISA_trigger(idx);
955 trigger = default_PCI_trigger(idx);
956 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
957 switch (mp_bus_id_to_type[bus]) {
958 case MP_BUS_ISA: /* ISA pin */
960 /* set before the switch */
963 case MP_BUS_EISA: /* EISA pin */
965 trigger = default_EISA_trigger(idx);
968 case MP_BUS_PCI: /* PCI pin */
970 /* set before the switch */
973 case MP_BUS_MCA: /* MCA pin */
975 trigger = default_MCA_trigger(idx);
980 printk(KERN_WARNING "broken BIOS!!\n");
992 case 2: /* reserved */
994 printk(KERN_WARNING "broken BIOS!!\n");
1003 default: /* invalid */
1005 printk(KERN_WARNING "broken BIOS!!\n");
1013 static inline int irq_polarity(int idx)
1015 return MPBIOS_polarity(idx);
1018 static inline int irq_trigger(int idx)
1020 return MPBIOS_trigger(idx);
1023 int (*ioapic_renumber_irq)(int ioapic, int irq);
1024 static int pin_2_irq(int idx, int apic, int pin)
1027 int bus = mp_irqs[idx].srcbus;
1030 * Debugging check, we are in big trouble if this message pops up!
1032 if (mp_irqs[idx].dstirq != pin)
1033 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1035 if (test_bit(bus, mp_bus_not_pci)) {
1036 irq = mp_irqs[idx].srcbusirq;
1039 * PCI IRQs are mapped in order
1043 irq += nr_ioapic_registers[i++];
1046 * For MPS mode, so far only needed by ES7000 platform
1048 if (ioapic_renumber_irq)
1049 irq = ioapic_renumber_irq(apic, irq);
1052 #ifdef CONFIG_X86_32
1054 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1056 if ((pin >= 16) && (pin <= 23)) {
1057 if (pirq_entries[pin-16] != -1) {
1058 if (!pirq_entries[pin-16]) {
1059 apic_printk(APIC_VERBOSE, KERN_DEBUG
1060 "disabling PIRQ%d\n", pin-16);
1062 irq = pirq_entries[pin-16];
1063 apic_printk(APIC_VERBOSE, KERN_DEBUG
1064 "using PIRQ%d -> IRQ %d\n",
1075 * Find a specific PCI IRQ entry.
1076 * Not an __init, possibly needed by modules
1078 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1079 struct io_apic_irq_attr *irq_attr)
1081 int apic, i, best_guess = -1;
1083 apic_printk(APIC_DEBUG,
1084 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1086 if (test_bit(bus, mp_bus_not_pci)) {
1087 apic_printk(APIC_VERBOSE,
1088 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1091 for (i = 0; i < mp_irq_entries; i++) {
1092 int lbus = mp_irqs[i].srcbus;
1094 for (apic = 0; apic < nr_ioapics; apic++)
1095 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1096 mp_irqs[i].dstapic == MP_APIC_ALL)
1099 if (!test_bit(lbus, mp_bus_not_pci) &&
1100 !mp_irqs[i].irqtype &&
1102 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1103 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1105 if (!(apic || IO_APIC_IRQ(irq)))
1108 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1109 set_io_apic_irq_attr(irq_attr, apic,
1116 * Use the first all-but-pin matching entry as a
1117 * best-guess fuzzy result for broken mptables.
1119 if (best_guess < 0) {
1120 set_io_apic_irq_attr(irq_attr, apic,
1130 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1132 void lock_vector_lock(void)
1134 /* Used to the online set of cpus does not change
1135 * during assign_irq_vector.
1137 spin_lock(&vector_lock);
1140 void unlock_vector_lock(void)
1142 spin_unlock(&vector_lock);
1146 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1149 * NOTE! The local APIC isn't very good at handling
1150 * multiple interrupts at the same interrupt level.
1151 * As the interrupt level is determined by taking the
1152 * vector number and shifting that right by 4, we
1153 * want to spread these out a bit so that they don't
1154 * all fall in the same interrupt level.
1156 * Also, we've got to be careful not to trash gate
1157 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1159 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1160 unsigned int old_vector;
1162 cpumask_var_t tmp_mask;
1164 if (cfg->move_in_progress)
1167 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1170 old_vector = cfg->vector;
1172 cpumask_and(tmp_mask, mask, cpu_online_mask);
1173 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1174 if (!cpumask_empty(tmp_mask)) {
1175 free_cpumask_var(tmp_mask);
1180 /* Only try and allocate irqs on cpus that are present */
1182 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1186 apic->vector_allocation_domain(cpu, tmp_mask);
1188 vector = current_vector;
1189 offset = current_offset;
1192 if (vector >= first_system_vector) {
1193 /* If out of vectors on large boxen, must share them. */
1194 offset = (offset + 1) % 8;
1195 vector = FIRST_DEVICE_VECTOR + offset;
1197 if (unlikely(current_vector == vector))
1200 if (test_bit(vector, used_vectors))
1203 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1204 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1207 current_vector = vector;
1208 current_offset = offset;
1210 cfg->move_in_progress = 1;
1211 cpumask_copy(cfg->old_domain, cfg->domain);
1213 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1214 per_cpu(vector_irq, new_cpu)[vector] = irq;
1215 cfg->vector = vector;
1216 cpumask_copy(cfg->domain, tmp_mask);
1220 free_cpumask_var(tmp_mask);
1224 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1227 unsigned long flags;
1229 spin_lock_irqsave(&vector_lock, flags);
1230 err = __assign_irq_vector(irq, cfg, mask);
1231 spin_unlock_irqrestore(&vector_lock, flags);
1235 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1239 BUG_ON(!cfg->vector);
1241 vector = cfg->vector;
1242 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1243 per_cpu(vector_irq, cpu)[vector] = -1;
1246 cpumask_clear(cfg->domain);
1248 if (likely(!cfg->move_in_progress))
1250 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1251 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1253 if (per_cpu(vector_irq, cpu)[vector] != irq)
1255 per_cpu(vector_irq, cpu)[vector] = -1;
1259 cfg->move_in_progress = 0;
1262 void __setup_vector_irq(int cpu)
1264 /* Initialize vector_irq on a new cpu */
1265 /* This function must be called with vector_lock held */
1267 struct irq_cfg *cfg;
1268 struct irq_desc *desc;
1270 /* Mark the inuse vectors */
1271 for_each_irq_desc(irq, desc) {
1272 cfg = desc->chip_data;
1273 if (!cpumask_test_cpu(cpu, cfg->domain))
1275 vector = cfg->vector;
1276 per_cpu(vector_irq, cpu)[vector] = irq;
1278 /* Mark the free vectors */
1279 for (vector = 0; vector < NR_VECTORS; ++vector) {
1280 irq = per_cpu(vector_irq, cpu)[vector];
1285 if (!cpumask_test_cpu(cpu, cfg->domain))
1286 per_cpu(vector_irq, cpu)[vector] = -1;
1290 static struct irq_chip ioapic_chip;
1291 static struct irq_chip ir_ioapic_chip;
1293 #define IOAPIC_AUTO -1
1294 #define IOAPIC_EDGE 0
1295 #define IOAPIC_LEVEL 1
1297 #ifdef CONFIG_X86_32
1298 static inline int IO_APIC_irq_trigger(int irq)
1302 for (apic = 0; apic < nr_ioapics; apic++) {
1303 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1304 idx = find_irq_entry(apic, pin, mp_INT);
1305 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1306 return irq_trigger(idx);
1310 * nonexistent IRQs are edge default
1315 static inline int IO_APIC_irq_trigger(int irq)
1321 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1324 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1325 trigger == IOAPIC_LEVEL)
1326 desc->status |= IRQ_LEVEL;
1328 desc->status &= ~IRQ_LEVEL;
1330 if (irq_remapped(irq)) {
1331 desc->status |= IRQ_MOVE_PCNTXT;
1333 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1337 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1338 handle_edge_irq, "edge");
1342 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1343 trigger == IOAPIC_LEVEL)
1344 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1348 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1349 handle_edge_irq, "edge");
1352 int setup_ioapic_entry(int apic_id, int irq,
1353 struct IO_APIC_route_entry *entry,
1354 unsigned int destination, int trigger,
1355 int polarity, int vector, int pin)
1358 * add it to the IO-APIC irq-routing table:
1360 memset(entry,0,sizeof(*entry));
1362 if (intr_remapping_enabled) {
1363 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1365 struct IR_IO_APIC_route_entry *ir_entry =
1366 (struct IR_IO_APIC_route_entry *) entry;
1370 panic("No mapping iommu for ioapic %d\n", apic_id);
1372 index = alloc_irte(iommu, irq, 1);
1374 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1376 memset(&irte, 0, sizeof(irte));
1379 irte.dst_mode = apic->irq_dest_mode;
1381 * Trigger mode in the IRTE will always be edge, and the
1382 * actual level or edge trigger will be setup in the IO-APIC
1383 * RTE. This will help simplify level triggered irq migration.
1384 * For more details, see the comments above explainig IO-APIC
1385 * irq migration in the presence of interrupt-remapping.
1387 irte.trigger_mode = 0;
1388 irte.dlvry_mode = apic->irq_delivery_mode;
1389 irte.vector = vector;
1390 irte.dest_id = IRTE_DEST(destination);
1392 /* Set source-id of interrupt request */
1393 set_ioapic_sid(&irte, apic_id);
1395 modify_irte(irq, &irte);
1397 ir_entry->index2 = (index >> 15) & 0x1;
1399 ir_entry->format = 1;
1400 ir_entry->index = (index & 0x7fff);
1402 * IO-APIC RTE will be configured with virtual vector.
1403 * irq handler will do the explicit EOI to the io-apic.
1405 ir_entry->vector = pin;
1407 entry->delivery_mode = apic->irq_delivery_mode;
1408 entry->dest_mode = apic->irq_dest_mode;
1409 entry->dest = destination;
1410 entry->vector = vector;
1413 entry->mask = 0; /* enable IRQ */
1414 entry->trigger = trigger;
1415 entry->polarity = polarity;
1417 /* Mask level triggered irqs.
1418 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1425 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1426 int trigger, int polarity)
1428 struct irq_cfg *cfg;
1429 struct IO_APIC_route_entry entry;
1432 if (!IO_APIC_IRQ(irq))
1435 cfg = desc->chip_data;
1437 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1440 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1442 apic_printk(APIC_VERBOSE,KERN_DEBUG
1443 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1444 "IRQ %d Mode:%i Active:%i)\n",
1445 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1446 irq, trigger, polarity);
1449 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1450 dest, trigger, polarity, cfg->vector, pin)) {
1451 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1452 mp_ioapics[apic_id].apicid, pin);
1453 __clear_irq_vector(irq, cfg);
1457 ioapic_register_intr(irq, desc, trigger);
1458 if (irq < nr_legacy_irqs)
1459 disable_8259A_irq(irq);
1461 ioapic_write_entry(apic_id, pin, entry);
1465 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1466 } mp_ioapic_routing[MAX_IO_APICS];
1468 static void __init setup_IO_APIC_irqs(void)
1470 int apic_id = 0, pin, idx, irq;
1472 struct irq_desc *desc;
1473 struct irq_cfg *cfg;
1474 int node = cpu_to_node(boot_cpu_id);
1476 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1479 if (!acpi_disabled && acpi_ioapic) {
1480 apic_id = mp_find_ioapic(0);
1486 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1487 idx = find_irq_entry(apic_id, pin, mp_INT);
1491 apic_printk(APIC_VERBOSE,
1492 KERN_DEBUG " %d-%d",
1493 mp_ioapics[apic_id].apicid, pin);
1495 apic_printk(APIC_VERBOSE, " %d-%d",
1496 mp_ioapics[apic_id].apicid, pin);
1500 apic_printk(APIC_VERBOSE,
1501 " (apicid-pin) not connected\n");
1505 irq = pin_2_irq(idx, apic_id, pin);
1508 * Skip the timer IRQ if there's a quirk handler
1509 * installed and if it returns 1:
1511 if (apic->multi_timer_check &&
1512 apic->multi_timer_check(apic_id, irq))
1515 desc = irq_to_desc_alloc_node(irq, node);
1517 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1520 cfg = desc->chip_data;
1521 add_pin_to_irq_node(cfg, node, apic_id, pin);
1523 * don't mark it in pin_programmed, so later acpi could
1524 * set it correctly when irq < 16
1526 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1527 irq_trigger(idx), irq_polarity(idx));
1531 apic_printk(APIC_VERBOSE,
1532 " (apicid-pin) not connected\n");
1536 * Set up the timer pin, possibly with the 8259A-master behind.
1538 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1541 struct IO_APIC_route_entry entry;
1543 if (intr_remapping_enabled)
1546 memset(&entry, 0, sizeof(entry));
1549 * We use logical delivery to get the timer IRQ
1552 entry.dest_mode = apic->irq_dest_mode;
1553 entry.mask = 0; /* don't mask IRQ for edge */
1554 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1555 entry.delivery_mode = apic->irq_delivery_mode;
1558 entry.vector = vector;
1561 * The timer IRQ doesn't have to know that behind the
1562 * scene we may have a 8259A-master in AEOI mode ...
1564 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1567 * Add it to the IO-APIC irq-routing table:
1569 ioapic_write_entry(apic_id, pin, entry);
1573 __apicdebuginit(void) print_IO_APIC(void)
1576 union IO_APIC_reg_00 reg_00;
1577 union IO_APIC_reg_01 reg_01;
1578 union IO_APIC_reg_02 reg_02;
1579 union IO_APIC_reg_03 reg_03;
1580 unsigned long flags;
1581 struct irq_cfg *cfg;
1582 struct irq_desc *desc;
1585 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1586 for (i = 0; i < nr_ioapics; i++)
1587 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1588 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1591 * We are a bit conservative about what we expect. We have to
1592 * know about every hardware change ASAP.
1594 printk(KERN_INFO "testing the IO APIC.......................\n");
1596 for (apic = 0; apic < nr_ioapics; apic++) {
1598 spin_lock_irqsave(&ioapic_lock, flags);
1599 reg_00.raw = io_apic_read(apic, 0);
1600 reg_01.raw = io_apic_read(apic, 1);
1601 if (reg_01.bits.version >= 0x10)
1602 reg_02.raw = io_apic_read(apic, 2);
1603 if (reg_01.bits.version >= 0x20)
1604 reg_03.raw = io_apic_read(apic, 3);
1605 spin_unlock_irqrestore(&ioapic_lock, flags);
1608 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1609 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1610 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1611 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1612 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1614 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1615 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1617 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1618 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1621 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1622 * but the value of reg_02 is read as the previous read register
1623 * value, so ignore it if reg_02 == reg_01.
1625 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1626 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1627 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1631 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1632 * or reg_03, but the value of reg_0[23] is read as the previous read
1633 * register value, so ignore it if reg_03 == reg_0[12].
1635 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1636 reg_03.raw != reg_01.raw) {
1637 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1638 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1641 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1643 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1644 " Stat Dmod Deli Vect: \n");
1646 for (i = 0; i <= reg_01.bits.entries; i++) {
1647 struct IO_APIC_route_entry entry;
1649 entry = ioapic_read_entry(apic, i);
1651 printk(KERN_DEBUG " %02x %03X ",
1656 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1661 entry.delivery_status,
1663 entry.delivery_mode,
1668 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1669 for_each_irq_desc(irq, desc) {
1670 struct irq_pin_list *entry;
1672 cfg = desc->chip_data;
1673 entry = cfg->irq_2_pin;
1676 printk(KERN_DEBUG "IRQ%d ", irq);
1677 for_each_irq_pin(entry, cfg->irq_2_pin)
1678 printk("-> %d:%d", entry->apic, entry->pin);
1682 printk(KERN_INFO ".................................... done.\n");
1687 __apicdebuginit(void) print_APIC_field(int base)
1693 for (i = 0; i < 8; i++)
1694 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1696 printk(KERN_CONT "\n");
1699 __apicdebuginit(void) print_local_APIC(void *dummy)
1701 unsigned int i, v, ver, maxlvt;
1704 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1705 smp_processor_id(), hard_smp_processor_id());
1706 v = apic_read(APIC_ID);
1707 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1708 v = apic_read(APIC_LVR);
1709 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1710 ver = GET_APIC_VERSION(v);
1711 maxlvt = lapic_get_maxlvt();
1713 v = apic_read(APIC_TASKPRI);
1714 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1716 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1717 if (!APIC_XAPIC(ver)) {
1718 v = apic_read(APIC_ARBPRI);
1719 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1720 v & APIC_ARBPRI_MASK);
1722 v = apic_read(APIC_PROCPRI);
1723 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1727 * Remote read supported only in the 82489DX and local APIC for
1728 * Pentium processors.
1730 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1731 v = apic_read(APIC_RRR);
1732 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1735 v = apic_read(APIC_LDR);
1736 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1737 if (!x2apic_enabled()) {
1738 v = apic_read(APIC_DFR);
1739 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1741 v = apic_read(APIC_SPIV);
1742 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1744 printk(KERN_DEBUG "... APIC ISR field:\n");
1745 print_APIC_field(APIC_ISR);
1746 printk(KERN_DEBUG "... APIC TMR field:\n");
1747 print_APIC_field(APIC_TMR);
1748 printk(KERN_DEBUG "... APIC IRR field:\n");
1749 print_APIC_field(APIC_IRR);
1751 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1753 apic_write(APIC_ESR, 0);
1755 v = apic_read(APIC_ESR);
1756 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1759 icr = apic_icr_read();
1760 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1761 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1763 v = apic_read(APIC_LVTT);
1764 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1766 if (maxlvt > 3) { /* PC is LVT#4. */
1767 v = apic_read(APIC_LVTPC);
1768 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1770 v = apic_read(APIC_LVT0);
1771 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1772 v = apic_read(APIC_LVT1);
1773 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1775 if (maxlvt > 2) { /* ERR is LVT#3. */
1776 v = apic_read(APIC_LVTERR);
1777 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1780 v = apic_read(APIC_TMICT);
1781 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1782 v = apic_read(APIC_TMCCT);
1783 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1784 v = apic_read(APIC_TDCR);
1785 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1787 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1788 v = apic_read(APIC_EFEAT);
1789 maxlvt = (v >> 16) & 0xff;
1790 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1791 v = apic_read(APIC_ECTRL);
1792 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1793 for (i = 0; i < maxlvt; i++) {
1794 v = apic_read(APIC_EILVTn(i));
1795 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1801 __apicdebuginit(void) print_local_APICs(int maxcpu)
1809 for_each_online_cpu(cpu) {
1812 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1817 __apicdebuginit(void) print_PIC(void)
1820 unsigned long flags;
1822 if (!nr_legacy_irqs)
1825 printk(KERN_DEBUG "\nprinting PIC contents\n");
1827 spin_lock_irqsave(&i8259A_lock, flags);
1829 v = inb(0xa1) << 8 | inb(0x21);
1830 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1832 v = inb(0xa0) << 8 | inb(0x20);
1833 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1837 v = inb(0xa0) << 8 | inb(0x20);
1841 spin_unlock_irqrestore(&i8259A_lock, flags);
1843 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1845 v = inb(0x4d1) << 8 | inb(0x4d0);
1846 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1849 static int __initdata show_lapic = 1;
1850 static __init int setup_show_lapic(char *arg)
1854 if (strcmp(arg, "all") == 0) {
1855 show_lapic = CONFIG_NR_CPUS;
1857 get_option(&arg, &num);
1864 __setup("show_lapic=", setup_show_lapic);
1866 __apicdebuginit(int) print_ICs(void)
1868 if (apic_verbosity == APIC_QUIET)
1873 /* don't print out if apic is not there */
1874 if (!cpu_has_apic && !apic_from_smp_config())
1877 print_local_APICs(show_lapic);
1883 fs_initcall(print_ICs);
1886 /* Where if anywhere is the i8259 connect in external int mode */
1887 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1889 void __init enable_IO_APIC(void)
1891 union IO_APIC_reg_01 reg_01;
1892 int i8259_apic, i8259_pin;
1894 unsigned long flags;
1897 * The number of IO-APIC IRQ registers (== #pins):
1899 for (apic = 0; apic < nr_ioapics; apic++) {
1900 spin_lock_irqsave(&ioapic_lock, flags);
1901 reg_01.raw = io_apic_read(apic, 1);
1902 spin_unlock_irqrestore(&ioapic_lock, flags);
1903 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1906 if (!nr_legacy_irqs)
1909 for(apic = 0; apic < nr_ioapics; apic++) {
1911 /* See if any of the pins is in ExtINT mode */
1912 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1913 struct IO_APIC_route_entry entry;
1914 entry = ioapic_read_entry(apic, pin);
1916 /* If the interrupt line is enabled and in ExtInt mode
1917 * I have found the pin where the i8259 is connected.
1919 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1920 ioapic_i8259.apic = apic;
1921 ioapic_i8259.pin = pin;
1927 /* Look to see what if the MP table has reported the ExtINT */
1928 /* If we could not find the appropriate pin by looking at the ioapic
1929 * the i8259 probably is not connected the ioapic but give the
1930 * mptable a chance anyway.
1932 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1933 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1934 /* Trust the MP table if nothing is setup in the hardware */
1935 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1936 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1937 ioapic_i8259.pin = i8259_pin;
1938 ioapic_i8259.apic = i8259_apic;
1940 /* Complain if the MP table and the hardware disagree */
1941 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1942 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1944 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1948 * Do not trust the IO-APIC being empty at bootup
1954 * Not an __init, needed by the reboot code
1956 void disable_IO_APIC(void)
1959 * Clear the IO-APIC before rebooting:
1963 if (!nr_legacy_irqs)
1967 * If the i8259 is routed through an IOAPIC
1968 * Put that IOAPIC in virtual wire mode
1969 * so legacy interrupts can be delivered.
1971 * With interrupt-remapping, for now we will use virtual wire A mode,
1972 * as virtual wire B is little complex (need to configure both
1973 * IOAPIC RTE aswell as interrupt-remapping table entry).
1974 * As this gets called during crash dump, keep this simple for now.
1976 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1977 struct IO_APIC_route_entry entry;
1979 memset(&entry, 0, sizeof(entry));
1980 entry.mask = 0; /* Enabled */
1981 entry.trigger = 0; /* Edge */
1983 entry.polarity = 0; /* High */
1984 entry.delivery_status = 0;
1985 entry.dest_mode = 0; /* Physical */
1986 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1988 entry.dest = read_apic_id();
1991 * Add it to the IO-APIC irq-routing table:
1993 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1997 * Use virtual wire A mode when interrupt remapping is enabled.
1999 if (cpu_has_apic || apic_from_smp_config())
2000 disconnect_bsp_APIC(!intr_remapping_enabled &&
2001 ioapic_i8259.pin != -1);
2004 #ifdef CONFIG_X86_32
2006 * function to set the IO-APIC physical IDs based on the
2007 * values stored in the MPC table.
2009 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2012 void __init setup_ioapic_ids_from_mpc(void)
2014 union IO_APIC_reg_00 reg_00;
2015 physid_mask_t phys_id_present_map;
2018 unsigned char old_id;
2019 unsigned long flags;
2024 * Don't check I/O APIC IDs for xAPIC systems. They have
2025 * no meaning without the serial APIC bus.
2027 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2028 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2031 * This is broken; anything with a real cpu count has to
2032 * circumvent this idiocy regardless.
2034 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2037 * Set the IOAPIC ID to the value stored in the MPC table.
2039 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2041 /* Read the register 0 value */
2042 spin_lock_irqsave(&ioapic_lock, flags);
2043 reg_00.raw = io_apic_read(apic_id, 0);
2044 spin_unlock_irqrestore(&ioapic_lock, flags);
2046 old_id = mp_ioapics[apic_id].apicid;
2048 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2049 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2050 apic_id, mp_ioapics[apic_id].apicid);
2051 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2053 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2057 * Sanity check, is the ID really free? Every APIC in a
2058 * system must have a unique ID or we get lots of nice
2059 * 'stuck on smp_invalidate_needed IPI wait' messages.
2061 if (apic->check_apicid_used(&phys_id_present_map,
2062 mp_ioapics[apic_id].apicid)) {
2063 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2064 apic_id, mp_ioapics[apic_id].apicid);
2065 for (i = 0; i < get_physical_broadcast(); i++)
2066 if (!physid_isset(i, phys_id_present_map))
2068 if (i >= get_physical_broadcast())
2069 panic("Max APIC ID exceeded!\n");
2070 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2072 physid_set(i, phys_id_present_map);
2073 mp_ioapics[apic_id].apicid = i;
2076 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2077 apic_printk(APIC_VERBOSE, "Setting %d in the "
2078 "phys_id_present_map\n",
2079 mp_ioapics[apic_id].apicid);
2080 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2085 * We need to adjust the IRQ routing table
2086 * if the ID changed.
2088 if (old_id != mp_ioapics[apic_id].apicid)
2089 for (i = 0; i < mp_irq_entries; i++)
2090 if (mp_irqs[i].dstapic == old_id)
2092 = mp_ioapics[apic_id].apicid;
2095 * Read the right value from the MPC table and
2096 * write it into the ID register.
2098 apic_printk(APIC_VERBOSE, KERN_INFO
2099 "...changing IO-APIC physical APIC ID to %d ...",
2100 mp_ioapics[apic_id].apicid);
2102 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2103 spin_lock_irqsave(&ioapic_lock, flags);
2104 io_apic_write(apic_id, 0, reg_00.raw);
2105 spin_unlock_irqrestore(&ioapic_lock, flags);
2110 spin_lock_irqsave(&ioapic_lock, flags);
2111 reg_00.raw = io_apic_read(apic_id, 0);
2112 spin_unlock_irqrestore(&ioapic_lock, flags);
2113 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2114 printk("could not set ID!\n");
2116 apic_printk(APIC_VERBOSE, " ok.\n");
2121 int no_timer_check __initdata;
2123 static int __init notimercheck(char *s)
2128 __setup("no_timer_check", notimercheck);
2131 * There is a nasty bug in some older SMP boards, their mptable lies
2132 * about the timer IRQ. We do the following to work around the situation:
2134 * - timer IRQ defaults to IO-APIC IRQ
2135 * - if this function detects that timer IRQs are defunct, then we fall
2136 * back to ISA timer IRQs
2138 static int __init timer_irq_works(void)
2140 unsigned long t1 = jiffies;
2141 unsigned long flags;
2146 local_save_flags(flags);
2148 /* Let ten ticks pass... */
2149 mdelay((10 * 1000) / HZ);
2150 local_irq_restore(flags);
2153 * Expect a few ticks at least, to be sure some possible
2154 * glue logic does not lock up after one or two first
2155 * ticks in a non-ExtINT mode. Also the local APIC
2156 * might have cached one ExtINT interrupt. Finally, at
2157 * least one tick may be lost due to delays.
2161 if (time_after(jiffies, t1 + 4))
2167 * In the SMP+IOAPIC case it might happen that there are an unspecified
2168 * number of pending IRQ events unhandled. These cases are very rare,
2169 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2170 * better to do it this way as thus we do not have to be aware of
2171 * 'pending' interrupts in the IRQ path, except at this point.
2174 * Edge triggered needs to resend any interrupt
2175 * that was delayed but this is now handled in the device
2180 * Starting up a edge-triggered IO-APIC interrupt is
2181 * nasty - we need to make sure that we get the edge.
2182 * If it is already asserted for some reason, we need
2183 * return 1 to indicate that is was pending.
2185 * This is not complete - we should be able to fake
2186 * an edge even if it isn't on the 8259A...
2189 static unsigned int startup_ioapic_irq(unsigned int irq)
2191 int was_pending = 0;
2192 unsigned long flags;
2193 struct irq_cfg *cfg;
2195 spin_lock_irqsave(&ioapic_lock, flags);
2196 if (irq < nr_legacy_irqs) {
2197 disable_8259A_irq(irq);
2198 if (i8259A_irq_pending(irq))
2202 __unmask_IO_APIC_irq(cfg);
2203 spin_unlock_irqrestore(&ioapic_lock, flags);
2208 static int ioapic_retrigger_irq(unsigned int irq)
2211 struct irq_cfg *cfg = irq_cfg(irq);
2212 unsigned long flags;
2214 spin_lock_irqsave(&vector_lock, flags);
2215 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2216 spin_unlock_irqrestore(&vector_lock, flags);
2222 * Level and edge triggered IO-APIC interrupts need different handling,
2223 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2224 * handled with the level-triggered descriptor, but that one has slightly
2225 * more overhead. Level-triggered interrupts cannot be handled with the
2226 * edge-triggered handler, without risking IRQ storms and other ugly
2231 void send_cleanup_vector(struct irq_cfg *cfg)
2233 cpumask_var_t cleanup_mask;
2235 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2237 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2238 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2240 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2241 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2242 free_cpumask_var(cleanup_mask);
2244 cfg->move_in_progress = 0;
2247 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2250 struct irq_pin_list *entry;
2251 u8 vector = cfg->vector;
2253 for_each_irq_pin(entry, cfg->irq_2_pin) {
2259 * With interrupt-remapping, destination information comes
2260 * from interrupt-remapping table entry.
2262 if (!irq_remapped(irq))
2263 io_apic_write(apic, 0x11 + pin*2, dest);
2264 reg = io_apic_read(apic, 0x10 + pin*2);
2265 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2267 io_apic_modify(apic, 0x10 + pin*2, reg);
2272 * Either sets desc->affinity to a valid value, and returns
2273 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2274 * leaves desc->affinity untouched.
2277 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2279 struct irq_cfg *cfg;
2282 if (!cpumask_intersects(mask, cpu_online_mask))
2286 cfg = desc->chip_data;
2287 if (assign_irq_vector(irq, cfg, mask))
2290 cpumask_copy(desc->affinity, mask);
2292 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2296 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2298 struct irq_cfg *cfg;
2299 unsigned long flags;
2305 cfg = desc->chip_data;
2307 spin_lock_irqsave(&ioapic_lock, flags);
2308 dest = set_desc_affinity(desc, mask);
2309 if (dest != BAD_APICID) {
2310 /* Only the high 8 bits are valid. */
2311 dest = SET_APIC_LOGICAL_ID(dest);
2312 __target_IO_APIC_irq(irq, dest, cfg);
2315 spin_unlock_irqrestore(&ioapic_lock, flags);
2321 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2323 struct irq_desc *desc;
2325 desc = irq_to_desc(irq);
2327 return set_ioapic_affinity_irq_desc(desc, mask);
2330 #ifdef CONFIG_INTR_REMAP
2333 * Migrate the IO-APIC irq in the presence of intr-remapping.
2335 * For both level and edge triggered, irq migration is a simple atomic
2336 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2338 * For level triggered, we eliminate the io-apic RTE modification (with the
2339 * updated vector information), by using a virtual vector (io-apic pin number).
2340 * Real vector that is used for interrupting cpu will be coming from
2341 * the interrupt-remapping table entry.
2344 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2346 struct irq_cfg *cfg;
2352 if (!cpumask_intersects(mask, cpu_online_mask))
2356 if (get_irte(irq, &irte))
2359 cfg = desc->chip_data;
2360 if (assign_irq_vector(irq, cfg, mask))
2363 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2365 irte.vector = cfg->vector;
2366 irte.dest_id = IRTE_DEST(dest);
2369 * Modified the IRTE and flushes the Interrupt entry cache.
2371 modify_irte(irq, &irte);
2373 if (cfg->move_in_progress)
2374 send_cleanup_vector(cfg);
2376 cpumask_copy(desc->affinity, mask);
2382 * Migrates the IRQ destination in the process context.
2384 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2385 const struct cpumask *mask)
2387 return migrate_ioapic_irq_desc(desc, mask);
2389 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2390 const struct cpumask *mask)
2392 struct irq_desc *desc = irq_to_desc(irq);
2394 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2397 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2398 const struct cpumask *mask)
2404 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2406 unsigned vector, me;
2412 me = smp_processor_id();
2413 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2416 struct irq_desc *desc;
2417 struct irq_cfg *cfg;
2418 irq = __get_cpu_var(vector_irq)[vector];
2423 desc = irq_to_desc(irq);
2428 spin_lock(&desc->lock);
2430 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2433 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2435 * Check if the vector that needs to be cleanedup is
2436 * registered at the cpu's IRR. If so, then this is not
2437 * the best time to clean it up. Lets clean it up in the
2438 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2441 if (irr & (1 << (vector % 32))) {
2442 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2445 __get_cpu_var(vector_irq)[vector] = -1;
2447 spin_unlock(&desc->lock);
2453 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2455 struct irq_desc *desc = *descp;
2456 struct irq_cfg *cfg = desc->chip_data;
2459 if (likely(!cfg->move_in_progress))
2462 me = smp_processor_id();
2464 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2465 send_cleanup_vector(cfg);
2468 static void irq_complete_move(struct irq_desc **descp)
2470 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2473 void irq_force_complete_move(int irq)
2475 struct irq_desc *desc = irq_to_desc(irq);
2476 struct irq_cfg *cfg = desc->chip_data;
2478 __irq_complete_move(&desc, cfg->vector);
2481 static inline void irq_complete_move(struct irq_desc **descp) {}
2484 static void ack_apic_edge(unsigned int irq)
2486 struct irq_desc *desc = irq_to_desc(irq);
2488 irq_complete_move(&desc);
2489 move_native_irq(irq);
2493 atomic_t irq_mis_count;
2495 static int use_eoi_reg __read_mostly;
2497 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2499 struct irq_pin_list *entry;
2501 for_each_irq_pin(entry, cfg->irq_2_pin) {
2502 if (irq_remapped(irq))
2503 io_apic_eoi(entry->apic, entry->pin);
2505 io_apic_eoi(entry->apic, cfg->vector);
2509 static void eoi_ioapic_irq(struct irq_desc *desc)
2511 struct irq_cfg *cfg;
2512 unsigned long flags;
2516 cfg = desc->chip_data;
2518 spin_lock_irqsave(&ioapic_lock, flags);
2519 __eoi_ioapic_irq(irq, cfg);
2520 spin_unlock_irqrestore(&ioapic_lock, flags);
2523 static int ioapic_supports_eoi(void)
2525 struct pci_dev *root;
2527 root = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2528 if (root && root->vendor == PCI_VENDOR_ID_INTEL &&
2529 mp_ioapics[0].apicver >= 0x2) {
2531 printk(KERN_INFO "IO-APIC supports EOI register\n");
2533 printk(KERN_INFO "IO-APIC doesn't support EOI\n");
2538 fs_initcall(ioapic_supports_eoi);
2540 static void ack_apic_level(unsigned int irq)
2542 struct irq_desc *desc = irq_to_desc(irq);
2545 struct irq_cfg *cfg;
2546 int do_unmask_irq = 0;
2548 irq_complete_move(&desc);
2549 #ifdef CONFIG_GENERIC_PENDING_IRQ
2550 /* If we are moving the irq we need to mask it */
2551 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2553 mask_IO_APIC_irq_desc(desc);
2558 * It appears there is an erratum which affects at least version 0x11
2559 * of I/O APIC (that's the 82093AA and cores integrated into various
2560 * chipsets). Under certain conditions a level-triggered interrupt is
2561 * erroneously delivered as edge-triggered one but the respective IRR
2562 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2563 * message but it will never arrive and further interrupts are blocked
2564 * from the source. The exact reason is so far unknown, but the
2565 * phenomenon was observed when two consecutive interrupt requests
2566 * from a given source get delivered to the same CPU and the source is
2567 * temporarily disabled in between.
2569 * A workaround is to simulate an EOI message manually. We achieve it
2570 * by setting the trigger mode to edge and then to level when the edge
2571 * trigger mode gets detected in the TMR of a local APIC for a
2572 * level-triggered interrupt. We mask the source for the time of the
2573 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2574 * The idea is from Manfred Spraul. --macro
2576 cfg = desc->chip_data;
2578 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2581 * We must acknowledge the irq before we move it or the acknowledge will
2582 * not propagate properly.
2586 /* Now we can move and renable the irq */
2587 if (unlikely(do_unmask_irq)) {
2588 /* Only migrate the irq if the ack has been received.
2590 * On rare occasions the broadcast level triggered ack gets
2591 * delayed going to ioapics, and if we reprogram the
2592 * vector while Remote IRR is still set the irq will never
2595 * To prevent this scenario we read the Remote IRR bit
2596 * of the ioapic. This has two effects.
2597 * - On any sane system the read of the ioapic will
2598 * flush writes (and acks) going to the ioapic from
2600 * - We get to see if the ACK has actually been delivered.
2602 * Based on failed experiments of reprogramming the
2603 * ioapic entry from outside of irq context starting
2604 * with masking the ioapic entry and then polling until
2605 * Remote IRR was clear before reprogramming the
2606 * ioapic I don't trust the Remote IRR bit to be
2607 * completey accurate.
2609 * However there appears to be no other way to plug
2610 * this race, so if the Remote IRR bit is not
2611 * accurate and is causing problems then it is a hardware bug
2612 * and you can go talk to the chipset vendor about it.
2614 cfg = desc->chip_data;
2615 if (!io_apic_level_ack_pending(cfg))
2616 move_masked_irq(irq);
2617 unmask_IO_APIC_irq_desc(desc);
2620 /* Tail end of version 0x11 I/O APIC bug workaround */
2621 if (!(v & (1 << (i & 0x1f)))) {
2622 atomic_inc(&irq_mis_count);
2625 eoi_ioapic_irq(desc);
2627 spin_lock(&ioapic_lock);
2628 __mask_and_edge_IO_APIC_irq(cfg);
2629 __unmask_and_level_IO_APIC_irq(cfg);
2630 spin_unlock(&ioapic_lock);
2635 #ifdef CONFIG_INTR_REMAP
2636 static void ir_ack_apic_edge(unsigned int irq)
2641 static void ir_ack_apic_level(unsigned int irq)
2643 struct irq_desc *desc = irq_to_desc(irq);
2646 eoi_ioapic_irq(desc);
2648 #endif /* CONFIG_INTR_REMAP */
2650 static struct irq_chip ioapic_chip __read_mostly = {
2652 .startup = startup_ioapic_irq,
2653 .mask = mask_IO_APIC_irq,
2654 .unmask = unmask_IO_APIC_irq,
2655 .ack = ack_apic_edge,
2656 .eoi = ack_apic_level,
2658 .set_affinity = set_ioapic_affinity_irq,
2660 .retrigger = ioapic_retrigger_irq,
2663 static struct irq_chip ir_ioapic_chip __read_mostly = {
2664 .name = "IR-IO-APIC",
2665 .startup = startup_ioapic_irq,
2666 .mask = mask_IO_APIC_irq,
2667 .unmask = unmask_IO_APIC_irq,
2668 #ifdef CONFIG_INTR_REMAP
2669 .ack = ir_ack_apic_edge,
2670 .eoi = ir_ack_apic_level,
2672 .set_affinity = set_ir_ioapic_affinity_irq,
2675 .retrigger = ioapic_retrigger_irq,
2678 static inline void init_IO_APIC_traps(void)
2681 struct irq_desc *desc;
2682 struct irq_cfg *cfg;
2685 * NOTE! The local APIC isn't very good at handling
2686 * multiple interrupts at the same interrupt level.
2687 * As the interrupt level is determined by taking the
2688 * vector number and shifting that right by 4, we
2689 * want to spread these out a bit so that they don't
2690 * all fall in the same interrupt level.
2692 * Also, we've got to be careful not to trash gate
2693 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2695 for_each_irq_desc(irq, desc) {
2696 cfg = desc->chip_data;
2697 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2699 * Hmm.. We don't have an entry for this,
2700 * so default to an old-fashioned 8259
2701 * interrupt if we can..
2703 if (irq < nr_legacy_irqs)
2704 make_8259A_irq(irq);
2706 /* Strange. Oh, well.. */
2707 desc->chip = &no_irq_chip;
2713 * The local APIC irq-chip implementation:
2716 static void mask_lapic_irq(unsigned int irq)
2720 v = apic_read(APIC_LVT0);
2721 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2724 static void unmask_lapic_irq(unsigned int irq)
2728 v = apic_read(APIC_LVT0);
2729 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2732 static void ack_lapic_irq(unsigned int irq)
2737 static struct irq_chip lapic_chip __read_mostly = {
2738 .name = "local-APIC",
2739 .mask = mask_lapic_irq,
2740 .unmask = unmask_lapic_irq,
2741 .ack = ack_lapic_irq,
2744 static void lapic_register_intr(int irq, struct irq_desc *desc)
2746 desc->status &= ~IRQ_LEVEL;
2747 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2751 static void __init setup_nmi(void)
2754 * Dirty trick to enable the NMI watchdog ...
2755 * We put the 8259A master into AEOI mode and
2756 * unmask on all local APICs LVT0 as NMI.
2758 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2759 * is from Maciej W. Rozycki - so we do not have to EOI from
2760 * the NMI handler or the timer interrupt.
2762 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2764 enable_NMI_through_LVT0();
2766 apic_printk(APIC_VERBOSE, " done.\n");
2770 * This looks a bit hackish but it's about the only one way of sending
2771 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2772 * not support the ExtINT mode, unfortunately. We need to send these
2773 * cycles as some i82489DX-based boards have glue logic that keeps the
2774 * 8259A interrupt line asserted until INTA. --macro
2776 static inline void __init unlock_ExtINT_logic(void)
2779 struct IO_APIC_route_entry entry0, entry1;
2780 unsigned char save_control, save_freq_select;
2782 pin = find_isa_irq_pin(8, mp_INT);
2787 apic = find_isa_irq_apic(8, mp_INT);
2793 entry0 = ioapic_read_entry(apic, pin);
2794 clear_IO_APIC_pin(apic, pin);
2796 memset(&entry1, 0, sizeof(entry1));
2798 entry1.dest_mode = 0; /* physical delivery */
2799 entry1.mask = 0; /* unmask IRQ now */
2800 entry1.dest = hard_smp_processor_id();
2801 entry1.delivery_mode = dest_ExtINT;
2802 entry1.polarity = entry0.polarity;
2806 ioapic_write_entry(apic, pin, entry1);
2808 save_control = CMOS_READ(RTC_CONTROL);
2809 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2810 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2812 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2817 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2821 CMOS_WRITE(save_control, RTC_CONTROL);
2822 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2823 clear_IO_APIC_pin(apic, pin);
2825 ioapic_write_entry(apic, pin, entry0);
2828 static int disable_timer_pin_1 __initdata;
2829 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2830 static int __init disable_timer_pin_setup(char *arg)
2832 disable_timer_pin_1 = 1;
2835 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2837 int timer_through_8259 __initdata;
2840 * This code may look a bit paranoid, but it's supposed to cooperate with
2841 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2842 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2843 * fanatically on his truly buggy board.
2845 * FIXME: really need to revamp this for all platforms.
2847 static inline void __init check_timer(void)
2849 struct irq_desc *desc = irq_to_desc(0);
2850 struct irq_cfg *cfg = desc->chip_data;
2851 int node = cpu_to_node(boot_cpu_id);
2852 int apic1, pin1, apic2, pin2;
2853 unsigned long flags;
2856 local_irq_save(flags);
2859 * get/set the timer IRQ vector:
2861 disable_8259A_irq(0);
2862 assign_irq_vector(0, cfg, apic->target_cpus());
2865 * As IRQ0 is to be enabled in the 8259A, the virtual
2866 * wire has to be disabled in the local APIC. Also
2867 * timer interrupts need to be acknowledged manually in
2868 * the 8259A for the i82489DX when using the NMI
2869 * watchdog as that APIC treats NMIs as level-triggered.
2870 * The AEOI mode will finish them in the 8259A
2873 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2875 #ifdef CONFIG_X86_32
2879 ver = apic_read(APIC_LVR);
2880 ver = GET_APIC_VERSION(ver);
2881 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2885 pin1 = find_isa_irq_pin(0, mp_INT);
2886 apic1 = find_isa_irq_apic(0, mp_INT);
2887 pin2 = ioapic_i8259.pin;
2888 apic2 = ioapic_i8259.apic;
2890 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2891 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2892 cfg->vector, apic1, pin1, apic2, pin2);
2895 * Some BIOS writers are clueless and report the ExtINTA
2896 * I/O APIC input from the cascaded 8259A as the timer
2897 * interrupt input. So just in case, if only one pin
2898 * was found above, try it both directly and through the
2902 if (intr_remapping_enabled)
2903 panic("BIOS bug: timer not connected to IO-APIC");
2907 } else if (pin2 == -1) {
2914 * Ok, does IRQ0 through the IOAPIC work?
2917 add_pin_to_irq_node(cfg, node, apic1, pin1);
2918 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2920 /* for edge trigger, setup_IO_APIC_irq already
2921 * leave it unmasked.
2922 * so only need to unmask if it is level-trigger
2923 * do we really have level trigger timer?
2926 idx = find_irq_entry(apic1, pin1, mp_INT);
2927 if (idx != -1 && irq_trigger(idx))
2928 unmask_IO_APIC_irq_desc(desc);
2930 if (timer_irq_works()) {
2931 if (nmi_watchdog == NMI_IO_APIC) {
2933 enable_8259A_irq(0);
2935 if (disable_timer_pin_1 > 0)
2936 clear_IO_APIC_pin(0, pin1);
2939 if (intr_remapping_enabled)
2940 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2941 local_irq_disable();
2942 clear_IO_APIC_pin(apic1, pin1);
2944 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2945 "8254 timer not connected to IO-APIC\n");
2947 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2948 "(IRQ0) through the 8259A ...\n");
2949 apic_printk(APIC_QUIET, KERN_INFO
2950 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2952 * legacy devices should be connected to IO APIC #0
2954 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2955 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2956 enable_8259A_irq(0);
2957 if (timer_irq_works()) {
2958 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2959 timer_through_8259 = 1;
2960 if (nmi_watchdog == NMI_IO_APIC) {
2961 disable_8259A_irq(0);
2963 enable_8259A_irq(0);
2968 * Cleanup, just in case ...
2970 local_irq_disable();
2971 disable_8259A_irq(0);
2972 clear_IO_APIC_pin(apic2, pin2);
2973 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2976 if (nmi_watchdog == NMI_IO_APIC) {
2977 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2978 "through the IO-APIC - disabling NMI Watchdog!\n");
2979 nmi_watchdog = NMI_NONE;
2981 #ifdef CONFIG_X86_32
2985 apic_printk(APIC_QUIET, KERN_INFO
2986 "...trying to set up timer as Virtual Wire IRQ...\n");
2988 lapic_register_intr(0, desc);
2989 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2990 enable_8259A_irq(0);
2992 if (timer_irq_works()) {
2993 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2996 local_irq_disable();
2997 disable_8259A_irq(0);
2998 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2999 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3001 apic_printk(APIC_QUIET, KERN_INFO
3002 "...trying to set up timer as ExtINT IRQ...\n");
3006 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3008 unlock_ExtINT_logic();
3010 if (timer_irq_works()) {
3011 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3014 local_irq_disable();
3015 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3016 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3017 "report. Then try booting with the 'noapic' option.\n");
3019 local_irq_restore(flags);
3023 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3024 * to devices. However there may be an I/O APIC pin available for
3025 * this interrupt regardless. The pin may be left unconnected, but
3026 * typically it will be reused as an ExtINT cascade interrupt for
3027 * the master 8259A. In the MPS case such a pin will normally be
3028 * reported as an ExtINT interrupt in the MP table. With ACPI
3029 * there is no provision for ExtINT interrupts, and in the absence
3030 * of an override it would be treated as an ordinary ISA I/O APIC
3031 * interrupt, that is edge-triggered and unmasked by default. We
3032 * used to do this, but it caused problems on some systems because
3033 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3034 * the same ExtINT cascade interrupt to drive the local APIC of the
3035 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3036 * the I/O APIC in all cases now. No actual device should request
3037 * it anyway. --macro
3039 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3041 void __init setup_IO_APIC(void)
3045 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3047 io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3049 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3051 * Set up IO-APIC IRQ routing.
3053 x86_init.mpparse.setup_ioapic_ids();
3056 setup_IO_APIC_irqs();
3057 init_IO_APIC_traps();
3063 * Called after all the initialization is done. If we didnt find any
3064 * APIC bugs then we can allow the modify fast path
3067 static int __init io_apic_bug_finalize(void)
3069 if (sis_apic_bug == -1)
3074 late_initcall(io_apic_bug_finalize);
3076 struct sysfs_ioapic_data {
3077 struct sys_device dev;
3078 struct IO_APIC_route_entry entry[0];
3080 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3082 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3084 struct IO_APIC_route_entry *entry;
3085 struct sysfs_ioapic_data *data;
3088 data = container_of(dev, struct sysfs_ioapic_data, dev);
3089 entry = data->entry;
3090 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3091 *entry = ioapic_read_entry(dev->id, i);
3096 static int ioapic_resume(struct sys_device *dev)
3098 struct IO_APIC_route_entry *entry;
3099 struct sysfs_ioapic_data *data;
3100 unsigned long flags;
3101 union IO_APIC_reg_00 reg_00;
3104 data = container_of(dev, struct sysfs_ioapic_data, dev);
3105 entry = data->entry;
3107 spin_lock_irqsave(&ioapic_lock, flags);
3108 reg_00.raw = io_apic_read(dev->id, 0);
3109 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3110 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3111 io_apic_write(dev->id, 0, reg_00.raw);
3113 spin_unlock_irqrestore(&ioapic_lock, flags);
3114 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3115 ioapic_write_entry(dev->id, i, entry[i]);
3120 static struct sysdev_class ioapic_sysdev_class = {
3122 .suspend = ioapic_suspend,
3123 .resume = ioapic_resume,
3126 static int __init ioapic_init_sysfs(void)
3128 struct sys_device * dev;
3131 error = sysdev_class_register(&ioapic_sysdev_class);
3135 for (i = 0; i < nr_ioapics; i++ ) {
3136 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3137 * sizeof(struct IO_APIC_route_entry);
3138 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3139 if (!mp_ioapic_data[i]) {
3140 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3143 dev = &mp_ioapic_data[i]->dev;
3145 dev->cls = &ioapic_sysdev_class;
3146 error = sysdev_register(dev);
3148 kfree(mp_ioapic_data[i]);
3149 mp_ioapic_data[i] = NULL;
3150 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3158 device_initcall(ioapic_init_sysfs);
3161 * Dynamic irq allocate and deallocation
3163 unsigned int create_irq_nr(unsigned int irq_want, int node)
3165 /* Allocate an unused irq */
3168 unsigned long flags;
3169 struct irq_cfg *cfg_new = NULL;
3170 struct irq_desc *desc_new = NULL;
3173 if (irq_want < nr_irqs_gsi)
3174 irq_want = nr_irqs_gsi;
3176 spin_lock_irqsave(&vector_lock, flags);
3177 for (new = irq_want; new < nr_irqs; new++) {
3178 desc_new = irq_to_desc_alloc_node(new, node);
3180 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3183 cfg_new = desc_new->chip_data;
3185 if (cfg_new->vector != 0)
3188 desc_new = move_irq_desc(desc_new, node);
3190 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3194 spin_unlock_irqrestore(&vector_lock, flags);
3197 dynamic_irq_init(irq);
3198 /* restore it, in case dynamic_irq_init clear it */
3200 desc_new->chip_data = cfg_new;
3205 int create_irq(void)
3207 int node = cpu_to_node(boot_cpu_id);
3208 unsigned int irq_want;
3211 irq_want = nr_irqs_gsi;
3212 irq = create_irq_nr(irq_want, node);
3220 void destroy_irq(unsigned int irq)
3222 unsigned long flags;
3223 struct irq_cfg *cfg;
3224 struct irq_desc *desc;
3226 /* store it, in case dynamic_irq_cleanup clear it */
3227 desc = irq_to_desc(irq);
3228 cfg = desc->chip_data;
3229 dynamic_irq_cleanup(irq);
3230 /* connect back irq_cfg */
3231 desc->chip_data = cfg;
3234 spin_lock_irqsave(&vector_lock, flags);
3235 __clear_irq_vector(irq, cfg);
3236 spin_unlock_irqrestore(&vector_lock, flags);
3240 * MSI message composition
3242 #ifdef CONFIG_PCI_MSI
3243 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3245 struct irq_cfg *cfg;
3253 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3257 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3259 if (irq_remapped(irq)) {
3264 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3265 BUG_ON(ir_index == -1);
3267 memset (&irte, 0, sizeof(irte));
3270 irte.dst_mode = apic->irq_dest_mode;
3271 irte.trigger_mode = 0; /* edge */
3272 irte.dlvry_mode = apic->irq_delivery_mode;
3273 irte.vector = cfg->vector;
3274 irte.dest_id = IRTE_DEST(dest);
3276 /* Set source-id of interrupt request */
3277 set_msi_sid(&irte, pdev);
3279 modify_irte(irq, &irte);
3281 msg->address_hi = MSI_ADDR_BASE_HI;
3282 msg->data = sub_handle;
3283 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3285 MSI_ADDR_IR_INDEX1(ir_index) |
3286 MSI_ADDR_IR_INDEX2(ir_index);
3288 if (x2apic_enabled())
3289 msg->address_hi = MSI_ADDR_BASE_HI |
3290 MSI_ADDR_EXT_DEST_ID(dest);
3292 msg->address_hi = MSI_ADDR_BASE_HI;
3296 ((apic->irq_dest_mode == 0) ?
3297 MSI_ADDR_DEST_MODE_PHYSICAL:
3298 MSI_ADDR_DEST_MODE_LOGICAL) |
3299 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3300 MSI_ADDR_REDIRECTION_CPU:
3301 MSI_ADDR_REDIRECTION_LOWPRI) |
3302 MSI_ADDR_DEST_ID(dest);
3305 MSI_DATA_TRIGGER_EDGE |
3306 MSI_DATA_LEVEL_ASSERT |
3307 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3308 MSI_DATA_DELIVERY_FIXED:
3309 MSI_DATA_DELIVERY_LOWPRI) |
3310 MSI_DATA_VECTOR(cfg->vector);
3316 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3318 struct irq_desc *desc = irq_to_desc(irq);
3319 struct irq_cfg *cfg;
3323 dest = set_desc_affinity(desc, mask);
3324 if (dest == BAD_APICID)
3327 cfg = desc->chip_data;
3329 read_msi_msg_desc(desc, &msg);
3331 msg.data &= ~MSI_DATA_VECTOR_MASK;
3332 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3333 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3334 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3336 write_msi_msg_desc(desc, &msg);
3340 #ifdef CONFIG_INTR_REMAP
3342 * Migrate the MSI irq to another cpumask. This migration is
3343 * done in the process context using interrupt-remapping hardware.
3346 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3348 struct irq_desc *desc = irq_to_desc(irq);
3349 struct irq_cfg *cfg = desc->chip_data;
3353 if (get_irte(irq, &irte))
3356 dest = set_desc_affinity(desc, mask);
3357 if (dest == BAD_APICID)
3360 irte.vector = cfg->vector;
3361 irte.dest_id = IRTE_DEST(dest);
3364 * atomically update the IRTE with the new destination and vector.
3366 modify_irte(irq, &irte);
3369 * After this point, all the interrupts will start arriving
3370 * at the new destination. So, time to cleanup the previous
3371 * vector allocation.
3373 if (cfg->move_in_progress)
3374 send_cleanup_vector(cfg);
3380 #endif /* CONFIG_SMP */
3383 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3384 * which implement the MSI or MSI-X Capability Structure.
3386 static struct irq_chip msi_chip = {
3388 .unmask = unmask_msi_irq,
3389 .mask = mask_msi_irq,
3390 .ack = ack_apic_edge,
3392 .set_affinity = set_msi_irq_affinity,
3394 .retrigger = ioapic_retrigger_irq,
3397 static struct irq_chip msi_ir_chip = {
3398 .name = "IR-PCI-MSI",
3399 .unmask = unmask_msi_irq,
3400 .mask = mask_msi_irq,
3401 #ifdef CONFIG_INTR_REMAP
3402 .ack = ir_ack_apic_edge,
3404 .set_affinity = ir_set_msi_irq_affinity,
3407 .retrigger = ioapic_retrigger_irq,
3411 * Map the PCI dev to the corresponding remapping hardware unit
3412 * and allocate 'nvec' consecutive interrupt-remapping table entries
3415 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3417 struct intel_iommu *iommu;
3420 iommu = map_dev_to_ir(dev);
3423 "Unable to map PCI %s to iommu\n", pci_name(dev));
3427 index = alloc_irte(iommu, irq, nvec);
3430 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3437 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3442 ret = msi_compose_msg(dev, irq, &msg);
3446 set_irq_msi(irq, msidesc);
3447 write_msi_msg(irq, &msg);
3449 if (irq_remapped(irq)) {
3450 struct irq_desc *desc = irq_to_desc(irq);
3452 * irq migration in process context
3454 desc->status |= IRQ_MOVE_PCNTXT;
3455 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3457 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3459 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3464 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3467 int ret, sub_handle;
3468 struct msi_desc *msidesc;
3469 unsigned int irq_want;
3470 struct intel_iommu *iommu = NULL;
3474 /* x86 doesn't support multiple MSI yet */
3475 if (type == PCI_CAP_ID_MSI && nvec > 1)
3478 node = dev_to_node(&dev->dev);
3479 irq_want = nr_irqs_gsi;
3481 list_for_each_entry(msidesc, &dev->msi_list, list) {
3482 irq = create_irq_nr(irq_want, node);
3486 if (!intr_remapping_enabled)
3491 * allocate the consecutive block of IRTE's
3494 index = msi_alloc_irte(dev, irq, nvec);
3500 iommu = map_dev_to_ir(dev);
3506 * setup the mapping between the irq and the IRTE
3507 * base index, the sub_handle pointing to the
3508 * appropriate interrupt remap table entry.
3510 set_irte_irq(irq, iommu, index, sub_handle);
3513 ret = setup_msi_irq(dev, msidesc, irq);
3525 void arch_teardown_msi_irq(unsigned int irq)
3530 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3532 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3534 struct irq_desc *desc = irq_to_desc(irq);
3535 struct irq_cfg *cfg;
3539 dest = set_desc_affinity(desc, mask);
3540 if (dest == BAD_APICID)
3543 cfg = desc->chip_data;
3545 dmar_msi_read(irq, &msg);
3547 msg.data &= ~MSI_DATA_VECTOR_MASK;
3548 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3549 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3550 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3552 dmar_msi_write(irq, &msg);
3557 #endif /* CONFIG_SMP */
3559 static struct irq_chip dmar_msi_type = {
3561 .unmask = dmar_msi_unmask,
3562 .mask = dmar_msi_mask,
3563 .ack = ack_apic_edge,
3565 .set_affinity = dmar_msi_set_affinity,
3567 .retrigger = ioapic_retrigger_irq,
3570 int arch_setup_dmar_msi(unsigned int irq)
3575 ret = msi_compose_msg(NULL, irq, &msg);
3578 dmar_msi_write(irq, &msg);
3579 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3585 #ifdef CONFIG_HPET_TIMER
3588 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3590 struct irq_desc *desc = irq_to_desc(irq);
3591 struct irq_cfg *cfg;
3595 dest = set_desc_affinity(desc, mask);
3596 if (dest == BAD_APICID)
3599 cfg = desc->chip_data;
3601 hpet_msi_read(irq, &msg);
3603 msg.data &= ~MSI_DATA_VECTOR_MASK;
3604 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3605 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3606 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3608 hpet_msi_write(irq, &msg);
3613 #endif /* CONFIG_SMP */
3615 static struct irq_chip hpet_msi_type = {
3617 .unmask = hpet_msi_unmask,
3618 .mask = hpet_msi_mask,
3619 .ack = ack_apic_edge,
3621 .set_affinity = hpet_msi_set_affinity,
3623 .retrigger = ioapic_retrigger_irq,
3626 int arch_setup_hpet_msi(unsigned int irq)
3630 struct irq_desc *desc = irq_to_desc(irq);
3632 ret = msi_compose_msg(NULL, irq, &msg);
3636 hpet_msi_write(irq, &msg);
3637 desc->status |= IRQ_MOVE_PCNTXT;
3638 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3645 #endif /* CONFIG_PCI_MSI */
3647 * Hypertransport interrupt support
3649 #ifdef CONFIG_HT_IRQ
3653 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3655 struct ht_irq_msg msg;
3656 fetch_ht_irq_msg(irq, &msg);
3658 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3659 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3661 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3662 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3664 write_ht_irq_msg(irq, &msg);
3667 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3669 struct irq_desc *desc = irq_to_desc(irq);
3670 struct irq_cfg *cfg;
3673 dest = set_desc_affinity(desc, mask);
3674 if (dest == BAD_APICID)
3677 cfg = desc->chip_data;
3679 target_ht_irq(irq, dest, cfg->vector);
3686 static struct irq_chip ht_irq_chip = {
3688 .mask = mask_ht_irq,
3689 .unmask = unmask_ht_irq,
3690 .ack = ack_apic_edge,
3692 .set_affinity = set_ht_irq_affinity,
3694 .retrigger = ioapic_retrigger_irq,
3697 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3699 struct irq_cfg *cfg;
3706 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3708 struct ht_irq_msg msg;
3711 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3712 apic->target_cpus());
3714 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3718 HT_IRQ_LOW_DEST_ID(dest) |
3719 HT_IRQ_LOW_VECTOR(cfg->vector) |
3720 ((apic->irq_dest_mode == 0) ?
3721 HT_IRQ_LOW_DM_PHYSICAL :
3722 HT_IRQ_LOW_DM_LOGICAL) |
3723 HT_IRQ_LOW_RQEOI_EDGE |
3724 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3725 HT_IRQ_LOW_MT_FIXED :
3726 HT_IRQ_LOW_MT_ARBITRATED) |
3727 HT_IRQ_LOW_IRQ_MASKED;
3729 write_ht_irq_msg(irq, &msg);
3731 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3732 handle_edge_irq, "edge");
3734 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3738 #endif /* CONFIG_HT_IRQ */
3740 int __init io_apic_get_redir_entries (int ioapic)
3742 union IO_APIC_reg_01 reg_01;
3743 unsigned long flags;
3745 spin_lock_irqsave(&ioapic_lock, flags);
3746 reg_01.raw = io_apic_read(ioapic, 1);
3747 spin_unlock_irqrestore(&ioapic_lock, flags);
3749 return reg_01.bits.entries;
3752 void __init probe_nr_irqs_gsi(void)
3756 nr = acpi_probe_gsi();
3757 if (nr > nr_irqs_gsi) {
3760 /* for acpi=off or acpi is not compiled in */
3764 for (idx = 0; idx < nr_ioapics; idx++)
3765 nr += io_apic_get_redir_entries(idx) + 1;
3767 if (nr > nr_irqs_gsi)
3771 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3774 #ifdef CONFIG_SPARSE_IRQ
3775 int __init arch_probe_nr_irqs(void)
3779 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3780 nr_irqs = NR_VECTORS * nr_cpu_ids;
3782 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3783 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3785 * for MSI and HT dyn irq
3787 nr += nr_irqs_gsi * 16;
3796 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3797 struct io_apic_irq_attr *irq_attr)
3799 struct irq_desc *desc;
3800 struct irq_cfg *cfg;
3803 int trigger, polarity;
3805 ioapic = irq_attr->ioapic;
3806 if (!IO_APIC_IRQ(irq)) {
3807 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3813 node = dev_to_node(dev);
3815 node = cpu_to_node(boot_cpu_id);
3817 desc = irq_to_desc_alloc_node(irq, node);
3819 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3823 pin = irq_attr->ioapic_pin;
3824 trigger = irq_attr->trigger;
3825 polarity = irq_attr->polarity;
3828 * IRQs < 16 are already in the irq_2_pin[] map
3830 if (irq >= nr_legacy_irqs) {
3831 cfg = desc->chip_data;
3832 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3833 printk(KERN_INFO "can not add pin %d for irq %d\n",
3839 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3844 int io_apic_set_pci_routing(struct device *dev, int irq,
3845 struct io_apic_irq_attr *irq_attr)
3849 * Avoid pin reprogramming. PRTs typically include entries
3850 * with redundant pin->gsi mappings (but unique PCI devices);
3851 * we only program the IOAPIC on the first.
3853 ioapic = irq_attr->ioapic;
3854 pin = irq_attr->ioapic_pin;
3855 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3856 pr_debug("Pin %d-%d already programmed\n",
3857 mp_ioapics[ioapic].apicid, pin);
3860 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3862 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3865 u8 __init io_apic_unique_id(u8 id)
3867 #ifdef CONFIG_X86_32
3868 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3869 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3870 return io_apic_get_unique_id(nr_ioapics, id);
3875 DECLARE_BITMAP(used, 256);
3877 bitmap_zero(used, 256);
3878 for (i = 0; i < nr_ioapics; i++) {
3879 struct mpc_ioapic *ia = &mp_ioapics[i];
3880 __set_bit(ia->apicid, used);
3882 if (!test_bit(id, used))
3884 return find_first_zero_bit(used, 256);
3888 #ifdef CONFIG_X86_32
3889 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3891 union IO_APIC_reg_00 reg_00;
3892 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3894 unsigned long flags;
3898 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3899 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3900 * supports up to 16 on one shared APIC bus.
3902 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3903 * advantage of new APIC bus architecture.
3906 if (physids_empty(apic_id_map))
3907 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3909 spin_lock_irqsave(&ioapic_lock, flags);
3910 reg_00.raw = io_apic_read(ioapic, 0);
3911 spin_unlock_irqrestore(&ioapic_lock, flags);
3913 if (apic_id >= get_physical_broadcast()) {
3914 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3915 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3916 apic_id = reg_00.bits.ID;
3920 * Every APIC in a system must have a unique ID or we get lots of nice
3921 * 'stuck on smp_invalidate_needed IPI wait' messages.
3923 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3925 for (i = 0; i < get_physical_broadcast(); i++) {
3926 if (!apic->check_apicid_used(&apic_id_map, i))
3930 if (i == get_physical_broadcast())
3931 panic("Max apic_id exceeded!\n");
3933 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3934 "trying %d\n", ioapic, apic_id, i);
3939 apic->apicid_to_cpu_present(apic_id, &tmp);
3940 physids_or(apic_id_map, apic_id_map, tmp);
3942 if (reg_00.bits.ID != apic_id) {
3943 reg_00.bits.ID = apic_id;
3945 spin_lock_irqsave(&ioapic_lock, flags);
3946 io_apic_write(ioapic, 0, reg_00.raw);
3947 reg_00.raw = io_apic_read(ioapic, 0);
3948 spin_unlock_irqrestore(&ioapic_lock, flags);
3951 if (reg_00.bits.ID != apic_id) {
3952 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3957 apic_printk(APIC_VERBOSE, KERN_INFO
3958 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3964 int __init io_apic_get_version(int ioapic)
3966 union IO_APIC_reg_01 reg_01;
3967 unsigned long flags;
3969 spin_lock_irqsave(&ioapic_lock, flags);
3970 reg_01.raw = io_apic_read(ioapic, 1);
3971 spin_unlock_irqrestore(&ioapic_lock, flags);
3973 return reg_01.bits.version;
3976 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3980 if (skip_ioapic_setup)
3983 for (i = 0; i < mp_irq_entries; i++)
3984 if (mp_irqs[i].irqtype == mp_INT &&
3985 mp_irqs[i].srcbusirq == bus_irq)
3987 if (i >= mp_irq_entries)
3990 *trigger = irq_trigger(i);
3991 *polarity = irq_polarity(i);
3996 * This function currently is only a helper for the i386 smp boot process where
3997 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3998 * so mask in all cases should simply be apic->target_cpus()
4001 void __init setup_ioapic_dest(void)
4003 int pin, ioapic = 0, irq, irq_entry;
4004 struct irq_desc *desc;
4005 const struct cpumask *mask;
4007 if (skip_ioapic_setup == 1)
4011 if (!acpi_disabled && acpi_ioapic) {
4012 ioapic = mp_find_ioapic(0);
4018 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4019 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4020 if (irq_entry == -1)
4022 irq = pin_2_irq(irq_entry, ioapic, pin);
4024 desc = irq_to_desc(irq);
4027 * Honour affinities which have been set in early boot
4030 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4031 mask = desc->affinity;
4033 mask = apic->target_cpus();
4035 if (intr_remapping_enabled)
4036 set_ir_ioapic_affinity_irq_desc(desc, mask);
4038 set_ioapic_affinity_irq_desc(desc, mask);
4044 #define IOAPIC_RESOURCE_NAME_SIZE 11
4046 static struct resource *ioapic_resources;
4048 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4051 struct resource *res;
4055 if (nr_ioapics <= 0)
4058 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4061 mem = alloc_bootmem(n);
4064 mem += sizeof(struct resource) * nr_ioapics;
4066 for (i = 0; i < nr_ioapics; i++) {
4068 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4069 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4070 mem += IOAPIC_RESOURCE_NAME_SIZE;
4073 ioapic_resources = res;
4078 void __init ioapic_init_mappings(void)
4080 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4081 struct resource *ioapic_res;
4084 ioapic_res = ioapic_setup_resources(nr_ioapics);
4085 for (i = 0; i < nr_ioapics; i++) {
4086 if (smp_found_config) {
4087 ioapic_phys = mp_ioapics[i].apicaddr;
4088 #ifdef CONFIG_X86_32
4091 "WARNING: bogus zero IO-APIC "
4092 "address found in MPTABLE, "
4093 "disabling IO/APIC support!\n");
4094 smp_found_config = 0;
4095 skip_ioapic_setup = 1;
4096 goto fake_ioapic_page;
4100 #ifdef CONFIG_X86_32
4103 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4104 ioapic_phys = __pa(ioapic_phys);
4106 set_fixmap_nocache(idx, ioapic_phys);
4107 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4108 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4112 ioapic_res->start = ioapic_phys;
4113 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4118 void __init ioapic_insert_resources(void)
4121 struct resource *r = ioapic_resources;
4126 "IO APIC resources couldn't be allocated.\n");
4130 for (i = 0; i < nr_ioapics; i++) {
4131 insert_resource(&iomem_resource, r);
4136 int mp_find_ioapic(int gsi)
4140 /* Find the IOAPIC that manages this GSI. */
4141 for (i = 0; i < nr_ioapics; i++) {
4142 if ((gsi >= mp_gsi_routing[i].gsi_base)
4143 && (gsi <= mp_gsi_routing[i].gsi_end))
4147 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4151 int mp_find_ioapic_pin(int ioapic, int gsi)
4153 if (WARN_ON(ioapic == -1))
4155 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4158 return gsi - mp_gsi_routing[ioapic].gsi_base;
4161 static int bad_ioapic(unsigned long address)
4163 if (nr_ioapics >= MAX_IO_APICS) {
4164 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4165 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4169 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4170 " found in table, skipping!\n");
4176 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4180 if (bad_ioapic(address))
4185 mp_ioapics[idx].type = MP_IOAPIC;
4186 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4187 mp_ioapics[idx].apicaddr = address;
4189 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4190 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4191 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4194 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4195 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4197 mp_gsi_routing[idx].gsi_base = gsi_base;
4198 mp_gsi_routing[idx].gsi_end = gsi_base +
4199 io_apic_get_redir_entries(idx);
4201 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4202 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4203 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4204 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);