2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/compiler.h>
14 #include <linux/irqdomain.h>
15 #include <linux/slab.h>
16 #include <asm/hw_irq.h>
18 #include <asm/i8259.h>
20 #include <asm/irq_remapping.h>
22 static DEFINE_RAW_SPINLOCK(vector_lock);
24 void lock_vector_lock(void)
26 /* Used to the online set of cpus does not change
27 * during assign_irq_vector.
29 raw_spin_lock(&vector_lock);
32 void unlock_vector_lock(void)
34 raw_spin_unlock(&vector_lock);
37 struct irq_cfg *irq_cfg(unsigned int irq)
39 return irq_get_chip_data(irq);
42 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
44 return irq_data->chip_data;
47 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
51 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
54 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
56 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
58 #ifdef CONFIG_X86_IO_APIC
59 INIT_LIST_HEAD(&cfg->irq_2_pin);
63 free_cpumask_var(cfg->domain);
69 struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
71 int res = irq_alloc_desc_at(at, node);
82 cfg = alloc_irq_cfg(at, node);
84 irq_set_chip_data(at, cfg);
90 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
94 irq_set_chip_data(at, NULL);
95 free_cpumask_var(cfg->domain);
96 free_cpumask_var(cfg->old_domain);
101 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
104 * NOTE! The local APIC isn't very good at handling
105 * multiple interrupts at the same interrupt level.
106 * As the interrupt level is determined by taking the
107 * vector number and shifting that right by 4, we
108 * want to spread these out a bit so that they don't
109 * all fall in the same interrupt level.
111 * Also, we've got to be careful not to trash gate
112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
114 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
115 static int current_offset = VECTOR_OFFSET_START % 16;
117 cpumask_var_t tmp_mask;
119 if (cfg->move_in_progress)
122 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
125 /* Only try and allocate irqs on cpus that are present */
127 cpumask_clear(cfg->old_domain);
128 cpu = cpumask_first_and(mask, cpu_online_mask);
129 while (cpu < nr_cpu_ids) {
130 int new_cpu, vector, offset;
132 apic->vector_allocation_domain(cpu, tmp_mask, mask);
134 if (cpumask_subset(tmp_mask, cfg->domain)) {
136 if (cpumask_equal(tmp_mask, cfg->domain))
139 * New cpumask using the vector is a proper subset of
140 * the current in use mask. So cleanup the vector
141 * allocation for the members that are not used anymore.
143 cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
144 cfg->move_in_progress =
145 cpumask_intersects(cfg->old_domain, cpu_online_mask);
146 cpumask_and(cfg->domain, cfg->domain, tmp_mask);
150 vector = current_vector;
151 offset = current_offset;
154 if (vector >= first_system_vector) {
155 offset = (offset + 1) % 16;
156 vector = FIRST_EXTERNAL_VECTOR + offset;
159 if (unlikely(current_vector == vector)) {
160 cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
161 cpumask_andnot(tmp_mask, mask, cfg->old_domain);
162 cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
166 if (test_bit(vector, used_vectors))
169 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) {
170 if (per_cpu(vector_irq, new_cpu)[vector] >
175 current_vector = vector;
176 current_offset = offset;
178 cpumask_copy(cfg->old_domain, cfg->domain);
179 cfg->move_in_progress =
180 cpumask_intersects(cfg->old_domain, cpu_online_mask);
182 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
183 per_cpu(vector_irq, new_cpu)[vector] = irq;
184 cfg->vector = vector;
185 cpumask_copy(cfg->domain, tmp_mask);
189 free_cpumask_var(tmp_mask);
194 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
199 raw_spin_lock_irqsave(&vector_lock, flags);
200 err = __assign_irq_vector(irq, cfg, mask);
201 raw_spin_unlock_irqrestore(&vector_lock, flags);
205 void clear_irq_vector(int irq, struct irq_cfg *cfg)
210 raw_spin_lock_irqsave(&vector_lock, flags);
211 BUG_ON(!cfg->vector);
213 vector = cfg->vector;
214 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
215 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
218 cpumask_clear(cfg->domain);
220 if (likely(!cfg->move_in_progress)) {
221 raw_spin_unlock_irqrestore(&vector_lock, flags);
225 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
226 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
228 if (per_cpu(vector_irq, cpu)[vector] != irq)
230 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
234 cfg->move_in_progress = 0;
235 raw_spin_unlock_irqrestore(&vector_lock, flags);
238 int __init arch_probe_nr_irqs(void)
242 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
243 nr_irqs = NR_VECTORS * nr_cpu_ids;
245 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
246 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
248 * for MSI and HT dyn irq
250 if (gsi_top <= NR_IRQS_LEGACY)
251 nr += 8 * nr_cpu_ids;
258 return nr_legacy_irqs();
261 int __init arch_early_irq_init(void)
263 return arch_early_ioapic_init();
266 static void __setup_vector_irq(int cpu)
268 /* Initialize vector_irq on a new cpu */
273 * vector_lock will make sure that we don't run into irq vector
274 * assignments that might be happening on another cpu in parallel,
275 * while we setup our initial vector to irq mappings.
277 raw_spin_lock(&vector_lock);
278 /* Mark the inuse vectors */
279 for_each_active_irq(irq) {
284 if (!cpumask_test_cpu(cpu, cfg->domain))
286 vector = cfg->vector;
287 per_cpu(vector_irq, cpu)[vector] = irq;
289 /* Mark the free vectors */
290 for (vector = 0; vector < NR_VECTORS; ++vector) {
291 irq = per_cpu(vector_irq, cpu)[vector];
292 if (irq <= VECTOR_UNDEFINED)
296 if (!cpumask_test_cpu(cpu, cfg->domain))
297 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
299 raw_spin_unlock(&vector_lock);
303 * Setup the vector to irq mappings.
305 void setup_vector_irq(int cpu)
310 * On most of the platforms, legacy PIC delivers the interrupts on the
311 * boot cpu. But there are certain platforms where PIC interrupts are
312 * delivered to multiple cpu's. If the legacy IRQ is handled by the
313 * legacy PIC, for the new cpu that is coming online, setup the static
314 * legacy vector to irq mapping:
316 for (irq = 0; irq < nr_legacy_irqs(); irq++)
317 per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
319 __setup_vector_irq(cpu);
322 int apic_retrigger_irq(struct irq_data *data)
324 struct irq_cfg *cfg = data->chip_data;
328 raw_spin_lock_irqsave(&vector_lock, flags);
329 cpu = cpumask_first_and(cfg->domain, cpu_online_mask);
330 apic->send_IPI_mask(cpumask_of(cpu), cfg->vector);
331 raw_spin_unlock_irqrestore(&vector_lock, flags);
336 void apic_ack_edge(struct irq_data *data)
338 irq_complete_move(data->chip_data);
344 * Either sets data->affinity to a valid value, and returns
345 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
346 * leaves data->affinity untouched.
348 int apic_set_affinity(struct irq_data *data, const struct cpumask *mask,
349 unsigned int *dest_id)
351 struct irq_cfg *cfg = data->chip_data;
352 unsigned int irq = data->irq;
355 if (!config_enabled(CONFIG_SMP))
358 if (!cpumask_intersects(mask, cpu_online_mask))
361 err = assign_irq_vector(irq, cfg, mask);
365 err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
367 if (assign_irq_vector(irq, cfg, data->affinity))
368 pr_err("Failed to recover vector for irq %d\n", irq);
372 cpumask_copy(data->affinity, mask);
378 void send_cleanup_vector(struct irq_cfg *cfg)
380 cpumask_var_t cleanup_mask;
382 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
385 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
386 apic->send_IPI_mask(cpumask_of(i),
387 IRQ_MOVE_CLEANUP_VECTOR);
389 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
390 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
391 free_cpumask_var(cleanup_mask);
393 cfg->move_in_progress = 0;
396 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
404 me = smp_processor_id();
405 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
408 struct irq_desc *desc;
411 irq = __this_cpu_read(vector_irq[vector]);
413 if (irq <= VECTOR_UNDEFINED)
416 desc = irq_to_desc(irq);
424 raw_spin_lock(&desc->lock);
427 * Check if the irq migration is in progress. If so, we
428 * haven't received the cleanup request yet for this irq.
430 if (cfg->move_in_progress)
433 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
436 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
438 * Check if the vector that needs to be cleanedup is
439 * registered at the cpu's IRR. If so, then this is not
440 * the best time to clean it up. Lets clean it up in the
441 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
444 if (irr & (1 << (vector % 32))) {
445 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
448 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
450 raw_spin_unlock(&desc->lock);
456 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
460 if (likely(!cfg->move_in_progress))
463 me = smp_processor_id();
465 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
466 send_cleanup_vector(cfg);
469 void irq_complete_move(struct irq_cfg *cfg)
471 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
474 void irq_force_complete_move(int irq)
476 struct irq_cfg *cfg = irq_cfg(irq);
481 __irq_complete_move(cfg, cfg->vector);
486 * Dynamic irq allocate and deallocation. Should be replaced by irq domains!
488 int arch_setup_hwirq(unsigned int irq, int node)
494 cfg = alloc_irq_cfg(irq, node);
498 raw_spin_lock_irqsave(&vector_lock, flags);
499 ret = __assign_irq_vector(irq, cfg, apic->target_cpus());
500 raw_spin_unlock_irqrestore(&vector_lock, flags);
503 irq_set_chip_data(irq, cfg);
505 free_irq_cfg(irq, cfg);
509 void arch_teardown_hwirq(unsigned int irq)
511 struct irq_cfg *cfg = irq_cfg(irq);
513 free_remapped_irq(irq);
514 clear_irq_vector(irq, cfg);
515 free_irq_cfg(irq, cfg);
518 static void __init print_APIC_field(int base)
524 for (i = 0; i < 8; i++)
525 pr_cont("%08x", apic_read(base + i*0x10));
530 static void __init print_local_APIC(void *dummy)
532 unsigned int i, v, ver, maxlvt;
535 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
536 smp_processor_id(), hard_smp_processor_id());
537 v = apic_read(APIC_ID);
538 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
539 v = apic_read(APIC_LVR);
540 pr_info("... APIC VERSION: %08x\n", v);
541 ver = GET_APIC_VERSION(v);
542 maxlvt = lapic_get_maxlvt();
544 v = apic_read(APIC_TASKPRI);
545 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
548 if (APIC_INTEGRATED(ver)) {
549 if (!APIC_XAPIC(ver)) {
550 v = apic_read(APIC_ARBPRI);
551 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
552 v, v & APIC_ARBPRI_MASK);
554 v = apic_read(APIC_PROCPRI);
555 pr_debug("... APIC PROCPRI: %08x\n", v);
559 * Remote read supported only in the 82489DX and local APIC for
560 * Pentium processors.
562 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
563 v = apic_read(APIC_RRR);
564 pr_debug("... APIC RRR: %08x\n", v);
567 v = apic_read(APIC_LDR);
568 pr_debug("... APIC LDR: %08x\n", v);
569 if (!x2apic_enabled()) {
570 v = apic_read(APIC_DFR);
571 pr_debug("... APIC DFR: %08x\n", v);
573 v = apic_read(APIC_SPIV);
574 pr_debug("... APIC SPIV: %08x\n", v);
576 pr_debug("... APIC ISR field:\n");
577 print_APIC_field(APIC_ISR);
578 pr_debug("... APIC TMR field:\n");
579 print_APIC_field(APIC_TMR);
580 pr_debug("... APIC IRR field:\n");
581 print_APIC_field(APIC_IRR);
584 if (APIC_INTEGRATED(ver)) {
585 /* Due to the Pentium erratum 3AP. */
587 apic_write(APIC_ESR, 0);
589 v = apic_read(APIC_ESR);
590 pr_debug("... APIC ESR: %08x\n", v);
593 icr = apic_icr_read();
594 pr_debug("... APIC ICR: %08x\n", (u32)icr);
595 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
597 v = apic_read(APIC_LVTT);
598 pr_debug("... APIC LVTT: %08x\n", v);
602 v = apic_read(APIC_LVTPC);
603 pr_debug("... APIC LVTPC: %08x\n", v);
605 v = apic_read(APIC_LVT0);
606 pr_debug("... APIC LVT0: %08x\n", v);
607 v = apic_read(APIC_LVT1);
608 pr_debug("... APIC LVT1: %08x\n", v);
612 v = apic_read(APIC_LVTERR);
613 pr_debug("... APIC LVTERR: %08x\n", v);
616 v = apic_read(APIC_TMICT);
617 pr_debug("... APIC TMICT: %08x\n", v);
618 v = apic_read(APIC_TMCCT);
619 pr_debug("... APIC TMCCT: %08x\n", v);
620 v = apic_read(APIC_TDCR);
621 pr_debug("... APIC TDCR: %08x\n", v);
623 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
624 v = apic_read(APIC_EFEAT);
625 maxlvt = (v >> 16) & 0xff;
626 pr_debug("... APIC EFEAT: %08x\n", v);
627 v = apic_read(APIC_ECTRL);
628 pr_debug("... APIC ECTRL: %08x\n", v);
629 for (i = 0; i < maxlvt; i++) {
630 v = apic_read(APIC_EILVTn(i));
631 pr_debug("... APIC EILVT%d: %08x\n", i, v);
637 static void __init print_local_APICs(int maxcpu)
645 for_each_online_cpu(cpu) {
648 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
653 static void __init print_PIC(void)
658 if (!nr_legacy_irqs())
661 pr_debug("\nprinting PIC contents\n");
663 raw_spin_lock_irqsave(&i8259A_lock, flags);
665 v = inb(0xa1) << 8 | inb(0x21);
666 pr_debug("... PIC IMR: %04x\n", v);
668 v = inb(0xa0) << 8 | inb(0x20);
669 pr_debug("... PIC IRR: %04x\n", v);
673 v = inb(0xa0) << 8 | inb(0x20);
677 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
679 pr_debug("... PIC ISR: %04x\n", v);
681 v = inb(0x4d1) << 8 | inb(0x4d0);
682 pr_debug("... PIC ELCR: %04x\n", v);
685 static int show_lapic __initdata = 1;
686 static __init int setup_show_lapic(char *arg)
690 if (strcmp(arg, "all") == 0) {
691 show_lapic = CONFIG_NR_CPUS;
693 get_option(&arg, &num);
700 __setup("show_lapic=", setup_show_lapic);
702 static int __init print_ICs(void)
704 if (apic_verbosity == APIC_QUIET)
709 /* don't print out if apic is not there */
710 if (!cpu_has_apic && !apic_from_smp_config())
713 print_local_APICs(show_lapic);
719 late_initcall(print_ICs);