1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
44 #include <asm/microcode.h>
45 #include <asm/microcode_intel.h>
47 #ifdef CONFIG_X86_LOCAL_APIC
48 #include <asm/uv/uv.h>
53 /* all of these masks are initialized in setup_cpu_local_masks() */
54 cpumask_var_t cpu_initialized_mask;
55 cpumask_var_t cpu_callout_mask;
56 cpumask_var_t cpu_callin_mask;
58 /* representing cpus for which sibling maps can be computed */
59 cpumask_var_t cpu_sibling_setup_mask;
61 /* correctly size the local cpu masks */
62 void __init setup_cpu_local_masks(void)
64 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
65 alloc_bootmem_cpumask_var(&cpu_callin_mask);
66 alloc_bootmem_cpumask_var(&cpu_callout_mask);
67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
70 static void default_init(struct cpuinfo_x86 *c)
73 cpu_detect_cache_sizes(c);
75 /* Not much we can do here... */
76 /* Check if at least it has cpuid */
77 if (c->cpuid_level == -1) {
78 /* No cpuid. It must be an ancient CPU */
80 strcpy(c->x86_model_id, "486");
82 strcpy(c->x86_model_id, "386");
87 static const struct cpu_dev default_cpu = {
88 .c_init = default_init,
89 .c_vendor = "Unknown",
90 .c_x86_vendor = X86_VENDOR_UNKNOWN,
93 static const struct cpu_dev *this_cpu = &default_cpu;
95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
98 * We need valid kernel segments for data and code in long mode too
99 * IRET will check the segment types kkeil 2000/10/28
100 * Also sysret mandates a special GDT layout
102 * TLS descriptors are currently at a different place compared to i386.
103 * Hopefully nobody expects them at a fixed place (Wine?)
105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
117 * Segments used for calling PnP BIOS have byte granularity.
118 * They code segments and data segments have fixed 64k limits,
119 * the transfer segment sizes are set at run time.
122 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
124 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
126 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
128 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
130 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 * The APM segments have byte granularity and their bases
133 * are set at run time. All have 64k limits.
136 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
138 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
140 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
142 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 GDT_STACK_CANARY_INIT
147 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
149 static int __init x86_mpx_setup(char *s)
151 /* require an exact match without trailing characters */
155 /* do not emit a message if the feature is not present */
156 if (!boot_cpu_has(X86_FEATURE_MPX))
159 setup_clear_cpu_cap(X86_FEATURE_MPX);
160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
163 __setup("nompx", x86_mpx_setup);
166 static int cachesize_override = -1;
167 static int disable_x86_serial_nr = 1;
169 static int __init cachesize_setup(char *str)
171 get_option(&str, &cachesize_override);
174 __setup("cachesize=", cachesize_setup);
176 static int __init x86_sep_setup(char *s)
178 setup_clear_cpu_cap(X86_FEATURE_SEP);
181 __setup("nosep", x86_sep_setup);
183 /* Standard macro to see if a specific flag is changeable */
184 static inline int flag_is_changeable_p(u32 flag)
189 * Cyrix and IDT cpus allow disabling of CPUID
190 * so the code below may return different results
191 * when it is executed before and after enabling
192 * the CPUID. Add "volatile" to not allow gcc to
193 * optimize the subsequent calls to this function.
195 asm volatile ("pushfl \n\t"
206 : "=&r" (f1), "=&r" (f2)
209 return ((f1^f2) & flag) != 0;
212 /* Probe for the CPUID instruction */
213 int have_cpuid_p(void)
215 return flag_is_changeable_p(X86_EFLAGS_ID);
218 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
220 unsigned long lo, hi;
222 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
225 /* Disable processor serial number: */
227 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
229 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
231 printk(KERN_NOTICE "CPU serial number disabled.\n");
232 clear_cpu_cap(c, X86_FEATURE_PN);
234 /* Disabling the serial number may affect the cpuid level */
235 c->cpuid_level = cpuid_eax(0);
238 static int __init x86_serial_nr_setup(char *s)
240 disable_x86_serial_nr = 0;
243 __setup("serialnumber", x86_serial_nr_setup);
245 static inline int flag_is_changeable_p(u32 flag)
249 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
254 static __init int setup_disable_smep(char *arg)
256 setup_clear_cpu_cap(X86_FEATURE_SMEP);
259 __setup("nosmep", setup_disable_smep);
261 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
263 if (cpu_has(c, X86_FEATURE_SMEP))
264 cr4_set_bits(X86_CR4_SMEP);
267 static __init int setup_disable_smap(char *arg)
269 setup_clear_cpu_cap(X86_FEATURE_SMAP);
272 __setup("nosmap", setup_disable_smap);
274 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
276 unsigned long eflags;
278 /* This should have been cleared long ago */
279 raw_local_save_flags(eflags);
280 BUG_ON(eflags & X86_EFLAGS_AC);
282 if (cpu_has(c, X86_FEATURE_SMAP)) {
283 #ifdef CONFIG_X86_SMAP
284 cr4_set_bits(X86_CR4_SMAP);
286 cr4_clear_bits(X86_CR4_SMAP);
292 * Some CPU features depend on higher CPUID levels, which may not always
293 * be available due to CPUID level capping or broken virtualization
294 * software. Add those features to this table to auto-disable them.
296 struct cpuid_dependent_feature {
301 static const struct cpuid_dependent_feature
302 cpuid_dependent_features[] = {
303 { X86_FEATURE_MWAIT, 0x00000005 },
304 { X86_FEATURE_DCA, 0x00000009 },
305 { X86_FEATURE_XSAVE, 0x0000000d },
309 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
311 const struct cpuid_dependent_feature *df;
313 for (df = cpuid_dependent_features; df->feature; df++) {
315 if (!cpu_has(c, df->feature))
318 * Note: cpuid_level is set to -1 if unavailable, but
319 * extended_extended_level is set to 0 if unavailable
320 * and the legitimate extended levels are all negative
321 * when signed; hence the weird messing around with
324 if (!((s32)df->level < 0 ?
325 (u32)df->level > (u32)c->extended_cpuid_level :
326 (s32)df->level > (s32)c->cpuid_level))
329 clear_cpu_cap(c, df->feature);
334 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
335 x86_cap_flag(df->feature), df->level);
340 * Naming convention should be: <Name> [(<Codename>)]
341 * This table only is used unless init_<vendor>() below doesn't set it;
342 * in particular, if CPUID levels 0x80000002..4 are supported, this
346 /* Look up CPU names by table lookup. */
347 static const char *table_lookup_model(struct cpuinfo_x86 *c)
350 const struct legacy_cpu_model_info *info;
352 if (c->x86_model >= 16)
353 return NULL; /* Range check */
358 info = this_cpu->legacy_models;
360 while (info->family) {
361 if (info->family == c->x86)
362 return info->model_names[c->x86_model];
366 return NULL; /* Not found */
369 __u32 cpu_caps_cleared[NCAPINTS];
370 __u32 cpu_caps_set[NCAPINTS];
372 void load_percpu_segment(int cpu)
375 loadsegment(fs, __KERNEL_PERCPU);
378 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
380 load_stack_canary_segment();
384 * Current gdt points %fs at the "master" per-cpu area: after this,
385 * it's on the real one.
387 void switch_to_new_gdt(int cpu)
389 struct desc_ptr gdt_descr;
391 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
392 gdt_descr.size = GDT_SIZE - 1;
393 load_gdt(&gdt_descr);
394 /* Reload the per-cpu base */
396 load_percpu_segment(cpu);
399 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
401 static void get_model_name(struct cpuinfo_x86 *c)
406 if (c->extended_cpuid_level < 0x80000004)
409 v = (unsigned int *)c->x86_model_id;
410 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
411 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
412 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
413 c->x86_model_id[48] = 0;
415 /* Trim whitespace */
416 p = q = s = &c->x86_model_id[0];
422 /* Note the last non-whitespace index */
432 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
434 unsigned int n, dummy, ebx, ecx, edx, l2size;
436 n = c->extended_cpuid_level;
438 if (n >= 0x80000005) {
439 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
440 c->x86_cache_size = (ecx>>24) + (edx>>24);
442 /* On K8 L1 TLB is inclusive, so don't count it */
447 if (n < 0x80000006) /* Some chips just has a large L1. */
450 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
454 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
456 /* do processor-specific cache resizing */
457 if (this_cpu->legacy_cache_size)
458 l2size = this_cpu->legacy_cache_size(c, l2size);
460 /* Allow user to override all this if necessary. */
461 if (cachesize_override != -1)
462 l2size = cachesize_override;
465 return; /* Again, no L2 cache is possible */
468 c->x86_cache_size = l2size;
471 u16 __read_mostly tlb_lli_4k[NR_INFO];
472 u16 __read_mostly tlb_lli_2m[NR_INFO];
473 u16 __read_mostly tlb_lli_4m[NR_INFO];
474 u16 __read_mostly tlb_lld_4k[NR_INFO];
475 u16 __read_mostly tlb_lld_2m[NR_INFO];
476 u16 __read_mostly tlb_lld_4m[NR_INFO];
477 u16 __read_mostly tlb_lld_1g[NR_INFO];
479 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
481 if (this_cpu->c_detect_tlb)
482 this_cpu->c_detect_tlb(c);
484 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
485 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
486 tlb_lli_4m[ENTRIES]);
488 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
489 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
490 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
493 void detect_ht(struct cpuinfo_x86 *c)
496 u32 eax, ebx, ecx, edx;
497 int index_msb, core_bits;
500 if (!cpu_has(c, X86_FEATURE_HT))
503 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
506 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
509 cpuid(1, &eax, &ebx, &ecx, &edx);
511 smp_num_siblings = (ebx & 0xff0000) >> 16;
513 if (smp_num_siblings == 1) {
514 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
518 if (smp_num_siblings <= 1)
521 index_msb = get_count_order(smp_num_siblings);
522 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
524 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
526 index_msb = get_count_order(smp_num_siblings);
528 core_bits = get_count_order(c->x86_max_cores);
530 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
531 ((1 << core_bits) - 1);
534 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
535 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
537 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
544 static void get_cpu_vendor(struct cpuinfo_x86 *c)
546 char *v = c->x86_vendor_id;
549 for (i = 0; i < X86_VENDOR_NUM; i++) {
553 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
554 (cpu_devs[i]->c_ident[1] &&
555 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
557 this_cpu = cpu_devs[i];
558 c->x86_vendor = this_cpu->c_x86_vendor;
564 "CPU: vendor_id '%s' unknown, using generic init.\n" \
565 "CPU: Your system may be unstable.\n", v);
567 c->x86_vendor = X86_VENDOR_UNKNOWN;
568 this_cpu = &default_cpu;
571 void cpu_detect(struct cpuinfo_x86 *c)
573 /* Get vendor name */
574 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
575 (unsigned int *)&c->x86_vendor_id[0],
576 (unsigned int *)&c->x86_vendor_id[8],
577 (unsigned int *)&c->x86_vendor_id[4]);
580 /* Intel-defined flags: level 0x00000001 */
581 if (c->cpuid_level >= 0x00000001) {
582 u32 junk, tfms, cap0, misc;
584 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
585 c->x86 = (tfms >> 8) & 0xf;
586 c->x86_model = (tfms >> 4) & 0xf;
587 c->x86_mask = tfms & 0xf;
590 c->x86 += (tfms >> 20) & 0xff;
592 c->x86_model += ((tfms >> 16) & 0xf) << 4;
594 if (cap0 & (1<<19)) {
595 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
596 c->x86_cache_alignment = c->x86_clflush_size;
601 void get_cpu_cap(struct cpuinfo_x86 *c)
606 /* Intel-defined flags: level 0x00000001 */
607 if (c->cpuid_level >= 0x00000001) {
608 u32 capability, excap;
610 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
611 c->x86_capability[0] = capability;
612 c->x86_capability[4] = excap;
615 /* Additional Intel-defined flags: level 0x00000007 */
616 if (c->cpuid_level >= 0x00000007) {
617 u32 eax, ebx, ecx, edx;
619 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
621 c->x86_capability[9] = ebx;
624 /* Extended state features: level 0x0000000d */
625 if (c->cpuid_level >= 0x0000000d) {
626 u32 eax, ebx, ecx, edx;
628 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
630 c->x86_capability[10] = eax;
633 /* Additional Intel-defined flags: level 0x0000000F */
634 if (c->cpuid_level >= 0x0000000F) {
635 u32 eax, ebx, ecx, edx;
637 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
638 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
639 c->x86_capability[11] = edx;
640 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
641 /* will be overridden if occupancy monitoring exists */
642 c->x86_cache_max_rmid = ebx;
644 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
645 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
646 c->x86_capability[12] = edx;
647 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) {
648 c->x86_cache_max_rmid = ecx;
649 c->x86_cache_occ_scale = ebx;
652 c->x86_cache_max_rmid = -1;
653 c->x86_cache_occ_scale = -1;
657 /* AMD-defined flags: level 0x80000001 */
658 xlvl = cpuid_eax(0x80000000);
659 c->extended_cpuid_level = xlvl;
661 if ((xlvl & 0xffff0000) == 0x80000000) {
662 if (xlvl >= 0x80000001) {
663 c->x86_capability[1] = cpuid_edx(0x80000001);
664 c->x86_capability[6] = cpuid_ecx(0x80000001);
668 if (c->extended_cpuid_level >= 0x80000008) {
669 u32 eax = cpuid_eax(0x80000008);
671 c->x86_virt_bits = (eax >> 8) & 0xff;
672 c->x86_phys_bits = eax & 0xff;
675 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
676 c->x86_phys_bits = 36;
679 if (c->extended_cpuid_level >= 0x80000007)
680 c->x86_power = cpuid_edx(0x80000007);
682 init_scattered_cpuid_features(c);
685 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
691 * First of all, decide if this is a 486 or higher
692 * It's a 486 if we can modify the AC flag
694 if (flag_is_changeable_p(X86_EFLAGS_AC))
699 for (i = 0; i < X86_VENDOR_NUM; i++)
700 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
701 c->x86_vendor_id[0] = 0;
702 cpu_devs[i]->c_identify(c);
703 if (c->x86_vendor_id[0]) {
712 * Do minimum CPU detection early.
713 * Fields really needed: vendor, cpuid_level, family, model, mask,
715 * The others are not touched to avoid unwanted side effects.
717 * WARNING: this function is only called on the BP. Don't add code here
718 * that is supposed to run on all CPUs.
720 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
723 c->x86_clflush_size = 64;
724 c->x86_phys_bits = 36;
725 c->x86_virt_bits = 48;
727 c->x86_clflush_size = 32;
728 c->x86_phys_bits = 32;
729 c->x86_virt_bits = 32;
731 c->x86_cache_alignment = c->x86_clflush_size;
733 memset(&c->x86_capability, 0, sizeof c->x86_capability);
734 c->extended_cpuid_level = 0;
737 identify_cpu_without_cpuid(c);
739 /* cyrix could have cpuid enabled via c_identify()*/
747 if (this_cpu->c_early_init)
748 this_cpu->c_early_init(c);
751 filter_cpuid_features(c, false);
753 if (this_cpu->c_bsp_init)
754 this_cpu->c_bsp_init(c);
756 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
760 void __init early_cpu_init(void)
762 const struct cpu_dev *const *cdev;
765 #ifdef CONFIG_PROCESSOR_SELECT
766 printk(KERN_INFO "KERNEL supported cpus:\n");
769 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
770 const struct cpu_dev *cpudev = *cdev;
772 if (count >= X86_VENDOR_NUM)
774 cpu_devs[count] = cpudev;
777 #ifdef CONFIG_PROCESSOR_SELECT
781 for (j = 0; j < 2; j++) {
782 if (!cpudev->c_ident[j])
784 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
790 early_identify_cpu(&boot_cpu_data);
794 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
795 * unfortunately, that's not true in practice because of early VIA
796 * chips and (more importantly) broken virtualizers that are not easy
797 * to detect. In the latter case it doesn't even *fail* reliably, so
798 * probing for it doesn't even work. Disable it completely on 32-bit
799 * unless we can find a reliable way to detect all the broken cases.
800 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
802 static void detect_nopl(struct cpuinfo_x86 *c)
805 clear_cpu_cap(c, X86_FEATURE_NOPL);
807 set_cpu_cap(c, X86_FEATURE_NOPL);
811 static void generic_identify(struct cpuinfo_x86 *c)
813 c->extended_cpuid_level = 0;
816 identify_cpu_without_cpuid(c);
818 /* cyrix could have cpuid enabled via c_identify()*/
828 if (c->cpuid_level >= 0x00000001) {
829 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
832 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
834 c->apicid = c->initial_apicid;
837 c->phys_proc_id = c->initial_apicid;
840 get_model_name(c); /* Default name */
845 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
848 * The heavy lifting of max_rmid and cache_occ_scale are handled
849 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
850 * in case CQM bits really aren't there in this CPU.
852 if (c != &boot_cpu_data) {
853 boot_cpu_data.x86_cache_max_rmid =
854 min(boot_cpu_data.x86_cache_max_rmid,
855 c->x86_cache_max_rmid);
860 * This does the hard work of actually picking apart the CPU stuff...
862 static void identify_cpu(struct cpuinfo_x86 *c)
866 c->loops_per_jiffy = loops_per_jiffy;
867 c->x86_cache_size = -1;
868 c->x86_vendor = X86_VENDOR_UNKNOWN;
869 c->x86_model = c->x86_mask = 0; /* So far unknown... */
870 c->x86_vendor_id[0] = '\0'; /* Unset */
871 c->x86_model_id[0] = '\0'; /* Unset */
872 c->x86_max_cores = 1;
873 c->x86_coreid_bits = 0;
875 c->x86_clflush_size = 64;
876 c->x86_phys_bits = 36;
877 c->x86_virt_bits = 48;
879 c->cpuid_level = -1; /* CPUID not detected */
880 c->x86_clflush_size = 32;
881 c->x86_phys_bits = 32;
882 c->x86_virt_bits = 32;
884 c->x86_cache_alignment = c->x86_clflush_size;
885 memset(&c->x86_capability, 0, sizeof c->x86_capability);
889 if (this_cpu->c_identify)
890 this_cpu->c_identify(c);
892 /* Clear/Set all flags overriden by options, after probe */
893 for (i = 0; i < NCAPINTS; i++) {
894 c->x86_capability[i] &= ~cpu_caps_cleared[i];
895 c->x86_capability[i] |= cpu_caps_set[i];
899 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
903 * Vendor-specific initialization. In this section we
904 * canonicalize the feature flags, meaning if there are
905 * features a certain CPU supports which CPUID doesn't
906 * tell us, CPUID claiming incorrect flags, or other bugs,
907 * we handle them here.
909 * At the end of this section, c->x86_capability better
910 * indicate the features this CPU genuinely supports!
912 if (this_cpu->c_init)
915 /* Disable the PN if appropriate */
916 squash_the_stupid_serial_number(c);
918 /* Set up SMEP/SMAP */
923 * The vendor-specific functions might have changed features.
924 * Now we do "generic changes."
927 /* Filter out anything that depends on CPUID levels we don't have */
928 filter_cpuid_features(c, true);
930 /* If the model name is still unset, do table lookup. */
931 if (!c->x86_model_id[0]) {
933 p = table_lookup_model(c);
935 strcpy(c->x86_model_id, p);
938 sprintf(c->x86_model_id, "%02x/%02x",
939 c->x86, c->x86_model);
948 x86_init_cache_qos(c);
951 * Clear/Set all flags overriden by options, need do it
952 * before following smp all cpus cap AND.
954 for (i = 0; i < NCAPINTS; i++) {
955 c->x86_capability[i] &= ~cpu_caps_cleared[i];
956 c->x86_capability[i] |= cpu_caps_set[i];
960 * On SMP, boot_cpu_data holds the common feature set between
961 * all CPUs; so make sure that we indicate which features are
962 * common between the CPUs. The first time this routine gets
963 * executed, c == &boot_cpu_data.
965 if (c != &boot_cpu_data) {
966 /* AND the already accumulated flags with these */
967 for (i = 0; i < NCAPINTS; i++)
968 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
970 /* OR, i.e. replicate the bug flags */
971 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
972 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
975 /* Init Machine Check Exception if available. */
978 select_idle_routine(c);
981 numa_add_cpu(smp_processor_id());
986 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
990 void enable_sep_cpu(void)
992 struct tss_struct *tss;
996 tss = &per_cpu(cpu_tss, cpu);
998 if (!boot_cpu_has(X86_FEATURE_SEP))
1002 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1003 * see the big comment in struct x86_hw_tss's definition.
1006 tss->x86_tss.ss1 = __KERNEL_CS;
1007 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1009 wrmsr(MSR_IA32_SYSENTER_ESP,
1010 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1013 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1020 void __init identify_boot_cpu(void)
1022 identify_cpu(&boot_cpu_data);
1023 init_amd_e400_c1e_mask();
1024 #ifdef CONFIG_X86_32
1028 cpu_detect_tlb(&boot_cpu_data);
1031 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1033 BUG_ON(c == &boot_cpu_data);
1035 #ifdef CONFIG_X86_32
1046 static const struct msr_range msr_range_array[] = {
1047 { 0x00000000, 0x00000418},
1048 { 0xc0000000, 0xc000040b},
1049 { 0xc0010000, 0xc0010142},
1050 { 0xc0011000, 0xc001103b},
1053 static void __print_cpu_msr(void)
1055 unsigned index_min, index_max;
1060 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1061 index_min = msr_range_array[i].min;
1062 index_max = msr_range_array[i].max;
1064 for (index = index_min; index < index_max; index++) {
1065 if (rdmsrl_safe(index, &val))
1067 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1072 static int show_msr;
1074 static __init int setup_show_msr(char *arg)
1078 get_option(&arg, &num);
1084 __setup("show_msr=", setup_show_msr);
1086 static __init int setup_noclflush(char *arg)
1088 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1089 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1092 __setup("noclflush", setup_noclflush);
1094 void print_cpu_info(struct cpuinfo_x86 *c)
1096 const char *vendor = NULL;
1098 if (c->x86_vendor < X86_VENDOR_NUM) {
1099 vendor = this_cpu->c_vendor;
1101 if (c->cpuid_level >= 0)
1102 vendor = c->x86_vendor_id;
1105 if (vendor && !strstr(c->x86_model_id, vendor))
1106 printk(KERN_CONT "%s ", vendor);
1108 if (c->x86_model_id[0])
1109 printk(KERN_CONT "%s", c->x86_model_id);
1111 printk(KERN_CONT "%d86", c->x86);
1113 printk(KERN_CONT " (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1115 if (c->x86_mask || c->cpuid_level >= 0)
1116 printk(KERN_CONT ", stepping: 0x%x)\n", c->x86_mask);
1118 printk(KERN_CONT ")\n");
1123 void print_cpu_msr(struct cpuinfo_x86 *c)
1125 if (c->cpu_index < show_msr)
1129 static __init int setup_disablecpuid(char *arg)
1133 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1134 setup_clear_cpu_cap(bit);
1140 __setup("clearcpuid=", setup_disablecpuid);
1142 #ifdef CONFIG_X86_64
1143 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1144 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1145 (unsigned long) debug_idt_table };
1147 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1148 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1151 * The following percpu variables are hot. Align current_task to
1152 * cacheline size such that they fall in the same cacheline.
1154 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1156 EXPORT_PER_CPU_SYMBOL(current_task);
1158 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1159 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1161 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1163 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1164 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1167 * Special IST stacks which the CPU switches to when it calls
1168 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1169 * limit), all of them are 4K, except the debug stack which
1172 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1173 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1174 [DEBUG_STACK - 1] = DEBUG_STKSZ
1177 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1178 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1180 /* May not be marked __init: used by software suspend */
1181 void syscall_init(void)
1184 * LSTAR and STAR live in a bit strange symbiosis.
1185 * They both write to the same internal register. STAR allows to
1186 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1188 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1189 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1191 #ifdef CONFIG_IA32_EMULATION
1192 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1194 * This only works on Intel CPUs.
1195 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1196 * This does not cause SYSENTER to jump to the wrong location, because
1197 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1199 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1200 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1201 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1203 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1204 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1205 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1206 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1209 /* Flags to clear on syscall */
1210 wrmsrl(MSR_SYSCALL_MASK,
1211 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1212 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1216 * Copies of the original ist values from the tss are only accessed during
1217 * debugging, no special alignment required.
1219 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1221 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1222 DEFINE_PER_CPU(int, debug_stack_usage);
1224 int is_debug_stack(unsigned long addr)
1226 return __this_cpu_read(debug_stack_usage) ||
1227 (addr <= __this_cpu_read(debug_stack_addr) &&
1228 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1230 NOKPROBE_SYMBOL(is_debug_stack);
1232 DEFINE_PER_CPU(u32, debug_idt_ctr);
1234 void debug_stack_set_zero(void)
1236 this_cpu_inc(debug_idt_ctr);
1239 NOKPROBE_SYMBOL(debug_stack_set_zero);
1241 void debug_stack_reset(void)
1243 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1245 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1248 NOKPROBE_SYMBOL(debug_stack_reset);
1250 #else /* CONFIG_X86_64 */
1252 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1253 EXPORT_PER_CPU_SYMBOL(current_task);
1254 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1255 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1258 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1259 * the top of the kernel stack. Use an extra percpu variable to track the
1260 * top of the kernel stack directly.
1262 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1263 (unsigned long)&init_thread_union + THREAD_SIZE;
1264 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1266 #ifdef CONFIG_CC_STACKPROTECTOR
1267 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1270 #endif /* CONFIG_X86_64 */
1273 * Clear all 6 debug registers:
1275 static void clear_all_debug_regs(void)
1279 for (i = 0; i < 8; i++) {
1280 /* Ignore db4, db5 */
1281 if ((i == 4) || (i == 5))
1290 * Restore debug regs if using kgdbwait and you have a kernel debugger
1291 * connection established.
1293 static void dbg_restore_debug_regs(void)
1295 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1296 arch_kgdb_ops.correct_hw_break();
1298 #else /* ! CONFIG_KGDB */
1299 #define dbg_restore_debug_regs()
1300 #endif /* ! CONFIG_KGDB */
1302 static void wait_for_master_cpu(int cpu)
1306 * wait for ACK from master CPU before continuing
1307 * with AP initialization
1309 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1310 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1316 * cpu_init() initializes state that is per-CPU. Some data is already
1317 * initialized (naturally) in the bootstrap process, such as the GDT
1318 * and IDT. We reload them nevertheless, this function acts as a
1319 * 'CPU state barrier', nothing should get across.
1320 * A lot of state is already set up in PDA init for 64 bit
1322 #ifdef CONFIG_X86_64
1326 struct orig_ist *oist;
1327 struct task_struct *me;
1328 struct tss_struct *t;
1330 int cpu = stack_smp_processor_id();
1333 wait_for_master_cpu(cpu);
1336 * Initialize the CR4 shadow before doing anything that could
1342 * Load microcode on this cpu if a valid microcode is available.
1343 * This is early microcode loading procedure.
1347 t = &per_cpu(cpu_tss, cpu);
1348 oist = &per_cpu(orig_ist, cpu);
1351 if (this_cpu_read(numa_node) == 0 &&
1352 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1353 set_numa_node(early_cpu_to_node(cpu));
1358 pr_debug("Initializing CPU#%d\n", cpu);
1360 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1363 * Initialize the per-CPU GDT with the boot GDT,
1364 * and set up the GDT descriptor:
1367 switch_to_new_gdt(cpu);
1372 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1375 wrmsrl(MSR_FS_BASE, 0);
1376 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1383 * set up and load the per-CPU TSS
1385 if (!oist->ist[0]) {
1386 char *estacks = per_cpu(exception_stacks, cpu);
1388 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1389 estacks += exception_stack_sizes[v];
1390 oist->ist[v] = t->x86_tss.ist[v] =
1391 (unsigned long)estacks;
1392 if (v == DEBUG_STACK-1)
1393 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1397 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1400 * <= is required because the CPU will access up to
1401 * 8 bits beyond the end of the IO permission bitmap.
1403 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1404 t->io_bitmap[i] = ~0UL;
1406 atomic_inc(&init_mm.mm_count);
1407 me->active_mm = &init_mm;
1409 enter_lazy_tlb(&init_mm, me);
1411 load_sp0(t, ¤t->thread);
1412 set_tss_desc(cpu, t);
1414 load_mm_ldt(&init_mm);
1416 clear_all_debug_regs();
1417 dbg_restore_debug_regs();
1429 int cpu = smp_processor_id();
1430 struct task_struct *curr = current;
1431 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1432 struct thread_struct *thread = &curr->thread;
1434 wait_for_master_cpu(cpu);
1437 * Initialize the CR4 shadow before doing anything that could
1442 show_ucode_info_early();
1444 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1446 if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de)
1447 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1450 switch_to_new_gdt(cpu);
1453 * Set up and load the per-CPU TSS and LDT
1455 atomic_inc(&init_mm.mm_count);
1456 curr->active_mm = &init_mm;
1458 enter_lazy_tlb(&init_mm, curr);
1460 load_sp0(t, thread);
1461 set_tss_desc(cpu, t);
1463 load_mm_ldt(&init_mm);
1465 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1467 #ifdef CONFIG_DOUBLEFAULT
1468 /* Set up doublefault TSS pointer in the GDT */
1469 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1472 clear_all_debug_regs();
1473 dbg_restore_debug_regs();
1479 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1480 void warn_pre_alternatives(void)
1482 WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1484 EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1487 inline bool __static_cpu_has_safe(u16 bit)
1489 return boot_cpu_has(bit);
1491 EXPORT_SYMBOL_GPL(__static_cpu_has_safe);
1493 static void bsp_resume(void)
1495 if (this_cpu->c_bsp_resume)
1496 this_cpu->c_bsp_resume(&boot_cpu_data);
1499 static struct syscore_ops cpu_syscore_ops = {
1500 .resume = bsp_resume,
1503 static int __init init_cpu_syscore(void)
1505 register_syscore_ops(&cpu_syscore_ops);
1508 core_initcall(init_cpu_syscore);