1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
25 #include <asm/cpumask.h>
26 #ifdef CONFIG_X86_LOCAL_APIC
27 #include <asm/mpspec.h>
29 #include <mach_apic.h>
30 #include <asm/genapic.h>
31 #include <asm/uv/uv.h>
34 #include <asm/pgtable.h>
35 #include <asm/processor.h>
37 #include <asm/atomic.h>
38 #include <asm/proto.h>
39 #include <asm/sections.h>
40 #include <asm/setup.h>
41 #include <asm/hypervisor.h>
47 /* all of these masks are initialized in setup_cpu_local_masks() */
48 cpumask_var_t cpu_callin_mask;
49 cpumask_var_t cpu_callout_mask;
50 cpumask_var_t cpu_initialized_mask;
52 /* representing cpus for which sibling maps can be computed */
53 cpumask_var_t cpu_sibling_setup_mask;
55 /* correctly size the local cpu masks */
56 void __init setup_cpu_local_masks(void)
58 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
59 alloc_bootmem_cpumask_var(&cpu_callin_mask);
60 alloc_bootmem_cpumask_var(&cpu_callout_mask);
61 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
64 #else /* CONFIG_X86_32 */
66 cpumask_t cpu_callin_map;
67 cpumask_t cpu_callout_map;
68 cpumask_t cpu_initialized;
69 cpumask_t cpu_sibling_setup_map;
71 #endif /* CONFIG_X86_32 */
74 static struct cpu_dev *this_cpu __cpuinitdata;
76 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
79 * We need valid kernel segments for data and code in long mode too
80 * IRET will check the segment types kkeil 2000/10/28
81 * Also sysret mandates a special GDT layout
83 * The TLS descriptors are currently at a different place compared to i386.
84 * Hopefully nobody expects them at a fixed place (Wine?)
86 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
87 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
88 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
89 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
90 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
91 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
93 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
94 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
95 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
96 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
98 * Segments used for calling PnP BIOS have byte granularity.
99 * They code segments and data segments have fixed 64k limits,
100 * the transfer segment sizes are set at run time.
103 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
105 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
107 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
109 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
111 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
113 * The APM segments have byte granularity and their bases
114 * are set at run time. All have 64k limits.
117 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
119 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
121 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
123 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
124 [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
127 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
130 static int cachesize_override __cpuinitdata = -1;
131 static int disable_x86_serial_nr __cpuinitdata = 1;
133 static int __init cachesize_setup(char *str)
135 get_option(&str, &cachesize_override);
138 __setup("cachesize=", cachesize_setup);
140 static int __init x86_fxsr_setup(char *s)
142 setup_clear_cpu_cap(X86_FEATURE_FXSR);
143 setup_clear_cpu_cap(X86_FEATURE_XMM);
146 __setup("nofxsr", x86_fxsr_setup);
148 static int __init x86_sep_setup(char *s)
150 setup_clear_cpu_cap(X86_FEATURE_SEP);
153 __setup("nosep", x86_sep_setup);
155 /* Standard macro to see if a specific flag is changeable */
156 static inline int flag_is_changeable_p(u32 flag)
161 * Cyrix and IDT cpus allow disabling of CPUID
162 * so the code below may return different results
163 * when it is executed before and after enabling
164 * the CPUID. Add "volatile" to not allow gcc to
165 * optimize the subsequent calls to this function.
167 asm volatile ("pushfl\n\t"
177 : "=&r" (f1), "=&r" (f2)
180 return ((f1^f2) & flag) != 0;
183 /* Probe for the CPUID instruction */
184 static int __cpuinit have_cpuid_p(void)
186 return flag_is_changeable_p(X86_EFLAGS_ID);
189 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
191 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
192 /* Disable processor serial number */
193 unsigned long lo, hi;
194 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
196 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
197 printk(KERN_NOTICE "CPU serial number disabled.\n");
198 clear_cpu_cap(c, X86_FEATURE_PN);
200 /* Disabling the serial number may affect the cpuid level */
201 c->cpuid_level = cpuid_eax(0);
205 static int __init x86_serial_nr_setup(char *s)
207 disable_x86_serial_nr = 0;
210 __setup("serialnumber", x86_serial_nr_setup);
212 static inline int flag_is_changeable_p(u32 flag)
216 /* Probe for the CPUID instruction */
217 static inline int have_cpuid_p(void)
221 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
227 * Naming convention should be: <Name> [(<Codename>)]
228 * This table only is used unless init_<vendor>() below doesn't set it;
229 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
233 /* Look up CPU names by table lookup. */
234 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
236 struct cpu_model_info *info;
238 if (c->x86_model >= 16)
239 return NULL; /* Range check */
244 info = this_cpu->c_models;
246 while (info && info->family) {
247 if (info->family == c->x86)
248 return info->model_names[c->x86_model];
251 return NULL; /* Not found */
254 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
256 void load_percpu_segment(int cpu)
259 loadsegment(fs, __KERNEL_PERCPU);
262 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
266 /* Current gdt points %fs at the "master" per-cpu area: after this,
267 * it's on the real one. */
268 void switch_to_new_gdt(int cpu)
270 struct desc_ptr gdt_descr;
272 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
273 gdt_descr.size = GDT_SIZE - 1;
274 load_gdt(&gdt_descr);
275 /* Reload the per-cpu base */
277 load_percpu_segment(cpu);
280 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
282 static void __cpuinit default_init(struct cpuinfo_x86 *c)
285 display_cacheinfo(c);
287 /* Not much we can do here... */
288 /* Check if at least it has cpuid */
289 if (c->cpuid_level == -1) {
290 /* No cpuid. It must be an ancient CPU */
292 strcpy(c->x86_model_id, "486");
293 else if (c->x86 == 3)
294 strcpy(c->x86_model_id, "386");
299 static struct cpu_dev __cpuinitdata default_cpu = {
300 .c_init = default_init,
301 .c_vendor = "Unknown",
302 .c_x86_vendor = X86_VENDOR_UNKNOWN,
305 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
310 if (c->extended_cpuid_level < 0x80000004)
313 v = (unsigned int *) c->x86_model_id;
314 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
315 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
316 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
317 c->x86_model_id[48] = 0;
319 /* Intel chips right-justify this string for some dumb reason;
320 undo that brain damage */
321 p = q = &c->x86_model_id[0];
327 while (q <= &c->x86_model_id[48])
328 *q++ = '\0'; /* Zero-pad the rest */
332 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
334 unsigned int n, dummy, ebx, ecx, edx, l2size;
336 n = c->extended_cpuid_level;
338 if (n >= 0x80000005) {
339 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
340 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
341 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
342 c->x86_cache_size = (ecx>>24) + (edx>>24);
344 /* On K8 L1 TLB is inclusive, so don't count it */
349 if (n < 0x80000006) /* Some chips just has a large L1. */
352 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
356 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
358 /* do processor-specific cache resizing */
359 if (this_cpu->c_size_cache)
360 l2size = this_cpu->c_size_cache(c, l2size);
362 /* Allow user to override all this if necessary. */
363 if (cachesize_override != -1)
364 l2size = cachesize_override;
367 return; /* Again, no L2 cache is possible */
370 c->x86_cache_size = l2size;
372 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
376 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
379 u32 eax, ebx, ecx, edx;
380 int index_msb, core_bits;
382 if (!cpu_has(c, X86_FEATURE_HT))
385 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
388 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
391 cpuid(1, &eax, &ebx, &ecx, &edx);
393 smp_num_siblings = (ebx & 0xff0000) >> 16;
395 if (smp_num_siblings == 1) {
396 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
397 } else if (smp_num_siblings > 1) {
399 if (smp_num_siblings > nr_cpu_ids) {
400 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
402 smp_num_siblings = 1;
406 index_msb = get_count_order(smp_num_siblings);
408 c->phys_proc_id = phys_pkg_id(index_msb);
410 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
413 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
415 index_msb = get_count_order(smp_num_siblings);
417 core_bits = get_count_order(c->x86_max_cores);
420 c->cpu_core_id = phys_pkg_id(index_msb) &
421 ((1 << core_bits) - 1);
423 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
424 ((1 << core_bits) - 1);
429 if ((c->x86_max_cores * smp_num_siblings) > 1) {
430 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
432 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
438 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
440 char *v = c->x86_vendor_id;
444 for (i = 0; i < X86_VENDOR_NUM; i++) {
448 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
449 (cpu_devs[i]->c_ident[1] &&
450 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
451 this_cpu = cpu_devs[i];
452 c->x86_vendor = this_cpu->c_x86_vendor;
459 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
460 printk(KERN_ERR "CPU: Your system may be unstable.\n");
463 c->x86_vendor = X86_VENDOR_UNKNOWN;
464 this_cpu = &default_cpu;
467 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
469 /* Get vendor name */
470 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
471 (unsigned int *)&c->x86_vendor_id[0],
472 (unsigned int *)&c->x86_vendor_id[8],
473 (unsigned int *)&c->x86_vendor_id[4]);
476 /* Intel-defined flags: level 0x00000001 */
477 if (c->cpuid_level >= 0x00000001) {
478 u32 junk, tfms, cap0, misc;
479 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
480 c->x86 = (tfms >> 8) & 0xf;
481 c->x86_model = (tfms >> 4) & 0xf;
482 c->x86_mask = tfms & 0xf;
484 c->x86 += (tfms >> 20) & 0xff;
486 c->x86_model += ((tfms >> 16) & 0xf) << 4;
487 if (cap0 & (1<<19)) {
488 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
489 c->x86_cache_alignment = c->x86_clflush_size;
494 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
499 /* Intel-defined flags: level 0x00000001 */
500 if (c->cpuid_level >= 0x00000001) {
501 u32 capability, excap;
502 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
503 c->x86_capability[0] = capability;
504 c->x86_capability[4] = excap;
507 /* AMD-defined flags: level 0x80000001 */
508 xlvl = cpuid_eax(0x80000000);
509 c->extended_cpuid_level = xlvl;
510 if ((xlvl & 0xffff0000) == 0x80000000) {
511 if (xlvl >= 0x80000001) {
512 c->x86_capability[1] = cpuid_edx(0x80000001);
513 c->x86_capability[6] = cpuid_ecx(0x80000001);
518 if (c->extended_cpuid_level >= 0x80000008) {
519 u32 eax = cpuid_eax(0x80000008);
521 c->x86_virt_bits = (eax >> 8) & 0xff;
522 c->x86_phys_bits = eax & 0xff;
526 if (c->extended_cpuid_level >= 0x80000007)
527 c->x86_power = cpuid_edx(0x80000007);
531 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
537 * First of all, decide if this is a 486 or higher
538 * It's a 486 if we can modify the AC flag
540 if (flag_is_changeable_p(X86_EFLAGS_AC))
545 for (i = 0; i < X86_VENDOR_NUM; i++)
546 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
547 c->x86_vendor_id[0] = 0;
548 cpu_devs[i]->c_identify(c);
549 if (c->x86_vendor_id[0]) {
558 * Do minimum CPU detection early.
559 * Fields really needed: vendor, cpuid_level, family, model, mask,
561 * The others are not touched to avoid unwanted side effects.
563 * WARNING: this function is only called on the BP. Don't add code here
564 * that is supposed to run on all CPUs.
566 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
569 c->x86_clflush_size = 64;
571 c->x86_clflush_size = 32;
573 c->x86_cache_alignment = c->x86_clflush_size;
575 memset(&c->x86_capability, 0, sizeof c->x86_capability);
576 c->extended_cpuid_level = 0;
579 identify_cpu_without_cpuid(c);
581 /* cyrix could have cpuid enabled via c_identify()*/
591 if (this_cpu->c_early_init)
592 this_cpu->c_early_init(c);
594 validate_pat_support(c);
597 c->cpu_index = boot_cpu_id;
601 void __init early_cpu_init(void)
603 struct cpu_dev **cdev;
606 printk("KERNEL supported cpus:\n");
607 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
608 struct cpu_dev *cpudev = *cdev;
611 if (count >= X86_VENDOR_NUM)
613 cpu_devs[count] = cpudev;
616 for (j = 0; j < 2; j++) {
617 if (!cpudev->c_ident[j])
619 printk(" %s %s\n", cpudev->c_vendor,
624 early_identify_cpu(&boot_cpu_data);
628 * The NOPL instruction is supposed to exist on all CPUs with
629 * family >= 6; unfortunately, that's not true in practice because
630 * of early VIA chips and (more importantly) broken virtualizers that
631 * are not easy to detect. In the latter case it doesn't even *fail*
632 * reliably, so probing for it doesn't even work. Disable it completely
633 * unless we can find a reliable way to detect all the broken cases.
635 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
637 clear_cpu_cap(c, X86_FEATURE_NOPL);
640 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
642 c->extended_cpuid_level = 0;
645 identify_cpu_without_cpuid(c);
647 /* cyrix could have cpuid enabled via c_identify()*/
657 if (c->cpuid_level >= 0x00000001) {
658 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
660 # ifdef CONFIG_X86_HT
661 c->apicid = phys_pkg_id(c->initial_apicid, 0);
663 c->apicid = c->initial_apicid;
668 c->phys_proc_id = c->initial_apicid;
672 get_model_name(c); /* Default name */
674 init_scattered_cpuid_features(c);
679 * This does the hard work of actually picking apart the CPU stuff...
681 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
685 c->loops_per_jiffy = loops_per_jiffy;
686 c->x86_cache_size = -1;
687 c->x86_vendor = X86_VENDOR_UNKNOWN;
688 c->x86_model = c->x86_mask = 0; /* So far unknown... */
689 c->x86_vendor_id[0] = '\0'; /* Unset */
690 c->x86_model_id[0] = '\0'; /* Unset */
691 c->x86_max_cores = 1;
692 c->x86_coreid_bits = 0;
694 c->x86_clflush_size = 64;
696 c->cpuid_level = -1; /* CPUID not detected */
697 c->x86_clflush_size = 32;
699 c->x86_cache_alignment = c->x86_clflush_size;
700 memset(&c->x86_capability, 0, sizeof c->x86_capability);
704 if (this_cpu->c_identify)
705 this_cpu->c_identify(c);
708 c->apicid = phys_pkg_id(0);
712 * Vendor-specific initialization. In this section we
713 * canonicalize the feature flags, meaning if there are
714 * features a certain CPU supports which CPUID doesn't
715 * tell us, CPUID claiming incorrect flags, or other bugs,
716 * we handle them here.
718 * At the end of this section, c->x86_capability better
719 * indicate the features this CPU genuinely supports!
721 if (this_cpu->c_init)
724 /* Disable the PN if appropriate */
725 squash_the_stupid_serial_number(c);
728 * The vendor-specific functions might have changed features. Now
729 * we do "generic changes."
732 /* If the model name is still unset, do table lookup. */
733 if (!c->x86_model_id[0]) {
735 p = table_lookup_model(c);
737 strcpy(c->x86_model_id, p);
740 sprintf(c->x86_model_id, "%02x/%02x",
741 c->x86, c->x86_model);
750 * On SMP, boot_cpu_data holds the common feature set between
751 * all CPUs; so make sure that we indicate which features are
752 * common between the CPUs. The first time this routine gets
753 * executed, c == &boot_cpu_data.
755 if (c != &boot_cpu_data) {
756 /* AND the already accumulated flags with these */
757 for (i = 0; i < NCAPINTS; i++)
758 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
761 /* Clear all flags overriden by options */
762 for (i = 0; i < NCAPINTS; i++)
763 c->x86_capability[i] &= ~cleared_cpu_caps[i];
765 #ifdef CONFIG_X86_MCE
766 /* Init Machine Check Exception if available. */
770 select_idle_routine(c);
772 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
773 numa_add_cpu(smp_processor_id());
778 static void vgetcpu_set_mode(void)
780 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
781 vgetcpu_mode = VGETCPU_RDTSCP;
783 vgetcpu_mode = VGETCPU_LSL;
787 void __init identify_boot_cpu(void)
789 identify_cpu(&boot_cpu_data);
798 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
800 BUG_ON(c == &boot_cpu_data);
813 static struct msr_range msr_range_array[] __cpuinitdata = {
814 { 0x00000000, 0x00000418},
815 { 0xc0000000, 0xc000040b},
816 { 0xc0010000, 0xc0010142},
817 { 0xc0011000, 0xc001103b},
820 static void __cpuinit print_cpu_msr(void)
825 unsigned index_min, index_max;
827 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
828 index_min = msr_range_array[i].min;
829 index_max = msr_range_array[i].max;
830 for (index = index_min; index < index_max; index++) {
831 if (rdmsrl_amd_safe(index, &val))
833 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
838 static int show_msr __cpuinitdata;
839 static __init int setup_show_msr(char *arg)
843 get_option(&arg, &num);
849 __setup("show_msr=", setup_show_msr);
851 static __init int setup_noclflush(char *arg)
853 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
856 __setup("noclflush", setup_noclflush);
858 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
862 if (c->x86_vendor < X86_VENDOR_NUM)
863 vendor = this_cpu->c_vendor;
864 else if (c->cpuid_level >= 0)
865 vendor = c->x86_vendor_id;
867 if (vendor && !strstr(c->x86_model_id, vendor))
868 printk(KERN_CONT "%s ", vendor);
870 if (c->x86_model_id[0])
871 printk(KERN_CONT "%s", c->x86_model_id);
873 printk(KERN_CONT "%d86", c->x86);
875 if (c->x86_mask || c->cpuid_level >= 0)
876 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
878 printk(KERN_CONT "\n");
881 if (c->cpu_index < show_msr)
889 static __init int setup_disablecpuid(char *arg)
892 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
893 setup_clear_cpu_cap(bit);
898 __setup("clearcpuid=", setup_disablecpuid);
901 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
903 DEFINE_PER_CPU_FIRST(union irq_stack_union,
904 irq_stack_union) __aligned(PAGE_SIZE);
905 DEFINE_PER_CPU(char *, irq_stack_ptr) =
906 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
908 DEFINE_PER_CPU(unsigned long, kernel_stack) =
909 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
910 EXPORT_PER_CPU_SYMBOL(kernel_stack);
912 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
914 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
915 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
916 __aligned(PAGE_SIZE);
918 extern asmlinkage void ignore_sysret(void);
920 /* May not be marked __init: used by software suspend */
921 void syscall_init(void)
924 * LSTAR and STAR live in a bit strange symbiosis.
925 * They both write to the same internal register. STAR allows to
926 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
928 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
929 wrmsrl(MSR_LSTAR, system_call);
930 wrmsrl(MSR_CSTAR, ignore_sysret);
932 #ifdef CONFIG_IA32_EMULATION
933 syscall32_cpu_init();
936 /* Flags to clear on syscall */
937 wrmsrl(MSR_SYSCALL_MASK,
938 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
941 unsigned long kernel_eflags;
944 * Copies of the original ist values from the tss are only accessed during
945 * debugging, no special alignment required.
947 DEFINE_PER_CPU(struct orig_ist, orig_ist);
951 /* Make sure %fs is initialized properly in idle threads */
952 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
954 memset(regs, 0, sizeof(struct pt_regs));
955 regs->fs = __KERNEL_PERCPU;
961 * cpu_init() initializes state that is per-CPU. Some data is already
962 * initialized (naturally) in the bootstrap process, such as the GDT
963 * and IDT. We reload them nevertheless, this function acts as a
964 * 'CPU state barrier', nothing should get across.
965 * A lot of state is already set up in PDA init for 64 bit
968 void __cpuinit cpu_init(void)
970 int cpu = stack_smp_processor_id();
971 struct tss_struct *t = &per_cpu(init_tss, cpu);
972 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
974 struct task_struct *me;
978 if (cpu != 0 && percpu_read(node_number) == 0 &&
979 cpu_to_node(cpu) != NUMA_NO_NODE)
980 percpu_write(node_number, cpu_to_node(cpu));
985 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
986 panic("CPU#%d already initialized!\n", cpu);
988 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
990 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
993 * Initialize the per-CPU GDT with the boot GDT,
994 * and set up the GDT descriptor:
997 switch_to_new_gdt(cpu);
1000 load_idt((const struct desc_ptr *)&idt_descr);
1002 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1005 wrmsrl(MSR_FS_BASE, 0);
1006 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1010 if (cpu != 0 && x2apic)
1014 * set up and load the per-CPU TSS
1016 if (!orig_ist->ist[0]) {
1017 static const unsigned int sizes[N_EXCEPTION_STACKS] = {
1018 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1019 [DEBUG_STACK - 1] = DEBUG_STKSZ
1021 char *estacks = per_cpu(exception_stacks, cpu);
1022 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1023 estacks += sizes[v];
1024 orig_ist->ist[v] = t->x86_tss.ist[v] =
1025 (unsigned long)estacks;
1029 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1031 * <= is required because the CPU will access up to
1032 * 8 bits beyond the end of the IO permission bitmap.
1034 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1035 t->io_bitmap[i] = ~0UL;
1037 atomic_inc(&init_mm.mm_count);
1038 me->active_mm = &init_mm;
1041 enter_lazy_tlb(&init_mm, me);
1043 load_sp0(t, ¤t->thread);
1044 set_tss_desc(cpu, t);
1046 load_LDT(&init_mm.context);
1050 * If the kgdb is connected no debug regs should be altered. This
1051 * is only applicable when KGDB and a KGDB I/O module are built
1052 * into the kernel and you are using early debugging with
1053 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1055 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1056 arch_kgdb_ops.correct_hw_break();
1060 * Clear all 6 debug registers:
1063 set_debugreg(0UL, 0);
1064 set_debugreg(0UL, 1);
1065 set_debugreg(0UL, 2);
1066 set_debugreg(0UL, 3);
1067 set_debugreg(0UL, 6);
1068 set_debugreg(0UL, 7);
1070 /* If the kgdb is connected no debug regs should be altered. */
1076 raw_local_save_flags(kernel_eflags);
1084 void __cpuinit cpu_init(void)
1086 int cpu = smp_processor_id();
1087 struct task_struct *curr = current;
1088 struct tss_struct *t = &per_cpu(init_tss, cpu);
1089 struct thread_struct *thread = &curr->thread;
1091 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1092 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1093 for (;;) local_irq_enable();
1096 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1098 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1099 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1101 load_idt(&idt_descr);
1102 switch_to_new_gdt(cpu);
1105 * Set up and load the per-CPU TSS and LDT
1107 atomic_inc(&init_mm.mm_count);
1108 curr->active_mm = &init_mm;
1111 enter_lazy_tlb(&init_mm, curr);
1113 load_sp0(t, thread);
1114 set_tss_desc(cpu, t);
1116 load_LDT(&init_mm.context);
1118 #ifdef CONFIG_DOUBLEFAULT
1119 /* Set up doublefault TSS pointer in the GDT */
1120 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1124 asm volatile ("mov %0, %%gs" : : "r" (0));
1126 /* Clear all 6 debug registers: */
1135 * Force FPU initialization:
1138 current_thread_info()->status = TS_XSAVE;
1140 current_thread_info()->status = 0;
1142 mxcsr_feature_mask_init();
1145 * Boot processor to setup the FP and extended state context info.
1147 if (smp_processor_id() == boot_cpu_id)
1148 init_thread_xstate();