1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
24 #ifdef CONFIG_X86_LOCAL_APIC
25 #include <asm/mpspec.h>
27 #include <mach_apic.h>
28 #include <asm/genapic.h>
32 #include <asm/pgtable.h>
33 #include <asm/processor.h>
35 #include <asm/atomic.h>
36 #include <asm/proto.h>
37 #include <asm/sections.h>
38 #include <asm/setup.h>
39 #include <asm/hypervisor.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_callin_mask;
47 cpumask_var_t cpu_callout_mask;
48 cpumask_var_t cpu_initialized_mask;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask;
53 #else /* CONFIG_X86_32 */
55 cpumask_t cpu_callin_map;
56 cpumask_t cpu_callout_map;
57 cpumask_t cpu_initialized;
58 cpumask_t cpu_sibling_setup_map;
60 #endif /* CONFIG_X86_32 */
63 static struct cpu_dev *this_cpu __cpuinitdata;
66 /* We need valid kernel segments for data and code in long mode too
67 * IRET will check the segment types kkeil 2000/10/28
68 * Also sysret mandates a special GDT layout
70 /* The TLS descriptors are currently at a different place compared to i386.
71 Hopefully nobody expects them at a fixed place (Wine?) */
72 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
73 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
74 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
75 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
76 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
77 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
78 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
81 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
82 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
83 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
84 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
85 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
87 * Segments used for calling PnP BIOS have byte granularity.
88 * They code segments and data segments have fixed 64k limits,
89 * the transfer segment sizes are set at run time.
92 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
94 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
96 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
98 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
100 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
102 * The APM segments have byte granularity and their bases
103 * are set at run time. All have 64k limits.
106 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
108 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
110 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
112 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
113 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
116 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
119 static int cachesize_override __cpuinitdata = -1;
120 static int disable_x86_serial_nr __cpuinitdata = 1;
122 static int __init cachesize_setup(char *str)
124 get_option(&str, &cachesize_override);
127 __setup("cachesize=", cachesize_setup);
129 static int __init x86_fxsr_setup(char *s)
131 setup_clear_cpu_cap(X86_FEATURE_FXSR);
132 setup_clear_cpu_cap(X86_FEATURE_XMM);
135 __setup("nofxsr", x86_fxsr_setup);
137 static int __init x86_sep_setup(char *s)
139 setup_clear_cpu_cap(X86_FEATURE_SEP);
142 __setup("nosep", x86_sep_setup);
144 /* Standard macro to see if a specific flag is changeable */
145 static inline int flag_is_changeable_p(u32 flag)
150 * Cyrix and IDT cpus allow disabling of CPUID
151 * so the code below may return different results
152 * when it is executed before and after enabling
153 * the CPUID. Add "volatile" to not allow gcc to
154 * optimize the subsequent calls to this function.
156 asm volatile ("pushfl\n\t"
166 : "=&r" (f1), "=&r" (f2)
169 return ((f1^f2) & flag) != 0;
172 /* Probe for the CPUID instruction */
173 static int __cpuinit have_cpuid_p(void)
175 return flag_is_changeable_p(X86_EFLAGS_ID);
178 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
180 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
181 /* Disable processor serial number */
182 unsigned long lo, hi;
183 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
185 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
186 printk(KERN_NOTICE "CPU serial number disabled.\n");
187 clear_cpu_cap(c, X86_FEATURE_PN);
189 /* Disabling the serial number may affect the cpuid level */
190 c->cpuid_level = cpuid_eax(0);
194 static int __init x86_serial_nr_setup(char *s)
196 disable_x86_serial_nr = 0;
199 __setup("serialnumber", x86_serial_nr_setup);
201 static inline int flag_is_changeable_p(u32 flag)
205 /* Probe for the CPUID instruction */
206 static inline int have_cpuid_p(void)
210 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
216 * Some CPU features depend on higher CPUID levels, which may not always
217 * be available due to CPUID level capping or broken virtualization
218 * software. Add those features to this table to auto-disable them.
220 struct cpuid_dependent_feature {
224 static const struct cpuid_dependent_feature __cpuinitconst
225 cpuid_dependent_features[] = {
226 { X86_FEATURE_MWAIT, 0x00000005 },
227 { X86_FEATURE_DCA, 0x00000009 },
228 { X86_FEATURE_XSAVE, 0x0000000d },
232 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
234 const struct cpuid_dependent_feature *df;
235 for (df = cpuid_dependent_features; df->feature; df++) {
237 * Note: cpuid_level is set to -1 if unavailable, but
238 * extended_extended_level is set to 0 if unavailable
239 * and the legitimate extended levels are all negative
240 * when signed; hence the weird messing around with
243 if (cpu_has(c, df->feature) &&
244 ((s32)df->level < 0 ?
245 (u32)df->level > (u32)c->extended_cpuid_level :
246 (s32)df->level > (s32)c->cpuid_level)) {
247 clear_cpu_cap(c, df->feature);
250 "CPU: CPU feature %s disabled "
251 "due to lack of CPUID level 0x%x\n",
252 x86_cap_flags[df->feature],
259 * Naming convention should be: <Name> [(<Codename>)]
260 * This table only is used unless init_<vendor>() below doesn't set it;
261 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
265 /* Look up CPU names by table lookup. */
266 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
268 struct cpu_model_info *info;
270 if (c->x86_model >= 16)
271 return NULL; /* Range check */
276 info = this_cpu->c_models;
278 while (info && info->family) {
279 if (info->family == c->x86)
280 return info->model_names[c->x86_model];
283 return NULL; /* Not found */
286 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
288 /* Current gdt points %fs at the "master" per-cpu area: after this,
289 * it's on the real one. */
290 void switch_to_new_gdt(void)
292 struct desc_ptr gdt_descr;
294 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
295 gdt_descr.size = GDT_SIZE - 1;
296 load_gdt(&gdt_descr);
298 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
302 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
304 static void __cpuinit default_init(struct cpuinfo_x86 *c)
307 display_cacheinfo(c);
309 /* Not much we can do here... */
310 /* Check if at least it has cpuid */
311 if (c->cpuid_level == -1) {
312 /* No cpuid. It must be an ancient CPU */
314 strcpy(c->x86_model_id, "486");
315 else if (c->x86 == 3)
316 strcpy(c->x86_model_id, "386");
321 static struct cpu_dev __cpuinitdata default_cpu = {
322 .c_init = default_init,
323 .c_vendor = "Unknown",
324 .c_x86_vendor = X86_VENDOR_UNKNOWN,
327 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
332 if (c->extended_cpuid_level < 0x80000004)
335 v = (unsigned int *) c->x86_model_id;
336 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
337 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
338 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
339 c->x86_model_id[48] = 0;
341 /* Intel chips right-justify this string for some dumb reason;
342 undo that brain damage */
343 p = q = &c->x86_model_id[0];
349 while (q <= &c->x86_model_id[48])
350 *q++ = '\0'; /* Zero-pad the rest */
354 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
356 unsigned int n, dummy, ebx, ecx, edx, l2size;
358 n = c->extended_cpuid_level;
360 if (n >= 0x80000005) {
361 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
362 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
363 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
364 c->x86_cache_size = (ecx>>24) + (edx>>24);
366 /* On K8 L1 TLB is inclusive, so don't count it */
371 if (n < 0x80000006) /* Some chips just has a large L1. */
374 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
378 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
380 /* do processor-specific cache resizing */
381 if (this_cpu->c_size_cache)
382 l2size = this_cpu->c_size_cache(c, l2size);
384 /* Allow user to override all this if necessary. */
385 if (cachesize_override != -1)
386 l2size = cachesize_override;
389 return; /* Again, no L2 cache is possible */
392 c->x86_cache_size = l2size;
394 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
398 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
401 u32 eax, ebx, ecx, edx;
402 int index_msb, core_bits;
404 if (!cpu_has(c, X86_FEATURE_HT))
407 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
410 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
413 cpuid(1, &eax, &ebx, &ecx, &edx);
415 smp_num_siblings = (ebx & 0xff0000) >> 16;
417 if (smp_num_siblings == 1) {
418 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
419 } else if (smp_num_siblings > 1) {
421 if (smp_num_siblings > nr_cpu_ids) {
422 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
424 smp_num_siblings = 1;
428 index_msb = get_count_order(smp_num_siblings);
430 c->phys_proc_id = phys_pkg_id(index_msb);
432 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
435 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
437 index_msb = get_count_order(smp_num_siblings);
439 core_bits = get_count_order(c->x86_max_cores);
442 c->cpu_core_id = phys_pkg_id(index_msb) &
443 ((1 << core_bits) - 1);
445 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
446 ((1 << core_bits) - 1);
451 if ((c->x86_max_cores * smp_num_siblings) > 1) {
452 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
454 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
460 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
462 char *v = c->x86_vendor_id;
466 for (i = 0; i < X86_VENDOR_NUM; i++) {
470 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
471 (cpu_devs[i]->c_ident[1] &&
472 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
473 this_cpu = cpu_devs[i];
474 c->x86_vendor = this_cpu->c_x86_vendor;
481 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
482 printk(KERN_ERR "CPU: Your system may be unstable.\n");
485 c->x86_vendor = X86_VENDOR_UNKNOWN;
486 this_cpu = &default_cpu;
489 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
491 /* Get vendor name */
492 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
493 (unsigned int *)&c->x86_vendor_id[0],
494 (unsigned int *)&c->x86_vendor_id[8],
495 (unsigned int *)&c->x86_vendor_id[4]);
498 /* Intel-defined flags: level 0x00000001 */
499 if (c->cpuid_level >= 0x00000001) {
500 u32 junk, tfms, cap0, misc;
501 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
502 c->x86 = (tfms >> 8) & 0xf;
503 c->x86_model = (tfms >> 4) & 0xf;
504 c->x86_mask = tfms & 0xf;
506 c->x86 += (tfms >> 20) & 0xff;
508 c->x86_model += ((tfms >> 16) & 0xf) << 4;
509 if (cap0 & (1<<19)) {
510 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
511 c->x86_cache_alignment = c->x86_clflush_size;
516 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
521 /* Intel-defined flags: level 0x00000001 */
522 if (c->cpuid_level >= 0x00000001) {
523 u32 capability, excap;
524 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
525 c->x86_capability[0] = capability;
526 c->x86_capability[4] = excap;
529 /* AMD-defined flags: level 0x80000001 */
530 xlvl = cpuid_eax(0x80000000);
531 c->extended_cpuid_level = xlvl;
532 if ((xlvl & 0xffff0000) == 0x80000000) {
533 if (xlvl >= 0x80000001) {
534 c->x86_capability[1] = cpuid_edx(0x80000001);
535 c->x86_capability[6] = cpuid_ecx(0x80000001);
540 if (c->extended_cpuid_level >= 0x80000008) {
541 u32 eax = cpuid_eax(0x80000008);
543 c->x86_virt_bits = (eax >> 8) & 0xff;
544 c->x86_phys_bits = eax & 0xff;
548 if (c->extended_cpuid_level >= 0x80000007)
549 c->x86_power = cpuid_edx(0x80000007);
553 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
559 * First of all, decide if this is a 486 or higher
560 * It's a 486 if we can modify the AC flag
562 if (flag_is_changeable_p(X86_EFLAGS_AC))
567 for (i = 0; i < X86_VENDOR_NUM; i++)
568 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
569 c->x86_vendor_id[0] = 0;
570 cpu_devs[i]->c_identify(c);
571 if (c->x86_vendor_id[0]) {
580 * Do minimum CPU detection early.
581 * Fields really needed: vendor, cpuid_level, family, model, mask,
583 * The others are not touched to avoid unwanted side effects.
585 * WARNING: this function is only called on the BP. Don't add code here
586 * that is supposed to run on all CPUs.
588 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
591 c->x86_clflush_size = 64;
593 c->x86_clflush_size = 32;
595 c->x86_cache_alignment = c->x86_clflush_size;
597 memset(&c->x86_capability, 0, sizeof c->x86_capability);
598 c->extended_cpuid_level = 0;
601 identify_cpu_without_cpuid(c);
603 /* cyrix could have cpuid enabled via c_identify()*/
613 if (this_cpu->c_early_init)
614 this_cpu->c_early_init(c);
617 c->cpu_index = boot_cpu_id;
619 filter_cpuid_features(c, false);
622 void __init early_cpu_init(void)
624 struct cpu_dev **cdev;
627 printk("KERNEL supported cpus:\n");
628 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
629 struct cpu_dev *cpudev = *cdev;
632 if (count >= X86_VENDOR_NUM)
634 cpu_devs[count] = cpudev;
637 for (j = 0; j < 2; j++) {
638 if (!cpudev->c_ident[j])
640 printk(" %s %s\n", cpudev->c_vendor,
645 early_identify_cpu(&boot_cpu_data);
649 * The NOPL instruction is supposed to exist on all CPUs with
650 * family >= 6; unfortunately, that's not true in practice because
651 * of early VIA chips and (more importantly) broken virtualizers that
652 * are not easy to detect. In the latter case it doesn't even *fail*
653 * reliably, so probing for it doesn't even work. Disable it completely
654 * unless we can find a reliable way to detect all the broken cases.
656 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
658 clear_cpu_cap(c, X86_FEATURE_NOPL);
661 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
663 c->extended_cpuid_level = 0;
666 identify_cpu_without_cpuid(c);
668 /* cyrix could have cpuid enabled via c_identify()*/
678 if (c->cpuid_level >= 0x00000001) {
679 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
681 # ifdef CONFIG_X86_HT
682 c->apicid = phys_pkg_id(c->initial_apicid, 0);
684 c->apicid = c->initial_apicid;
689 c->phys_proc_id = c->initial_apicid;
693 get_model_name(c); /* Default name */
695 init_scattered_cpuid_features(c);
700 * This does the hard work of actually picking apart the CPU stuff...
702 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
706 c->loops_per_jiffy = loops_per_jiffy;
707 c->x86_cache_size = -1;
708 c->x86_vendor = X86_VENDOR_UNKNOWN;
709 c->x86_model = c->x86_mask = 0; /* So far unknown... */
710 c->x86_vendor_id[0] = '\0'; /* Unset */
711 c->x86_model_id[0] = '\0'; /* Unset */
712 c->x86_max_cores = 1;
713 c->x86_coreid_bits = 0;
715 c->x86_clflush_size = 64;
717 c->cpuid_level = -1; /* CPUID not detected */
718 c->x86_clflush_size = 32;
720 c->x86_cache_alignment = c->x86_clflush_size;
721 memset(&c->x86_capability, 0, sizeof c->x86_capability);
725 if (this_cpu->c_identify)
726 this_cpu->c_identify(c);
729 c->apicid = phys_pkg_id(0);
733 * Vendor-specific initialization. In this section we
734 * canonicalize the feature flags, meaning if there are
735 * features a certain CPU supports which CPUID doesn't
736 * tell us, CPUID claiming incorrect flags, or other bugs,
737 * we handle them here.
739 * At the end of this section, c->x86_capability better
740 * indicate the features this CPU genuinely supports!
742 if (this_cpu->c_init)
745 /* Disable the PN if appropriate */
746 squash_the_stupid_serial_number(c);
749 * The vendor-specific functions might have changed features. Now
750 * we do "generic changes."
753 /* Filter out anything that depends on CPUID levels we don't have */
754 filter_cpuid_features(c, true);
756 /* If the model name is still unset, do table lookup. */
757 if (!c->x86_model_id[0]) {
759 p = table_lookup_model(c);
761 strcpy(c->x86_model_id, p);
764 sprintf(c->x86_model_id, "%02x/%02x",
765 c->x86, c->x86_model);
774 * On SMP, boot_cpu_data holds the common feature set between
775 * all CPUs; so make sure that we indicate which features are
776 * common between the CPUs. The first time this routine gets
777 * executed, c == &boot_cpu_data.
779 if (c != &boot_cpu_data) {
780 /* AND the already accumulated flags with these */
781 for (i = 0; i < NCAPINTS; i++)
782 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
785 /* Clear all flags overriden by options */
786 for (i = 0; i < NCAPINTS; i++)
787 c->x86_capability[i] &= ~cleared_cpu_caps[i];
789 #ifdef CONFIG_X86_MCE
790 /* Init Machine Check Exception if available. */
794 select_idle_routine(c);
796 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
797 numa_add_cpu(smp_processor_id());
802 static void vgetcpu_set_mode(void)
804 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
805 vgetcpu_mode = VGETCPU_RDTSCP;
807 vgetcpu_mode = VGETCPU_LSL;
811 void __init identify_boot_cpu(void)
813 identify_cpu(&boot_cpu_data);
822 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
824 BUG_ON(c == &boot_cpu_data);
837 static struct msr_range msr_range_array[] __cpuinitdata = {
838 { 0x00000000, 0x00000418},
839 { 0xc0000000, 0xc000040b},
840 { 0xc0010000, 0xc0010142},
841 { 0xc0011000, 0xc001103b},
844 static void __cpuinit print_cpu_msr(void)
849 unsigned index_min, index_max;
851 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
852 index_min = msr_range_array[i].min;
853 index_max = msr_range_array[i].max;
854 for (index = index_min; index < index_max; index++) {
855 if (rdmsrl_amd_safe(index, &val))
857 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
862 static int show_msr __cpuinitdata;
863 static __init int setup_show_msr(char *arg)
867 get_option(&arg, &num);
873 __setup("show_msr=", setup_show_msr);
875 static __init int setup_noclflush(char *arg)
877 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
880 __setup("noclflush", setup_noclflush);
882 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
886 if (c->x86_vendor < X86_VENDOR_NUM)
887 vendor = this_cpu->c_vendor;
888 else if (c->cpuid_level >= 0)
889 vendor = c->x86_vendor_id;
891 if (vendor && !strstr(c->x86_model_id, vendor))
892 printk(KERN_CONT "%s ", vendor);
894 if (c->x86_model_id[0])
895 printk(KERN_CONT "%s", c->x86_model_id);
897 printk(KERN_CONT "%d86", c->x86);
899 if (c->x86_mask || c->cpuid_level >= 0)
900 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
902 printk(KERN_CONT "\n");
905 if (c->cpu_index < show_msr)
913 static __init int setup_disablecpuid(char *arg)
916 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
917 setup_clear_cpu_cap(bit);
922 __setup("clearcpuid=", setup_disablecpuid);
925 struct x8664_pda **_cpu_pda __read_mostly;
926 EXPORT_SYMBOL(_cpu_pda);
928 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
930 static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
932 void __cpuinit pda_init(int cpu)
934 struct x8664_pda *pda = cpu_pda(cpu);
936 /* Setup up data that may be needed in __get_free_pages early */
939 /* Memory clobbers used to order PDA accessed */
941 wrmsrl(MSR_GS_BASE, pda);
944 pda->cpunumber = cpu;
946 pda->kernelstack = (unsigned long)stack_thread_info() -
947 PDA_STACKOFFSET + THREAD_SIZE;
948 pda->active_mm = &init_mm;
952 /* others are initialized in smpboot.c */
953 pda->pcurrent = &init_task;
954 pda->irqstackptr = boot_cpu_stack;
955 pda->irqstackptr += IRQSTACKSIZE - 64;
957 if (!pda->irqstackptr) {
958 pda->irqstackptr = (char *)
959 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
960 if (!pda->irqstackptr)
961 panic("cannot allocate irqstack for cpu %d",
963 pda->irqstackptr += IRQSTACKSIZE - 64;
966 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
967 pda->nodenumber = cpu_to_node(cpu);
971 static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
972 DEBUG_STKSZ] __page_aligned_bss;
974 extern asmlinkage void ignore_sysret(void);
976 /* May not be marked __init: used by software suspend */
977 void syscall_init(void)
980 * LSTAR and STAR live in a bit strange symbiosis.
981 * They both write to the same internal register. STAR allows to
982 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
984 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
985 wrmsrl(MSR_LSTAR, system_call);
986 wrmsrl(MSR_CSTAR, ignore_sysret);
988 #ifdef CONFIG_IA32_EMULATION
989 syscall32_cpu_init();
992 /* Flags to clear on syscall */
993 wrmsrl(MSR_SYSCALL_MASK,
994 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
997 unsigned long kernel_eflags;
1000 * Copies of the original ist values from the tss are only accessed during
1001 * debugging, no special alignment required.
1003 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1007 /* Make sure %fs is initialized properly in idle threads */
1008 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1010 memset(regs, 0, sizeof(struct pt_regs));
1011 regs->fs = __KERNEL_PERCPU;
1017 * cpu_init() initializes state that is per-CPU. Some data is already
1018 * initialized (naturally) in the bootstrap process, such as the GDT
1019 * and IDT. We reload them nevertheless, this function acts as a
1020 * 'CPU state barrier', nothing should get across.
1021 * A lot of state is already set up in PDA init for 64 bit
1023 #ifdef CONFIG_X86_64
1024 void __cpuinit cpu_init(void)
1026 int cpu = stack_smp_processor_id();
1027 struct tss_struct *t = &per_cpu(init_tss, cpu);
1028 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
1030 char *estacks = NULL;
1031 struct task_struct *me;
1034 /* CPU 0 is initialised in head64.c */
1038 estacks = boot_exception_stacks;
1042 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1043 panic("CPU#%d already initialized!\n", cpu);
1045 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1047 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1050 * Initialize the per-CPU GDT with the boot GDT,
1051 * and set up the GDT descriptor:
1054 switch_to_new_gdt();
1055 load_idt((const struct desc_ptr *)&idt_descr);
1057 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1060 wrmsrl(MSR_FS_BASE, 0);
1061 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1065 if (cpu != 0 && x2apic)
1069 * set up and load the per-CPU TSS
1071 if (!orig_ist->ist[0]) {
1072 static const unsigned int order[N_EXCEPTION_STACKS] = {
1073 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
1074 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
1076 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1078 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
1080 panic("Cannot allocate exception "
1081 "stack %ld %d\n", v, cpu);
1083 estacks += PAGE_SIZE << order[v];
1084 orig_ist->ist[v] = t->x86_tss.ist[v] =
1085 (unsigned long)estacks;
1089 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1091 * <= is required because the CPU will access up to
1092 * 8 bits beyond the end of the IO permission bitmap.
1094 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1095 t->io_bitmap[i] = ~0UL;
1097 atomic_inc(&init_mm.mm_count);
1098 me->active_mm = &init_mm;
1101 enter_lazy_tlb(&init_mm, me);
1103 load_sp0(t, ¤t->thread);
1104 set_tss_desc(cpu, t);
1106 load_LDT(&init_mm.context);
1110 * If the kgdb is connected no debug regs should be altered. This
1111 * is only applicable when KGDB and a KGDB I/O module are built
1112 * into the kernel and you are using early debugging with
1113 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1115 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1116 arch_kgdb_ops.correct_hw_break();
1120 * Clear all 6 debug registers:
1123 set_debugreg(0UL, 0);
1124 set_debugreg(0UL, 1);
1125 set_debugreg(0UL, 2);
1126 set_debugreg(0UL, 3);
1127 set_debugreg(0UL, 6);
1128 set_debugreg(0UL, 7);
1130 /* If the kgdb is connected no debug regs should be altered. */
1136 raw_local_save_flags(kernel_eflags);
1144 void __cpuinit cpu_init(void)
1146 int cpu = smp_processor_id();
1147 struct task_struct *curr = current;
1148 struct tss_struct *t = &per_cpu(init_tss, cpu);
1149 struct thread_struct *thread = &curr->thread;
1151 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1152 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1153 for (;;) local_irq_enable();
1156 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1158 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1159 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1161 load_idt(&idt_descr);
1162 switch_to_new_gdt();
1165 * Set up and load the per-CPU TSS and LDT
1167 atomic_inc(&init_mm.mm_count);
1168 curr->active_mm = &init_mm;
1171 enter_lazy_tlb(&init_mm, curr);
1173 load_sp0(t, thread);
1174 set_tss_desc(cpu, t);
1176 load_LDT(&init_mm.context);
1178 #ifdef CONFIG_DOUBLEFAULT
1179 /* Set up doublefault TSS pointer in the GDT */
1180 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1184 asm volatile ("mov %0, %%gs" : : "r" (0));
1186 /* Clear all 6 debug registers: */
1195 * Force FPU initialization:
1198 current_thread_info()->status = TS_XSAVE;
1200 current_thread_info()->status = 0;
1202 mxcsr_feature_mask_init();
1205 * Boot processor to setup the FP and extended state context info.
1207 if (smp_processor_id() == boot_cpu_id)
1208 init_thread_xstate();