2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
41 #include <asm/processor.h>
42 #include <asm/hw_irq.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
97 static DEFINE_PER_CPU(struct mce, mces_seen);
98 static int cpu_missing;
101 * CPU/chipset specific EDAC code can register a notifier call here to print
102 * MCE errors in a human-readable form.
104 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
105 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
107 static int default_decode_mce(struct notifier_block *nb, unsigned long val,
110 pr_emerg(HW_ERR "No human readable MCE decoding support on this CPU type.\n");
111 pr_emerg(HW_ERR "Run the message through 'mcelog --ascii' to decode.\n");
116 static struct notifier_block mce_dec_nb = {
117 .notifier_call = default_decode_mce,
121 /* MCA banks polled by the period polling timer for corrected events */
122 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
123 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
126 static DEFINE_PER_CPU(struct work_struct, mce_work);
128 /* Do initial initialization of a struct mce */
129 void mce_setup(struct mce *m)
131 memset(m, 0, sizeof(struct mce));
132 m->cpu = m->extcpu = smp_processor_id();
134 /* We hope get_seconds stays lockless */
135 m->time = get_seconds();
136 m->cpuvendor = boot_cpu_data.x86_vendor;
137 m->cpuid = cpuid_eax(1);
139 m->socketid = cpu_data(m->extcpu).phys_proc_id;
141 m->apicid = cpu_data(m->extcpu).initial_apicid;
142 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
145 DEFINE_PER_CPU(struct mce, injectm);
146 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
149 * Lockless MCE logging infrastructure.
150 * This avoids deadlocks on printk locks without having to break locks. Also
151 * separate MCEs from kernel messages to avoid bogus bug reports.
154 static struct mce_log mcelog = {
155 .signature = MCE_LOG_SIGNATURE,
157 .recordlen = sizeof(struct mce),
160 void mce_log(struct mce *mce)
162 unsigned next, entry;
164 /* Emit the trace record: */
165 trace_mce_record(mce);
170 entry = rcu_dereference_check_mce(mcelog.next);
173 * If edac_mce is enabled, it will check the error type
174 * and will process it, if it is a known error.
175 * Otherwise, the error will be sent through mcelog
178 if (edac_mce_parse(mce))
182 * When the buffer fills up discard new entries.
183 * Assume that the earlier errors are the more
186 if (entry >= MCE_LOG_LEN) {
187 set_bit(MCE_OVERFLOW,
188 (unsigned long *)&mcelog.flags);
191 /* Old left over entry. Skip: */
192 if (mcelog.entry[entry].finished) {
200 if (cmpxchg(&mcelog.next, entry, next) == entry)
203 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
205 mcelog.entry[entry].finished = 1;
209 set_bit(0, &mce_need_notify);
212 static void print_mce(struct mce *m)
214 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
215 m->extcpu, m->mcgstatus, m->bank, m->status);
218 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
219 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
222 if (m->cs == __KERNEL_CS)
223 print_symbol("{%s}", m->ip);
227 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
229 pr_cont("ADDR %llx ", m->addr);
231 pr_cont("MISC %llx ", m->misc);
234 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
235 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
238 * Print out human-readable details about the MCE error,
239 * (if the CPU has an implementation for that)
241 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
244 #define PANIC_TIMEOUT 5 /* 5 seconds */
246 static atomic_t mce_paniced;
248 static int fake_panic;
249 static atomic_t mce_fake_paniced;
251 /* Panic in progress. Enable interrupts and wait for final IPI */
252 static void wait_for_panic(void)
254 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
258 while (timeout-- > 0)
260 if (panic_timeout == 0)
261 panic_timeout = mce_panic_timeout;
262 panic("Panicing machine check CPU died");
265 static void mce_panic(char *msg, struct mce *final, char *exp)
271 * Make sure only one CPU runs in machine check panic
273 if (atomic_inc_return(&mce_paniced) > 1)
280 /* Don't log too much for fake panic */
281 if (atomic_inc_return(&mce_fake_paniced) > 1)
284 /* First print corrected ones that are still unlogged */
285 for (i = 0; i < MCE_LOG_LEN; i++) {
286 struct mce *m = &mcelog.entry[i];
287 if (!(m->status & MCI_STATUS_VAL))
289 if (!(m->status & MCI_STATUS_UC)) {
292 apei_err = apei_write_mce(m);
295 /* Now print uncorrected but with the final one last */
296 for (i = 0; i < MCE_LOG_LEN; i++) {
297 struct mce *m = &mcelog.entry[i];
298 if (!(m->status & MCI_STATUS_VAL))
300 if (!(m->status & MCI_STATUS_UC))
302 if (!final || memcmp(m, final, sizeof(struct mce))) {
305 apei_err = apei_write_mce(m);
311 apei_err = apei_write_mce(final);
314 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
316 pr_emerg(HW_ERR "Machine check: %s\n", exp);
318 if (panic_timeout == 0)
319 panic_timeout = mce_panic_timeout;
322 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
325 /* Support code for software error injection */
327 static int msr_to_offset(u32 msr)
329 unsigned bank = __this_cpu_read(injectm.bank);
332 return offsetof(struct mce, ip);
333 if (msr == MSR_IA32_MCx_STATUS(bank))
334 return offsetof(struct mce, status);
335 if (msr == MSR_IA32_MCx_ADDR(bank))
336 return offsetof(struct mce, addr);
337 if (msr == MSR_IA32_MCx_MISC(bank))
338 return offsetof(struct mce, misc);
339 if (msr == MSR_IA32_MCG_STATUS)
340 return offsetof(struct mce, mcgstatus);
344 /* MSR access wrappers used for error injection */
345 static u64 mce_rdmsrl(u32 msr)
349 if (__this_cpu_read(injectm.finished)) {
350 int offset = msr_to_offset(msr);
354 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
357 if (rdmsrl_safe(msr, &v)) {
358 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
360 * Return zero in case the access faulted. This should
361 * not happen normally but can happen if the CPU does
362 * something weird, or if the code is buggy.
370 static void mce_wrmsrl(u32 msr, u64 v)
372 if (__this_cpu_read(injectm.finished)) {
373 int offset = msr_to_offset(msr);
376 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
383 * Simple lockless ring to communicate PFNs from the exception handler with the
384 * process context work function. This is vastly simplified because there's
385 * only a single reader and a single writer.
387 #define MCE_RING_SIZE 16 /* we use one entry less */
390 unsigned short start;
392 unsigned long ring[MCE_RING_SIZE];
394 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
396 /* Runs with CPU affinity in workqueue */
397 static int mce_ring_empty(void)
399 struct mce_ring *r = &__get_cpu_var(mce_ring);
401 return r->start == r->end;
404 static int mce_ring_get(unsigned long *pfn)
411 r = &__get_cpu_var(mce_ring);
412 if (r->start == r->end)
414 *pfn = r->ring[r->start];
415 r->start = (r->start + 1) % MCE_RING_SIZE;
422 /* Always runs in MCE context with preempt off */
423 static int mce_ring_add(unsigned long pfn)
425 struct mce_ring *r = &__get_cpu_var(mce_ring);
428 next = (r->end + 1) % MCE_RING_SIZE;
429 if (next == r->start)
431 r->ring[r->end] = pfn;
437 int mce_available(struct cpuinfo_x86 *c)
441 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
444 static void mce_schedule_work(void)
446 if (!mce_ring_empty()) {
447 struct work_struct *work = &__get_cpu_var(mce_work);
448 if (!work_pending(work))
454 * Get the address of the instruction at the time of the machine check
457 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
460 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
468 m->ip = mce_rdmsrl(rip_msr);
471 #ifdef CONFIG_X86_LOCAL_APIC
473 * Called after interrupts have been reenabled again
474 * when a MCE happened during an interrupts off region
477 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
488 static void mce_report_event(struct pt_regs *regs)
490 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
493 * Triggering the work queue here is just an insurance
494 * policy in case the syscall exit notify handler
495 * doesn't run soon enough or ends up running on the
496 * wrong CPU (can happen when audit sleeps)
502 #ifdef CONFIG_X86_LOCAL_APIC
504 * Without APIC do not notify. The event will be picked
511 * When interrupts are disabled we cannot use
512 * kernel services safely. Trigger an self interrupt
513 * through the APIC to instead do the notification
514 * after interrupts are reenabled again.
516 apic->send_IPI_self(MCE_SELF_VECTOR);
519 * Wait for idle afterwards again so that we don't leave the
520 * APIC in a non idle state because the normal APIC writes
523 apic_wait_icr_idle();
527 DEFINE_PER_CPU(unsigned, mce_poll_count);
530 * Poll for corrected events or events that happened before reset.
531 * Those are just logged through /dev/mcelog.
533 * This is executed in standard interrupt context.
535 * Note: spec recommends to panic for fatal unsignalled
536 * errors here. However this would be quite problematic --
537 * we would need to reimplement the Monarch handling and
538 * it would mess up the exclusion between exception handler
539 * and poll hander -- * so we skip this for now.
540 * These cases should not happen anyways, or only when the CPU
541 * is already totally * confused. In this case it's likely it will
542 * not fully execute the machine check handler either.
544 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
549 percpu_inc(mce_poll_count);
553 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
554 for (i = 0; i < banks; i++) {
555 if (!mce_banks[i].ctl || !test_bit(i, *b))
564 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
565 if (!(m.status & MCI_STATUS_VAL))
569 * Uncorrected or signalled events are handled by the exception
570 * handler when it is enabled, so don't process those here.
572 * TBD do the same check for MCI_STATUS_EN here?
574 if (!(flags & MCP_UC) &&
575 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
578 if (m.status & MCI_STATUS_MISCV)
579 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
580 if (m.status & MCI_STATUS_ADDRV)
581 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
583 if (!(flags & MCP_TIMESTAMP))
586 * Don't get the IP here because it's unlikely to
587 * have anything to do with the actual error location.
589 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
591 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
592 add_taint(TAINT_MACHINE_CHECK);
596 * Clear state for this bank.
598 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
602 * Don't clear MCG_STATUS here because it's only defined for
608 EXPORT_SYMBOL_GPL(machine_check_poll);
611 * Do a quick check if any of the events requires a panic.
612 * This decides if we keep the events around or clear them.
614 static int mce_no_way_out(struct mce *m, char **msg)
618 for (i = 0; i < banks; i++) {
619 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
620 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
627 * Variable to establish order between CPUs while scanning.
628 * Each CPU spins initially until executing is equal its number.
630 static atomic_t mce_executing;
633 * Defines order of CPUs on entry. First CPU becomes Monarch.
635 static atomic_t mce_callin;
638 * Check if a timeout waiting for other CPUs happened.
640 static int mce_timed_out(u64 *t)
643 * The others already did panic for some reason.
644 * Bail out like in a timeout.
645 * rmb() to tell the compiler that system_state
646 * might have been modified by someone else.
649 if (atomic_read(&mce_paniced))
651 if (!monarch_timeout)
653 if ((s64)*t < SPINUNIT) {
654 /* CHECKME: Make panic default for 1 too? */
656 mce_panic("Timeout synchronizing machine check over CPUs",
663 touch_nmi_watchdog();
668 * The Monarch's reign. The Monarch is the CPU who entered
669 * the machine check handler first. It waits for the others to
670 * raise the exception too and then grades them. When any
671 * error is fatal panic. Only then let the others continue.
673 * The other CPUs entering the MCE handler will be controlled by the
674 * Monarch. They are called Subjects.
676 * This way we prevent any potential data corruption in a unrecoverable case
677 * and also makes sure always all CPU's errors are examined.
679 * Also this detects the case of a machine check event coming from outer
680 * space (not detected by any CPUs) In this case some external agent wants
681 * us to shut down, so panic too.
683 * The other CPUs might still decide to panic if the handler happens
684 * in a unrecoverable place, but in this case the system is in a semi-stable
685 * state and won't corrupt anything by itself. It's ok to let the others
686 * continue for a bit first.
688 * All the spin loops have timeouts; when a timeout happens a CPU
689 * typically elects itself to be Monarch.
691 static void mce_reign(void)
694 struct mce *m = NULL;
695 int global_worst = 0;
700 * This CPU is the Monarch and the other CPUs have run
701 * through their handlers.
702 * Grade the severity of the errors of all the CPUs.
704 for_each_possible_cpu(cpu) {
705 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
707 if (severity > global_worst) {
709 global_worst = severity;
710 m = &per_cpu(mces_seen, cpu);
715 * Cannot recover? Panic here then.
716 * This dumps all the mces in the log buffer and stops the
719 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
720 mce_panic("Fatal Machine check", m, msg);
723 * For UC somewhere we let the CPU who detects it handle it.
724 * Also must let continue the others, otherwise the handling
725 * CPU could deadlock on a lock.
729 * No machine check event found. Must be some external
730 * source or one CPU is hung. Panic.
732 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
733 mce_panic("Machine check from unknown source", NULL, NULL);
736 * Now clear all the mces_seen so that they don't reappear on
739 for_each_possible_cpu(cpu)
740 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
743 static atomic_t global_nwo;
746 * Start of Monarch synchronization. This waits until all CPUs have
747 * entered the exception handler and then determines if any of them
748 * saw a fatal event that requires panic. Then it executes them
749 * in the entry order.
750 * TBD double check parallel CPU hotunplug
752 static int mce_start(int *no_way_out)
755 int cpus = num_online_cpus();
756 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
761 atomic_add(*no_way_out, &global_nwo);
763 * global_nwo should be updated before mce_callin
766 order = atomic_inc_return(&mce_callin);
771 while (atomic_read(&mce_callin) != cpus) {
772 if (mce_timed_out(&timeout)) {
773 atomic_set(&global_nwo, 0);
780 * mce_callin should be read before global_nwo
786 * Monarch: Starts executing now, the others wait.
788 atomic_set(&mce_executing, 1);
791 * Subject: Now start the scanning loop one by one in
792 * the original callin order.
793 * This way when there are any shared banks it will be
794 * only seen by one CPU before cleared, avoiding duplicates.
796 while (atomic_read(&mce_executing) < order) {
797 if (mce_timed_out(&timeout)) {
798 atomic_set(&global_nwo, 0);
806 * Cache the global no_way_out state.
808 *no_way_out = atomic_read(&global_nwo);
814 * Synchronize between CPUs after main scanning loop.
815 * This invokes the bulk of the Monarch processing.
817 static int mce_end(int order)
820 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
828 * Allow others to run.
830 atomic_inc(&mce_executing);
833 /* CHECKME: Can this race with a parallel hotplug? */
834 int cpus = num_online_cpus();
837 * Monarch: Wait for everyone to go through their scanning
840 while (atomic_read(&mce_executing) <= cpus) {
841 if (mce_timed_out(&timeout))
851 * Subject: Wait for Monarch to finish.
853 while (atomic_read(&mce_executing) != 0) {
854 if (mce_timed_out(&timeout))
860 * Don't reset anything. That's done by the Monarch.
866 * Reset all global state.
869 atomic_set(&global_nwo, 0);
870 atomic_set(&mce_callin, 0);
874 * Let others run again.
876 atomic_set(&mce_executing, 0);
881 * Check if the address reported by the CPU is in a format we can parse.
882 * It would be possible to add code for most other cases, but all would
883 * be somewhat complicated (e.g. segment offset would require an instruction
884 * parser). So only support physical addresses upto page granuality for now.
886 static int mce_usable_address(struct mce *m)
888 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
890 if ((m->misc & 0x3f) > PAGE_SHIFT)
892 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
897 static void mce_clear_state(unsigned long *toclear)
901 for (i = 0; i < banks; i++) {
902 if (test_bit(i, toclear))
903 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
908 * The actual machine check handler. This only handles real
909 * exceptions when something got corrupted coming in through int 18.
911 * This is executed in NMI context not subject to normal locking rules. This
912 * implies that most kernel services cannot be safely used. Don't even
913 * think about putting a printk in there!
915 * On Intel systems this is entered on all CPUs in parallel through
916 * MCE broadcast. However some CPUs might be broken beyond repair,
917 * so be always careful when synchronizing with others.
919 void do_machine_check(struct pt_regs *regs, long error_code)
921 struct mce m, *final;
926 * Establish sequential order between the CPUs entering the machine
931 * If no_way_out gets set, there is no safe way to recover from this
932 * MCE. If tolerant is cranked up, we'll try anyway.
936 * If kill_it gets set, there might be a way to recover from this
940 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
941 char *msg = "Unknown";
943 atomic_inc(&mce_entry);
945 percpu_inc(mce_exception_count);
947 if (notify_die(DIE_NMI, "machine check", regs, error_code,
948 18, SIGKILL) == NOTIFY_STOP)
955 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
956 final = &__get_cpu_var(mces_seen);
959 no_way_out = mce_no_way_out(&m, &msg);
964 * When no restart IP must always kill or panic.
966 if (!(m.mcgstatus & MCG_STATUS_RIPV))
970 * Go through all the banks in exclusion of the other CPUs.
971 * This way we don't report duplicated events on shared banks
972 * because the first one to see it will clear it.
974 order = mce_start(&no_way_out);
975 for (i = 0; i < banks; i++) {
976 __clear_bit(i, toclear);
977 if (!mce_banks[i].ctl)
984 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
985 if ((m.status & MCI_STATUS_VAL) == 0)
989 * Non uncorrected or non signaled errors are handled by
990 * machine_check_poll. Leave them alone, unless this panics.
992 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
997 * Set taint even when machine check was not enabled.
999 add_taint(TAINT_MACHINE_CHECK);
1001 severity = mce_severity(&m, tolerant, NULL);
1004 * When machine check was for corrected handler don't touch,
1005 * unless we're panicing.
1007 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1009 __set_bit(i, toclear);
1010 if (severity == MCE_NO_SEVERITY) {
1012 * Machine check event was not enabled. Clear, but
1019 * Kill on action required.
1021 if (severity == MCE_AR_SEVERITY)
1024 if (m.status & MCI_STATUS_MISCV)
1025 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1026 if (m.status & MCI_STATUS_ADDRV)
1027 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1030 * Action optional error. Queue address for later processing.
1031 * When the ring overflows we just ignore the AO error.
1032 * RED-PEN add some logging mechanism when
1033 * usable_address or mce_add_ring fails.
1034 * RED-PEN don't ignore overflow for tolerant == 0
1036 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1037 mce_ring_add(m.addr >> PAGE_SHIFT);
1039 mce_get_rip(&m, regs);
1042 if (severity > worst) {
1049 mce_clear_state(toclear);
1052 * Do most of the synchronization with other CPUs.
1053 * When there's any problem use only local no_way_out state.
1055 if (mce_end(order) < 0)
1056 no_way_out = worst >= MCE_PANIC_SEVERITY;
1059 * If we have decided that we just CAN'T continue, and the user
1060 * has not set tolerant to an insane level, give up and die.
1062 * This is mainly used in the case when the system doesn't
1063 * support MCE broadcasting or it has been disabled.
1065 if (no_way_out && tolerant < 3)
1066 mce_panic("Fatal machine check on current CPU", final, msg);
1069 * If the error seems to be unrecoverable, something should be
1070 * done. Try to kill as little as possible. If we can kill just
1071 * one task, do that. If the user has set the tolerance very
1072 * high, don't try to do anything at all.
1075 if (kill_it && tolerant < 3)
1076 force_sig(SIGBUS, current);
1078 /* notify userspace ASAP */
1079 set_thread_flag(TIF_MCE_NOTIFY);
1082 mce_report_event(regs);
1083 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1085 atomic_dec(&mce_entry);
1088 EXPORT_SYMBOL_GPL(do_machine_check);
1090 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1091 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1093 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1097 * Called after mce notification in process context. This code
1098 * is allowed to sleep. Call the high level VM handler to process
1099 * any corrupted pages.
1100 * Assume that the work queue code only calls this one at a time
1102 * Note we don't disable preemption, so this code might run on the wrong
1103 * CPU. In this case the event is picked up by the scheduled work queue.
1104 * This is merely a fast path to expedite processing in some common
1107 void mce_notify_process(void)
1111 while (mce_ring_get(&pfn))
1112 memory_failure(pfn, MCE_VECTOR);
1115 static void mce_process_work(struct work_struct *dummy)
1117 mce_notify_process();
1120 #ifdef CONFIG_X86_MCE_INTEL
1122 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1123 * @cpu: The CPU on which the event occurred.
1124 * @status: Event status information
1126 * This function should be called by the thermal interrupt after the
1127 * event has been processed and the decision was made to log the event
1130 * The status parameter will be saved to the 'status' field of 'struct mce'
1131 * and historically has been the register value of the
1132 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1134 void mce_log_therm_throt_event(__u64 status)
1139 m.bank = MCE_THERMAL_BANK;
1143 #endif /* CONFIG_X86_MCE_INTEL */
1146 * Periodic polling timer for "silent" machine check errors. If the
1147 * poller finds an MCE, poll 2x faster. When the poller finds no more
1148 * errors, poll 2x slower (up to check_interval seconds).
1150 static int check_interval = 5 * 60; /* 5 minutes */
1152 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1153 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1155 static void mce_start_timer(unsigned long data)
1157 struct timer_list *t = &per_cpu(mce_timer, data);
1160 WARN_ON(smp_processor_id() != data);
1162 if (mce_available(¤t_cpu_data)) {
1163 machine_check_poll(MCP_TIMESTAMP,
1164 &__get_cpu_var(mce_poll_banks));
1168 * Alert userspace if needed. If we logged an MCE, reduce the
1169 * polling interval, otherwise increase the polling interval.
1171 n = &__get_cpu_var(mce_next_interval);
1172 if (mce_notify_irq())
1173 *n = max(*n/2, HZ/100);
1175 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1177 t->expires = jiffies + *n;
1178 add_timer_on(t, smp_processor_id());
1181 static void mce_do_trigger(struct work_struct *work)
1183 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1186 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1189 * Notify the user(s) about new machine check events.
1190 * Can be called from interrupt context, but not from machine check/NMI
1193 int mce_notify_irq(void)
1195 /* Not more than two messages every minute */
1196 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1198 clear_thread_flag(TIF_MCE_NOTIFY);
1200 if (test_and_clear_bit(0, &mce_need_notify)) {
1201 wake_up_interruptible(&mce_wait);
1204 * There is no risk of missing notifications because
1205 * work_pending is always cleared before the function is
1208 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1209 schedule_work(&mce_trigger_work);
1211 if (__ratelimit(&ratelimit))
1212 pr_info(HW_ERR "Machine check events logged\n");
1218 EXPORT_SYMBOL_GPL(mce_notify_irq);
1220 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1224 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1227 for (i = 0; i < banks; i++) {
1228 struct mce_bank *b = &mce_banks[i];
1237 * Initialize Machine Checks for a CPU.
1239 static int __cpuinit __mcheck_cpu_cap_init(void)
1244 rdmsrl(MSR_IA32_MCG_CAP, cap);
1246 b = cap & MCG_BANKCNT_MASK;
1248 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1250 if (b > MAX_NR_BANKS) {
1252 "MCE: Using only %u machine check banks out of %u\n",
1257 /* Don't support asymmetric configurations today */
1258 WARN_ON(banks != 0 && b != banks);
1261 int err = __mcheck_cpu_mce_banks_init();
1267 /* Use accurate RIP reporting if available. */
1268 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1269 rip_msr = MSR_IA32_MCG_EIP;
1271 if (cap & MCG_SER_P)
1277 static void __mcheck_cpu_init_generic(void)
1279 mce_banks_t all_banks;
1284 * Log the machine checks left over from the previous reset.
1286 bitmap_fill(all_banks, MAX_NR_BANKS);
1287 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1289 set_in_cr4(X86_CR4_MCE);
1291 rdmsrl(MSR_IA32_MCG_CAP, cap);
1292 if (cap & MCG_CTL_P)
1293 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1295 for (i = 0; i < banks; i++) {
1296 struct mce_bank *b = &mce_banks[i];
1300 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1301 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1305 /* Add per CPU specific workarounds here */
1306 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1308 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1309 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1313 /* This should be disabled by the BIOS, but isn't always */
1314 if (c->x86_vendor == X86_VENDOR_AMD) {
1315 if (c->x86 == 15 && banks > 4) {
1317 * disable GART TBL walk error reporting, which
1318 * trips off incorrectly with the IOMMU & 3ware
1321 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1323 if (c->x86 <= 17 && mce_bootlog < 0) {
1325 * Lots of broken BIOS around that don't clear them
1326 * by default and leave crap in there. Don't log:
1331 * Various K7s with broken bank 0 around. Always disable
1334 if (c->x86 == 6 && banks > 0)
1335 mce_banks[0].ctl = 0;
1338 if (c->x86_vendor == X86_VENDOR_INTEL) {
1340 * SDM documents that on family 6 bank 0 should not be written
1341 * because it aliases to another special BIOS controlled
1343 * But it's not aliased anymore on model 0x1a+
1344 * Don't ignore bank 0 completely because there could be a
1345 * valid event later, merely don't write CTL0.
1348 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1349 mce_banks[0].init = 0;
1352 * All newer Intel systems support MCE broadcasting. Enable
1353 * synchronization with a one second timeout.
1355 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1356 monarch_timeout < 0)
1357 monarch_timeout = USEC_PER_SEC;
1360 * There are also broken BIOSes on some Pentium M and
1363 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1366 if (monarch_timeout < 0)
1367 monarch_timeout = 0;
1368 if (mce_bootlog != 0)
1369 mce_panic_timeout = 30;
1374 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1378 switch (c->x86_vendor) {
1379 case X86_VENDOR_INTEL:
1380 intel_p5_mcheck_init(c);
1382 case X86_VENDOR_CENTAUR:
1383 winchip_mcheck_init(c);
1388 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1390 switch (c->x86_vendor) {
1391 case X86_VENDOR_INTEL:
1392 mce_intel_feature_init(c);
1394 case X86_VENDOR_AMD:
1395 mce_amd_feature_init(c);
1402 static void __mcheck_cpu_init_timer(void)
1404 struct timer_list *t = &__get_cpu_var(mce_timer);
1405 int *n = &__get_cpu_var(mce_next_interval);
1407 setup_timer(t, mce_start_timer, smp_processor_id());
1412 *n = check_interval * HZ;
1415 t->expires = round_jiffies(jiffies + *n);
1416 add_timer_on(t, smp_processor_id());
1419 /* Handle unconfigured int18 (should never happen) */
1420 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1422 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1423 smp_processor_id());
1426 /* Call the installed machine check handler for this CPU setup. */
1427 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1428 unexpected_machine_check;
1431 * Called for each booted CPU to set up machine checks.
1432 * Must be called with preempt off:
1434 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1439 __mcheck_cpu_ancient_init(c);
1441 if (!mce_available(c))
1444 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1449 machine_check_vector = do_machine_check;
1451 __mcheck_cpu_init_generic();
1452 __mcheck_cpu_init_vendor(c);
1453 __mcheck_cpu_init_timer();
1454 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1459 * Character device to read and clear the MCE log.
1462 static DEFINE_SPINLOCK(mce_state_lock);
1463 static int open_count; /* #times opened */
1464 static int open_exclu; /* already open exclusive? */
1466 static int mce_open(struct inode *inode, struct file *file)
1468 spin_lock(&mce_state_lock);
1470 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1471 spin_unlock(&mce_state_lock);
1476 if (file->f_flags & O_EXCL)
1480 spin_unlock(&mce_state_lock);
1482 return nonseekable_open(inode, file);
1485 static int mce_release(struct inode *inode, struct file *file)
1487 spin_lock(&mce_state_lock);
1492 spin_unlock(&mce_state_lock);
1497 static void collect_tscs(void *data)
1499 unsigned long *cpu_tsc = (unsigned long *)data;
1501 rdtscll(cpu_tsc[smp_processor_id()]);
1504 static int mce_apei_read_done;
1506 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1507 static int __mce_read_apei(char __user **ubuf, size_t usize)
1513 if (usize < sizeof(struct mce))
1516 rc = apei_read_mce(&m, &record_id);
1517 /* Error or no more MCE record */
1519 mce_apei_read_done = 1;
1523 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1526 * In fact, we should have cleared the record after that has
1527 * been flushed to the disk or sent to network in
1528 * /sbin/mcelog, but we have no interface to support that now,
1529 * so just clear it to avoid duplication.
1531 rc = apei_clear_mce(record_id);
1533 mce_apei_read_done = 1;
1536 *ubuf += sizeof(struct mce);
1541 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1544 char __user *buf = ubuf;
1545 unsigned long *cpu_tsc;
1546 unsigned prev, next;
1549 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1553 mutex_lock(&mce_read_mutex);
1555 if (!mce_apei_read_done) {
1556 err = __mce_read_apei(&buf, usize);
1557 if (err || buf != ubuf)
1561 next = rcu_dereference_check_mce(mcelog.next);
1563 /* Only supports full reads right now */
1565 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1571 for (i = prev; i < next; i++) {
1572 unsigned long start = jiffies;
1574 while (!mcelog.entry[i].finished) {
1575 if (time_after_eq(jiffies, start + 2)) {
1576 memset(mcelog.entry + i, 0,
1577 sizeof(struct mce));
1583 err |= copy_to_user(buf, mcelog.entry + i,
1584 sizeof(struct mce));
1585 buf += sizeof(struct mce);
1590 memset(mcelog.entry + prev, 0,
1591 (next - prev) * sizeof(struct mce));
1593 next = cmpxchg(&mcelog.next, prev, 0);
1594 } while (next != prev);
1596 synchronize_sched();
1599 * Collect entries that were still getting written before the
1602 on_each_cpu(collect_tscs, cpu_tsc, 1);
1604 for (i = next; i < MCE_LOG_LEN; i++) {
1605 if (mcelog.entry[i].finished &&
1606 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1607 err |= copy_to_user(buf, mcelog.entry+i,
1608 sizeof(struct mce));
1610 buf += sizeof(struct mce);
1611 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1619 mutex_unlock(&mce_read_mutex);
1622 return err ? err : buf - ubuf;
1625 static unsigned int mce_poll(struct file *file, poll_table *wait)
1627 poll_wait(file, &mce_wait, wait);
1628 if (rcu_dereference_check_mce(mcelog.next))
1629 return POLLIN | POLLRDNORM;
1630 if (!mce_apei_read_done && apei_check_mce())
1631 return POLLIN | POLLRDNORM;
1635 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1637 int __user *p = (int __user *)arg;
1639 if (!capable(CAP_SYS_ADMIN))
1643 case MCE_GET_RECORD_LEN:
1644 return put_user(sizeof(struct mce), p);
1645 case MCE_GET_LOG_LEN:
1646 return put_user(MCE_LOG_LEN, p);
1647 case MCE_GETCLEAR_FLAGS: {
1651 flags = mcelog.flags;
1652 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1654 return put_user(flags, p);
1661 /* Modified in mce-inject.c, so not static or const */
1662 struct file_operations mce_chrdev_ops = {
1664 .release = mce_release,
1667 .unlocked_ioctl = mce_ioctl,
1668 .llseek = no_llseek,
1670 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1672 static struct miscdevice mce_log_device = {
1679 * mce=off Disables machine check
1680 * mce=no_cmci Disables CMCI
1681 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1682 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1683 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1684 * monarchtimeout is how long to wait for other CPUs on machine
1685 * check, or 0 to not wait
1686 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1687 * mce=nobootlog Don't log MCEs from before booting.
1689 static int __init mcheck_enable(char *str)
1697 if (!strcmp(str, "off"))
1699 else if (!strcmp(str, "no_cmci"))
1700 mce_cmci_disabled = 1;
1701 else if (!strcmp(str, "dont_log_ce"))
1702 mce_dont_log_ce = 1;
1703 else if (!strcmp(str, "ignore_ce"))
1705 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1706 mce_bootlog = (str[0] == 'b');
1707 else if (isdigit(str[0])) {
1708 get_option(&str, &tolerant);
1711 get_option(&str, &monarch_timeout);
1714 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1720 __setup("mce", mcheck_enable);
1722 int __init mcheck_init(void)
1724 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1726 mcheck_intel_therm_init();
1736 * Disable machine checks on suspend and shutdown. We can't really handle
1739 static int mce_disable_error_reporting(void)
1743 for (i = 0; i < banks; i++) {
1744 struct mce_bank *b = &mce_banks[i];
1747 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1752 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1754 return mce_disable_error_reporting();
1757 static int mce_shutdown(struct sys_device *dev)
1759 return mce_disable_error_reporting();
1763 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1764 * Only one CPU is active at this time, the others get re-added later using
1767 static int mce_resume(struct sys_device *dev)
1769 __mcheck_cpu_init_generic();
1770 __mcheck_cpu_init_vendor(¤t_cpu_data);
1775 static void mce_cpu_restart(void *data)
1777 del_timer_sync(&__get_cpu_var(mce_timer));
1778 if (!mce_available(¤t_cpu_data))
1780 __mcheck_cpu_init_generic();
1781 __mcheck_cpu_init_timer();
1784 /* Reinit MCEs after user configuration changes */
1785 static void mce_restart(void)
1787 on_each_cpu(mce_cpu_restart, NULL, 1);
1790 /* Toggle features for corrected errors */
1791 static void mce_disable_ce(void *all)
1793 if (!mce_available(¤t_cpu_data))
1796 del_timer_sync(&__get_cpu_var(mce_timer));
1800 static void mce_enable_ce(void *all)
1802 if (!mce_available(¤t_cpu_data))
1807 __mcheck_cpu_init_timer();
1810 static struct sysdev_class mce_sysclass = {
1811 .suspend = mce_suspend,
1812 .shutdown = mce_shutdown,
1813 .resume = mce_resume,
1814 .name = "machinecheck",
1817 DEFINE_PER_CPU(struct sys_device, mce_dev);
1820 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1822 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1824 return container_of(attr, struct mce_bank, attr);
1827 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1830 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1833 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1834 const char *buf, size_t size)
1838 if (strict_strtoull(buf, 0, &new) < 0)
1841 attr_to_bank(attr)->ctl = new;
1848 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1850 strcpy(buf, mce_helper);
1852 return strlen(mce_helper) + 1;
1855 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1856 const char *buf, size_t siz)
1860 strncpy(mce_helper, buf, sizeof(mce_helper));
1861 mce_helper[sizeof(mce_helper)-1] = 0;
1862 p = strchr(mce_helper, '\n');
1867 return strlen(mce_helper) + !!p;
1870 static ssize_t set_ignore_ce(struct sys_device *s,
1871 struct sysdev_attribute *attr,
1872 const char *buf, size_t size)
1876 if (strict_strtoull(buf, 0, &new) < 0)
1879 if (mce_ignore_ce ^ !!new) {
1881 /* disable ce features */
1882 on_each_cpu(mce_disable_ce, (void *)1, 1);
1885 /* enable ce features */
1887 on_each_cpu(mce_enable_ce, (void *)1, 1);
1893 static ssize_t set_cmci_disabled(struct sys_device *s,
1894 struct sysdev_attribute *attr,
1895 const char *buf, size_t size)
1899 if (strict_strtoull(buf, 0, &new) < 0)
1902 if (mce_cmci_disabled ^ !!new) {
1905 on_each_cpu(mce_disable_ce, NULL, 1);
1906 mce_cmci_disabled = 1;
1909 mce_cmci_disabled = 0;
1910 on_each_cpu(mce_enable_ce, NULL, 1);
1916 static ssize_t store_int_with_restart(struct sys_device *s,
1917 struct sysdev_attribute *attr,
1918 const char *buf, size_t size)
1920 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1925 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1926 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1927 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1928 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1930 static struct sysdev_ext_attribute attr_check_interval = {
1931 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1932 store_int_with_restart),
1936 static struct sysdev_ext_attribute attr_ignore_ce = {
1937 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1941 static struct sysdev_ext_attribute attr_cmci_disabled = {
1942 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1946 static struct sysdev_attribute *mce_attrs[] = {
1947 &attr_tolerant.attr,
1948 &attr_check_interval.attr,
1950 &attr_monarch_timeout.attr,
1951 &attr_dont_log_ce.attr,
1952 &attr_ignore_ce.attr,
1953 &attr_cmci_disabled.attr,
1957 static cpumask_var_t mce_dev_initialized;
1959 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1960 static __cpuinit int mce_create_device(unsigned int cpu)
1965 if (!mce_available(&boot_cpu_data))
1968 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1969 per_cpu(mce_dev, cpu).id = cpu;
1970 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1972 err = sysdev_register(&per_cpu(mce_dev, cpu));
1976 for (i = 0; mce_attrs[i]; i++) {
1977 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1981 for (j = 0; j < banks; j++) {
1982 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1983 &mce_banks[j].attr);
1987 cpumask_set_cpu(cpu, mce_dev_initialized);
1992 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1995 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1997 sysdev_unregister(&per_cpu(mce_dev, cpu));
2002 static __cpuinit void mce_remove_device(unsigned int cpu)
2006 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2009 for (i = 0; mce_attrs[i]; i++)
2010 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2012 for (i = 0; i < banks; i++)
2013 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2015 sysdev_unregister(&per_cpu(mce_dev, cpu));
2016 cpumask_clear_cpu(cpu, mce_dev_initialized);
2019 /* Make sure there are no machine checks on offlined CPUs. */
2020 static void __cpuinit mce_disable_cpu(void *h)
2022 unsigned long action = *(unsigned long *)h;
2025 if (!mce_available(¤t_cpu_data))
2028 if (!(action & CPU_TASKS_FROZEN))
2030 for (i = 0; i < banks; i++) {
2031 struct mce_bank *b = &mce_banks[i];
2034 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2038 static void __cpuinit mce_reenable_cpu(void *h)
2040 unsigned long action = *(unsigned long *)h;
2043 if (!mce_available(¤t_cpu_data))
2046 if (!(action & CPU_TASKS_FROZEN))
2048 for (i = 0; i < banks; i++) {
2049 struct mce_bank *b = &mce_banks[i];
2052 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2056 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2057 static int __cpuinit
2058 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2060 unsigned int cpu = (unsigned long)hcpu;
2061 struct timer_list *t = &per_cpu(mce_timer, cpu);
2065 case CPU_ONLINE_FROZEN:
2066 mce_create_device(cpu);
2067 if (threshold_cpu_callback)
2068 threshold_cpu_callback(action, cpu);
2071 case CPU_DEAD_FROZEN:
2072 if (threshold_cpu_callback)
2073 threshold_cpu_callback(action, cpu);
2074 mce_remove_device(cpu);
2076 case CPU_DOWN_PREPARE:
2077 case CPU_DOWN_PREPARE_FROZEN:
2079 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2081 case CPU_DOWN_FAILED:
2082 case CPU_DOWN_FAILED_FROZEN:
2083 if (!mce_ignore_ce && check_interval) {
2084 t->expires = round_jiffies(jiffies +
2085 __get_cpu_var(mce_next_interval));
2086 add_timer_on(t, cpu);
2088 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2091 /* intentionally ignoring frozen here */
2092 cmci_rediscover(cpu);
2098 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2099 .notifier_call = mce_cpu_callback,
2102 static __init void mce_init_banks(void)
2106 for (i = 0; i < banks; i++) {
2107 struct mce_bank *b = &mce_banks[i];
2108 struct sysdev_attribute *a = &b->attr;
2110 sysfs_attr_init(&a->attr);
2111 a->attr.name = b->attrname;
2112 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2114 a->attr.mode = 0644;
2115 a->show = show_bank;
2116 a->store = set_bank;
2120 static __init int mcheck_init_device(void)
2125 if (!mce_available(&boot_cpu_data))
2128 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2132 err = sysdev_class_register(&mce_sysclass);
2136 for_each_online_cpu(i) {
2137 err = mce_create_device(i);
2142 register_hotcpu_notifier(&mce_cpu_notifier);
2143 misc_register(&mce_log_device);
2148 device_initcall(mcheck_init_device);
2151 * Old style boot options parsing. Only for compatibility.
2153 static int __init mcheck_disable(char *str)
2158 __setup("nomce", mcheck_disable);
2160 #ifdef CONFIG_DEBUG_FS
2161 struct dentry *mce_get_debugfs_dir(void)
2163 static struct dentry *dmce;
2166 dmce = debugfs_create_dir("mce", NULL);
2171 static void mce_reset(void)
2174 atomic_set(&mce_fake_paniced, 0);
2175 atomic_set(&mce_executing, 0);
2176 atomic_set(&mce_callin, 0);
2177 atomic_set(&global_nwo, 0);
2180 static int fake_panic_get(void *data, u64 *val)
2186 static int fake_panic_set(void *data, u64 val)
2193 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2194 fake_panic_set, "%llu\n");
2196 static int __init mcheck_debugfs_init(void)
2198 struct dentry *dmce, *ffake_panic;
2200 dmce = mce_get_debugfs_dir();
2203 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2210 late_initcall(mcheck_debugfs_init);