2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <asm/processor.h>
38 #include <asm/hw_irq.h>
45 #include "mce-internal.h"
48 /* Handle unconfigured int18 (should never happen) */
49 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
51 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
55 /* Call the installed machine check handler for this CPU setup. */
56 void (*machine_check_vector)(struct pt_regs *, long error_code) =
57 unexpected_machine_check;
61 #ifdef CONFIG_X86_NEW_MCE
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant = 1;
81 static unsigned long notify_user;
83 static int mce_bootlog = -1;
84 static int monarch_timeout = -1;
86 static char trigger[128];
87 static char *trigger_argv[2] = { trigger, NULL };
89 static unsigned long dont_init_banks;
91 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
92 static DEFINE_PER_CPU(struct mce, mces_seen);
93 static int cpu_missing;
96 /* MCA banks polled by the period polling timer for corrected events */
97 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
98 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
101 static inline int skip_bank_init(int i)
103 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
106 /* Do initial initialization of a struct mce */
107 void mce_setup(struct mce *m)
109 memset(m, 0, sizeof(struct mce));
110 m->cpu = m->extcpu = smp_processor_id();
112 /* We hope get_seconds stays lockless */
113 m->time = get_seconds();
114 m->cpuvendor = boot_cpu_data.x86_vendor;
115 m->cpuid = cpuid_eax(1);
117 m->socketid = cpu_data(m->extcpu).phys_proc_id;
119 m->apicid = cpu_data(m->extcpu).initial_apicid;
120 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
123 DEFINE_PER_CPU(struct mce, injectm);
124 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
127 * Lockless MCE logging infrastructure.
128 * This avoids deadlocks on printk locks without having to break locks. Also
129 * separate MCEs from kernel messages to avoid bogus bug reports.
132 static struct mce_log mcelog = {
133 .signature = MCE_LOG_SIGNATURE,
135 .recordlen = sizeof(struct mce),
138 void mce_log(struct mce *mce)
140 unsigned next, entry;
145 entry = rcu_dereference(mcelog.next);
148 * When the buffer fills up discard new entries.
149 * Assume that the earlier errors are the more
152 if (entry >= MCE_LOG_LEN) {
153 set_bit(MCE_OVERFLOW,
154 (unsigned long *)&mcelog.flags);
157 /* Old left over entry. Skip: */
158 if (mcelog.entry[entry].finished) {
166 if (cmpxchg(&mcelog.next, entry, next) == entry)
169 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
171 mcelog.entry[entry].finished = 1;
175 set_bit(0, ¬ify_user);
178 static void print_mce(struct mce *m)
180 printk(KERN_EMERG "\n"
181 KERN_EMERG "HARDWARE ERROR\n"
183 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
184 m->extcpu, m->mcgstatus, m->bank, m->status);
186 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
187 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
189 if (m->cs == __KERNEL_CS)
190 print_symbol("{%s}", m->ip);
193 printk(KERN_EMERG "TSC %llx ", m->tsc);
195 printk("ADDR %llx ", m->addr);
197 printk("MISC %llx ", m->misc);
199 printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
200 m->cpuvendor, m->cpuid, m->time, m->socketid,
202 printk(KERN_EMERG "This is not a software problem!\n");
203 printk(KERN_EMERG "Run through mcelog --ascii to decode "
204 "and contact your hardware vendor\n");
207 #define PANIC_TIMEOUT 5 /* 5 seconds */
209 static atomic_t mce_paniced;
211 /* Panic in progress. Enable interrupts and wait for final IPI */
212 static void wait_for_panic(void)
214 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
217 while (timeout-- > 0)
219 panic("Panicing machine check CPU died");
222 static void mce_panic(char *msg, struct mce *final, char *exp)
227 * Make sure only one CPU runs in machine check panic
229 if (atomic_add_return(1, &mce_paniced) > 1)
235 /* First print corrected ones that are still unlogged */
236 for (i = 0; i < MCE_LOG_LEN; i++) {
237 struct mce *m = &mcelog.entry[i];
238 if ((m->status & MCI_STATUS_VAL) &&
239 !(m->status & MCI_STATUS_UC))
242 /* Now print uncorrected but with the final one last */
243 for (i = 0; i < MCE_LOG_LEN; i++) {
244 struct mce *m = &mcelog.entry[i];
245 if (!(m->status & MCI_STATUS_VAL))
247 if (!final || memcmp(m, final, sizeof(struct mce)))
253 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
255 printk(KERN_EMERG "Machine check: %s\n", exp);
259 /* Support code for software error injection */
261 static int msr_to_offset(u32 msr)
263 unsigned bank = __get_cpu_var(injectm.bank);
265 return offsetof(struct mce, ip);
266 if (msr == MSR_IA32_MC0_STATUS + bank*4)
267 return offsetof(struct mce, status);
268 if (msr == MSR_IA32_MC0_ADDR + bank*4)
269 return offsetof(struct mce, addr);
270 if (msr == MSR_IA32_MC0_MISC + bank*4)
271 return offsetof(struct mce, misc);
272 if (msr == MSR_IA32_MCG_STATUS)
273 return offsetof(struct mce, mcgstatus);
277 /* MSR access wrappers used for error injection */
278 static u64 mce_rdmsrl(u32 msr)
281 if (__get_cpu_var(injectm).finished) {
282 int offset = msr_to_offset(msr);
285 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
291 static void mce_wrmsrl(u32 msr, u64 v)
293 if (__get_cpu_var(injectm).finished) {
294 int offset = msr_to_offset(msr);
296 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
302 int mce_available(struct cpuinfo_x86 *c)
306 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
310 * Get the address of the instruction at the time of the machine check
313 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
316 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
324 m->ip = mce_rdmsrl(rip_msr);
327 #ifdef CONFIG_X86_LOCAL_APIC
329 * Called after interrupts have been reenabled again
330 * when a MCE happened during an interrupts off region
333 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
343 static void mce_report_event(struct pt_regs *regs)
345 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
350 #ifdef CONFIG_X86_LOCAL_APIC
352 * Without APIC do not notify. The event will be picked
359 * When interrupts are disabled we cannot use
360 * kernel services safely. Trigger an self interrupt
361 * through the APIC to instead do the notification
362 * after interrupts are reenabled again.
364 apic->send_IPI_self(MCE_SELF_VECTOR);
367 * Wait for idle afterwards again so that we don't leave the
368 * APIC in a non idle state because the normal APIC writes
371 apic_wait_icr_idle();
375 DEFINE_PER_CPU(unsigned, mce_poll_count);
378 * Poll for corrected events or events that happened before reset.
379 * Those are just logged through /dev/mcelog.
381 * This is executed in standard interrupt context.
383 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
388 __get_cpu_var(mce_poll_count)++;
392 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
393 for (i = 0; i < banks; i++) {
394 if (!bank[i] || !test_bit(i, *b))
403 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
404 if (!(m.status & MCI_STATUS_VAL))
408 * Uncorrected events are handled by the exception handler
409 * when it is enabled. But when the exception is disabled log
412 * TBD do the same check for MCI_STATUS_EN here?
414 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
417 if (m.status & MCI_STATUS_MISCV)
418 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
419 if (m.status & MCI_STATUS_ADDRV)
420 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
422 if (!(flags & MCP_TIMESTAMP))
425 * Don't get the IP here because it's unlikely to
426 * have anything to do with the actual error location.
428 if (!(flags & MCP_DONTLOG)) {
430 add_taint(TAINT_MACHINE_CHECK);
434 * Clear state for this bank.
436 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
440 * Don't clear MCG_STATUS here because it's only defined for
446 EXPORT_SYMBOL_GPL(machine_check_poll);
449 * Do a quick check if any of the events requires a panic.
450 * This decides if we keep the events around or clear them.
452 static int mce_no_way_out(struct mce *m, char **msg)
456 for (i = 0; i < banks; i++) {
457 m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
458 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
465 * Variable to establish order between CPUs while scanning.
466 * Each CPU spins initially until executing is equal its number.
468 static atomic_t mce_executing;
471 * Defines order of CPUs on entry. First CPU becomes Monarch.
473 static atomic_t mce_callin;
476 * Check if a timeout waiting for other CPUs happened.
478 static int mce_timed_out(u64 *t)
481 * The others already did panic for some reason.
482 * Bail out like in a timeout.
483 * rmb() to tell the compiler that system_state
484 * might have been modified by someone else.
487 if (atomic_read(&mce_paniced))
489 if (!monarch_timeout)
491 if ((s64)*t < SPINUNIT) {
492 /* CHECKME: Make panic default for 1 too? */
494 mce_panic("Timeout synchronizing machine check over CPUs",
501 touch_nmi_watchdog();
506 * The Monarch's reign. The Monarch is the CPU who entered
507 * the machine check handler first. It waits for the others to
508 * raise the exception too and then grades them. When any
509 * error is fatal panic. Only then let the others continue.
511 * The other CPUs entering the MCE handler will be controlled by the
512 * Monarch. They are called Subjects.
514 * This way we prevent any potential data corruption in a unrecoverable case
515 * and also makes sure always all CPU's errors are examined.
517 * Also this detects the case of an machine check event coming from outer
518 * space (not detected by any CPUs) In this case some external agent wants
519 * us to shut down, so panic too.
521 * The other CPUs might still decide to panic if the handler happens
522 * in a unrecoverable place, but in this case the system is in a semi-stable
523 * state and won't corrupt anything by itself. It's ok to let the others
524 * continue for a bit first.
526 * All the spin loops have timeouts; when a timeout happens a CPU
527 * typically elects itself to be Monarch.
529 static void mce_reign(void)
532 struct mce *m = NULL;
533 int global_worst = 0;
538 * This CPU is the Monarch and the other CPUs have run
539 * through their handlers.
540 * Grade the severity of the errors of all the CPUs.
542 for_each_possible_cpu(cpu) {
543 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
545 if (severity > global_worst) {
547 global_worst = severity;
548 m = &per_cpu(mces_seen, cpu);
553 * Cannot recover? Panic here then.
554 * This dumps all the mces in the log buffer and stops the
557 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
558 mce_panic("Fatal Machine check", m, msg);
561 * For UC somewhere we let the CPU who detects it handle it.
562 * Also must let continue the others, otherwise the handling
563 * CPU could deadlock on a lock.
567 * No machine check event found. Must be some external
568 * source or one CPU is hung. Panic.
570 if (!m && tolerant < 3)
571 mce_panic("Machine check from unknown source", NULL, NULL);
574 * Now clear all the mces_seen so that they don't reappear on
577 for_each_possible_cpu(cpu)
578 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
581 static atomic_t global_nwo;
584 * Start of Monarch synchronization. This waits until all CPUs have
585 * entered the exception handler and then determines if any of them
586 * saw a fatal event that requires panic. Then it executes them
587 * in the entry order.
588 * TBD double check parallel CPU hotunplug
590 static int mce_start(int no_way_out, int *order)
593 int cpus = num_online_cpus();
594 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
601 atomic_add(no_way_out, &global_nwo);
606 while (atomic_read(&mce_callin) != cpus) {
607 if (mce_timed_out(&timeout)) {
608 atomic_set(&global_nwo, 0);
616 * Cache the global no_way_out state.
618 nwo = atomic_read(&global_nwo);
621 * Monarch starts executing now, the others wait.
624 atomic_set(&mce_executing, 1);
629 * Now start the scanning loop one by one
630 * in the original callin order.
631 * This way when there are any shared banks it will
632 * be only seen by one CPU before cleared, avoiding duplicates.
634 while (atomic_read(&mce_executing) < *order) {
635 if (mce_timed_out(&timeout)) {
636 atomic_set(&global_nwo, 0);
646 * Synchronize between CPUs after main scanning loop.
647 * This invokes the bulk of the Monarch processing.
649 static int mce_end(int order)
652 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
660 * Allow others to run.
662 atomic_inc(&mce_executing);
665 /* CHECKME: Can this race with a parallel hotplug? */
666 int cpus = num_online_cpus();
669 * Monarch: Wait for everyone to go through their scanning
672 while (atomic_read(&mce_executing) <= cpus) {
673 if (mce_timed_out(&timeout))
683 * Subject: Wait for Monarch to finish.
685 while (atomic_read(&mce_executing) != 0) {
686 if (mce_timed_out(&timeout))
692 * Don't reset anything. That's done by the Monarch.
698 * Reset all global state.
701 atomic_set(&global_nwo, 0);
702 atomic_set(&mce_callin, 0);
706 * Let others run again.
708 atomic_set(&mce_executing, 0);
712 static void mce_clear_state(unsigned long *toclear)
716 for (i = 0; i < banks; i++) {
717 if (test_bit(i, toclear))
718 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
723 * The actual machine check handler. This only handles real
724 * exceptions when something got corrupted coming in through int 18.
726 * This is executed in NMI context not subject to normal locking rules. This
727 * implies that most kernel services cannot be safely used. Don't even
728 * think about putting a printk in there!
730 * On Intel systems this is entered on all CPUs in parallel through
731 * MCE broadcast. However some CPUs might be broken beyond repair,
732 * so be always careful when synchronizing with others.
734 void do_machine_check(struct pt_regs *regs, long error_code)
736 struct mce m, *final;
741 * Establish sequential order between the CPUs entering the machine
747 * If no_way_out gets set, there is no safe way to recover from this
748 * MCE. If tolerant is cranked up, we'll try anyway.
752 * If kill_it gets set, there might be a way to recover from this
756 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
757 char *msg = "Unknown";
759 atomic_inc(&mce_entry);
761 __get_cpu_var(mce_exception_count)++;
763 if (notify_die(DIE_NMI, "machine check", regs, error_code,
764 18, SIGKILL) == NOTIFY_STOP)
769 order = atomic_add_return(1, &mce_callin);
772 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
773 no_way_out = mce_no_way_out(&m, &msg);
775 final = &__get_cpu_var(mces_seen);
781 * Go through all the banks in exclusion of the other CPUs.
782 * This way we don't report duplicated events on shared banks
783 * because the first one to see it will clear it.
785 no_way_out = mce_start(no_way_out, &order);
786 for (i = 0; i < banks; i++) {
787 __clear_bit(i, toclear);
795 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
796 if ((m.status & MCI_STATUS_VAL) == 0)
800 * Non uncorrected errors are handled by machine_check_poll
801 * Leave them alone, unless this panics.
803 if ((m.status & MCI_STATUS_UC) == 0 && !no_way_out)
807 * Set taint even when machine check was not enabled.
809 add_taint(TAINT_MACHINE_CHECK);
811 __set_bit(i, toclear);
813 if (m.status & MCI_STATUS_EN) {
815 * If this error was uncorrectable and there was
816 * an overflow, we're in trouble. If no overflow,
817 * we might get away with just killing a task.
819 if (m.status & MCI_STATUS_UC)
823 * Machine check event was not enabled. Clear, but
829 if (m.status & MCI_STATUS_MISCV)
830 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
831 if (m.status & MCI_STATUS_ADDRV)
832 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
834 mce_get_rip(&m, regs);
837 severity = mce_severity(&m, tolerant, NULL);
838 if (severity > worst) {
845 mce_clear_state(toclear);
848 * Do most of the synchronization with other CPUs.
849 * When there's any problem use only local no_way_out state.
851 if (mce_end(order) < 0)
852 no_way_out = worst >= MCE_PANIC_SEVERITY;
855 * If we have decided that we just CAN'T continue, and the user
856 * has not set tolerant to an insane level, give up and die.
858 * This is mainly used in the case when the system doesn't
859 * support MCE broadcasting or it has been disabled.
861 if (no_way_out && tolerant < 3)
862 mce_panic("Fatal machine check on current CPU", final, msg);
865 * If the error seems to be unrecoverable, something should be
866 * done. Try to kill as little as possible. If we can kill just
867 * one task, do that. If the user has set the tolerance very
868 * high, don't try to do anything at all.
870 if (kill_it && tolerant < 3) {
874 * If the EIPV bit is set, it means the saved IP is the
875 * instruction which caused the MCE.
877 if (m.mcgstatus & MCG_STATUS_EIPV)
878 user_space = final->ip && (final->cs & 3);
881 * If we know that the error was in user space, send a
882 * SIGBUS. Otherwise, panic if tolerance is low.
884 * force_sig() takes an awful lot of locks and has a slight
885 * risk of deadlocking.
888 force_sig(SIGBUS, current);
889 } else if (panic_on_oops || tolerant < 2) {
890 mce_panic("Uncorrected machine check", final, msg);
894 /* notify userspace ASAP */
895 set_thread_flag(TIF_MCE_NOTIFY);
898 mce_report_event(regs);
899 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
901 atomic_dec(&mce_entry);
904 EXPORT_SYMBOL_GPL(do_machine_check);
906 #ifdef CONFIG_X86_MCE_INTEL
908 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
909 * @cpu: The CPU on which the event occurred.
910 * @status: Event status information
912 * This function should be called by the thermal interrupt after the
913 * event has been processed and the decision was made to log the event
916 * The status parameter will be saved to the 'status' field of 'struct mce'
917 * and historically has been the register value of the
918 * MSR_IA32_THERMAL_STATUS (Intel) msr.
920 void mce_log_therm_throt_event(__u64 status)
925 m.bank = MCE_THERMAL_BANK;
929 #endif /* CONFIG_X86_MCE_INTEL */
932 * Periodic polling timer for "silent" machine check errors. If the
933 * poller finds an MCE, poll 2x faster. When the poller finds no more
934 * errors, poll 2x slower (up to check_interval seconds).
936 static int check_interval = 5 * 60; /* 5 minutes */
938 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
939 static DEFINE_PER_CPU(struct timer_list, mce_timer);
941 static void mcheck_timer(unsigned long data)
943 struct timer_list *t = &per_cpu(mce_timer, data);
946 WARN_ON(smp_processor_id() != data);
948 if (mce_available(¤t_cpu_data)) {
949 machine_check_poll(MCP_TIMESTAMP,
950 &__get_cpu_var(mce_poll_banks));
954 * Alert userspace if needed. If we logged an MCE, reduce the
955 * polling interval, otherwise increase the polling interval.
957 n = &__get_cpu_var(next_interval);
958 if (mce_notify_user())
959 *n = max(*n/2, HZ/100);
961 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
963 t->expires = jiffies + *n;
967 static void mce_do_trigger(struct work_struct *work)
969 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
972 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
975 * Notify the user(s) about new machine check events.
976 * Can be called from interrupt context, but not from machine check/NMI
979 int mce_notify_user(void)
981 /* Not more than two messages every minute */
982 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
984 clear_thread_flag(TIF_MCE_NOTIFY);
986 if (test_and_clear_bit(0, ¬ify_user)) {
987 wake_up_interruptible(&mce_wait);
990 * There is no risk of missing notifications because
991 * work_pending is always cleared before the function is
994 if (trigger[0] && !work_pending(&mce_trigger_work))
995 schedule_work(&mce_trigger_work);
997 if (__ratelimit(&ratelimit))
998 printk(KERN_INFO "Machine check events logged\n");
1004 EXPORT_SYMBOL_GPL(mce_notify_user);
1007 * Initialize Machine Checks for a CPU.
1009 static int mce_cap_init(void)
1014 rdmsrl(MSR_IA32_MCG_CAP, cap);
1016 b = cap & MCG_BANKCNT_MASK;
1017 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1019 if (b > MAX_NR_BANKS) {
1021 "MCE: Using only %u machine check banks out of %u\n",
1026 /* Don't support asymmetric configurations today */
1027 WARN_ON(banks != 0 && b != banks);
1030 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
1033 memset(bank, 0xff, banks * sizeof(u64));
1036 /* Use accurate RIP reporting if available. */
1037 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1038 rip_msr = MSR_IA32_MCG_EIP;
1043 static void mce_init(void)
1045 mce_banks_t all_banks;
1050 * Log the machine checks left over from the previous reset.
1052 bitmap_fill(all_banks, MAX_NR_BANKS);
1053 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1055 set_in_cr4(X86_CR4_MCE);
1057 rdmsrl(MSR_IA32_MCG_CAP, cap);
1058 if (cap & MCG_CTL_P)
1059 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1061 for (i = 0; i < banks; i++) {
1062 if (skip_bank_init(i))
1064 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
1065 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
1069 /* Add per CPU specific workarounds here */
1070 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
1072 /* This should be disabled by the BIOS, but isn't always */
1073 if (c->x86_vendor == X86_VENDOR_AMD) {
1074 if (c->x86 == 15 && banks > 4) {
1076 * disable GART TBL walk error reporting, which
1077 * trips off incorrectly with the IOMMU & 3ware
1080 clear_bit(10, (unsigned long *)&bank[4]);
1082 if (c->x86 <= 17 && mce_bootlog < 0) {
1084 * Lots of broken BIOS around that don't clear them
1085 * by default and leave crap in there. Don't log:
1090 * Various K7s with broken bank 0 around. Always disable
1097 if (c->x86_vendor == X86_VENDOR_INTEL) {
1099 * SDM documents that on family 6 bank 0 should not be written
1100 * because it aliases to another special BIOS controlled
1102 * But it's not aliased anymore on model 0x1a+
1103 * Don't ignore bank 0 completely because there could be a
1104 * valid event later, merely don't write CTL0.
1107 if (c->x86 == 6 && c->x86_model < 0x1A)
1108 __set_bit(0, &dont_init_banks);
1111 * All newer Intel systems support MCE broadcasting. Enable
1112 * synchronization with a one second timeout.
1114 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1115 monarch_timeout < 0)
1116 monarch_timeout = USEC_PER_SEC;
1118 if (monarch_timeout < 0)
1119 monarch_timeout = 0;
1122 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1126 switch (c->x86_vendor) {
1127 case X86_VENDOR_INTEL:
1128 if (mce_p5_enabled())
1129 intel_p5_mcheck_init(c);
1131 case X86_VENDOR_CENTAUR:
1132 winchip_mcheck_init(c);
1137 static void mce_cpu_features(struct cpuinfo_x86 *c)
1139 switch (c->x86_vendor) {
1140 case X86_VENDOR_INTEL:
1141 mce_intel_feature_init(c);
1143 case X86_VENDOR_AMD:
1144 mce_amd_feature_init(c);
1151 static void mce_init_timer(void)
1153 struct timer_list *t = &__get_cpu_var(mce_timer);
1154 int *n = &__get_cpu_var(next_interval);
1156 *n = check_interval * HZ;
1159 setup_timer(t, mcheck_timer, smp_processor_id());
1160 t->expires = round_jiffies(jiffies + *n);
1165 * Called for each booted CPU to set up machine checks.
1166 * Must be called with preempt off:
1168 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1173 mce_ancient_init(c);
1175 if (!mce_available(c))
1178 if (mce_cap_init() < 0) {
1184 machine_check_vector = do_machine_check;
1187 mce_cpu_features(c);
1192 * Character device to read and clear the MCE log.
1195 static DEFINE_SPINLOCK(mce_state_lock);
1196 static int open_count; /* #times opened */
1197 static int open_exclu; /* already open exclusive? */
1199 static int mce_open(struct inode *inode, struct file *file)
1201 spin_lock(&mce_state_lock);
1203 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1204 spin_unlock(&mce_state_lock);
1209 if (file->f_flags & O_EXCL)
1213 spin_unlock(&mce_state_lock);
1215 return nonseekable_open(inode, file);
1218 static int mce_release(struct inode *inode, struct file *file)
1220 spin_lock(&mce_state_lock);
1225 spin_unlock(&mce_state_lock);
1230 static void collect_tscs(void *data)
1232 unsigned long *cpu_tsc = (unsigned long *)data;
1234 rdtscll(cpu_tsc[smp_processor_id()]);
1237 static DEFINE_MUTEX(mce_read_mutex);
1239 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1242 char __user *buf = ubuf;
1243 unsigned long *cpu_tsc;
1244 unsigned prev, next;
1247 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1251 mutex_lock(&mce_read_mutex);
1252 next = rcu_dereference(mcelog.next);
1254 /* Only supports full reads right now */
1255 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1256 mutex_unlock(&mce_read_mutex);
1265 for (i = prev; i < next; i++) {
1266 unsigned long start = jiffies;
1268 while (!mcelog.entry[i].finished) {
1269 if (time_after_eq(jiffies, start + 2)) {
1270 memset(mcelog.entry + i, 0,
1271 sizeof(struct mce));
1277 err |= copy_to_user(buf, mcelog.entry + i,
1278 sizeof(struct mce));
1279 buf += sizeof(struct mce);
1284 memset(mcelog.entry + prev, 0,
1285 (next - prev) * sizeof(struct mce));
1287 next = cmpxchg(&mcelog.next, prev, 0);
1288 } while (next != prev);
1290 synchronize_sched();
1293 * Collect entries that were still getting written before the
1296 on_each_cpu(collect_tscs, cpu_tsc, 1);
1298 for (i = next; i < MCE_LOG_LEN; i++) {
1299 if (mcelog.entry[i].finished &&
1300 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1301 err |= copy_to_user(buf, mcelog.entry+i,
1302 sizeof(struct mce));
1304 buf += sizeof(struct mce);
1305 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1308 mutex_unlock(&mce_read_mutex);
1311 return err ? -EFAULT : buf - ubuf;
1314 static unsigned int mce_poll(struct file *file, poll_table *wait)
1316 poll_wait(file, &mce_wait, wait);
1317 if (rcu_dereference(mcelog.next))
1318 return POLLIN | POLLRDNORM;
1322 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1324 int __user *p = (int __user *)arg;
1326 if (!capable(CAP_SYS_ADMIN))
1330 case MCE_GET_RECORD_LEN:
1331 return put_user(sizeof(struct mce), p);
1332 case MCE_GET_LOG_LEN:
1333 return put_user(MCE_LOG_LEN, p);
1334 case MCE_GETCLEAR_FLAGS: {
1338 flags = mcelog.flags;
1339 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1341 return put_user(flags, p);
1348 /* Modified in mce-inject.c, so not static or const */
1349 struct file_operations mce_chrdev_ops = {
1351 .release = mce_release,
1354 .unlocked_ioctl = mce_ioctl,
1356 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1358 static struct miscdevice mce_log_device = {
1365 * mce=off disables machine check
1366 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1367 * monarchtimeout is how long to wait for other CPUs on machine
1368 * check, or 0 to not wait
1369 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1370 * mce=nobootlog Don't log MCEs from before booting.
1372 static int __init mcheck_enable(char *str)
1378 if (!strcmp(str, "off"))
1380 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1381 mce_bootlog = (str[0] == 'b');
1382 else if (isdigit(str[0])) {
1383 get_option(&str, &tolerant);
1386 get_option(&str, &monarch_timeout);
1389 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1395 __setup("mce", mcheck_enable);
1402 * Disable machine checks on suspend and shutdown. We can't really handle
1405 static int mce_disable(void)
1409 for (i = 0; i < banks; i++) {
1410 if (!skip_bank_init(i))
1411 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1416 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1418 return mce_disable();
1421 static int mce_shutdown(struct sys_device *dev)
1423 return mce_disable();
1427 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1428 * Only one CPU is active at this time, the others get re-added later using
1431 static int mce_resume(struct sys_device *dev)
1434 mce_cpu_features(¤t_cpu_data);
1439 static void mce_cpu_restart(void *data)
1441 del_timer_sync(&__get_cpu_var(mce_timer));
1442 if (mce_available(¤t_cpu_data))
1447 /* Reinit MCEs after user configuration changes */
1448 static void mce_restart(void)
1450 on_each_cpu(mce_cpu_restart, NULL, 1);
1453 static struct sysdev_class mce_sysclass = {
1454 .suspend = mce_suspend,
1455 .shutdown = mce_shutdown,
1456 .resume = mce_resume,
1457 .name = "machinecheck",
1460 DEFINE_PER_CPU(struct sys_device, mce_dev);
1463 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1465 static struct sysdev_attribute *bank_attrs;
1467 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1470 u64 b = bank[attr - bank_attrs];
1472 return sprintf(buf, "%llx\n", b);
1475 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1476 const char *buf, size_t size)
1480 if (strict_strtoull(buf, 0, &new) < 0)
1483 bank[attr - bank_attrs] = new;
1490 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1492 strcpy(buf, trigger);
1494 return strlen(trigger) + 1;
1497 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1498 const char *buf, size_t siz)
1503 strncpy(trigger, buf, sizeof(trigger));
1504 trigger[sizeof(trigger)-1] = 0;
1505 len = strlen(trigger);
1506 p = strchr(trigger, '\n');
1514 static ssize_t store_int_with_restart(struct sys_device *s,
1515 struct sysdev_attribute *attr,
1516 const char *buf, size_t size)
1518 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1523 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1524 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1525 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1527 static struct sysdev_ext_attribute attr_check_interval = {
1528 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1529 store_int_with_restart),
1533 static struct sysdev_attribute *mce_attrs[] = {
1534 &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger,
1535 &attr_monarch_timeout.attr,
1539 static cpumask_var_t mce_dev_initialized;
1541 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1542 static __cpuinit int mce_create_device(unsigned int cpu)
1547 if (!mce_available(&boot_cpu_data))
1550 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1551 per_cpu(mce_dev, cpu).id = cpu;
1552 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1554 err = sysdev_register(&per_cpu(mce_dev, cpu));
1558 for (i = 0; mce_attrs[i]; i++) {
1559 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1563 for (i = 0; i < banks; i++) {
1564 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1569 cpumask_set_cpu(cpu, mce_dev_initialized);
1574 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1577 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1579 sysdev_unregister(&per_cpu(mce_dev, cpu));
1584 static __cpuinit void mce_remove_device(unsigned int cpu)
1588 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1591 for (i = 0; mce_attrs[i]; i++)
1592 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1594 for (i = 0; i < banks; i++)
1595 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1597 sysdev_unregister(&per_cpu(mce_dev, cpu));
1598 cpumask_clear_cpu(cpu, mce_dev_initialized);
1601 /* Make sure there are no machine checks on offlined CPUs. */
1602 static void mce_disable_cpu(void *h)
1604 unsigned long action = *(unsigned long *)h;
1607 if (!mce_available(¤t_cpu_data))
1609 if (!(action & CPU_TASKS_FROZEN))
1611 for (i = 0; i < banks; i++) {
1612 if (!skip_bank_init(i))
1613 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1617 static void mce_reenable_cpu(void *h)
1619 unsigned long action = *(unsigned long *)h;
1622 if (!mce_available(¤t_cpu_data))
1625 if (!(action & CPU_TASKS_FROZEN))
1627 for (i = 0; i < banks; i++) {
1628 if (!skip_bank_init(i))
1629 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1633 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1634 static int __cpuinit
1635 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1637 unsigned int cpu = (unsigned long)hcpu;
1638 struct timer_list *t = &per_cpu(mce_timer, cpu);
1642 case CPU_ONLINE_FROZEN:
1643 mce_create_device(cpu);
1644 if (threshold_cpu_callback)
1645 threshold_cpu_callback(action, cpu);
1648 case CPU_DEAD_FROZEN:
1649 if (threshold_cpu_callback)
1650 threshold_cpu_callback(action, cpu);
1651 mce_remove_device(cpu);
1653 case CPU_DOWN_PREPARE:
1654 case CPU_DOWN_PREPARE_FROZEN:
1656 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1658 case CPU_DOWN_FAILED:
1659 case CPU_DOWN_FAILED_FROZEN:
1660 t->expires = round_jiffies(jiffies +
1661 __get_cpu_var(next_interval));
1662 add_timer_on(t, cpu);
1663 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1666 /* intentionally ignoring frozen here */
1667 cmci_rediscover(cpu);
1673 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1674 .notifier_call = mce_cpu_callback,
1677 static __init int mce_init_banks(void)
1681 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1686 for (i = 0; i < banks; i++) {
1687 struct sysdev_attribute *a = &bank_attrs[i];
1689 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1693 a->attr.mode = 0644;
1694 a->show = show_bank;
1695 a->store = set_bank;
1701 kfree(bank_attrs[i].attr.name);
1708 static __init int mce_init_device(void)
1713 if (!mce_available(&boot_cpu_data))
1716 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1718 err = mce_init_banks();
1722 err = sysdev_class_register(&mce_sysclass);
1726 for_each_online_cpu(i) {
1727 err = mce_create_device(i);
1732 register_hotcpu_notifier(&mce_cpu_notifier);
1733 misc_register(&mce_log_device);
1738 device_initcall(mce_init_device);
1740 #else /* CONFIG_X86_OLD_MCE: */
1743 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
1745 /* This has to be run for each processor */
1746 void mcheck_init(struct cpuinfo_x86 *c)
1748 if (mce_disabled == 1)
1751 switch (c->x86_vendor) {
1752 case X86_VENDOR_AMD:
1756 case X86_VENDOR_INTEL:
1758 intel_p5_mcheck_init(c);
1760 intel_p6_mcheck_init(c);
1762 intel_p4_mcheck_init(c);
1765 case X86_VENDOR_CENTAUR:
1767 winchip_mcheck_init(c);
1773 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
1776 static int __init mcheck_enable(char *str)
1782 __setup("mce", mcheck_enable);
1784 #endif /* CONFIG_X86_OLD_MCE */
1787 * Old style boot options parsing. Only for compatibility.
1789 static int __init mcheck_disable(char *str)
1794 __setup("nomce", mcheck_disable);