2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kobject.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
33 #include <asm/processor.h>
34 #include <asm/uaccess.h>
42 /* Handle unconfigured int18 (should never happen) */
43 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
45 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
49 /* Call the installed machine check handler for this CPU setup. */
50 void (*machine_check_vector)(struct pt_regs *, long error_code) =
51 unexpected_machine_check;
54 #define MISC_MCELOG_MINOR 227
58 static int mce_dont_init;
62 * 0: always panic on uncorrected errors, log corrected errors
63 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
64 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
65 * 3: never panic or SIGBUS, log all errors (for testing only)
67 static int tolerant = 1;
70 static unsigned long notify_user;
72 static int mce_bootlog = -1;
73 static atomic_t mce_events;
75 static char trigger[128];
76 static char *trigger_argv[2] = { trigger, NULL };
78 static unsigned long dont_init_banks;
80 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
82 /* MCA banks polled by the period polling timer for corrected events */
83 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
84 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
87 static inline int skip_bank_init(int i)
89 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
92 /* Do initial initialization of a struct mce */
93 void mce_setup(struct mce *m)
95 memset(m, 0, sizeof(struct mce));
96 m->cpu = smp_processor_id();
101 * Lockless MCE logging infrastructure.
102 * This avoids deadlocks on printk locks without having to break locks. Also
103 * separate MCEs from kernel messages to avoid bogus bug reports.
106 static struct mce_log mcelog = {
111 void mce_log(struct mce *mce)
113 unsigned next, entry;
115 atomic_inc(&mce_events);
119 entry = rcu_dereference(mcelog.next);
122 * When the buffer fills up discard new entries.
123 * Assume that the earlier errors are the more
126 if (entry >= MCE_LOG_LEN) {
127 set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags);
130 /* Old left over entry. Skip: */
131 if (mcelog.entry[entry].finished) {
139 if (cmpxchg(&mcelog.next, entry, next) == entry)
142 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
144 mcelog.entry[entry].finished = 1;
147 set_bit(0, ¬ify_user);
150 static void print_mce(struct mce *m)
152 printk(KERN_EMERG "\n"
153 KERN_EMERG "HARDWARE ERROR\n"
155 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
156 m->cpu, m->mcgstatus, m->bank, m->status);
158 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
159 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
161 if (m->cs == __KERNEL_CS)
162 print_symbol("{%s}", m->ip);
165 printk(KERN_EMERG "TSC %llx ", m->tsc);
167 printk("ADDR %llx ", m->addr);
169 printk("MISC %llx ", m->misc);
171 printk(KERN_EMERG "This is not a software problem!\n");
172 printk(KERN_EMERG "Run through mcelog --ascii to decode "
173 "and contact your hardware vendor\n");
176 static void mce_panic(char *msg, struct mce *backup, u64 start)
181 for (i = 0; i < MCE_LOG_LEN; i++) {
182 u64 tsc = mcelog.entry[i].tsc;
184 if ((s64)(tsc - start) < 0)
186 print_mce(&mcelog.entry[i]);
187 if (backup && mcelog.entry[i].tsc == backup->tsc)
195 int mce_available(struct cpuinfo_x86 *c)
199 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
202 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
204 if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
212 /* Assume the RIP in the MSR is exact. Is this true? */
213 m->mcgstatus |= MCG_STATUS_EIPV;
214 rdmsrl(rip_msr, m->ip);
220 * Poll for corrected events or events that happened before reset.
221 * Those are just logged through /dev/mcelog.
223 * This is executed in standard interrupt context.
225 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
232 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
233 for (i = 0; i < banks; i++) {
234 if (!bank[i] || !test_bit(i, *b))
243 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
244 if (!(m.status & MCI_STATUS_VAL))
248 * Uncorrected events are handled by the exception handler
249 * when it is enabled. But when the exception is disabled log
252 * TBD do the same check for MCI_STATUS_EN here?
254 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
257 if (m.status & MCI_STATUS_MISCV)
258 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
259 if (m.status & MCI_STATUS_ADDRV)
260 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
262 if (!(flags & MCP_TIMESTAMP))
265 * Don't get the IP here because it's unlikely to
266 * have anything to do with the actual error location.
268 if (!(flags & MCP_DONTLOG)) {
270 add_taint(TAINT_MACHINE_CHECK);
274 * Clear state for this bank.
276 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
280 * Don't clear MCG_STATUS here because it's only defined for
286 * The actual machine check handler. This only handles real
287 * exceptions when something got corrupted coming in through int 18.
289 * This is executed in NMI context not subject to normal locking rules. This
290 * implies that most kernel services cannot be safely used. Don't even
291 * think about putting a printk in there!
293 void do_machine_check(struct pt_regs *regs, long error_code)
295 struct mce m, panicm;
296 int panicm_found = 0;
300 * If no_way_out gets set, there is no safe way to recover from this
301 * MCE. If tolerant is cranked up, we'll try anyway.
305 * If kill_it gets set, there might be a way to recover from this
309 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
311 atomic_inc(&mce_entry);
313 if (notify_die(DIE_NMI, "machine check", regs, error_code,
314 18, SIGKILL) == NOTIFY_STOP)
321 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
323 /* if the restart IP is not valid, we're done for */
324 if (!(m.mcgstatus & MCG_STATUS_RIPV))
330 for (i = 0; i < banks; i++) {
331 __clear_bit(i, toclear);
339 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
340 if ((m.status & MCI_STATUS_VAL) == 0)
344 * Non uncorrected errors are handled by machine_check_poll
347 if ((m.status & MCI_STATUS_UC) == 0)
351 * Set taint even when machine check was not enabled.
353 add_taint(TAINT_MACHINE_CHECK);
355 __set_bit(i, toclear);
357 if (m.status & MCI_STATUS_EN) {
358 /* if PCC was set, there's no way out */
359 no_way_out |= !!(m.status & MCI_STATUS_PCC);
361 * If this error was uncorrectable and there was
362 * an overflow, we're in trouble. If no overflow,
363 * we might get away with just killing a task.
365 if (m.status & MCI_STATUS_UC) {
366 if (tolerant < 1 || m.status & MCI_STATUS_OVER)
372 * Machine check event was not enabled. Clear, but
378 if (m.status & MCI_STATUS_MISCV)
379 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
380 if (m.status & MCI_STATUS_ADDRV)
381 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
383 mce_get_rip(&m, regs);
387 * Did this bank cause the exception?
389 * Assume that the bank with uncorrectable errors did it,
390 * and that there is only a single one:
392 if ((m.status & MCI_STATUS_UC) &&
393 (m.status & MCI_STATUS_EN)) {
400 * If we didn't find an uncorrectable error, pick
401 * the last one (shouldn't happen, just being safe).
407 * If we have decided that we just CAN'T continue, and the user
408 * has not set tolerant to an insane level, give up and die.
410 if (no_way_out && tolerant < 3)
411 mce_panic("Machine check", &panicm, mcestart);
414 * If the error seems to be unrecoverable, something should be
415 * done. Try to kill as little as possible. If we can kill just
416 * one task, do that. If the user has set the tolerance very
417 * high, don't try to do anything at all.
419 if (kill_it && tolerant < 3) {
423 * If the EIPV bit is set, it means the saved IP is the
424 * instruction which caused the MCE.
426 if (m.mcgstatus & MCG_STATUS_EIPV)
427 user_space = panicm.ip && (panicm.cs & 3);
430 * If we know that the error was in user space, send a
431 * SIGBUS. Otherwise, panic if tolerance is low.
433 * force_sig() takes an awful lot of locks and has a slight
434 * risk of deadlocking.
437 force_sig(SIGBUS, current);
438 } else if (panic_on_oops || tolerant < 2) {
439 mce_panic("Uncorrected machine check",
444 /* notify userspace ASAP */
445 set_thread_flag(TIF_MCE_NOTIFY);
447 /* the last thing we do is clear state */
448 for (i = 0; i < banks; i++) {
449 if (test_bit(i, toclear))
450 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
452 wrmsrl(MSR_IA32_MCG_STATUS, 0);
454 atomic_dec(&mce_entry);
457 #ifdef CONFIG_X86_MCE_INTEL
459 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
460 * @cpu: The CPU on which the event occurred.
461 * @status: Event status information
463 * This function should be called by the thermal interrupt after the
464 * event has been processed and the decision was made to log the event
467 * The status parameter will be saved to the 'status' field of 'struct mce'
468 * and historically has been the register value of the
469 * MSR_IA32_THERMAL_STATUS (Intel) msr.
471 void mce_log_therm_throt_event(__u64 status)
476 m.bank = MCE_THERMAL_BANK;
480 #endif /* CONFIG_X86_MCE_INTEL */
483 * Periodic polling timer for "silent" machine check errors. If the
484 * poller finds an MCE, poll 2x faster. When the poller finds no more
485 * errors, poll 2x slower (up to check_interval seconds).
487 static int check_interval = 5 * 60; /* 5 minutes */
489 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
490 static DEFINE_PER_CPU(struct timer_list, mce_timer);
492 static void mcheck_timer(unsigned long data)
494 struct timer_list *t = &per_cpu(mce_timer, data);
497 WARN_ON(smp_processor_id() != data);
499 if (mce_available(¤t_cpu_data)) {
500 machine_check_poll(MCP_TIMESTAMP,
501 &__get_cpu_var(mce_poll_banks));
505 * Alert userspace if needed. If we logged an MCE, reduce the
506 * polling interval, otherwise increase the polling interval.
508 n = &__get_cpu_var(next_interval);
509 if (mce_notify_user()) {
510 *n = max(*n/2, HZ/100);
512 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
515 t->expires = jiffies + *n;
519 static void mce_do_trigger(struct work_struct *work)
521 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
524 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
527 * Notify the user(s) about new machine check events.
528 * Can be called from interrupt context, but not from machine check/NMI
531 int mce_notify_user(void)
533 /* Not more than two messages every minute */
534 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
536 clear_thread_flag(TIF_MCE_NOTIFY);
538 if (test_and_clear_bit(0, ¬ify_user)) {
539 wake_up_interruptible(&mce_wait);
542 * There is no risk of missing notifications because
543 * work_pending is always cleared before the function is
546 if (trigger[0] && !work_pending(&mce_trigger_work))
547 schedule_work(&mce_trigger_work);
549 if (__ratelimit(&ratelimit))
550 printk(KERN_INFO "Machine check events logged\n");
557 /* see if the idle task needs to notify userspace: */
559 mce_idle_callback(struct notifier_block *nfb, unsigned long action,
562 /* IDLE_END should be safe - interrupts are back on */
563 if (action == IDLE_END && test_thread_flag(TIF_MCE_NOTIFY))
569 static struct notifier_block mce_idle_notifier = {
570 .notifier_call = mce_idle_callback,
573 static __init int periodic_mcheck_init(void)
575 idle_notifier_register(&mce_idle_notifier);
578 __initcall(periodic_mcheck_init);
581 * Initialize Machine Checks for a CPU.
583 static int mce_cap_init(void)
588 rdmsrl(MSR_IA32_MCG_CAP, cap);
590 b = cap & MCG_BANKCNT_MASK;
591 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
593 if (b > MAX_NR_BANKS) {
595 "MCE: Using only %u machine check banks out of %u\n",
600 /* Don't support asymmetric configurations today */
601 WARN_ON(banks != 0 && b != banks);
604 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
607 memset(bank, 0xff, banks * sizeof(u64));
610 /* Use accurate RIP reporting if available. */
611 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
612 rip_msr = MSR_IA32_MCG_EIP;
617 static void mce_init(void *dummy)
619 mce_banks_t all_banks;
624 * Log the machine checks left over from the previous reset.
626 bitmap_fill(all_banks, MAX_NR_BANKS);
627 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
629 set_in_cr4(X86_CR4_MCE);
631 rdmsrl(MSR_IA32_MCG_CAP, cap);
633 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
635 for (i = 0; i < banks; i++) {
636 if (skip_bank_init(i))
638 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
639 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
643 /* Add per CPU specific workarounds here */
644 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
646 /* This should be disabled by the BIOS, but isn't always */
647 if (c->x86_vendor == X86_VENDOR_AMD) {
648 if (c->x86 == 15 && banks > 4) {
650 * disable GART TBL walk error reporting, which
651 * trips off incorrectly with the IOMMU & 3ware
654 clear_bit(10, (unsigned long *)&bank[4]);
656 if (c->x86 <= 17 && mce_bootlog < 0) {
658 * Lots of broken BIOS around that don't clear them
659 * by default and leave crap in there. Don't log:
664 * Various K7s with broken bank 0 around. Always disable
671 if (c->x86_vendor == X86_VENDOR_INTEL) {
673 * SDM documents that on family 6 bank 0 should not be written
674 * because it aliases to another special BIOS controlled
676 * But it's not aliased anymore on model 0x1a+
677 * Don't ignore bank 0 completely because there could be a
678 * valid event later, merely don't write CTL0.
681 if (c->x86 == 6 && c->x86_model < 0x1A)
682 __set_bit(0, &dont_init_banks);
686 static void mce_cpu_features(struct cpuinfo_x86 *c)
688 switch (c->x86_vendor) {
689 case X86_VENDOR_INTEL:
690 mce_intel_feature_init(c);
693 mce_amd_feature_init(c);
700 static void mce_init_timer(void)
702 struct timer_list *t = &__get_cpu_var(mce_timer);
703 int *n = &__get_cpu_var(next_interval);
705 *n = check_interval * HZ;
708 setup_timer(t, mcheck_timer, smp_processor_id());
709 t->expires = round_jiffies(jiffies + *n);
714 * Called for each booted CPU to set up machine checks.
715 * Must be called with preempt off:
717 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
719 if (!mce_available(c))
722 if (mce_cap_init() < 0) {
728 machine_check_vector = do_machine_check;
736 * Character device to read and clear the MCE log.
739 static DEFINE_SPINLOCK(mce_state_lock);
740 static int open_count; /* #times opened */
741 static int open_exclu; /* already open exclusive? */
743 static int mce_open(struct inode *inode, struct file *file)
746 spin_lock(&mce_state_lock);
748 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
749 spin_unlock(&mce_state_lock);
755 if (file->f_flags & O_EXCL)
759 spin_unlock(&mce_state_lock);
762 return nonseekable_open(inode, file);
765 static int mce_release(struct inode *inode, struct file *file)
767 spin_lock(&mce_state_lock);
772 spin_unlock(&mce_state_lock);
777 static void collect_tscs(void *data)
779 unsigned long *cpu_tsc = (unsigned long *)data;
781 rdtscll(cpu_tsc[smp_processor_id()]);
784 static DEFINE_MUTEX(mce_read_mutex);
786 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
789 char __user *buf = ubuf;
790 unsigned long *cpu_tsc;
794 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
798 mutex_lock(&mce_read_mutex);
799 next = rcu_dereference(mcelog.next);
801 /* Only supports full reads right now */
802 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
803 mutex_unlock(&mce_read_mutex);
812 for (i = prev; i < next; i++) {
813 unsigned long start = jiffies;
815 while (!mcelog.entry[i].finished) {
816 if (time_after_eq(jiffies, start + 2)) {
817 memset(mcelog.entry + i, 0,
824 err |= copy_to_user(buf, mcelog.entry + i,
826 buf += sizeof(struct mce);
831 memset(mcelog.entry + prev, 0,
832 (next - prev) * sizeof(struct mce));
834 next = cmpxchg(&mcelog.next, prev, 0);
835 } while (next != prev);
840 * Collect entries that were still getting written before the
843 on_each_cpu(collect_tscs, cpu_tsc, 1);
845 for (i = next; i < MCE_LOG_LEN; i++) {
846 if (mcelog.entry[i].finished &&
847 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
848 err |= copy_to_user(buf, mcelog.entry+i,
851 buf += sizeof(struct mce);
852 memset(&mcelog.entry[i], 0, sizeof(struct mce));
855 mutex_unlock(&mce_read_mutex);
858 return err ? -EFAULT : buf - ubuf;
861 static unsigned int mce_poll(struct file *file, poll_table *wait)
863 poll_wait(file, &mce_wait, wait);
864 if (rcu_dereference(mcelog.next))
865 return POLLIN | POLLRDNORM;
869 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
871 int __user *p = (int __user *)arg;
873 if (!capable(CAP_SYS_ADMIN))
877 case MCE_GET_RECORD_LEN:
878 return put_user(sizeof(struct mce), p);
879 case MCE_GET_LOG_LEN:
880 return put_user(MCE_LOG_LEN, p);
881 case MCE_GETCLEAR_FLAGS: {
885 flags = mcelog.flags;
886 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
888 return put_user(flags, p);
895 static const struct file_operations mce_chrdev_ops = {
897 .release = mce_release,
900 .unlocked_ioctl = mce_ioctl,
903 static struct miscdevice mce_log_device = {
910 * Old style boot options parsing. Only for compatibility.
912 static int __init mcheck_disable(char *str)
917 __setup("nomce", mcheck_disable);
920 * mce=off disables machine check
921 * mce=TOLERANCELEVEL (number, see above)
922 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
923 * mce=nobootlog Don't log MCEs from before booting.
925 static int __init mcheck_enable(char *str)
927 if (!strcmp(str, "off"))
929 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
930 mce_bootlog = (str[0] == 'b');
931 else if (isdigit(str[0]))
932 get_option(&str, &tolerant);
934 printk(KERN_INFO "mce= argument %s ignored. Please use /sys\n",
940 __setup("mce=", mcheck_enable);
947 * Disable machine checks on suspend and shutdown. We can't really handle
950 static int mce_disable(void)
954 for (i = 0; i < banks; i++) {
955 if (!skip_bank_init(i))
956 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
961 static int mce_suspend(struct sys_device *dev, pm_message_t state)
963 return mce_disable();
966 static int mce_shutdown(struct sys_device *dev)
968 return mce_disable();
972 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
973 * Only one CPU is active at this time, the others get re-added later using
976 static int mce_resume(struct sys_device *dev)
979 mce_cpu_features(¤t_cpu_data);
984 static void mce_cpu_restart(void *data)
986 del_timer_sync(&__get_cpu_var(mce_timer));
987 if (mce_available(¤t_cpu_data))
992 /* Reinit MCEs after user configuration changes */
993 static void mce_restart(void)
995 on_each_cpu(mce_cpu_restart, NULL, 1);
998 static struct sysdev_class mce_sysclass = {
999 .suspend = mce_suspend,
1000 .shutdown = mce_shutdown,
1001 .resume = mce_resume,
1002 .name = "machinecheck",
1005 DEFINE_PER_CPU(struct sys_device, mce_dev);
1008 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1010 /* Why are there no generic functions for this? */
1011 #define ACCESSOR(name, var, start) \
1012 static ssize_t show_ ## name(struct sys_device *s, \
1013 struct sysdev_attribute *attr, \
1015 return sprintf(buf, "%Lx\n", (u64)var); \
1017 static ssize_t set_ ## name(struct sys_device *s, \
1018 struct sysdev_attribute *attr, \
1019 const char *buf, size_t siz) { \
1021 u64 new = simple_strtoull(buf, &end, 0); \
1030 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
1032 static struct sysdev_attribute *bank_attrs;
1034 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1037 u64 b = bank[attr - bank_attrs];
1039 return sprintf(buf, "%llx\n", b);
1042 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1043 const char *buf, size_t siz)
1046 u64 new = simple_strtoull(buf, &end, 0);
1051 bank[attr - bank_attrs] = new;
1058 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1060 strcpy(buf, trigger);
1062 return strlen(trigger) + 1;
1065 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1066 const char *buf, size_t siz)
1071 strncpy(trigger, buf, sizeof(trigger));
1072 trigger[sizeof(trigger)-1] = 0;
1073 len = strlen(trigger);
1074 p = strchr(trigger, '\n');
1082 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1083 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1085 ACCESSOR(check_interval, check_interval, mce_restart())
1087 static struct sysdev_attribute *mce_attrs[] = {
1088 &attr_tolerant.attr, &attr_check_interval, &attr_trigger,
1092 static cpumask_var_t mce_dev_initialized;
1094 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1095 static __cpuinit int mce_create_device(unsigned int cpu)
1100 if (!mce_available(&boot_cpu_data))
1103 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1104 per_cpu(mce_dev, cpu).id = cpu;
1105 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1107 err = sysdev_register(&per_cpu(mce_dev, cpu));
1111 for (i = 0; mce_attrs[i]; i++) {
1112 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1116 for (i = 0; i < banks; i++) {
1117 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1122 cpumask_set_cpu(cpu, mce_dev_initialized);
1127 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1130 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1132 sysdev_unregister(&per_cpu(mce_dev, cpu));
1137 static __cpuinit void mce_remove_device(unsigned int cpu)
1141 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1144 for (i = 0; mce_attrs[i]; i++)
1145 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1147 for (i = 0; i < banks; i++)
1148 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1150 sysdev_unregister(&per_cpu(mce_dev, cpu));
1151 cpumask_clear_cpu(cpu, mce_dev_initialized);
1154 /* Make sure there are no machine checks on offlined CPUs. */
1155 static void mce_disable_cpu(void *h)
1157 unsigned long action = *(unsigned long *)h;
1160 if (!mce_available(¤t_cpu_data))
1162 if (!(action & CPU_TASKS_FROZEN))
1164 for (i = 0; i < banks; i++) {
1165 if (!skip_bank_init(i))
1166 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1170 static void mce_reenable_cpu(void *h)
1172 unsigned long action = *(unsigned long *)h;
1175 if (!mce_available(¤t_cpu_data))
1178 if (!(action & CPU_TASKS_FROZEN))
1180 for (i = 0; i < banks; i++) {
1181 if (!skip_bank_init(i))
1182 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1186 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1187 static int __cpuinit
1188 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1190 unsigned int cpu = (unsigned long)hcpu;
1191 struct timer_list *t = &per_cpu(mce_timer, cpu);
1195 case CPU_ONLINE_FROZEN:
1196 mce_create_device(cpu);
1197 if (threshold_cpu_callback)
1198 threshold_cpu_callback(action, cpu);
1201 case CPU_DEAD_FROZEN:
1202 if (threshold_cpu_callback)
1203 threshold_cpu_callback(action, cpu);
1204 mce_remove_device(cpu);
1206 case CPU_DOWN_PREPARE:
1207 case CPU_DOWN_PREPARE_FROZEN:
1209 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1211 case CPU_DOWN_FAILED:
1212 case CPU_DOWN_FAILED_FROZEN:
1213 t->expires = round_jiffies(jiffies +
1214 __get_cpu_var(next_interval));
1215 add_timer_on(t, cpu);
1216 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1219 /* intentionally ignoring frozen here */
1220 cmci_rediscover(cpu);
1226 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1227 .notifier_call = mce_cpu_callback,
1230 static __init int mce_init_banks(void)
1234 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1239 for (i = 0; i < banks; i++) {
1240 struct sysdev_attribute *a = &bank_attrs[i];
1242 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1246 a->attr.mode = 0644;
1247 a->show = show_bank;
1248 a->store = set_bank;
1254 kfree(bank_attrs[i].attr.name);
1261 static __init int mce_init_device(void)
1266 if (!mce_available(&boot_cpu_data))
1269 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1271 err = mce_init_banks();
1275 err = sysdev_class_register(&mce_sysclass);
1279 for_each_online_cpu(i) {
1280 err = mce_create_device(i);
1285 register_hotcpu_notifier(&mce_cpu_notifier);
1286 misc_register(&mce_log_device);
1291 device_initcall(mce_init_device);
1293 #else /* CONFIG_X86_32: */
1298 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
1300 /* This has to be run for each processor */
1301 void mcheck_init(struct cpuinfo_x86 *c)
1303 if (mce_disabled == 1)
1306 switch (c->x86_vendor) {
1307 case X86_VENDOR_AMD:
1311 case X86_VENDOR_INTEL:
1313 intel_p5_mcheck_init(c);
1315 intel_p6_mcheck_init(c);
1317 intel_p4_mcheck_init(c);
1320 case X86_VENDOR_CENTAUR:
1322 winchip_mcheck_init(c);
1328 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
1331 static int __init mcheck_disable(char *str)
1337 static int __init mcheck_enable(char *str)
1343 __setup("nomce", mcheck_disable);
1344 __setup("mce", mcheck_enable);
1346 #endif /* CONFIG_X86_32 */