2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kobject.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
33 #include <asm/processor.h>
34 #include <asm/uaccess.h>
42 /* Handle unconfigured int18 (should never happen) */
43 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
45 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
49 /* Call the installed machine check handler for this CPU setup. */
50 void (*machine_check_vector)(struct pt_regs *, long error_code) =
51 unexpected_machine_check;
55 #ifdef CONFIG_X86_NEW_MCE
57 #define MISC_MCELOG_MINOR 227
63 * 0: always panic on uncorrected errors, log corrected errors
64 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
65 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
66 * 3: never panic or SIGBUS, log all errors (for testing only)
68 static int tolerant = 1;
71 static unsigned long notify_user;
73 static int mce_bootlog = -1;
74 static atomic_t mce_events;
76 static char trigger[128];
77 static char *trigger_argv[2] = { trigger, NULL };
79 static unsigned long dont_init_banks;
81 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
83 /* MCA banks polled by the period polling timer for corrected events */
84 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
85 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
88 static inline int skip_bank_init(int i)
90 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
93 /* Do initial initialization of a struct mce */
94 void mce_setup(struct mce *m)
96 memset(m, 0, sizeof(struct mce));
97 m->cpu = smp_processor_id();
101 DEFINE_PER_CPU(struct mce, injectm);
102 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
105 * Lockless MCE logging infrastructure.
106 * This avoids deadlocks on printk locks without having to break locks. Also
107 * separate MCEs from kernel messages to avoid bogus bug reports.
110 static struct mce_log mcelog = {
115 void mce_log(struct mce *mce)
117 unsigned next, entry;
119 atomic_inc(&mce_events);
123 entry = rcu_dereference(mcelog.next);
126 * When the buffer fills up discard new entries.
127 * Assume that the earlier errors are the more
130 if (entry >= MCE_LOG_LEN) {
131 set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags);
134 /* Old left over entry. Skip: */
135 if (mcelog.entry[entry].finished) {
143 if (cmpxchg(&mcelog.next, entry, next) == entry)
146 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
148 mcelog.entry[entry].finished = 1;
151 set_bit(0, ¬ify_user);
154 static void print_mce(struct mce *m)
156 printk(KERN_EMERG "\n"
157 KERN_EMERG "HARDWARE ERROR\n"
159 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
160 m->cpu, m->mcgstatus, m->bank, m->status);
162 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
163 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
165 if (m->cs == __KERNEL_CS)
166 print_symbol("{%s}", m->ip);
169 printk(KERN_EMERG "TSC %llx ", m->tsc);
171 printk("ADDR %llx ", m->addr);
173 printk("MISC %llx ", m->misc);
175 printk(KERN_EMERG "This is not a software problem!\n");
176 printk(KERN_EMERG "Run through mcelog --ascii to decode "
177 "and contact your hardware vendor\n");
180 static void mce_panic(char *msg, struct mce *backup, u64 start)
186 for (i = 0; i < MCE_LOG_LEN; i++) {
187 u64 tsc = mcelog.entry[i].tsc;
189 if ((s64)(tsc - start) < 0)
191 print_mce(&mcelog.entry[i]);
192 if (backup && mcelog.entry[i].tsc == backup->tsc)
200 /* Support code for software error injection */
202 static int msr_to_offset(u32 msr)
204 unsigned bank = __get_cpu_var(injectm.bank);
206 return offsetof(struct mce, ip);
207 if (msr == MSR_IA32_MC0_STATUS + bank*4)
208 return offsetof(struct mce, status);
209 if (msr == MSR_IA32_MC0_ADDR + bank*4)
210 return offsetof(struct mce, addr);
211 if (msr == MSR_IA32_MC0_MISC + bank*4)
212 return offsetof(struct mce, misc);
213 if (msr == MSR_IA32_MCG_STATUS)
214 return offsetof(struct mce, mcgstatus);
218 /* MSR access wrappers used for error injection */
219 static u64 mce_rdmsrl(u32 msr)
222 if (__get_cpu_var(injectm).finished) {
223 int offset = msr_to_offset(msr);
226 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
232 static void mce_wrmsrl(u32 msr, u64 v)
234 if (__get_cpu_var(injectm).finished) {
235 int offset = msr_to_offset(msr);
237 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
243 int mce_available(struct cpuinfo_x86 *c)
247 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
250 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
252 if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
260 /* Assume the RIP in the MSR is exact. Is this true? */
261 m->mcgstatus |= MCG_STATUS_EIPV;
262 m->ip = mce_rdmsrl(rip_msr);
268 * Poll for corrected events or events that happened before reset.
269 * Those are just logged through /dev/mcelog.
271 * This is executed in standard interrupt context.
273 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
280 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
281 for (i = 0; i < banks; i++) {
282 if (!bank[i] || !test_bit(i, *b))
291 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
292 if (!(m.status & MCI_STATUS_VAL))
296 * Uncorrected events are handled by the exception handler
297 * when it is enabled. But when the exception is disabled log
300 * TBD do the same check for MCI_STATUS_EN here?
302 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
305 if (m.status & MCI_STATUS_MISCV)
306 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
307 if (m.status & MCI_STATUS_ADDRV)
308 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
310 if (!(flags & MCP_TIMESTAMP))
313 * Don't get the IP here because it's unlikely to
314 * have anything to do with the actual error location.
316 if (!(flags & MCP_DONTLOG)) {
318 add_taint(TAINT_MACHINE_CHECK);
322 * Clear state for this bank.
324 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
328 * Don't clear MCG_STATUS here because it's only defined for
334 EXPORT_SYMBOL_GPL(machine_check_poll);
337 * The actual machine check handler. This only handles real
338 * exceptions when something got corrupted coming in through int 18.
340 * This is executed in NMI context not subject to normal locking rules. This
341 * implies that most kernel services cannot be safely used. Don't even
342 * think about putting a printk in there!
344 void do_machine_check(struct pt_regs *regs, long error_code)
346 struct mce m, panicm;
347 int panicm_found = 0;
351 * If no_way_out gets set, there is no safe way to recover from this
352 * MCE. If tolerant is cranked up, we'll try anyway.
356 * If kill_it gets set, there might be a way to recover from this
360 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
362 atomic_inc(&mce_entry);
364 if (notify_die(DIE_NMI, "machine check", regs, error_code,
365 18, SIGKILL) == NOTIFY_STOP)
372 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
374 /* if the restart IP is not valid, we're done for */
375 if (!(m.mcgstatus & MCG_STATUS_RIPV))
381 for (i = 0; i < banks; i++) {
382 __clear_bit(i, toclear);
390 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
391 if ((m.status & MCI_STATUS_VAL) == 0)
395 * Non uncorrected errors are handled by machine_check_poll
398 if ((m.status & MCI_STATUS_UC) == 0)
402 * Set taint even when machine check was not enabled.
404 add_taint(TAINT_MACHINE_CHECK);
406 __set_bit(i, toclear);
408 if (m.status & MCI_STATUS_EN) {
409 /* if PCC was set, there's no way out */
410 no_way_out |= !!(m.status & MCI_STATUS_PCC);
412 * If this error was uncorrectable and there was
413 * an overflow, we're in trouble. If no overflow,
414 * we might get away with just killing a task.
416 if (m.status & MCI_STATUS_UC) {
417 if (tolerant < 1 || m.status & MCI_STATUS_OVER)
423 * Machine check event was not enabled. Clear, but
429 if (m.status & MCI_STATUS_MISCV)
430 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
431 if (m.status & MCI_STATUS_ADDRV)
432 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
434 mce_get_rip(&m, regs);
438 * Did this bank cause the exception?
440 * Assume that the bank with uncorrectable errors did it,
441 * and that there is only a single one:
443 if ((m.status & MCI_STATUS_UC) &&
444 (m.status & MCI_STATUS_EN)) {
451 * If we didn't find an uncorrectable error, pick
452 * the last one (shouldn't happen, just being safe).
458 * If we have decided that we just CAN'T continue, and the user
459 * has not set tolerant to an insane level, give up and die.
461 if (no_way_out && tolerant < 3)
462 mce_panic("Machine check", &panicm, mcestart);
465 * If the error seems to be unrecoverable, something should be
466 * done. Try to kill as little as possible. If we can kill just
467 * one task, do that. If the user has set the tolerance very
468 * high, don't try to do anything at all.
470 if (kill_it && tolerant < 3) {
474 * If the EIPV bit is set, it means the saved IP is the
475 * instruction which caused the MCE.
477 if (m.mcgstatus & MCG_STATUS_EIPV)
478 user_space = panicm.ip && (panicm.cs & 3);
481 * If we know that the error was in user space, send a
482 * SIGBUS. Otherwise, panic if tolerance is low.
484 * force_sig() takes an awful lot of locks and has a slight
485 * risk of deadlocking.
488 force_sig(SIGBUS, current);
489 } else if (panic_on_oops || tolerant < 2) {
490 mce_panic("Uncorrected machine check",
495 /* notify userspace ASAP */
496 set_thread_flag(TIF_MCE_NOTIFY);
498 /* the last thing we do is clear state */
499 for (i = 0; i < banks; i++) {
500 if (test_bit(i, toclear))
501 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
503 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
505 atomic_dec(&mce_entry);
508 EXPORT_SYMBOL_GPL(do_machine_check);
510 #ifdef CONFIG_X86_MCE_INTEL
512 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
513 * @cpu: The CPU on which the event occurred.
514 * @status: Event status information
516 * This function should be called by the thermal interrupt after the
517 * event has been processed and the decision was made to log the event
520 * The status parameter will be saved to the 'status' field of 'struct mce'
521 * and historically has been the register value of the
522 * MSR_IA32_THERMAL_STATUS (Intel) msr.
524 void mce_log_therm_throt_event(__u64 status)
529 m.bank = MCE_THERMAL_BANK;
533 #endif /* CONFIG_X86_MCE_INTEL */
536 * Periodic polling timer for "silent" machine check errors. If the
537 * poller finds an MCE, poll 2x faster. When the poller finds no more
538 * errors, poll 2x slower (up to check_interval seconds).
540 static int check_interval = 5 * 60; /* 5 minutes */
542 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
543 static DEFINE_PER_CPU(struct timer_list, mce_timer);
545 static void mcheck_timer(unsigned long data)
547 struct timer_list *t = &per_cpu(mce_timer, data);
550 WARN_ON(smp_processor_id() != data);
552 if (mce_available(¤t_cpu_data)) {
553 machine_check_poll(MCP_TIMESTAMP,
554 &__get_cpu_var(mce_poll_banks));
558 * Alert userspace if needed. If we logged an MCE, reduce the
559 * polling interval, otherwise increase the polling interval.
561 n = &__get_cpu_var(next_interval);
562 if (mce_notify_user()) {
563 *n = max(*n/2, HZ/100);
565 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
568 t->expires = jiffies + *n;
572 static void mce_do_trigger(struct work_struct *work)
574 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
577 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
580 * Notify the user(s) about new machine check events.
581 * Can be called from interrupt context, but not from machine check/NMI
584 int mce_notify_user(void)
586 /* Not more than two messages every minute */
587 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
589 clear_thread_flag(TIF_MCE_NOTIFY);
591 if (test_and_clear_bit(0, ¬ify_user)) {
592 wake_up_interruptible(&mce_wait);
595 * There is no risk of missing notifications because
596 * work_pending is always cleared before the function is
599 if (trigger[0] && !work_pending(&mce_trigger_work))
600 schedule_work(&mce_trigger_work);
602 if (__ratelimit(&ratelimit))
603 printk(KERN_INFO "Machine check events logged\n");
609 EXPORT_SYMBOL_GPL(mce_notify_user);
612 * Initialize Machine Checks for a CPU.
614 static int mce_cap_init(void)
619 rdmsrl(MSR_IA32_MCG_CAP, cap);
621 b = cap & MCG_BANKCNT_MASK;
622 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
624 if (b > MAX_NR_BANKS) {
626 "MCE: Using only %u machine check banks out of %u\n",
631 /* Don't support asymmetric configurations today */
632 WARN_ON(banks != 0 && b != banks);
635 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
638 memset(bank, 0xff, banks * sizeof(u64));
641 /* Use accurate RIP reporting if available. */
642 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
643 rip_msr = MSR_IA32_MCG_EIP;
648 static void mce_init(void *dummy)
650 mce_banks_t all_banks;
655 * Log the machine checks left over from the previous reset.
657 bitmap_fill(all_banks, MAX_NR_BANKS);
658 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
660 set_in_cr4(X86_CR4_MCE);
662 rdmsrl(MSR_IA32_MCG_CAP, cap);
664 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
666 for (i = 0; i < banks; i++) {
667 if (skip_bank_init(i))
669 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
670 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
674 /* Add per CPU specific workarounds here */
675 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
677 /* This should be disabled by the BIOS, but isn't always */
678 if (c->x86_vendor == X86_VENDOR_AMD) {
679 if (c->x86 == 15 && banks > 4) {
681 * disable GART TBL walk error reporting, which
682 * trips off incorrectly with the IOMMU & 3ware
685 clear_bit(10, (unsigned long *)&bank[4]);
687 if (c->x86 <= 17 && mce_bootlog < 0) {
689 * Lots of broken BIOS around that don't clear them
690 * by default and leave crap in there. Don't log:
695 * Various K7s with broken bank 0 around. Always disable
702 if (c->x86_vendor == X86_VENDOR_INTEL) {
704 * SDM documents that on family 6 bank 0 should not be written
705 * because it aliases to another special BIOS controlled
707 * But it's not aliased anymore on model 0x1a+
708 * Don't ignore bank 0 completely because there could be a
709 * valid event later, merely don't write CTL0.
712 if (c->x86 == 6 && c->x86_model < 0x1A)
713 __set_bit(0, &dont_init_banks);
717 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
721 switch (c->x86_vendor) {
722 case X86_VENDOR_INTEL:
723 if (mce_p5_enabled())
724 intel_p5_mcheck_init(c);
726 case X86_VENDOR_CENTAUR:
727 winchip_mcheck_init(c);
732 static void mce_cpu_features(struct cpuinfo_x86 *c)
734 switch (c->x86_vendor) {
735 case X86_VENDOR_INTEL:
736 mce_intel_feature_init(c);
739 mce_amd_feature_init(c);
746 static void mce_init_timer(void)
748 struct timer_list *t = &__get_cpu_var(mce_timer);
749 int *n = &__get_cpu_var(next_interval);
751 *n = check_interval * HZ;
754 setup_timer(t, mcheck_timer, smp_processor_id());
755 t->expires = round_jiffies(jiffies + *n);
760 * Called for each booted CPU to set up machine checks.
761 * Must be called with preempt off:
763 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
770 if (!mce_available(c))
773 if (mce_cap_init() < 0) {
779 machine_check_vector = do_machine_check;
787 * Character device to read and clear the MCE log.
790 static DEFINE_SPINLOCK(mce_state_lock);
791 static int open_count; /* #times opened */
792 static int open_exclu; /* already open exclusive? */
794 static int mce_open(struct inode *inode, struct file *file)
797 spin_lock(&mce_state_lock);
799 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
800 spin_unlock(&mce_state_lock);
806 if (file->f_flags & O_EXCL)
810 spin_unlock(&mce_state_lock);
813 return nonseekable_open(inode, file);
816 static int mce_release(struct inode *inode, struct file *file)
818 spin_lock(&mce_state_lock);
823 spin_unlock(&mce_state_lock);
828 static void collect_tscs(void *data)
830 unsigned long *cpu_tsc = (unsigned long *)data;
832 rdtscll(cpu_tsc[smp_processor_id()]);
835 static DEFINE_MUTEX(mce_read_mutex);
837 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
840 char __user *buf = ubuf;
841 unsigned long *cpu_tsc;
845 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
849 mutex_lock(&mce_read_mutex);
850 next = rcu_dereference(mcelog.next);
852 /* Only supports full reads right now */
853 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
854 mutex_unlock(&mce_read_mutex);
863 for (i = prev; i < next; i++) {
864 unsigned long start = jiffies;
866 while (!mcelog.entry[i].finished) {
867 if (time_after_eq(jiffies, start + 2)) {
868 memset(mcelog.entry + i, 0,
875 err |= copy_to_user(buf, mcelog.entry + i,
877 buf += sizeof(struct mce);
882 memset(mcelog.entry + prev, 0,
883 (next - prev) * sizeof(struct mce));
885 next = cmpxchg(&mcelog.next, prev, 0);
886 } while (next != prev);
891 * Collect entries that were still getting written before the
894 on_each_cpu(collect_tscs, cpu_tsc, 1);
896 for (i = next; i < MCE_LOG_LEN; i++) {
897 if (mcelog.entry[i].finished &&
898 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
899 err |= copy_to_user(buf, mcelog.entry+i,
902 buf += sizeof(struct mce);
903 memset(&mcelog.entry[i], 0, sizeof(struct mce));
906 mutex_unlock(&mce_read_mutex);
909 return err ? -EFAULT : buf - ubuf;
912 static unsigned int mce_poll(struct file *file, poll_table *wait)
914 poll_wait(file, &mce_wait, wait);
915 if (rcu_dereference(mcelog.next))
916 return POLLIN | POLLRDNORM;
920 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
922 int __user *p = (int __user *)arg;
924 if (!capable(CAP_SYS_ADMIN))
928 case MCE_GET_RECORD_LEN:
929 return put_user(sizeof(struct mce), p);
930 case MCE_GET_LOG_LEN:
931 return put_user(MCE_LOG_LEN, p);
932 case MCE_GETCLEAR_FLAGS: {
936 flags = mcelog.flags;
937 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
939 return put_user(flags, p);
946 /* Modified in mce-inject.c, so not static or const */
947 struct file_operations mce_chrdev_ops = {
949 .release = mce_release,
952 .unlocked_ioctl = mce_ioctl,
954 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
956 static struct miscdevice mce_log_device = {
963 * mce=off disables machine check
964 * mce=TOLERANCELEVEL (number, see above)
965 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
966 * mce=nobootlog Don't log MCEs from before booting.
968 static int __init mcheck_enable(char *str)
974 if (!strcmp(str, "off"))
976 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
977 mce_bootlog = (str[0] == 'b');
978 else if (isdigit(str[0]))
979 get_option(&str, &tolerant);
981 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
987 __setup("mce", mcheck_enable);
994 * Disable machine checks on suspend and shutdown. We can't really handle
997 static int mce_disable(void)
1001 for (i = 0; i < banks; i++) {
1002 if (!skip_bank_init(i))
1003 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1008 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1010 return mce_disable();
1013 static int mce_shutdown(struct sys_device *dev)
1015 return mce_disable();
1019 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1020 * Only one CPU is active at this time, the others get re-added later using
1023 static int mce_resume(struct sys_device *dev)
1026 mce_cpu_features(¤t_cpu_data);
1031 static void mce_cpu_restart(void *data)
1033 del_timer_sync(&__get_cpu_var(mce_timer));
1034 if (mce_available(¤t_cpu_data))
1039 /* Reinit MCEs after user configuration changes */
1040 static void mce_restart(void)
1042 on_each_cpu(mce_cpu_restart, NULL, 1);
1045 static struct sysdev_class mce_sysclass = {
1046 .suspend = mce_suspend,
1047 .shutdown = mce_shutdown,
1048 .resume = mce_resume,
1049 .name = "machinecheck",
1052 DEFINE_PER_CPU(struct sys_device, mce_dev);
1055 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1057 /* Why are there no generic functions for this? */
1058 #define ACCESSOR(name, var, start) \
1059 static ssize_t show_ ## name(struct sys_device *s, \
1060 struct sysdev_attribute *attr, \
1062 return sprintf(buf, "%Lx\n", (u64)var); \
1064 static ssize_t set_ ## name(struct sys_device *s, \
1065 struct sysdev_attribute *attr, \
1066 const char *buf, size_t siz) { \
1068 u64 new = simple_strtoull(buf, &end, 0); \
1077 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
1079 static struct sysdev_attribute *bank_attrs;
1081 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1084 u64 b = bank[attr - bank_attrs];
1086 return sprintf(buf, "%llx\n", b);
1089 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1090 const char *buf, size_t siz)
1093 u64 new = simple_strtoull(buf, &end, 0);
1098 bank[attr - bank_attrs] = new;
1105 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1107 strcpy(buf, trigger);
1109 return strlen(trigger) + 1;
1112 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1113 const char *buf, size_t siz)
1118 strncpy(trigger, buf, sizeof(trigger));
1119 trigger[sizeof(trigger)-1] = 0;
1120 len = strlen(trigger);
1121 p = strchr(trigger, '\n');
1129 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1130 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1132 ACCESSOR(check_interval, check_interval, mce_restart())
1134 static struct sysdev_attribute *mce_attrs[] = {
1135 &attr_tolerant.attr, &attr_check_interval, &attr_trigger,
1139 static cpumask_var_t mce_dev_initialized;
1141 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1142 static __cpuinit int mce_create_device(unsigned int cpu)
1147 if (!mce_available(&boot_cpu_data))
1150 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1151 per_cpu(mce_dev, cpu).id = cpu;
1152 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1154 err = sysdev_register(&per_cpu(mce_dev, cpu));
1158 for (i = 0; mce_attrs[i]; i++) {
1159 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1163 for (i = 0; i < banks; i++) {
1164 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1169 cpumask_set_cpu(cpu, mce_dev_initialized);
1174 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1177 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1179 sysdev_unregister(&per_cpu(mce_dev, cpu));
1184 static __cpuinit void mce_remove_device(unsigned int cpu)
1188 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1191 for (i = 0; mce_attrs[i]; i++)
1192 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1194 for (i = 0; i < banks; i++)
1195 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1197 sysdev_unregister(&per_cpu(mce_dev, cpu));
1198 cpumask_clear_cpu(cpu, mce_dev_initialized);
1201 /* Make sure there are no machine checks on offlined CPUs. */
1202 static void mce_disable_cpu(void *h)
1204 unsigned long action = *(unsigned long *)h;
1207 if (!mce_available(¤t_cpu_data))
1209 if (!(action & CPU_TASKS_FROZEN))
1211 for (i = 0; i < banks; i++) {
1212 if (!skip_bank_init(i))
1213 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1217 static void mce_reenable_cpu(void *h)
1219 unsigned long action = *(unsigned long *)h;
1222 if (!mce_available(¤t_cpu_data))
1225 if (!(action & CPU_TASKS_FROZEN))
1227 for (i = 0; i < banks; i++) {
1228 if (!skip_bank_init(i))
1229 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1233 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1234 static int __cpuinit
1235 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1237 unsigned int cpu = (unsigned long)hcpu;
1238 struct timer_list *t = &per_cpu(mce_timer, cpu);
1242 case CPU_ONLINE_FROZEN:
1243 mce_create_device(cpu);
1244 if (threshold_cpu_callback)
1245 threshold_cpu_callback(action, cpu);
1248 case CPU_DEAD_FROZEN:
1249 if (threshold_cpu_callback)
1250 threshold_cpu_callback(action, cpu);
1251 mce_remove_device(cpu);
1253 case CPU_DOWN_PREPARE:
1254 case CPU_DOWN_PREPARE_FROZEN:
1256 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1258 case CPU_DOWN_FAILED:
1259 case CPU_DOWN_FAILED_FROZEN:
1260 t->expires = round_jiffies(jiffies +
1261 __get_cpu_var(next_interval));
1262 add_timer_on(t, cpu);
1263 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1266 /* intentionally ignoring frozen here */
1267 cmci_rediscover(cpu);
1273 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1274 .notifier_call = mce_cpu_callback,
1277 static __init int mce_init_banks(void)
1281 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1286 for (i = 0; i < banks; i++) {
1287 struct sysdev_attribute *a = &bank_attrs[i];
1289 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1293 a->attr.mode = 0644;
1294 a->show = show_bank;
1295 a->store = set_bank;
1301 kfree(bank_attrs[i].attr.name);
1308 static __init int mce_init_device(void)
1313 if (!mce_available(&boot_cpu_data))
1316 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1318 err = mce_init_banks();
1322 err = sysdev_class_register(&mce_sysclass);
1326 for_each_online_cpu(i) {
1327 err = mce_create_device(i);
1332 register_hotcpu_notifier(&mce_cpu_notifier);
1333 misc_register(&mce_log_device);
1338 device_initcall(mce_init_device);
1340 #else /* CONFIG_X86_OLD_MCE: */
1343 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
1345 /* This has to be run for each processor */
1346 void mcheck_init(struct cpuinfo_x86 *c)
1348 if (mce_disabled == 1)
1351 switch (c->x86_vendor) {
1352 case X86_VENDOR_AMD:
1356 case X86_VENDOR_INTEL:
1358 intel_p5_mcheck_init(c);
1360 intel_p6_mcheck_init(c);
1362 intel_p4_mcheck_init(c);
1365 case X86_VENDOR_CENTAUR:
1367 winchip_mcheck_init(c);
1373 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
1376 static int __init mcheck_enable(char *str)
1382 __setup("mce", mcheck_enable);
1384 #endif /* CONFIG_X86_OLD_MCE */
1387 * Old style boot options parsing. Only for compatibility.
1389 static int __init mcheck_disable(char *str)
1394 __setup("nomce", mcheck_disable);