2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
31 #include <linux/smp.h>
34 #include <asm/processor.h>
41 /* Handle unconfigured int18 (should never happen) */
42 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
44 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
48 /* Call the installed machine check handler for this CPU setup. */
49 void (*machine_check_vector)(struct pt_regs *, long error_code) =
50 unexpected_machine_check;
54 #ifdef CONFIG_X86_NEW_MCE
56 #define MISC_MCELOG_MINOR 227
60 DEFINE_PER_CPU(unsigned, mce_exception_count);
64 * 0: always panic on uncorrected errors, log corrected errors
65 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
66 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
67 * 3: never panic or SIGBUS, log all errors (for testing only)
69 static int tolerant = 1;
72 static unsigned long notify_user;
74 static int mce_bootlog = -1;
76 static char trigger[128];
77 static char *trigger_argv[2] = { trigger, NULL };
79 static unsigned long dont_init_banks;
81 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
83 /* MCA banks polled by the period polling timer for corrected events */
84 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
85 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
88 static inline int skip_bank_init(int i)
90 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
93 /* Do initial initialization of a struct mce */
94 void mce_setup(struct mce *m)
96 memset(m, 0, sizeof(struct mce));
97 m->cpu = m->extcpu = smp_processor_id();
101 DEFINE_PER_CPU(struct mce, injectm);
102 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
105 * Lockless MCE logging infrastructure.
106 * This avoids deadlocks on printk locks without having to break locks. Also
107 * separate MCEs from kernel messages to avoid bogus bug reports.
110 static struct mce_log mcelog = {
111 .signature = MCE_LOG_SIGNATURE,
113 .recordlen = sizeof(struct mce),
116 void mce_log(struct mce *mce)
118 unsigned next, entry;
123 entry = rcu_dereference(mcelog.next);
126 * When the buffer fills up discard new entries.
127 * Assume that the earlier errors are the more
130 if (entry >= MCE_LOG_LEN) {
131 set_bit(MCE_OVERFLOW,
132 (unsigned long *)&mcelog.flags);
135 /* Old left over entry. Skip: */
136 if (mcelog.entry[entry].finished) {
144 if (cmpxchg(&mcelog.next, entry, next) == entry)
147 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
149 mcelog.entry[entry].finished = 1;
152 set_bit(0, ¬ify_user);
155 static void print_mce(struct mce *m)
157 printk(KERN_EMERG "\n"
158 KERN_EMERG "HARDWARE ERROR\n"
160 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
161 m->extcpu, m->mcgstatus, m->bank, m->status);
163 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
164 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
166 if (m->cs == __KERNEL_CS)
167 print_symbol("{%s}", m->ip);
170 printk(KERN_EMERG "TSC %llx ", m->tsc);
172 printk("ADDR %llx ", m->addr);
174 printk("MISC %llx ", m->misc);
176 printk(KERN_EMERG "This is not a software problem!\n");
177 printk(KERN_EMERG "Run through mcelog --ascii to decode "
178 "and contact your hardware vendor\n");
181 static void mce_panic(char *msg, struct mce *backup, u64 start)
187 for (i = 0; i < MCE_LOG_LEN; i++) {
188 u64 tsc = mcelog.entry[i].tsc;
190 if ((s64)(tsc - start) < 0)
192 print_mce(&mcelog.entry[i]);
193 if (backup && mcelog.entry[i].tsc == backup->tsc)
201 /* Support code for software error injection */
203 static int msr_to_offset(u32 msr)
205 unsigned bank = __get_cpu_var(injectm.bank);
207 return offsetof(struct mce, ip);
208 if (msr == MSR_IA32_MC0_STATUS + bank*4)
209 return offsetof(struct mce, status);
210 if (msr == MSR_IA32_MC0_ADDR + bank*4)
211 return offsetof(struct mce, addr);
212 if (msr == MSR_IA32_MC0_MISC + bank*4)
213 return offsetof(struct mce, misc);
214 if (msr == MSR_IA32_MCG_STATUS)
215 return offsetof(struct mce, mcgstatus);
219 /* MSR access wrappers used for error injection */
220 static u64 mce_rdmsrl(u32 msr)
223 if (__get_cpu_var(injectm).finished) {
224 int offset = msr_to_offset(msr);
227 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
233 static void mce_wrmsrl(u32 msr, u64 v)
235 if (__get_cpu_var(injectm).finished) {
236 int offset = msr_to_offset(msr);
238 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
244 int mce_available(struct cpuinfo_x86 *c)
248 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
251 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
253 if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
261 /* Assume the RIP in the MSR is exact. Is this true? */
262 m->mcgstatus |= MCG_STATUS_EIPV;
263 m->ip = mce_rdmsrl(rip_msr);
268 DEFINE_PER_CPU(unsigned, mce_poll_count);
271 * Poll for corrected events or events that happened before reset.
272 * Those are just logged through /dev/mcelog.
274 * This is executed in standard interrupt context.
276 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
281 __get_cpu_var(mce_poll_count)++;
285 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
286 for (i = 0; i < banks; i++) {
287 if (!bank[i] || !test_bit(i, *b))
296 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
297 if (!(m.status & MCI_STATUS_VAL))
301 * Uncorrected events are handled by the exception handler
302 * when it is enabled. But when the exception is disabled log
305 * TBD do the same check for MCI_STATUS_EN here?
307 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
310 if (m.status & MCI_STATUS_MISCV)
311 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
312 if (m.status & MCI_STATUS_ADDRV)
313 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
315 if (!(flags & MCP_TIMESTAMP))
318 * Don't get the IP here because it's unlikely to
319 * have anything to do with the actual error location.
321 if (!(flags & MCP_DONTLOG)) {
323 add_taint(TAINT_MACHINE_CHECK);
327 * Clear state for this bank.
329 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
333 * Don't clear MCG_STATUS here because it's only defined for
339 EXPORT_SYMBOL_GPL(machine_check_poll);
342 * The actual machine check handler. This only handles real
343 * exceptions when something got corrupted coming in through int 18.
345 * This is executed in NMI context not subject to normal locking rules. This
346 * implies that most kernel services cannot be safely used. Don't even
347 * think about putting a printk in there!
349 void do_machine_check(struct pt_regs *regs, long error_code)
351 struct mce m, panicm;
352 int panicm_found = 0;
356 * If no_way_out gets set, there is no safe way to recover from this
357 * MCE. If tolerant is cranked up, we'll try anyway.
361 * If kill_it gets set, there might be a way to recover from this
365 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
367 atomic_inc(&mce_entry);
369 __get_cpu_var(mce_exception_count)++;
371 if (notify_die(DIE_NMI, "machine check", regs, error_code,
372 18, SIGKILL) == NOTIFY_STOP)
379 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
381 /* if the restart IP is not valid, we're done for */
382 if (!(m.mcgstatus & MCG_STATUS_RIPV))
388 for (i = 0; i < banks; i++) {
389 __clear_bit(i, toclear);
397 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
398 if ((m.status & MCI_STATUS_VAL) == 0)
402 * Non uncorrected errors are handled by machine_check_poll
405 if ((m.status & MCI_STATUS_UC) == 0)
409 * Set taint even when machine check was not enabled.
411 add_taint(TAINT_MACHINE_CHECK);
413 __set_bit(i, toclear);
415 if (m.status & MCI_STATUS_EN) {
416 /* if PCC was set, there's no way out */
417 no_way_out |= !!(m.status & MCI_STATUS_PCC);
419 * If this error was uncorrectable and there was
420 * an overflow, we're in trouble. If no overflow,
421 * we might get away with just killing a task.
423 if (m.status & MCI_STATUS_UC) {
424 if (tolerant < 1 || m.status & MCI_STATUS_OVER)
430 * Machine check event was not enabled. Clear, but
436 if (m.status & MCI_STATUS_MISCV)
437 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
438 if (m.status & MCI_STATUS_ADDRV)
439 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
441 mce_get_rip(&m, regs);
445 * Did this bank cause the exception?
447 * Assume that the bank with uncorrectable errors did it,
448 * and that there is only a single one:
450 if ((m.status & MCI_STATUS_UC) &&
451 (m.status & MCI_STATUS_EN)) {
458 * If we didn't find an uncorrectable error, pick
459 * the last one (shouldn't happen, just being safe).
465 * If we have decided that we just CAN'T continue, and the user
466 * has not set tolerant to an insane level, give up and die.
468 if (no_way_out && tolerant < 3)
469 mce_panic("Machine check", &panicm, mcestart);
472 * If the error seems to be unrecoverable, something should be
473 * done. Try to kill as little as possible. If we can kill just
474 * one task, do that. If the user has set the tolerance very
475 * high, don't try to do anything at all.
477 if (kill_it && tolerant < 3) {
481 * If the EIPV bit is set, it means the saved IP is the
482 * instruction which caused the MCE.
484 if (m.mcgstatus & MCG_STATUS_EIPV)
485 user_space = panicm.ip && (panicm.cs & 3);
488 * If we know that the error was in user space, send a
489 * SIGBUS. Otherwise, panic if tolerance is low.
491 * force_sig() takes an awful lot of locks and has a slight
492 * risk of deadlocking.
495 force_sig(SIGBUS, current);
496 } else if (panic_on_oops || tolerant < 2) {
497 mce_panic("Uncorrected machine check",
502 /* notify userspace ASAP */
503 set_thread_flag(TIF_MCE_NOTIFY);
505 /* the last thing we do is clear state */
506 for (i = 0; i < banks; i++) {
507 if (test_bit(i, toclear))
508 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
510 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
512 atomic_dec(&mce_entry);
515 EXPORT_SYMBOL_GPL(do_machine_check);
517 #ifdef CONFIG_X86_MCE_INTEL
519 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
520 * @cpu: The CPU on which the event occurred.
521 * @status: Event status information
523 * This function should be called by the thermal interrupt after the
524 * event has been processed and the decision was made to log the event
527 * The status parameter will be saved to the 'status' field of 'struct mce'
528 * and historically has been the register value of the
529 * MSR_IA32_THERMAL_STATUS (Intel) msr.
531 void mce_log_therm_throt_event(__u64 status)
536 m.bank = MCE_THERMAL_BANK;
540 #endif /* CONFIG_X86_MCE_INTEL */
543 * Periodic polling timer for "silent" machine check errors. If the
544 * poller finds an MCE, poll 2x faster. When the poller finds no more
545 * errors, poll 2x slower (up to check_interval seconds).
547 static int check_interval = 5 * 60; /* 5 minutes */
549 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
550 static DEFINE_PER_CPU(struct timer_list, mce_timer);
552 static void mcheck_timer(unsigned long data)
554 struct timer_list *t = &per_cpu(mce_timer, data);
557 WARN_ON(smp_processor_id() != data);
559 if (mce_available(¤t_cpu_data)) {
560 machine_check_poll(MCP_TIMESTAMP,
561 &__get_cpu_var(mce_poll_banks));
565 * Alert userspace if needed. If we logged an MCE, reduce the
566 * polling interval, otherwise increase the polling interval.
568 n = &__get_cpu_var(next_interval);
569 if (mce_notify_user())
570 *n = max(*n/2, HZ/100);
572 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
574 t->expires = jiffies + *n;
578 static void mce_do_trigger(struct work_struct *work)
580 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
583 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
586 * Notify the user(s) about new machine check events.
587 * Can be called from interrupt context, but not from machine check/NMI
590 int mce_notify_user(void)
592 /* Not more than two messages every minute */
593 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
595 clear_thread_flag(TIF_MCE_NOTIFY);
597 if (test_and_clear_bit(0, ¬ify_user)) {
598 wake_up_interruptible(&mce_wait);
601 * There is no risk of missing notifications because
602 * work_pending is always cleared before the function is
605 if (trigger[0] && !work_pending(&mce_trigger_work))
606 schedule_work(&mce_trigger_work);
608 if (__ratelimit(&ratelimit))
609 printk(KERN_INFO "Machine check events logged\n");
615 EXPORT_SYMBOL_GPL(mce_notify_user);
618 * Initialize Machine Checks for a CPU.
620 static int mce_cap_init(void)
625 rdmsrl(MSR_IA32_MCG_CAP, cap);
627 b = cap & MCG_BANKCNT_MASK;
628 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
630 if (b > MAX_NR_BANKS) {
632 "MCE: Using only %u machine check banks out of %u\n",
637 /* Don't support asymmetric configurations today */
638 WARN_ON(banks != 0 && b != banks);
641 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
644 memset(bank, 0xff, banks * sizeof(u64));
647 /* Use accurate RIP reporting if available. */
648 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
649 rip_msr = MSR_IA32_MCG_EIP;
654 static void mce_init(void)
656 mce_banks_t all_banks;
661 * Log the machine checks left over from the previous reset.
663 bitmap_fill(all_banks, MAX_NR_BANKS);
664 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
666 set_in_cr4(X86_CR4_MCE);
668 rdmsrl(MSR_IA32_MCG_CAP, cap);
670 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
672 for (i = 0; i < banks; i++) {
673 if (skip_bank_init(i))
675 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
676 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
680 /* Add per CPU specific workarounds here */
681 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
683 /* This should be disabled by the BIOS, but isn't always */
684 if (c->x86_vendor == X86_VENDOR_AMD) {
685 if (c->x86 == 15 && banks > 4) {
687 * disable GART TBL walk error reporting, which
688 * trips off incorrectly with the IOMMU & 3ware
691 clear_bit(10, (unsigned long *)&bank[4]);
693 if (c->x86 <= 17 && mce_bootlog < 0) {
695 * Lots of broken BIOS around that don't clear them
696 * by default and leave crap in there. Don't log:
701 * Various K7s with broken bank 0 around. Always disable
708 if (c->x86_vendor == X86_VENDOR_INTEL) {
710 * SDM documents that on family 6 bank 0 should not be written
711 * because it aliases to another special BIOS controlled
713 * But it's not aliased anymore on model 0x1a+
714 * Don't ignore bank 0 completely because there could be a
715 * valid event later, merely don't write CTL0.
718 if (c->x86 == 6 && c->x86_model < 0x1A)
719 __set_bit(0, &dont_init_banks);
723 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
727 switch (c->x86_vendor) {
728 case X86_VENDOR_INTEL:
729 if (mce_p5_enabled())
730 intel_p5_mcheck_init(c);
732 case X86_VENDOR_CENTAUR:
733 winchip_mcheck_init(c);
738 static void mce_cpu_features(struct cpuinfo_x86 *c)
740 switch (c->x86_vendor) {
741 case X86_VENDOR_INTEL:
742 mce_intel_feature_init(c);
745 mce_amd_feature_init(c);
752 static void mce_init_timer(void)
754 struct timer_list *t = &__get_cpu_var(mce_timer);
755 int *n = &__get_cpu_var(next_interval);
757 *n = check_interval * HZ;
760 setup_timer(t, mcheck_timer, smp_processor_id());
761 t->expires = round_jiffies(jiffies + *n);
766 * Called for each booted CPU to set up machine checks.
767 * Must be called with preempt off:
769 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
776 if (!mce_available(c))
779 if (mce_cap_init() < 0) {
785 machine_check_vector = do_machine_check;
793 * Character device to read and clear the MCE log.
796 static DEFINE_SPINLOCK(mce_state_lock);
797 static int open_count; /* #times opened */
798 static int open_exclu; /* already open exclusive? */
800 static int mce_open(struct inode *inode, struct file *file)
802 spin_lock(&mce_state_lock);
804 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
805 spin_unlock(&mce_state_lock);
810 if (file->f_flags & O_EXCL)
814 spin_unlock(&mce_state_lock);
816 return nonseekable_open(inode, file);
819 static int mce_release(struct inode *inode, struct file *file)
821 spin_lock(&mce_state_lock);
826 spin_unlock(&mce_state_lock);
831 static void collect_tscs(void *data)
833 unsigned long *cpu_tsc = (unsigned long *)data;
835 rdtscll(cpu_tsc[smp_processor_id()]);
838 static DEFINE_MUTEX(mce_read_mutex);
840 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
843 char __user *buf = ubuf;
844 unsigned long *cpu_tsc;
848 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
852 mutex_lock(&mce_read_mutex);
853 next = rcu_dereference(mcelog.next);
855 /* Only supports full reads right now */
856 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
857 mutex_unlock(&mce_read_mutex);
866 for (i = prev; i < next; i++) {
867 unsigned long start = jiffies;
869 while (!mcelog.entry[i].finished) {
870 if (time_after_eq(jiffies, start + 2)) {
871 memset(mcelog.entry + i, 0,
878 err |= copy_to_user(buf, mcelog.entry + i,
880 buf += sizeof(struct mce);
885 memset(mcelog.entry + prev, 0,
886 (next - prev) * sizeof(struct mce));
888 next = cmpxchg(&mcelog.next, prev, 0);
889 } while (next != prev);
894 * Collect entries that were still getting written before the
897 on_each_cpu(collect_tscs, cpu_tsc, 1);
899 for (i = next; i < MCE_LOG_LEN; i++) {
900 if (mcelog.entry[i].finished &&
901 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
902 err |= copy_to_user(buf, mcelog.entry+i,
905 buf += sizeof(struct mce);
906 memset(&mcelog.entry[i], 0, sizeof(struct mce));
909 mutex_unlock(&mce_read_mutex);
912 return err ? -EFAULT : buf - ubuf;
915 static unsigned int mce_poll(struct file *file, poll_table *wait)
917 poll_wait(file, &mce_wait, wait);
918 if (rcu_dereference(mcelog.next))
919 return POLLIN | POLLRDNORM;
923 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
925 int __user *p = (int __user *)arg;
927 if (!capable(CAP_SYS_ADMIN))
931 case MCE_GET_RECORD_LEN:
932 return put_user(sizeof(struct mce), p);
933 case MCE_GET_LOG_LEN:
934 return put_user(MCE_LOG_LEN, p);
935 case MCE_GETCLEAR_FLAGS: {
939 flags = mcelog.flags;
940 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
942 return put_user(flags, p);
949 /* Modified in mce-inject.c, so not static or const */
950 struct file_operations mce_chrdev_ops = {
952 .release = mce_release,
955 .unlocked_ioctl = mce_ioctl,
957 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
959 static struct miscdevice mce_log_device = {
966 * mce=off disables machine check
967 * mce=TOLERANCELEVEL (number, see above)
968 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
969 * mce=nobootlog Don't log MCEs from before booting.
971 static int __init mcheck_enable(char *str)
977 if (!strcmp(str, "off"))
979 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
980 mce_bootlog = (str[0] == 'b');
981 else if (isdigit(str[0]))
982 get_option(&str, &tolerant);
984 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
990 __setup("mce", mcheck_enable);
997 * Disable machine checks on suspend and shutdown. We can't really handle
1000 static int mce_disable(void)
1004 for (i = 0; i < banks; i++) {
1005 if (!skip_bank_init(i))
1006 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1011 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1013 return mce_disable();
1016 static int mce_shutdown(struct sys_device *dev)
1018 return mce_disable();
1022 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1023 * Only one CPU is active at this time, the others get re-added later using
1026 static int mce_resume(struct sys_device *dev)
1029 mce_cpu_features(¤t_cpu_data);
1034 static void mce_cpu_restart(void *data)
1036 del_timer_sync(&__get_cpu_var(mce_timer));
1037 if (mce_available(¤t_cpu_data))
1042 /* Reinit MCEs after user configuration changes */
1043 static void mce_restart(void)
1045 on_each_cpu(mce_cpu_restart, NULL, 1);
1048 static struct sysdev_class mce_sysclass = {
1049 .suspend = mce_suspend,
1050 .shutdown = mce_shutdown,
1051 .resume = mce_resume,
1052 .name = "machinecheck",
1055 DEFINE_PER_CPU(struct sys_device, mce_dev);
1058 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1060 static struct sysdev_attribute *bank_attrs;
1062 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1065 u64 b = bank[attr - bank_attrs];
1067 return sprintf(buf, "%llx\n", b);
1070 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1071 const char *buf, size_t size)
1075 if (strict_strtoull(buf, 0, &new) < 0)
1078 bank[attr - bank_attrs] = new;
1085 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1087 strcpy(buf, trigger);
1089 return strlen(trigger) + 1;
1092 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1093 const char *buf, size_t siz)
1098 strncpy(trigger, buf, sizeof(trigger));
1099 trigger[sizeof(trigger)-1] = 0;
1100 len = strlen(trigger);
1101 p = strchr(trigger, '\n');
1109 static ssize_t store_int_with_restart(struct sys_device *s,
1110 struct sysdev_attribute *attr,
1111 const char *buf, size_t size)
1113 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1118 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1119 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1121 static struct sysdev_ext_attribute attr_check_interval = {
1122 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1123 store_int_with_restart),
1127 static struct sysdev_attribute *mce_attrs[] = {
1128 &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger,
1132 static cpumask_var_t mce_dev_initialized;
1134 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1135 static __cpuinit int mce_create_device(unsigned int cpu)
1140 if (!mce_available(&boot_cpu_data))
1143 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1144 per_cpu(mce_dev, cpu).id = cpu;
1145 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1147 err = sysdev_register(&per_cpu(mce_dev, cpu));
1151 for (i = 0; mce_attrs[i]; i++) {
1152 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1156 for (i = 0; i < banks; i++) {
1157 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1162 cpumask_set_cpu(cpu, mce_dev_initialized);
1167 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1170 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1172 sysdev_unregister(&per_cpu(mce_dev, cpu));
1177 static __cpuinit void mce_remove_device(unsigned int cpu)
1181 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1184 for (i = 0; mce_attrs[i]; i++)
1185 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1187 for (i = 0; i < banks; i++)
1188 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1190 sysdev_unregister(&per_cpu(mce_dev, cpu));
1191 cpumask_clear_cpu(cpu, mce_dev_initialized);
1194 /* Make sure there are no machine checks on offlined CPUs. */
1195 static void mce_disable_cpu(void *h)
1197 unsigned long action = *(unsigned long *)h;
1200 if (!mce_available(¤t_cpu_data))
1202 if (!(action & CPU_TASKS_FROZEN))
1204 for (i = 0; i < banks; i++) {
1205 if (!skip_bank_init(i))
1206 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1210 static void mce_reenable_cpu(void *h)
1212 unsigned long action = *(unsigned long *)h;
1215 if (!mce_available(¤t_cpu_data))
1218 if (!(action & CPU_TASKS_FROZEN))
1220 for (i = 0; i < banks; i++) {
1221 if (!skip_bank_init(i))
1222 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1226 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1227 static int __cpuinit
1228 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1230 unsigned int cpu = (unsigned long)hcpu;
1231 struct timer_list *t = &per_cpu(mce_timer, cpu);
1235 case CPU_ONLINE_FROZEN:
1236 mce_create_device(cpu);
1237 if (threshold_cpu_callback)
1238 threshold_cpu_callback(action, cpu);
1241 case CPU_DEAD_FROZEN:
1242 if (threshold_cpu_callback)
1243 threshold_cpu_callback(action, cpu);
1244 mce_remove_device(cpu);
1246 case CPU_DOWN_PREPARE:
1247 case CPU_DOWN_PREPARE_FROZEN:
1249 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1251 case CPU_DOWN_FAILED:
1252 case CPU_DOWN_FAILED_FROZEN:
1253 t->expires = round_jiffies(jiffies +
1254 __get_cpu_var(next_interval));
1255 add_timer_on(t, cpu);
1256 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1259 /* intentionally ignoring frozen here */
1260 cmci_rediscover(cpu);
1266 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1267 .notifier_call = mce_cpu_callback,
1270 static __init int mce_init_banks(void)
1274 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1279 for (i = 0; i < banks; i++) {
1280 struct sysdev_attribute *a = &bank_attrs[i];
1282 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1286 a->attr.mode = 0644;
1287 a->show = show_bank;
1288 a->store = set_bank;
1294 kfree(bank_attrs[i].attr.name);
1301 static __init int mce_init_device(void)
1306 if (!mce_available(&boot_cpu_data))
1309 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1311 err = mce_init_banks();
1315 err = sysdev_class_register(&mce_sysclass);
1319 for_each_online_cpu(i) {
1320 err = mce_create_device(i);
1325 register_hotcpu_notifier(&mce_cpu_notifier);
1326 misc_register(&mce_log_device);
1331 device_initcall(mce_init_device);
1333 #else /* CONFIG_X86_OLD_MCE: */
1336 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
1338 /* This has to be run for each processor */
1339 void mcheck_init(struct cpuinfo_x86 *c)
1341 if (mce_disabled == 1)
1344 switch (c->x86_vendor) {
1345 case X86_VENDOR_AMD:
1349 case X86_VENDOR_INTEL:
1351 intel_p5_mcheck_init(c);
1353 intel_p6_mcheck_init(c);
1355 intel_p4_mcheck_init(c);
1358 case X86_VENDOR_CENTAUR:
1360 winchip_mcheck_init(c);
1366 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
1369 static int __init mcheck_enable(char *str)
1375 __setup("mce", mcheck_enable);
1377 #endif /* CONFIG_X86_OLD_MCE */
1380 * Old style boot options parsing. Only for compatibility.
1382 static int __init mcheck_disable(char *str)
1387 __setup("nomce", mcheck_disable);