2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
29 #include <asm/stacktrace.h>
32 static u64 perf_event_mask __read_mostly;
34 /* The maximal number of PEBS events: */
35 #define MAX_PEBS_EVENTS 4
37 /* The size of a BTS record in bytes: */
38 #define BTS_RECORD_SIZE 24
40 /* The size of a per-cpu BTS buffer in bytes: */
41 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
43 /* The BTS overflow threshold in bytes from the end of the buffer: */
44 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
48 * Bits in the debugctlmsr controlling branch tracing.
50 #define X86_DEBUGCTL_TR (1 << 6)
51 #define X86_DEBUGCTL_BTS (1 << 7)
52 #define X86_DEBUGCTL_BTINT (1 << 8)
53 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
54 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
57 * A debug store configuration.
59 * We only support architectures that use 64bit fields.
64 u64 bts_absolute_maximum;
65 u64 bts_interrupt_threshold;
68 u64 pebs_absolute_maximum;
69 u64 pebs_interrupt_threshold;
70 u64 pebs_event_reset[MAX_PEBS_EVENTS];
73 struct event_constraint {
75 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
83 struct cpu_hw_events {
84 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
85 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
86 unsigned long interrupts;
88 struct debug_store *ds;
92 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
93 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
96 #define EVENT_CONSTRAINT(c, n, m) { \
97 { .idxmsk64[0] = (n) }, \
100 .weight = HWEIGHT64((u64)(n)), \
103 #define INTEL_EVENT_CONSTRAINT(c, n) \
104 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
106 #define FIXED_EVENT_CONSTRAINT(c, n) \
107 EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK)
109 #define EVENT_CONSTRAINT_END \
110 EVENT_CONSTRAINT(0, 0, 0)
112 #define for_each_event_constraint(e, c) \
113 for ((e) = (c); (e)->cmask; (e)++)
116 * struct x86_pmu - generic x86 pmu
121 int (*handle_irq)(struct pt_regs *);
122 void (*disable_all)(void);
123 void (*enable_all)(void);
124 void (*enable)(struct hw_perf_event *, int);
125 void (*disable)(struct hw_perf_event *, int);
128 u64 (*event_map)(int);
129 u64 (*raw_event)(u64);
132 int num_events_fixed;
138 void (*enable_bts)(u64 config);
139 void (*disable_bts)(void);
141 struct event_constraint *
142 (*get_event_constraints)(struct cpu_hw_events *cpuc,
143 struct perf_event *event);
145 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
146 struct perf_event *event);
147 struct event_constraint *event_constraints;
150 static struct x86_pmu x86_pmu __read_mostly;
152 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
156 static int x86_perf_event_set_period(struct perf_event *event,
157 struct hw_perf_event *hwc, int idx);
160 * Not sure about some of these
162 static const u64 p6_perfmon_event_map[] =
164 [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
165 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
166 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
167 [PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
168 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
169 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
170 [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
173 static u64 p6_pmu_event_map(int hw_event)
175 return p6_perfmon_event_map[hw_event];
179 * Event setting that is specified not to count anything.
180 * We use this to effectively disable a counter.
182 * L2_RQSTS with 0 MESI unit mask.
184 #define P6_NOP_EVENT 0x0000002EULL
186 static u64 p6_pmu_raw_event(u64 hw_event)
188 #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
189 #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
190 #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
191 #define P6_EVNTSEL_INV_MASK 0x00800000ULL
192 #define P6_EVNTSEL_REG_MASK 0xFF000000ULL
194 #define P6_EVNTSEL_MASK \
195 (P6_EVNTSEL_EVENT_MASK | \
196 P6_EVNTSEL_UNIT_MASK | \
197 P6_EVNTSEL_EDGE_MASK | \
198 P6_EVNTSEL_INV_MASK | \
201 return hw_event & P6_EVNTSEL_MASK;
204 static struct event_constraint intel_p6_event_constraints[] =
206 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
207 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
208 INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
209 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
210 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
211 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
216 * Intel PerfMon v3. Used on Core2 and later.
218 static const u64 intel_perfmon_event_map[] =
220 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
221 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
222 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
223 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
224 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
225 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
226 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
229 static struct event_constraint intel_core_event_constraints[] =
231 FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
232 FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
233 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
234 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
235 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
236 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
237 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
238 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
239 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
240 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
241 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
245 static struct event_constraint intel_nehalem_event_constraints[] =
247 FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
248 FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
249 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
250 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
251 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
252 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
253 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
254 INTEL_EVENT_CONSTRAINT(0x4c, 0x3), /* LOAD_HIT_PRE */
255 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
256 INTEL_EVENT_CONSTRAINT(0x52, 0x3), /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
257 INTEL_EVENT_CONSTRAINT(0x53, 0x3), /* L1D_CACHE_LOCK_FB_HIT */
258 INTEL_EVENT_CONSTRAINT(0xc5, 0x3), /* CACHE_LOCK_CYCLES */
262 static struct event_constraint intel_gen_event_constraints[] =
264 FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
265 FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
269 static u64 intel_pmu_event_map(int hw_event)
271 return intel_perfmon_event_map[hw_event];
275 * Generalized hw caching related hw_event table, filled
276 * in on a per model basis. A value of 0 means
277 * 'not supported', -1 means 'hw_event makes no sense on
278 * this CPU', any other value means the raw hw_event
282 #define C(x) PERF_COUNT_HW_CACHE_##x
284 static u64 __read_mostly hw_cache_event_ids
285 [PERF_COUNT_HW_CACHE_MAX]
286 [PERF_COUNT_HW_CACHE_OP_MAX]
287 [PERF_COUNT_HW_CACHE_RESULT_MAX];
289 static __initconst u64 nehalem_hw_cache_event_ids
290 [PERF_COUNT_HW_CACHE_MAX]
291 [PERF_COUNT_HW_CACHE_OP_MAX]
292 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
296 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
297 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
300 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
301 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
303 [ C(OP_PREFETCH) ] = {
304 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
305 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
310 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
311 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
314 [ C(RESULT_ACCESS) ] = -1,
315 [ C(RESULT_MISS) ] = -1,
317 [ C(OP_PREFETCH) ] = {
318 [ C(RESULT_ACCESS) ] = 0x0,
319 [ C(RESULT_MISS) ] = 0x0,
324 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
325 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
328 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
329 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
331 [ C(OP_PREFETCH) ] = {
332 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
333 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
338 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
339 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
342 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
343 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
345 [ C(OP_PREFETCH) ] = {
346 [ C(RESULT_ACCESS) ] = 0x0,
347 [ C(RESULT_MISS) ] = 0x0,
352 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
353 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
356 [ C(RESULT_ACCESS) ] = -1,
357 [ C(RESULT_MISS) ] = -1,
359 [ C(OP_PREFETCH) ] = {
360 [ C(RESULT_ACCESS) ] = -1,
361 [ C(RESULT_MISS) ] = -1,
366 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
367 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
370 [ C(RESULT_ACCESS) ] = -1,
371 [ C(RESULT_MISS) ] = -1,
373 [ C(OP_PREFETCH) ] = {
374 [ C(RESULT_ACCESS) ] = -1,
375 [ C(RESULT_MISS) ] = -1,
380 static __initconst u64 core2_hw_cache_event_ids
381 [PERF_COUNT_HW_CACHE_MAX]
382 [PERF_COUNT_HW_CACHE_OP_MAX]
383 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
387 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
388 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
391 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
392 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
394 [ C(OP_PREFETCH) ] = {
395 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
396 [ C(RESULT_MISS) ] = 0,
401 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
402 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
405 [ C(RESULT_ACCESS) ] = -1,
406 [ C(RESULT_MISS) ] = -1,
408 [ C(OP_PREFETCH) ] = {
409 [ C(RESULT_ACCESS) ] = 0,
410 [ C(RESULT_MISS) ] = 0,
415 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
416 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
419 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
420 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
422 [ C(OP_PREFETCH) ] = {
423 [ C(RESULT_ACCESS) ] = 0,
424 [ C(RESULT_MISS) ] = 0,
429 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
430 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
433 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
434 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
436 [ C(OP_PREFETCH) ] = {
437 [ C(RESULT_ACCESS) ] = 0,
438 [ C(RESULT_MISS) ] = 0,
443 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
444 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
447 [ C(RESULT_ACCESS) ] = -1,
448 [ C(RESULT_MISS) ] = -1,
450 [ C(OP_PREFETCH) ] = {
451 [ C(RESULT_ACCESS) ] = -1,
452 [ C(RESULT_MISS) ] = -1,
457 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
458 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
461 [ C(RESULT_ACCESS) ] = -1,
462 [ C(RESULT_MISS) ] = -1,
464 [ C(OP_PREFETCH) ] = {
465 [ C(RESULT_ACCESS) ] = -1,
466 [ C(RESULT_MISS) ] = -1,
471 static __initconst u64 atom_hw_cache_event_ids
472 [PERF_COUNT_HW_CACHE_MAX]
473 [PERF_COUNT_HW_CACHE_OP_MAX]
474 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
478 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
479 [ C(RESULT_MISS) ] = 0,
482 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
483 [ C(RESULT_MISS) ] = 0,
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = 0x0,
487 [ C(RESULT_MISS) ] = 0,
492 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
493 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = 0,
501 [ C(RESULT_MISS) ] = 0,
506 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
507 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
510 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
511 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = 0,
515 [ C(RESULT_MISS) ] = 0,
520 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
521 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
524 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
525 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0,
529 [ C(RESULT_MISS) ] = 0,
534 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
535 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
538 [ C(RESULT_ACCESS) ] = -1,
539 [ C(RESULT_MISS) ] = -1,
541 [ C(OP_PREFETCH) ] = {
542 [ C(RESULT_ACCESS) ] = -1,
543 [ C(RESULT_MISS) ] = -1,
548 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
549 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
552 [ C(RESULT_ACCESS) ] = -1,
553 [ C(RESULT_MISS) ] = -1,
555 [ C(OP_PREFETCH) ] = {
556 [ C(RESULT_ACCESS) ] = -1,
557 [ C(RESULT_MISS) ] = -1,
562 static u64 intel_pmu_raw_event(u64 hw_event)
564 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
565 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
566 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
567 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
568 #define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
570 #define CORE_EVNTSEL_MASK \
571 (INTEL_ARCH_EVTSEL_MASK | \
572 INTEL_ARCH_UNIT_MASK | \
573 INTEL_ARCH_EDGE_MASK | \
574 INTEL_ARCH_INV_MASK | \
577 return hw_event & CORE_EVNTSEL_MASK;
580 static __initconst u64 amd_hw_cache_event_ids
581 [PERF_COUNT_HW_CACHE_MAX]
582 [PERF_COUNT_HW_CACHE_OP_MAX]
583 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
587 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
588 [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
591 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
592 [ C(RESULT_MISS) ] = 0,
594 [ C(OP_PREFETCH) ] = {
595 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
596 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
601 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
602 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
605 [ C(RESULT_ACCESS) ] = -1,
606 [ C(RESULT_MISS) ] = -1,
608 [ C(OP_PREFETCH) ] = {
609 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
610 [ C(RESULT_MISS) ] = 0,
615 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
616 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
619 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
620 [ C(RESULT_MISS) ] = 0,
622 [ C(OP_PREFETCH) ] = {
623 [ C(RESULT_ACCESS) ] = 0,
624 [ C(RESULT_MISS) ] = 0,
629 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
630 [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
633 [ C(RESULT_ACCESS) ] = 0,
634 [ C(RESULT_MISS) ] = 0,
636 [ C(OP_PREFETCH) ] = {
637 [ C(RESULT_ACCESS) ] = 0,
638 [ C(RESULT_MISS) ] = 0,
643 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
644 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
647 [ C(RESULT_ACCESS) ] = -1,
648 [ C(RESULT_MISS) ] = -1,
650 [ C(OP_PREFETCH) ] = {
651 [ C(RESULT_ACCESS) ] = -1,
652 [ C(RESULT_MISS) ] = -1,
657 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
658 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
661 [ C(RESULT_ACCESS) ] = -1,
662 [ C(RESULT_MISS) ] = -1,
664 [ C(OP_PREFETCH) ] = {
665 [ C(RESULT_ACCESS) ] = -1,
666 [ C(RESULT_MISS) ] = -1,
672 * AMD Performance Monitor K7 and later.
674 static const u64 amd_perfmon_event_map[] =
676 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
677 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
678 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
679 [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
680 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
681 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
684 static u64 amd_pmu_event_map(int hw_event)
686 return amd_perfmon_event_map[hw_event];
689 static u64 amd_pmu_raw_event(u64 hw_event)
691 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
692 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
693 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
694 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
695 #define K7_EVNTSEL_REG_MASK 0x0FF000000ULL
697 #define K7_EVNTSEL_MASK \
698 (K7_EVNTSEL_EVENT_MASK | \
699 K7_EVNTSEL_UNIT_MASK | \
700 K7_EVNTSEL_EDGE_MASK | \
701 K7_EVNTSEL_INV_MASK | \
704 return hw_event & K7_EVNTSEL_MASK;
708 * Propagate event elapsed time into the generic event.
709 * Can only be executed on the CPU where the event is active.
710 * Returns the delta events processed.
713 x86_perf_event_update(struct perf_event *event,
714 struct hw_perf_event *hwc, int idx)
716 int shift = 64 - x86_pmu.event_bits;
717 u64 prev_raw_count, new_raw_count;
720 if (idx == X86_PMC_IDX_FIXED_BTS)
724 * Careful: an NMI might modify the previous event value.
726 * Our tactic to handle this is to first atomically read and
727 * exchange a new raw count - then add that new-prev delta
728 * count to the generic event atomically:
731 prev_raw_count = atomic64_read(&hwc->prev_count);
732 rdmsrl(hwc->event_base + idx, new_raw_count);
734 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
735 new_raw_count) != prev_raw_count)
739 * Now we have the new raw value and have updated the prev
740 * timestamp already. We can now calculate the elapsed delta
741 * (event-)time and add that to the generic event.
743 * Careful, not all hw sign-extends above the physical width
746 delta = (new_raw_count << shift) - (prev_raw_count << shift);
749 atomic64_add(delta, &event->count);
750 atomic64_sub(delta, &hwc->period_left);
752 return new_raw_count;
755 static atomic_t active_events;
756 static DEFINE_MUTEX(pmc_reserve_mutex);
758 static bool reserve_pmc_hardware(void)
760 #ifdef CONFIG_X86_LOCAL_APIC
763 if (nmi_watchdog == NMI_LOCAL_APIC)
764 disable_lapic_nmi_watchdog();
766 for (i = 0; i < x86_pmu.num_events; i++) {
767 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
771 for (i = 0; i < x86_pmu.num_events; i++) {
772 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
779 #ifdef CONFIG_X86_LOCAL_APIC
781 for (i--; i >= 0; i--)
782 release_evntsel_nmi(x86_pmu.eventsel + i);
784 i = x86_pmu.num_events;
787 for (i--; i >= 0; i--)
788 release_perfctr_nmi(x86_pmu.perfctr + i);
790 if (nmi_watchdog == NMI_LOCAL_APIC)
791 enable_lapic_nmi_watchdog();
797 static void release_pmc_hardware(void)
799 #ifdef CONFIG_X86_LOCAL_APIC
802 for (i = 0; i < x86_pmu.num_events; i++) {
803 release_perfctr_nmi(x86_pmu.perfctr + i);
804 release_evntsel_nmi(x86_pmu.eventsel + i);
807 if (nmi_watchdog == NMI_LOCAL_APIC)
808 enable_lapic_nmi_watchdog();
812 static inline bool bts_available(void)
814 return x86_pmu.enable_bts != NULL;
817 static inline void init_debug_store_on_cpu(int cpu)
819 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
824 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
825 (u32)((u64)(unsigned long)ds),
826 (u32)((u64)(unsigned long)ds >> 32));
829 static inline void fini_debug_store_on_cpu(int cpu)
831 if (!per_cpu(cpu_hw_events, cpu).ds)
834 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
837 static void release_bts_hardware(void)
841 if (!bts_available())
846 for_each_online_cpu(cpu)
847 fini_debug_store_on_cpu(cpu);
849 for_each_possible_cpu(cpu) {
850 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
855 per_cpu(cpu_hw_events, cpu).ds = NULL;
857 kfree((void *)(unsigned long)ds->bts_buffer_base);
864 static int reserve_bts_hardware(void)
868 if (!bts_available())
873 for_each_possible_cpu(cpu) {
874 struct debug_store *ds;
878 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
879 if (unlikely(!buffer))
882 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
888 ds->bts_buffer_base = (u64)(unsigned long)buffer;
889 ds->bts_index = ds->bts_buffer_base;
890 ds->bts_absolute_maximum =
891 ds->bts_buffer_base + BTS_BUFFER_SIZE;
892 ds->bts_interrupt_threshold =
893 ds->bts_absolute_maximum - BTS_OVFL_TH;
895 per_cpu(cpu_hw_events, cpu).ds = ds;
900 release_bts_hardware();
902 for_each_online_cpu(cpu)
903 init_debug_store_on_cpu(cpu);
911 static void hw_perf_event_destroy(struct perf_event *event)
913 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
914 release_pmc_hardware();
915 release_bts_hardware();
916 mutex_unlock(&pmc_reserve_mutex);
920 static inline int x86_pmu_initialized(void)
922 return x86_pmu.handle_irq != NULL;
926 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
928 unsigned int cache_type, cache_op, cache_result;
931 config = attr->config;
933 cache_type = (config >> 0) & 0xff;
934 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
937 cache_op = (config >> 8) & 0xff;
938 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
941 cache_result = (config >> 16) & 0xff;
942 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
945 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
958 static void intel_pmu_enable_bts(u64 config)
960 unsigned long debugctlmsr;
962 debugctlmsr = get_debugctlmsr();
964 debugctlmsr |= X86_DEBUGCTL_TR;
965 debugctlmsr |= X86_DEBUGCTL_BTS;
966 debugctlmsr |= X86_DEBUGCTL_BTINT;
968 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
969 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
971 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
972 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
974 update_debugctlmsr(debugctlmsr);
977 static void intel_pmu_disable_bts(void)
979 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
980 unsigned long debugctlmsr;
985 debugctlmsr = get_debugctlmsr();
988 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
989 X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
991 update_debugctlmsr(debugctlmsr);
995 * Setup the hardware configuration for a given attr_type
997 static int __hw_perf_event_init(struct perf_event *event)
999 struct perf_event_attr *attr = &event->attr;
1000 struct hw_perf_event *hwc = &event->hw;
1004 if (!x86_pmu_initialized())
1008 if (!atomic_inc_not_zero(&active_events)) {
1009 mutex_lock(&pmc_reserve_mutex);
1010 if (atomic_read(&active_events) == 0) {
1011 if (!reserve_pmc_hardware())
1014 err = reserve_bts_hardware();
1017 atomic_inc(&active_events);
1018 mutex_unlock(&pmc_reserve_mutex);
1023 event->destroy = hw_perf_event_destroy;
1026 * Generate PMC IRQs:
1027 * (keep 'enabled' bit clear for now)
1029 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
1034 * Count user and OS events unless requested not to.
1036 if (!attr->exclude_user)
1037 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
1038 if (!attr->exclude_kernel)
1039 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
1041 if (!hwc->sample_period) {
1042 hwc->sample_period = x86_pmu.max_period;
1043 hwc->last_period = hwc->sample_period;
1044 atomic64_set(&hwc->period_left, hwc->sample_period);
1047 * If we have a PMU initialized but no APIC
1048 * interrupts, we cannot sample hardware
1049 * events (user-space has to fall back and
1050 * sample via a hrtimer based software event):
1057 * Raw hw_event type provide the config in the hw_event structure
1059 if (attr->type == PERF_TYPE_RAW) {
1060 hwc->config |= x86_pmu.raw_event(attr->config);
1064 if (attr->type == PERF_TYPE_HW_CACHE)
1065 return set_ext_hw_attr(hwc, attr);
1067 if (attr->config >= x86_pmu.max_events)
1073 config = x86_pmu.event_map(attr->config);
1084 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
1085 (hwc->sample_period == 1)) {
1086 /* BTS is not supported by this architecture. */
1087 if (!bts_available())
1090 /* BTS is currently only allowed for user-mode. */
1091 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1095 hwc->config |= config;
1100 static void p6_pmu_disable_all(void)
1102 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1111 /* p6 only has one enable register */
1112 rdmsrl(MSR_P6_EVNTSEL0, val);
1113 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1114 wrmsrl(MSR_P6_EVNTSEL0, val);
1117 static void intel_pmu_disable_all(void)
1119 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1127 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1129 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1130 intel_pmu_disable_bts();
1133 static void amd_pmu_disable_all(void)
1135 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1143 * ensure we write the disable before we start disabling the
1144 * events proper, so that amd_pmu_enable_event() does the
1149 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1152 if (!test_bit(idx, cpuc->active_mask))
1154 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
1155 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
1157 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1158 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1162 void hw_perf_disable(void)
1164 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1166 if (!x86_pmu_initialized())
1172 x86_pmu.disable_all();
1175 static void p6_pmu_enable_all(void)
1177 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1186 /* p6 only has one enable register */
1187 rdmsrl(MSR_P6_EVNTSEL0, val);
1188 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1189 wrmsrl(MSR_P6_EVNTSEL0, val);
1192 static void intel_pmu_enable_all(void)
1194 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1202 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1204 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1205 struct perf_event *event =
1206 cpuc->events[X86_PMC_IDX_FIXED_BTS];
1208 if (WARN_ON_ONCE(!event))
1211 intel_pmu_enable_bts(event->hw.config);
1215 static void amd_pmu_enable_all(void)
1217 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1226 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1227 struct perf_event *event = cpuc->events[idx];
1230 if (!test_bit(idx, cpuc->active_mask))
1233 val = event->hw.config;
1234 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1235 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1239 static const struct pmu pmu;
1241 static inline int is_x86_event(struct perf_event *event)
1243 return event->pmu == &pmu;
1246 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1248 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
1249 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1250 int i, j, w, wmax, num = 0;
1251 struct hw_perf_event *hwc;
1253 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1255 for (i = 0; i < n; i++) {
1257 x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
1261 * fastpath, try to reuse previous register
1263 for (i = 0; i < n; i++) {
1264 hwc = &cpuc->event_list[i]->hw;
1267 /* never assigned */
1271 /* constraint still honored */
1272 if (!test_bit(hwc->idx, c->idxmsk))
1275 /* not already used */
1276 if (test_bit(hwc->idx, used_mask))
1280 pr_debug("CPU%d fast config=0x%llx idx=%d assign=%c\n",
1284 assign ? 'y' : 'n');
1287 set_bit(hwc->idx, used_mask);
1289 assign[i] = hwc->idx;
1298 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1301 * weight = number of possible counters
1303 * 1 = most constrained, only works on one counter
1304 * wmax = least constrained, works on any counter
1306 * assign events to counters starting with most
1307 * constrained events.
1309 wmax = x86_pmu.num_events;
1312 * when fixed event counters are present,
1313 * wmax is incremented by 1 to account
1314 * for one more choice
1316 if (x86_pmu.num_events_fixed)
1319 for (w = 1, num = n; num && w <= wmax; w++) {
1320 /* for each event */
1321 for (i = 0; num && i < n; i++) {
1323 hwc = &cpuc->event_list[i]->hw;
1328 for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
1329 if (!test_bit(j, used_mask))
1333 if (j == X86_PMC_IDX_MAX)
1337 pr_debug("CPU%d slow config=0x%llx idx=%d assign=%c\n",
1341 assign ? 'y' : 'n');
1344 set_bit(j, used_mask);
1353 * scheduling failed or is just a simulation,
1354 * free resources if necessary
1356 if (!assign || num) {
1357 for (i = 0; i < n; i++) {
1358 if (x86_pmu.put_event_constraints)
1359 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
1362 return num ? -ENOSPC : 0;
1366 * dogrp: true if must collect siblings events (group)
1367 * returns total number of events and error code
1369 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1371 struct perf_event *event;
1374 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
1376 /* current number of events already accepted */
1379 if (is_x86_event(leader)) {
1382 cpuc->event_list[n] = leader;
1388 list_for_each_entry(event, &leader->sibling_list, group_entry) {
1389 if (!is_x86_event(event) ||
1390 event->state <= PERF_EVENT_STATE_OFF)
1396 cpuc->event_list[n] = event;
1403 static inline void x86_assign_hw_event(struct perf_event *event,
1404 struct hw_perf_event *hwc, int idx)
1408 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
1409 hwc->config_base = 0;
1410 hwc->event_base = 0;
1411 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
1412 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1414 * We set it so that event_base + idx in wrmsr/rdmsr maps to
1415 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1418 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1420 hwc->config_base = x86_pmu.eventsel;
1421 hwc->event_base = x86_pmu.perfctr;
1425 void hw_perf_enable(void)
1427 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1428 struct perf_event *event;
1429 struct hw_perf_event *hwc;
1432 if (!x86_pmu_initialized())
1434 if (cpuc->n_added) {
1436 * apply assignment obtained either from
1437 * hw_perf_group_sched_in() or x86_pmu_enable()
1439 * step1: save events moving to new counters
1440 * step2: reprogram moved events into new counters
1442 for (i = 0; i < cpuc->n_events; i++) {
1444 event = cpuc->event_list[i];
1447 if (hwc->idx == -1 || hwc->idx == cpuc->assign[i])
1450 x86_pmu.disable(hwc, hwc->idx);
1452 clear_bit(hwc->idx, cpuc->active_mask);
1454 cpuc->events[hwc->idx] = NULL;
1456 x86_perf_event_update(event, hwc, hwc->idx);
1461 for (i = 0; i < cpuc->n_events; i++) {
1463 event = cpuc->event_list[i];
1466 if (hwc->idx == -1) {
1467 x86_assign_hw_event(event, hwc, cpuc->assign[i]);
1468 x86_perf_event_set_period(event, hwc, hwc->idx);
1471 * need to mark as active because x86_pmu_disable()
1472 * clear active_mask and eventsp[] yet it preserves
1475 set_bit(hwc->idx, cpuc->active_mask);
1476 cpuc->events[hwc->idx] = event;
1478 x86_pmu.enable(hwc, hwc->idx);
1479 perf_event_update_userpage(event);
1482 perf_events_lapic_init();
1484 x86_pmu.enable_all();
1487 static inline u64 intel_pmu_get_status(void)
1491 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1496 static inline void intel_pmu_ack_status(u64 ack)
1498 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1501 static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1503 (void)checking_wrmsrl(hwc->config_base + idx,
1504 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
1507 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1509 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
1513 intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
1515 int idx = __idx - X86_PMC_IDX_FIXED;
1518 mask = 0xfULL << (idx * 4);
1520 rdmsrl(hwc->config_base, ctrl_val);
1522 (void)checking_wrmsrl(hwc->config_base, ctrl_val);
1526 p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1528 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1529 u64 val = P6_NOP_EVENT;
1532 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1534 (void)checking_wrmsrl(hwc->config_base + idx, val);
1538 intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1540 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1541 intel_pmu_disable_bts();
1545 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1546 intel_pmu_disable_fixed(hwc, idx);
1550 x86_pmu_disable_event(hwc, idx);
1554 amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1556 x86_pmu_disable_event(hwc, idx);
1559 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1562 * Set the next IRQ period, based on the hwc->period_left value.
1563 * To be called with the event disabled in hw:
1566 x86_perf_event_set_period(struct perf_event *event,
1567 struct hw_perf_event *hwc, int idx)
1569 s64 left = atomic64_read(&hwc->period_left);
1570 s64 period = hwc->sample_period;
1573 if (idx == X86_PMC_IDX_FIXED_BTS)
1577 * If we are way outside a reasonable range then just skip forward:
1579 if (unlikely(left <= -period)) {
1581 atomic64_set(&hwc->period_left, left);
1582 hwc->last_period = period;
1586 if (unlikely(left <= 0)) {
1588 atomic64_set(&hwc->period_left, left);
1589 hwc->last_period = period;
1593 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1595 if (unlikely(left < 2))
1598 if (left > x86_pmu.max_period)
1599 left = x86_pmu.max_period;
1601 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1604 * The hw event starts counting from this event offset,
1605 * mark it to be able to extra future deltas:
1607 atomic64_set(&hwc->prev_count, (u64)-left);
1609 err = checking_wrmsrl(hwc->event_base + idx,
1610 (u64)(-left) & x86_pmu.event_mask);
1612 perf_event_update_userpage(event);
1618 intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
1620 int idx = __idx - X86_PMC_IDX_FIXED;
1621 u64 ctrl_val, bits, mask;
1625 * Enable IRQ generation (0x8),
1626 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1630 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1632 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1635 mask = 0xfULL << (idx * 4);
1637 rdmsrl(hwc->config_base, ctrl_val);
1640 err = checking_wrmsrl(hwc->config_base, ctrl_val);
1643 static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1645 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1650 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1652 (void)checking_wrmsrl(hwc->config_base + idx, val);
1656 static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1658 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1659 if (!__get_cpu_var(cpu_hw_events).enabled)
1662 intel_pmu_enable_bts(hwc->config);
1666 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1667 intel_pmu_enable_fixed(hwc, idx);
1671 x86_pmu_enable_event(hwc, idx);
1674 static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1676 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1679 x86_pmu_enable_event(hwc, idx);
1683 * activate a single event
1685 * The event is added to the group of enabled events
1686 * but only if it can be scehduled with existing events.
1688 * Called with PMU disabled. If successful and return value 1,
1689 * then guaranteed to call perf_enable() and hw_perf_enable()
1691 static int x86_pmu_enable(struct perf_event *event)
1693 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1694 struct hw_perf_event *hwc;
1695 int assign[X86_PMC_IDX_MAX];
1700 n0 = cpuc->n_events;
1701 n = collect_events(cpuc, event, false);
1705 ret = x86_schedule_events(cpuc, n, assign);
1709 * copy new assignment, now we know it is possible
1710 * will be used by hw_perf_enable()
1712 memcpy(cpuc->assign, assign, n*sizeof(int));
1715 cpuc->n_added = n - n0;
1718 x86_perf_event_set_period(event, hwc, hwc->idx);
1723 static void x86_pmu_unthrottle(struct perf_event *event)
1725 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1726 struct hw_perf_event *hwc = &event->hw;
1728 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1729 cpuc->events[hwc->idx] != event))
1732 x86_pmu.enable(hwc, hwc->idx);
1735 void perf_event_print_debug(void)
1737 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1738 struct cpu_hw_events *cpuc;
1739 unsigned long flags;
1742 if (!x86_pmu.num_events)
1745 local_irq_save(flags);
1747 cpu = smp_processor_id();
1748 cpuc = &per_cpu(cpu_hw_events, cpu);
1750 if (x86_pmu.version >= 2) {
1751 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1752 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1753 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1754 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1757 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1758 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1759 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1760 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1762 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1764 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1765 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1766 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1768 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1770 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1771 cpu, idx, pmc_ctrl);
1772 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1773 cpu, idx, pmc_count);
1774 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1775 cpu, idx, prev_left);
1777 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1778 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1780 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1781 cpu, idx, pmc_count);
1783 local_irq_restore(flags);
1786 static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
1788 struct debug_store *ds = cpuc->ds;
1794 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
1795 struct bts_record *at, *top;
1796 struct perf_output_handle handle;
1797 struct perf_event_header header;
1798 struct perf_sample_data data;
1799 struct pt_regs regs;
1807 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
1808 top = (struct bts_record *)(unsigned long)ds->bts_index;
1813 ds->bts_index = ds->bts_buffer_base;
1816 data.period = event->hw.last_period;
1822 * Prepare a generic sample, i.e. fill in the invariant fields.
1823 * We will overwrite the from and to address before we output
1826 perf_prepare_sample(&header, &data, event, ®s);
1828 if (perf_output_begin(&handle, event,
1829 header.size * (top - at), 1, 1))
1832 for (; at < top; at++) {
1836 perf_output_sample(&handle, &header, &data, event);
1839 perf_output_end(&handle);
1841 /* There's new data available. */
1842 event->hw.interrupts++;
1843 event->pending_kill = POLL_IN;
1846 static void x86_pmu_disable(struct perf_event *event)
1848 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1849 struct hw_perf_event *hwc = &event->hw;
1850 int i, idx = hwc->idx;
1853 * Must be done before we disable, otherwise the nmi handler
1854 * could reenable again:
1856 clear_bit(idx, cpuc->active_mask);
1857 x86_pmu.disable(hwc, idx);
1860 * Make sure the cleared pointer becomes visible before we
1861 * (potentially) free the event:
1866 * Drain the remaining delta count out of a event
1867 * that we are disabling:
1869 x86_perf_event_update(event, hwc, idx);
1871 /* Drain the remaining BTS records. */
1872 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
1873 intel_pmu_drain_bts_buffer(cpuc);
1875 cpuc->events[idx] = NULL;
1877 for (i = 0; i < cpuc->n_events; i++) {
1878 if (event == cpuc->event_list[i]) {
1880 if (x86_pmu.put_event_constraints)
1881 x86_pmu.put_event_constraints(cpuc, event);
1883 while (++i < cpuc->n_events)
1884 cpuc->event_list[i-1] = cpuc->event_list[i];
1889 perf_event_update_userpage(event);
1893 * Save and restart an expired event. Called by NMI contexts,
1894 * so it has to be careful about preempting normal event ops:
1896 static int intel_pmu_save_and_restart(struct perf_event *event)
1898 struct hw_perf_event *hwc = &event->hw;
1902 x86_perf_event_update(event, hwc, idx);
1903 ret = x86_perf_event_set_period(event, hwc, idx);
1905 if (event->state == PERF_EVENT_STATE_ACTIVE)
1906 intel_pmu_enable_event(hwc, idx);
1911 static void intel_pmu_reset(void)
1913 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
1914 unsigned long flags;
1917 if (!x86_pmu.num_events)
1920 local_irq_save(flags);
1922 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1924 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1925 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1926 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1928 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1929 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1932 ds->bts_index = ds->bts_buffer_base;
1934 local_irq_restore(flags);
1937 static int p6_pmu_handle_irq(struct pt_regs *regs)
1939 struct perf_sample_data data;
1940 struct cpu_hw_events *cpuc;
1941 struct perf_event *event;
1942 struct hw_perf_event *hwc;
1943 int idx, handled = 0;
1949 cpuc = &__get_cpu_var(cpu_hw_events);
1951 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1952 if (!test_bit(idx, cpuc->active_mask))
1955 event = cpuc->events[idx];
1958 val = x86_perf_event_update(event, hwc, idx);
1959 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1966 data.period = event->hw.last_period;
1968 if (!x86_perf_event_set_period(event, hwc, idx))
1971 if (perf_event_overflow(event, 1, &data, regs))
1972 p6_pmu_disable_event(hwc, idx);
1976 inc_irq_stat(apic_perf_irqs);
1982 * This handler is triggered by the local APIC, so the APIC IRQ handling
1985 static int intel_pmu_handle_irq(struct pt_regs *regs)
1987 struct perf_sample_data data;
1988 struct cpu_hw_events *cpuc;
1995 cpuc = &__get_cpu_var(cpu_hw_events);
1998 intel_pmu_drain_bts_buffer(cpuc);
1999 status = intel_pmu_get_status();
2007 if (++loops > 100) {
2008 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
2009 perf_event_print_debug();
2015 inc_irq_stat(apic_perf_irqs);
2017 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2018 struct perf_event *event = cpuc->events[bit];
2020 clear_bit(bit, (unsigned long *) &status);
2021 if (!test_bit(bit, cpuc->active_mask))
2024 if (!intel_pmu_save_and_restart(event))
2027 data.period = event->hw.last_period;
2029 if (perf_event_overflow(event, 1, &data, regs))
2030 intel_pmu_disable_event(&event->hw, bit);
2033 intel_pmu_ack_status(ack);
2036 * Repeat if there is more work to be done:
2038 status = intel_pmu_get_status();
2047 static int amd_pmu_handle_irq(struct pt_regs *regs)
2049 struct perf_sample_data data;
2050 struct cpu_hw_events *cpuc;
2051 struct perf_event *event;
2052 struct hw_perf_event *hwc;
2053 int idx, handled = 0;
2059 cpuc = &__get_cpu_var(cpu_hw_events);
2061 for (idx = 0; idx < x86_pmu.num_events; idx++) {
2062 if (!test_bit(idx, cpuc->active_mask))
2065 event = cpuc->events[idx];
2068 val = x86_perf_event_update(event, hwc, idx);
2069 if (val & (1ULL << (x86_pmu.event_bits - 1)))
2076 data.period = event->hw.last_period;
2078 if (!x86_perf_event_set_period(event, hwc, idx))
2081 if (perf_event_overflow(event, 1, &data, regs))
2082 amd_pmu_disable_event(hwc, idx);
2086 inc_irq_stat(apic_perf_irqs);
2091 void smp_perf_pending_interrupt(struct pt_regs *regs)
2095 inc_irq_stat(apic_pending_irqs);
2096 perf_event_do_pending();
2100 void set_perf_event_pending(void)
2102 #ifdef CONFIG_X86_LOCAL_APIC
2103 if (!x86_pmu.apic || !x86_pmu_initialized())
2106 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
2110 void perf_events_lapic_init(void)
2112 #ifdef CONFIG_X86_LOCAL_APIC
2113 if (!x86_pmu.apic || !x86_pmu_initialized())
2117 * Always use NMI for PMU
2119 apic_write(APIC_LVTPC, APIC_DM_NMI);
2123 static int __kprobes
2124 perf_event_nmi_handler(struct notifier_block *self,
2125 unsigned long cmd, void *__args)
2127 struct die_args *args = __args;
2128 struct pt_regs *regs;
2130 if (!atomic_read(&active_events))
2144 #ifdef CONFIG_X86_LOCAL_APIC
2145 apic_write(APIC_LVTPC, APIC_DM_NMI);
2148 * Can't rely on the handled return value to say it was our NMI, two
2149 * events could trigger 'simultaneously' raising two back-to-back NMIs.
2151 * If the first NMI handles both, the latter will be empty and daze
2154 x86_pmu.handle_irq(regs);
2159 static struct event_constraint unconstrained;
2161 static struct event_constraint bts_constraint =
2162 EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
2164 static struct event_constraint *
2165 intel_special_constraints(struct perf_event *event)
2167 unsigned int hw_event;
2169 hw_event = event->hw.config & INTEL_ARCH_EVENT_MASK;
2171 if (unlikely((hw_event ==
2172 x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
2173 (event->hw.sample_period == 1))) {
2175 return &bts_constraint;
2180 static struct event_constraint *
2181 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2183 struct event_constraint *c;
2185 c = intel_special_constraints(event);
2189 if (x86_pmu.event_constraints) {
2190 for_each_event_constraint(c, x86_pmu.event_constraints) {
2191 if ((event->hw.config & c->cmask) == c->code)
2196 return &unconstrained;
2199 static struct event_constraint *
2200 amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2202 return &unconstrained;
2205 static int x86_event_sched_in(struct perf_event *event,
2206 struct perf_cpu_context *cpuctx, int cpu)
2210 event->state = PERF_EVENT_STATE_ACTIVE;
2212 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
2214 if (!is_x86_event(event))
2215 ret = event->pmu->enable(event);
2217 if (!ret && !is_software_event(event))
2218 cpuctx->active_oncpu++;
2220 if (!ret && event->attr.exclusive)
2221 cpuctx->exclusive = 1;
2226 static void x86_event_sched_out(struct perf_event *event,
2227 struct perf_cpu_context *cpuctx, int cpu)
2229 event->state = PERF_EVENT_STATE_INACTIVE;
2232 if (!is_x86_event(event))
2233 event->pmu->disable(event);
2235 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
2237 if (!is_software_event(event))
2238 cpuctx->active_oncpu--;
2240 if (event->attr.exclusive || !cpuctx->active_oncpu)
2241 cpuctx->exclusive = 0;
2245 * Called to enable a whole group of events.
2246 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
2247 * Assumes the caller has disabled interrupts and has
2248 * frozen the PMU with hw_perf_save_disable.
2250 * called with PMU disabled. If successful and return value 1,
2251 * then guaranteed to call perf_enable() and hw_perf_enable()
2253 int hw_perf_group_sched_in(struct perf_event *leader,
2254 struct perf_cpu_context *cpuctx,
2255 struct perf_event_context *ctx, int cpu)
2257 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2258 struct perf_event *sub;
2259 int assign[X86_PMC_IDX_MAX];
2262 /* n0 = total number of events */
2263 n0 = collect_events(cpuc, leader, true);
2267 ret = x86_schedule_events(cpuc, n0, assign);
2271 ret = x86_event_sched_in(leader, cpuctx, cpu);
2276 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
2277 if (sub->state > PERF_EVENT_STATE_OFF) {
2278 ret = x86_event_sched_in(sub, cpuctx, cpu);
2285 * copy new assignment, now we know it is possible
2286 * will be used by hw_perf_enable()
2288 memcpy(cpuc->assign, assign, n0*sizeof(int));
2290 cpuc->n_events = n0;
2292 ctx->nr_active += n1;
2295 * 1 means successful and events are active
2296 * This is not quite true because we defer
2297 * actual activation until hw_perf_enable() but
2298 * this way we* ensure caller won't try to enable
2303 x86_event_sched_out(leader, cpuctx, cpu);
2305 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
2306 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
2307 x86_event_sched_out(sub, cpuctx, cpu);
2315 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
2316 .notifier_call = perf_event_nmi_handler,
2321 static __initconst struct x86_pmu p6_pmu = {
2323 .handle_irq = p6_pmu_handle_irq,
2324 .disable_all = p6_pmu_disable_all,
2325 .enable_all = p6_pmu_enable_all,
2326 .enable = p6_pmu_enable_event,
2327 .disable = p6_pmu_disable_event,
2328 .eventsel = MSR_P6_EVNTSEL0,
2329 .perfctr = MSR_P6_PERFCTR0,
2330 .event_map = p6_pmu_event_map,
2331 .raw_event = p6_pmu_raw_event,
2332 .max_events = ARRAY_SIZE(p6_perfmon_event_map),
2334 .max_period = (1ULL << 31) - 1,
2338 * Events have 40 bits implemented. However they are designed such
2339 * that bits [32-39] are sign extensions of bit 31. As such the
2340 * effective width of a event for P6-like PMU is 32 bits only.
2342 * See IA-32 Intel Architecture Software developer manual Vol 3B
2345 .event_mask = (1ULL << 32) - 1,
2346 .get_event_constraints = intel_get_event_constraints,
2347 .event_constraints = intel_p6_event_constraints
2350 static __initconst struct x86_pmu intel_pmu = {
2352 .handle_irq = intel_pmu_handle_irq,
2353 .disable_all = intel_pmu_disable_all,
2354 .enable_all = intel_pmu_enable_all,
2355 .enable = intel_pmu_enable_event,
2356 .disable = intel_pmu_disable_event,
2357 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2358 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2359 .event_map = intel_pmu_event_map,
2360 .raw_event = intel_pmu_raw_event,
2361 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2364 * Intel PMCs cannot be accessed sanely above 32 bit width,
2365 * so we install an artificial 1<<31 period regardless of
2366 * the generic event period:
2368 .max_period = (1ULL << 31) - 1,
2369 .enable_bts = intel_pmu_enable_bts,
2370 .disable_bts = intel_pmu_disable_bts,
2371 .get_event_constraints = intel_get_event_constraints
2374 static __initconst struct x86_pmu amd_pmu = {
2376 .handle_irq = amd_pmu_handle_irq,
2377 .disable_all = amd_pmu_disable_all,
2378 .enable_all = amd_pmu_enable_all,
2379 .enable = amd_pmu_enable_event,
2380 .disable = amd_pmu_disable_event,
2381 .eventsel = MSR_K7_EVNTSEL0,
2382 .perfctr = MSR_K7_PERFCTR0,
2383 .event_map = amd_pmu_event_map,
2384 .raw_event = amd_pmu_raw_event,
2385 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
2388 .event_mask = (1ULL << 48) - 1,
2390 /* use highest bit to detect overflow */
2391 .max_period = (1ULL << 47) - 1,
2392 .get_event_constraints = amd_get_event_constraints
2395 static __init int p6_pmu_init(void)
2397 switch (boot_cpu_data.x86_model) {
2399 case 3: /* Pentium Pro */
2401 case 6: /* Pentium II */
2404 case 11: /* Pentium III */
2410 pr_cont("unsupported p6 CPU model %d ",
2411 boot_cpu_data.x86_model);
2420 static __init int intel_pmu_init(void)
2422 union cpuid10_edx edx;
2423 union cpuid10_eax eax;
2424 unsigned int unused;
2428 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2429 /* check for P6 processor family */
2430 if (boot_cpu_data.x86 == 6) {
2431 return p6_pmu_init();
2438 * Check whether the Architectural PerfMon supports
2439 * Branch Misses Retired hw_event or not.
2441 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
2442 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
2445 version = eax.split.version_id;
2449 x86_pmu = intel_pmu;
2450 x86_pmu.version = version;
2451 x86_pmu.num_events = eax.split.num_events;
2452 x86_pmu.event_bits = eax.split.bit_width;
2453 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
2456 * Quirk: v2 perfmon does not report fixed-purpose events, so
2457 * assume at least 3 events:
2459 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
2462 * Install the hw-cache-events table:
2464 switch (boot_cpu_data.x86_model) {
2465 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2466 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2467 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2468 case 29: /* six-core 45 nm xeon "Dunnington" */
2469 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2470 sizeof(hw_cache_event_ids));
2472 x86_pmu.event_constraints = intel_core_event_constraints;
2473 pr_cont("Core2 events, ");
2476 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2477 sizeof(hw_cache_event_ids));
2479 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2480 pr_cont("Nehalem/Corei7 events, ");
2483 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2484 sizeof(hw_cache_event_ids));
2486 x86_pmu.event_constraints = intel_gen_event_constraints;
2487 pr_cont("Atom events, ");
2491 * default constraints for v2 and up
2493 x86_pmu.event_constraints = intel_gen_event_constraints;
2494 pr_cont("generic architected perfmon, ");
2499 static __init int amd_pmu_init(void)
2501 /* Performance-monitoring supported from K7 and later: */
2502 if (boot_cpu_data.x86 < 6)
2507 /* Events are common for all AMDs */
2508 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
2509 sizeof(hw_cache_event_ids));
2514 static void __init pmu_check_apic(void)
2520 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
2521 pr_info("no hardware sampling interrupt available.\n");
2524 void __init init_hw_perf_events(void)
2528 pr_info("Performance Events: ");
2530 switch (boot_cpu_data.x86_vendor) {
2531 case X86_VENDOR_INTEL:
2532 err = intel_pmu_init();
2534 case X86_VENDOR_AMD:
2535 err = amd_pmu_init();
2541 pr_cont("no PMU driver, software events only.\n");
2547 pr_cont("%s PMU driver.\n", x86_pmu.name);
2549 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
2550 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2551 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
2552 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
2554 perf_event_mask = (1 << x86_pmu.num_events) - 1;
2555 perf_max_events = x86_pmu.num_events;
2557 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
2558 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2559 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
2560 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
2564 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
2565 x86_pmu.intel_ctrl = perf_event_mask;
2567 perf_events_lapic_init();
2568 register_die_notifier(&perf_event_nmi_notifier);
2570 unconstrained = (struct event_constraint)
2571 EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1, 0);
2573 pr_info("... version: %d\n", x86_pmu.version);
2574 pr_info("... bit width: %d\n", x86_pmu.event_bits);
2575 pr_info("... generic registers: %d\n", x86_pmu.num_events);
2576 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
2577 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2578 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
2579 pr_info("... event mask: %016Lx\n", perf_event_mask);
2582 static inline void x86_pmu_read(struct perf_event *event)
2584 x86_perf_event_update(event, &event->hw, event->hw.idx);
2587 static const struct pmu pmu = {
2588 .enable = x86_pmu_enable,
2589 .disable = x86_pmu_disable,
2590 .read = x86_pmu_read,
2591 .unthrottle = x86_pmu_unthrottle,
2595 * validate a single event group
2597 * validation include:
2598 * - check events are compatible which each other
2599 * - events do not compete for the same counter
2600 * - number of events <= number of counters
2602 * validation ensures the group can be loaded onto the
2603 * PMU if it was the only group available.
2605 static int validate_group(struct perf_event *event)
2607 struct perf_event *leader = event->group_leader;
2608 struct cpu_hw_events *fake_cpuc;
2612 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
2617 * the event is not yet connected with its
2618 * siblings therefore we must first collect
2619 * existing siblings, then add the new event
2620 * before we can simulate the scheduling
2623 n = collect_events(fake_cpuc, leader, true);
2627 fake_cpuc->n_events = n;
2628 n = collect_events(fake_cpuc, event, false);
2632 fake_cpuc->n_events = n;
2634 ret = x86_schedule_events(fake_cpuc, n, NULL);
2642 const struct pmu *hw_perf_event_init(struct perf_event *event)
2644 const struct pmu *tmp;
2647 err = __hw_perf_event_init(event);
2650 * we temporarily connect event to its pmu
2651 * such that validate_group() can classify
2652 * it as an x86 event using is_x86_event()
2657 if (event->group_leader != event)
2658 err = validate_group(event);
2664 event->destroy(event);
2665 return ERR_PTR(err);
2676 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
2678 if (entry->nr < PERF_MAX_STACK_DEPTH)
2679 entry->ip[entry->nr++] = ip;
2682 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
2683 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
2687 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
2689 /* Ignore warnings */
2692 static void backtrace_warning(void *data, char *msg)
2694 /* Ignore warnings */
2697 static int backtrace_stack(void *data, char *name)
2702 static void backtrace_address(void *data, unsigned long addr, int reliable)
2704 struct perf_callchain_entry *entry = data;
2707 callchain_store(entry, addr);
2710 static const struct stacktrace_ops backtrace_ops = {
2711 .warning = backtrace_warning,
2712 .warning_symbol = backtrace_warning_symbol,
2713 .stack = backtrace_stack,
2714 .address = backtrace_address,
2715 .walk_stack = print_context_stack_bp,
2718 #include "../dumpstack.h"
2721 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
2723 callchain_store(entry, PERF_CONTEXT_KERNEL);
2724 callchain_store(entry, regs->ip);
2726 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
2730 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
2732 static unsigned long
2733 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
2735 unsigned long offset, addr = (unsigned long)from;
2736 int type = in_nmi() ? KM_NMI : KM_IRQ0;
2737 unsigned long size, len = 0;
2743 ret = __get_user_pages_fast(addr, 1, 0, &page);
2747 offset = addr & (PAGE_SIZE - 1);
2748 size = min(PAGE_SIZE - offset, n - len);
2750 map = kmap_atomic(page, type);
2751 memcpy(to, map+offset, size);
2752 kunmap_atomic(map, type);
2764 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
2766 unsigned long bytes;
2768 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
2770 return bytes == sizeof(*frame);
2774 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
2776 struct stack_frame frame;
2777 const void __user *fp;
2779 if (!user_mode(regs))
2780 regs = task_pt_regs(current);
2782 fp = (void __user *)regs->bp;
2784 callchain_store(entry, PERF_CONTEXT_USER);
2785 callchain_store(entry, regs->ip);
2787 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2788 frame.next_frame = NULL;
2789 frame.return_address = 0;
2791 if (!copy_stack_frame(fp, &frame))
2794 if ((unsigned long)fp < regs->sp)
2797 callchain_store(entry, frame.return_address);
2798 fp = frame.next_frame;
2803 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
2810 is_user = user_mode(regs);
2812 if (is_user && current->state != TASK_RUNNING)
2816 perf_callchain_kernel(regs, entry);
2819 perf_callchain_user(regs, entry);
2822 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2824 struct perf_callchain_entry *entry;
2827 entry = &__get_cpu_var(pmc_nmi_entry);
2829 entry = &__get_cpu_var(pmc_irq_entry);
2833 perf_do_callchain(regs, entry);
2838 void hw_perf_event_setup_online(int cpu)
2840 init_debug_store_on_cpu(cpu);