arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/timer.h>
  37 #include <asm/desc.h>
  38 #include <asm/ldt.h>
  39
  40 #include "perf_event.h"
  41
  42 struct x86_pmu x86_pmu __read_mostly;
  43
  44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  45         .enabled = 1,
  46 };
  47
  48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
  49
  50 u64 __read_mostly hw_cache_event_ids
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54 u64 __read_mostly hw_cache_extra_regs
  55                                 [PERF_COUNT_HW_CACHE_MAX]
  56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  58
  59 /*
  60  * Propagate event elapsed time into the generic event.
  61  * Can only be executed on the CPU where the event is active.
  62  * Returns the delta events processed.
  63  */
  64 u64 x86_perf_event_update(struct perf_event *event)
  65 {
  66         struct hw_perf_event *hwc = &event->hw;
  67         int shift = 64 - x86_pmu.cntval_bits;
  68         u64 prev_raw_count, new_raw_count;
  69         int idx = hwc->idx;
  70         s64 delta;
  71
  72         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  73                 return 0;
  74
  75         /*
  76          * Careful: an NMI might modify the previous event value.
  77          *
  78          * Our tactic to handle this is to first atomically read and
  79          * exchange a new raw count - then add that new-prev delta
  80          * count to the generic event atomically:
  81          */
  82 again:
  83         prev_raw_count = local64_read(&hwc->prev_count);
  84         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  85
  86         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  87                                         new_raw_count) != prev_raw_count)
  88                 goto again;
  89
  90         /*
  91          * Now we have the new raw value and have updated the prev
  92          * timestamp already. We can now calculate the elapsed delta
  93          * (event-)time and add that to the generic event.
  94          *
  95          * Careful, not all hw sign-extends above the physical width
  96          * of the count.
  97          */
  98         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  99         delta >>= shift;
 100
 101         local64_add(delta, &event->count);
 102         local64_sub(delta, &hwc->period_left);
 103
 104         return new_raw_count;
 105 }
 106
 107 /*
 108  * Find and validate any extra registers to set up.
 109  */
 110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 111 {
 112         struct hw_perf_event_extra *reg;
 113         struct extra_reg *er;
 114
 115         reg = &event->hw.extra_reg;
 116
 117         if (!x86_pmu.extra_regs)
 118                 return 0;
 119
 120         for (er = x86_pmu.extra_regs; er->msr; er++) {
 121                 if (er->event != (config & er->config_mask))
 122                         continue;
 123                 if (event->attr.config1 & ~er->valid_mask)
 124                         return -EINVAL;
 125                 /* Check if the extra msrs can be safely accessed*/
 126                 if (!er->extra_msr_access)
 127                         return -ENXIO;
 128
 129                 reg->idx = er->idx;
 130                 reg->config = event->attr.config1;
 131                 reg->reg = er->msr;
 132                 break;
 133         }
 134         return 0;
 135 }
 136
 137 static atomic_t active_events;
 138 static DEFINE_MUTEX(pmc_reserve_mutex);
 139
 140 #ifdef CONFIG_X86_LOCAL_APIC
 141
 142 static bool reserve_pmc_hardware(void)
 143 {
 144         int i;
 145
 146         for (i = 0; i < x86_pmu.num_counters; i++) {
 147                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 148                         goto perfctr_fail;
 149         }
 150
 151         for (i = 0; i < x86_pmu.num_counters; i++) {
 152                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 153                         goto eventsel_fail;
 154         }
 155
 156         return true;
 157
 158 eventsel_fail:
 159         for (i--; i >= 0; i--)
 160                 release_evntsel_nmi(x86_pmu_config_addr(i));
 161
 162         i = x86_pmu.num_counters;
 163
 164 perfctr_fail:
 165         for (i--; i >= 0; i--)
 166                 release_perfctr_nmi(x86_pmu_event_addr(i));
 167
 168         return false;
 169 }
 170
 171 static void release_pmc_hardware(void)
 172 {
 173         int i;
 174
 175         for (i = 0; i < x86_pmu.num_counters; i++) {
 176                 release_perfctr_nmi(x86_pmu_event_addr(i));
 177                 release_evntsel_nmi(x86_pmu_config_addr(i));
 178         }
 179 }
 180
 181 #else
 182
 183 static bool reserve_pmc_hardware(void) { return true; }
 184 static void release_pmc_hardware(void) {}
 185
 186 #endif
 187
 188 static bool check_hw_exists(void)
 189 {
 190         u64 val, val_fail, val_new= ~0;
 191         int i, reg, reg_fail, ret = 0;
 192         int bios_fail = 0;
 193         int reg_safe = -1;
 194
 195         /*
 196          * Check to see if the BIOS enabled any of the counters, if so
 197          * complain and bail.
 198          */
 199         for (i = 0; i < x86_pmu.num_counters; i++) {
 200                 reg = x86_pmu_config_addr(i);
 201                 ret = rdmsrl_safe(reg, &val);
 202                 if (ret)
 203                         goto msr_fail;
 204                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 205                         bios_fail = 1;
 206                         val_fail = val;
 207                         reg_fail = reg;
 208                 } else {
 209                         reg_safe = i;
 210                 }
 211         }
 212
 213         if (x86_pmu.num_counters_fixed) {
 214                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 215                 ret = rdmsrl_safe(reg, &val);
 216                 if (ret)
 217                         goto msr_fail;
 218                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 219                         if (val & (0x03 << i*4)) {
 220                                 bios_fail = 1;
 221                                 val_fail = val;
 222                                 reg_fail = reg;
 223                         }
 224                 }
 225         }
 226
 227         /*
 228          * If all the counters are enabled, the below test will always
 229          * fail.  The tools will also become useless in this scenario.
 230          * Just fail and disable the hardware counters.
 231          */
 232
 233         if (reg_safe == -1) {
 234                 reg = reg_safe;
 235                 goto msr_fail;
 236         }
 237
 238         /*
 239          * Read the current value, change it and read it back to see if it
 240          * matches, this is needed to detect certain hardware emulators
 241          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 242          */
 243         reg = x86_pmu_event_addr(reg_safe);
 244         if (rdmsrl_safe(reg, &val))
 245                 goto msr_fail;
 246         val ^= 0xffffUL;
 247         ret = wrmsrl_safe(reg, val);
 248         ret |= rdmsrl_safe(reg, &val_new);
 249         if (ret || val != val_new)
 250                 goto msr_fail;
 251
 252         /*
 253          * We still allow the PMU driver to operate:
 254          */
 255         if (bios_fail) {
 256                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 257                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 258         }
 259
 260         return true;
 261
 262 msr_fail:
 263         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 264         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 265                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 266                 reg, val_new);
 267
 268         return false;
 269 }
 270
 271 static void hw_perf_event_destroy(struct perf_event *event)
 272 {
 273         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 274                 release_pmc_hardware();
 275                 release_ds_buffers();
 276                 mutex_unlock(&pmc_reserve_mutex);
 277         }
 278 }
 279
 280 void hw_perf_lbr_event_destroy(struct perf_event *event)
 281 {
 282         hw_perf_event_destroy(event);
 283
 284         /* undo the lbr/bts event accounting */
 285         x86_del_exclusive(x86_lbr_exclusive_lbr);
 286 }
 287
 288 static inline int x86_pmu_initialized(void)
 289 {
 290         return x86_pmu.handle_irq != NULL;
 291 }
 292
 293 static inline int
 294 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 295 {
 296         struct perf_event_attr *attr = &event->attr;
 297         unsigned int cache_type, cache_op, cache_result;
 298         u64 config, val;
 299
 300         config = attr->config;
 301
 302         cache_type = (config >>  0) & 0xff;
 303         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 304                 return -EINVAL;
 305
 306         cache_op = (config >>  8) & 0xff;
 307         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 308                 return -EINVAL;
 309
 310         cache_result = (config >> 16) & 0xff;
 311         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 312                 return -EINVAL;
 313
 314         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 315
 316         if (val == 0)
 317                 return -ENOENT;
 318
 319         if (val == -1)
 320                 return -EINVAL;
 321
 322         hwc->config |= val;
 323         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 324         return x86_pmu_extra_regs(val, event);
 325 }
 326
 327 /*
 328  * Check if we can create event of a certain type (that no conflicting events
 329  * are present).
 330  */
 331 int x86_add_exclusive(unsigned int what)
 332 {
 333         int ret = -EBUSY, i;
 334
 335         if (atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what]))
 336                 return 0;
 337
 338         mutex_lock(&pmc_reserve_mutex);
 339         for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++)
 340                 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 341                         goto out;
 342
 343         atomic_inc(&x86_pmu.lbr_exclusive[what]);
 344         ret = 0;
 345
 346 out:
 347         mutex_unlock(&pmc_reserve_mutex);
 348         return ret;
 349 }
 350
 351 void x86_del_exclusive(unsigned int what)
 352 {
 353         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 354 }
 355
 356 int x86_setup_perfctr(struct perf_event *event)
 357 {
 358         struct perf_event_attr *attr = &event->attr;
 359         struct hw_perf_event *hwc = &event->hw;
 360         u64 config;
 361
 362         if (!is_sampling_event(event)) {
 363                 hwc->sample_period = x86_pmu.max_period;
 364                 hwc->last_period = hwc->sample_period;
 365                 local64_set(&hwc->period_left, hwc->sample_period);
 366         }
 367
 368         if (attr->type == PERF_TYPE_RAW)
 369                 return x86_pmu_extra_regs(event->attr.config, event);
 370
 371         if (attr->type == PERF_TYPE_HW_CACHE)
 372                 return set_ext_hw_attr(hwc, event);
 373
 374         if (attr->config >= x86_pmu.max_events)
 375                 return -EINVAL;
 376
 377         /*
 378          * The generic map:
 379          */
 380         config = x86_pmu.event_map(attr->config);
 381
 382         if (config == 0)
 383                 return -ENOENT;
 384
 385         if (config == -1LL)
 386                 return -EINVAL;
 387
 388         /*
 389          * Branch tracing:
 390          */
 391         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 392             !attr->freq && hwc->sample_period == 1) {
 393                 /* BTS is not supported by this architecture. */
 394                 if (!x86_pmu.bts_active)
 395                         return -EOPNOTSUPP;
 396
 397                 /* BTS is currently only allowed for user-mode. */
 398                 if (!attr->exclude_kernel)
 399                         return -EOPNOTSUPP;
 400
 401                 /* disallow bts if conflicting events are present */
 402                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
 403                         return -EBUSY;
 404
 405                 event->destroy = hw_perf_lbr_event_destroy;
 406         }
 407
 408         hwc->config |= config;
 409
 410         return 0;
 411 }
 412
 413 /*
 414  * check that branch_sample_type is compatible with
 415  * settings needed for precise_ip > 1 which implies
 416  * using the LBR to capture ALL taken branches at the
 417  * priv levels of the measurement
 418  */
 419 static inline int precise_br_compat(struct perf_event *event)
 420 {
 421         u64 m = event->attr.branch_sample_type;
 422         u64 b = 0;
 423
 424         /* must capture all branches */
 425         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 426                 return 0;
 427
 428         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 429
 430         if (!event->attr.exclude_user)
 431                 b |= PERF_SAMPLE_BRANCH_USER;
 432
 433         if (!event->attr.exclude_kernel)
 434                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 435
 436         /*
 437          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 438          */
 439
 440         return m == b;
 441 }
 442
 443 int x86_pmu_hw_config(struct perf_event *event)
 444 {
 445         if (event->attr.precise_ip) {
 446                 int precise = 0;
 447
 448                 /* Support for constant skid */
 449                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 450                         precise++;
 451
 452                         /* Support for IP fixup */
 453                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 454                                 precise++;
 455                 }
 456
 457                 if (event->attr.precise_ip > precise)
 458                         return -EOPNOTSUPP;
 459         }
 460         /*
 461          * check that PEBS LBR correction does not conflict with
 462          * whatever the user is asking with attr->branch_sample_type
 463          */
 464         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 465                 u64 *br_type = &event->attr.branch_sample_type;
 466
 467                 if (has_branch_stack(event)) {
 468                         if (!precise_br_compat(event))
 469                                 return -EOPNOTSUPP;
 470
 471                         /* branch_sample_type is compatible */
 472
 473                 } else {
 474                         /*
 475                          * user did not specify  branch_sample_type
 476                          *
 477                          * For PEBS fixups, we capture all
 478                          * the branches at the priv level of the
 479                          * event.
 480                          */
 481                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 482
 483                         if (!event->attr.exclude_user)
 484                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 485
 486                         if (!event->attr.exclude_kernel)
 487                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 488                 }
 489         }
 490
 491         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 492                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 493
 494         /*
 495          * Generate PMC IRQs:
 496          * (keep 'enabled' bit clear for now)
 497          */
 498         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 499
 500         /*
 501          * Count user and OS events unless requested not to
 502          */
 503         if (!event->attr.exclude_user)
 504                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 505         if (!event->attr.exclude_kernel)
 506                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 507
 508         if (event->attr.type == PERF_TYPE_RAW)
 509                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 510
 511         if (event->attr.sample_period && x86_pmu.limit_period) {
 512                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 513                                 event->attr.sample_period)
 514                         return -EINVAL;
 515         }
 516
 517         return x86_setup_perfctr(event);
 518 }
 519
 520 /*
 521  * Setup the hardware configuration for a given attr_type
 522  */
 523 static int __x86_pmu_event_init(struct perf_event *event)
 524 {
 525         int err;
 526
 527         if (!x86_pmu_initialized())
 528                 return -ENODEV;
 529
 530         err = 0;
 531         if (!atomic_inc_not_zero(&active_events)) {
 532                 mutex_lock(&pmc_reserve_mutex);
 533                 if (atomic_read(&active_events) == 0) {
 534                         if (!reserve_pmc_hardware())
 535                                 err = -EBUSY;
 536                         else
 537                                 reserve_ds_buffers();
 538                 }
 539                 if (!err)
 540                         atomic_inc(&active_events);
 541                 mutex_unlock(&pmc_reserve_mutex);
 542         }
 543         if (err)
 544                 return err;
 545
 546         event->destroy = hw_perf_event_destroy;
 547
 548         event->hw.idx = -1;
 549         event->hw.last_cpu = -1;
 550         event->hw.last_tag = ~0ULL;
 551
 552         /* mark unused */
 553         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 554         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 555
 556         return x86_pmu.hw_config(event);
 557 }
 558
 559 void x86_pmu_disable_all(void)
 560 {
 561         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 562         int idx;
 563
 564         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 565                 u64 val;
 566
 567                 if (!test_bit(idx, cpuc->active_mask))
 568                         continue;
 569                 rdmsrl(x86_pmu_config_addr(idx), val);
 570                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 571                         continue;
 572                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 573                 wrmsrl(x86_pmu_config_addr(idx), val);
 574         }
 575 }
 576
 577 static void x86_pmu_disable(struct pmu *pmu)
 578 {
 579         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 580
 581         if (!x86_pmu_initialized())
 582                 return;
 583
 584         if (!cpuc->enabled)
 585                 return;
 586
 587         cpuc->n_added = 0;
 588         cpuc->enabled = 0;
 589         barrier();
 590
 591         x86_pmu.disable_all();
 592 }
 593
 594 void x86_pmu_enable_all(int added)
 595 {
 596         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 597         int idx;
 598
 599         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 600                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 601
 602                 if (!test_bit(idx, cpuc->active_mask))
 603                         continue;
 604
 605                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 606         }
 607 }
 608
 609 static struct pmu pmu;
 610
 611 static inline int is_x86_event(struct perf_event *event)
 612 {
 613         return event->pmu == &pmu;
 614 }
 615
 616 /*
 617  * Event scheduler state:
 618  *
 619  * Assign events iterating over all events and counters, beginning
 620  * with events with least weights first. Keep the current iterator
 621  * state in struct sched_state.
 622  */
 623 struct sched_state {
 624         int     weight;
 625         int     event;          /* event index */
 626         int     counter;        /* counter index */
 627         int     unassigned;     /* number of events to be assigned left */
 628         int     nr_gp;          /* number of GP counters used */
 629         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 630 };
 631
 632 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 633 #define SCHED_STATES_MAX        2
 634
 635 struct perf_sched {
 636         int                     max_weight;
 637         int                     max_events;
 638         int                     max_gp;
 639         int                     saved_states;
 640         struct event_constraint **constraints;
 641         struct sched_state      state;
 642         struct sched_state      saved[SCHED_STATES_MAX];
 643 };
 644
 645 /*
 646  * Initialize interator that runs through all events and counters.
 647  */
 648 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 649                             int num, int wmin, int wmax, int gpmax)
 650 {
 651         int idx;
 652
 653         memset(sched, 0, sizeof(*sched));
 654         sched->max_events       = num;
 655         sched->max_weight       = wmax;
 656         sched->max_gp           = gpmax;
 657         sched->constraints      = constraints;
 658
 659         for (idx = 0; idx < num; idx++) {
 660                 if (constraints[idx]->weight == wmin)
 661                         break;
 662         }
 663
 664         sched->state.event      = idx;          /* start with min weight */
 665         sched->state.weight     = wmin;
 666         sched->state.unassigned = num;
 667 }
 668
 669 static void perf_sched_save_state(struct perf_sched *sched)
 670 {
 671         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 672                 return;
 673
 674         sched->saved[sched->saved_states] = sched->state;
 675         sched->saved_states++;
 676 }
 677
 678 static bool perf_sched_restore_state(struct perf_sched *sched)
 679 {
 680         if (!sched->saved_states)
 681                 return false;
 682
 683         sched->saved_states--;
 684         sched->state = sched->saved[sched->saved_states];
 685
 686         /* continue with next counter: */
 687         clear_bit(sched->state.counter++, sched->state.used);
 688
 689         return true;
 690 }
 691
 692 /*
 693  * Select a counter for the current event to schedule. Return true on
 694  * success.
 695  */
 696 static bool __perf_sched_find_counter(struct perf_sched *sched)
 697 {
 698         struct event_constraint *c;
 699         int idx;
 700
 701         if (!sched->state.unassigned)
 702                 return false;
 703
 704         if (sched->state.event >= sched->max_events)
 705                 return false;
 706
 707         c = sched->constraints[sched->state.event];
 708         /* Prefer fixed purpose counters */
 709         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 710                 idx = INTEL_PMC_IDX_FIXED;
 711                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 712                         if (!__test_and_set_bit(idx, sched->state.used))
 713                                 goto done;
 714                 }
 715         }
 716
 717         /* Grab the first unused counter starting with idx */
 718         idx = sched->state.counter;
 719         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 720                 if (!__test_and_set_bit(idx, sched->state.used)) {
 721                         if (sched->state.nr_gp++ >= sched->max_gp)
 722                                 return false;
 723
 724                         goto done;
 725                 }
 726         }
 727
 728         return false;
 729
 730 done:
 731         sched->state.counter = idx;
 732
 733         if (c->overlap)
 734                 perf_sched_save_state(sched);
 735
 736         return true;
 737 }
 738
 739 static bool perf_sched_find_counter(struct perf_sched *sched)
 740 {
 741         while (!__perf_sched_find_counter(sched)) {
 742                 if (!perf_sched_restore_state(sched))
 743                         return false;
 744         }
 745
 746         return true;
 747 }
 748
 749 /*
 750  * Go through all unassigned events and find the next one to schedule.
 751  * Take events with the least weight first. Return true on success.
 752  */
 753 static bool perf_sched_next_event(struct perf_sched *sched)
 754 {
 755         struct event_constraint *c;
 756
 757         if (!sched->state.unassigned || !--sched->state.unassigned)
 758                 return false;
 759
 760         do {
 761                 /* next event */
 762                 sched->state.event++;
 763                 if (sched->state.event >= sched->max_events) {
 764                         /* next weight */
 765                         sched->state.event = 0;
 766                         sched->state.weight++;
 767                         if (sched->state.weight > sched->max_weight)
 768                                 return false;
 769                 }
 770                 c = sched->constraints[sched->state.event];
 771         } while (c->weight != sched->state.weight);
 772
 773         sched->state.counter = 0;       /* start with first counter */
 774
 775         return true;
 776 }
 777
 778 /*
 779  * Assign a counter for each event.
 780  */
 781 int perf_assign_events(struct event_constraint **constraints, int n,
 782                         int wmin, int wmax, int gpmax, int *assign)
 783 {
 784         struct perf_sched sched;
 785
 786         perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
 787
 788         do {
 789                 if (!perf_sched_find_counter(&sched))
 790                         break;  /* failed */
 791                 if (assign)
 792                         assign[sched.state.event] = sched.state.counter;
 793         } while (perf_sched_next_event(&sched));
 794
 795         return sched.state.unassigned;
 796 }
 797 EXPORT_SYMBOL_GPL(perf_assign_events);
 798
 799 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 800 {
 801         struct event_constraint *c;
 802         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 803         struct perf_event *e;
 804         int i, wmin, wmax, unsched = 0;
 805         struct hw_perf_event *hwc;
 806
 807         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 808
 809         if (x86_pmu.start_scheduling)
 810                 x86_pmu.start_scheduling(cpuc);
 811
 812         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 813                 cpuc->event_constraint[i] = NULL;
 814                 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 815                 cpuc->event_constraint[i] = c;
 816
 817                 wmin = min(wmin, c->weight);
 818                 wmax = max(wmax, c->weight);
 819         }
 820
 821         /*
 822          * fastpath, try to reuse previous register
 823          */
 824         for (i = 0; i < n; i++) {
 825                 hwc = &cpuc->event_list[i]->hw;
 826                 c = cpuc->event_constraint[i];
 827
 828                 /* never assigned */
 829                 if (hwc->idx == -1)
 830                         break;
 831
 832                 /* constraint still honored */
 833                 if (!test_bit(hwc->idx, c->idxmsk))
 834                         break;
 835
 836                 /* not already used */
 837                 if (test_bit(hwc->idx, used_mask))
 838                         break;
 839
 840                 __set_bit(hwc->idx, used_mask);
 841                 if (assign)
 842                         assign[i] = hwc->idx;
 843         }
 844
 845         /* slow path */
 846         if (i != n) {
 847                 int gpmax = x86_pmu.num_counters;
 848
 849                 /*
 850                  * Do not allow scheduling of more than half the available
 851                  * generic counters.
 852                  *
 853                  * This helps avoid counter starvation of sibling thread by
 854                  * ensuring at most half the counters cannot be in exclusive
 855                  * mode. There is no designated counters for the limits. Any
 856                  * N/2 counters can be used. This helps with events with
 857                  * specific counter constraints.
 858                  */
 859                 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
 860                     READ_ONCE(cpuc->excl_cntrs->exclusive_present))
 861                         gpmax /= 2;
 862
 863                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 864                                              wmax, gpmax, assign);
 865         }
 866
 867         /*
 868          * In case of success (unsched = 0), mark events as committed,
 869          * so we do not put_constraint() in case new events are added
 870          * and fail to be scheduled
 871          *
 872          * We invoke the lower level commit callback to lock the resource
 873          *
 874          * We do not need to do all of this in case we are called to
 875          * validate an event group (assign == NULL)
 876          */
 877         if (!unsched && assign) {
 878                 for (i = 0; i < n; i++) {
 879                         e = cpuc->event_list[i];
 880                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 881                         if (x86_pmu.commit_scheduling)
 882                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
 883                 }
 884         }
 885
 886         if (!assign || unsched) {
 887
 888                 for (i = 0; i < n; i++) {
 889                         e = cpuc->event_list[i];
 890                         /*
 891                          * do not put_constraint() on comitted events,
 892                          * because they are good to go
 893                          */
 894                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 895                                 continue;
 896
 897                         /*
 898                          * release events that failed scheduling
 899                          */
 900                         if (x86_pmu.put_event_constraints)
 901                                 x86_pmu.put_event_constraints(cpuc, e);
 902                 }
 903         }
 904
 905         if (x86_pmu.stop_scheduling)
 906                 x86_pmu.stop_scheduling(cpuc);
 907
 908         return unsched ? -EINVAL : 0;
 909 }
 910
 911 /*
 912  * dogrp: true if must collect siblings events (group)
 913  * returns total number of events and error code
 914  */
 915 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 916 {
 917         struct perf_event *event;
 918         int n, max_count;
 919
 920         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 921
 922         /* current number of events already accepted */
 923         n = cpuc->n_events;
 924
 925         if (is_x86_event(leader)) {
 926                 if (n >= max_count)
 927                         return -EINVAL;
 928                 cpuc->event_list[n] = leader;
 929                 n++;
 930         }
 931         if (!dogrp)
 932                 return n;
 933
 934         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 935                 if (!is_x86_event(event) ||
 936                     event->state <= PERF_EVENT_STATE_OFF)
 937                         continue;
 938
 939                 if (n >= max_count)
 940                         return -EINVAL;
 941
 942                 cpuc->event_list[n] = event;
 943                 n++;
 944         }
 945         return n;
 946 }
 947
 948 static inline void x86_assign_hw_event(struct perf_event *event,
 949                                 struct cpu_hw_events *cpuc, int i)
 950 {
 951         struct hw_perf_event *hwc = &event->hw;
 952
 953         hwc->idx = cpuc->assign[i];
 954         hwc->last_cpu = smp_processor_id();
 955         hwc->last_tag = ++cpuc->tags[i];
 956
 957         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 958                 hwc->config_base = 0;
 959                 hwc->event_base = 0;
 960         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 961                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 962                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 963                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 964         } else {
 965                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 966                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 967                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 968         }
 969 }
 970
 971 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 972                                         struct cpu_hw_events *cpuc,
 973                                         int i)
 974 {
 975         return hwc->idx == cpuc->assign[i] &&
 976                 hwc->last_cpu == smp_processor_id() &&
 977                 hwc->last_tag == cpuc->tags[i];
 978 }
 979
 980 static void x86_pmu_start(struct perf_event *event, int flags);
 981
 982 static void x86_pmu_enable(struct pmu *pmu)
 983 {
 984         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 985         struct perf_event *event;
 986         struct hw_perf_event *hwc;
 987         int i, added = cpuc->n_added;
 988
 989         if (!x86_pmu_initialized())
 990                 return;
 991
 992         if (cpuc->enabled)
 993                 return;
 994
 995         if (cpuc->n_added) {
 996                 int n_running = cpuc->n_events - cpuc->n_added;
 997                 /*
 998                  * apply assignment obtained either from
 999                  * hw_perf_group_sched_in() or x86_pmu_enable()
1000                  *
1001                  * step1: save events moving to new counters
1002                  */
1003                 for (i = 0; i < n_running; i++) {
1004                         event = cpuc->event_list[i];
1005                         hwc = &event->hw;
1006
1007                         /*
1008                          * we can avoid reprogramming counter if:
1009                          * - assigned same counter as last time
1010                          * - running on same CPU as last time
1011                          * - no other event has used the counter since
1012                          */
1013                         if (hwc->idx == -1 ||
1014                             match_prev_assignment(hwc, cpuc, i))
1015                                 continue;
1016
1017                         /*
1018                          * Ensure we don't accidentally enable a stopped
1019                          * counter simply because we rescheduled.
1020                          */
1021                         if (hwc->state & PERF_HES_STOPPED)
1022                                 hwc->state |= PERF_HES_ARCH;
1023
1024                         x86_pmu_stop(event, PERF_EF_UPDATE);
1025                 }
1026
1027                 /*
1028                  * step2: reprogram moved events into new counters
1029                  */
1030                 for (i = 0; i < cpuc->n_events; i++) {
1031                         event = cpuc->event_list[i];
1032                         hwc = &event->hw;
1033
1034                         if (!match_prev_assignment(hwc, cpuc, i))
1035                                 x86_assign_hw_event(event, cpuc, i);
1036                         else if (i < n_running)
1037                                 continue;
1038
1039                         if (hwc->state & PERF_HES_ARCH)
1040                                 continue;
1041
1042                         x86_pmu_start(event, PERF_EF_RELOAD);
1043                 }
1044                 cpuc->n_added = 0;
1045                 perf_events_lapic_init();
1046         }
1047
1048         cpuc->enabled = 1;
1049         barrier();
1050
1051         x86_pmu.enable_all(added);
1052 }
1053
1054 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1055
1056 /*
1057  * Set the next IRQ period, based on the hwc->period_left value.
1058  * To be called with the event disabled in hw:
1059  */
1060 int x86_perf_event_set_period(struct perf_event *event)
1061 {
1062         struct hw_perf_event *hwc = &event->hw;
1063         s64 left = local64_read(&hwc->period_left);
1064         s64 period = hwc->sample_period;
1065         int ret = 0, idx = hwc->idx;
1066
1067         if (idx == INTEL_PMC_IDX_FIXED_BTS)
1068                 return 0;
1069
1070         /*
1071          * If we are way outside a reasonable range then just skip forward:
1072          */
1073         if (unlikely(left <= -period)) {
1074                 left = period;
1075                 local64_set(&hwc->period_left, left);
1076                 hwc->last_period = period;
1077                 ret = 1;
1078         }
1079
1080         if (unlikely(left <= 0)) {
1081                 left += period;
1082                 local64_set(&hwc->period_left, left);
1083                 hwc->last_period = period;
1084                 ret = 1;
1085         }
1086         /*
1087          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1088          */
1089         if (unlikely(left < 2))
1090                 left = 2;
1091
1092         if (left > x86_pmu.max_period)
1093                 left = x86_pmu.max_period;
1094
1095         if (x86_pmu.limit_period)
1096                 left = x86_pmu.limit_period(event, left);
1097
1098         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1099
1100         /*
1101          * The hw event starts counting from this event offset,
1102          * mark it to be able to extra future deltas:
1103          */
1104         local64_set(&hwc->prev_count, (u64)-left);
1105
1106         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1107
1108         /*
1109          * Due to erratum on certan cpu we need
1110          * a second write to be sure the register
1111          * is updated properly
1112          */
1113         if (x86_pmu.perfctr_second_write) {
1114                 wrmsrl(hwc->event_base,
1115                         (u64)(-left) & x86_pmu.cntval_mask);
1116         }
1117
1118         perf_event_update_userpage(event);
1119
1120         return ret;
1121 }
1122
1123 void x86_pmu_enable_event(struct perf_event *event)
1124 {
1125         if (__this_cpu_read(cpu_hw_events.enabled))
1126                 __x86_pmu_enable_event(&event->hw,
1127                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1128 }
1129
1130 /*
1131  * Add a single event to the PMU.
1132  *
1133  * The event is added to the group of enabled events
1134  * but only if it can be scehduled with existing events.
1135  */
1136 static int x86_pmu_add(struct perf_event *event, int flags)
1137 {
1138         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1139         struct hw_perf_event *hwc;
1140         int assign[X86_PMC_IDX_MAX];
1141         int n, n0, ret;
1142
1143         hwc = &event->hw;
1144
1145         n0 = cpuc->n_events;
1146         ret = n = collect_events(cpuc, event, false);
1147         if (ret < 0)
1148                 goto out;
1149
1150         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1151         if (!(flags & PERF_EF_START))
1152                 hwc->state |= PERF_HES_ARCH;
1153
1154         /*
1155          * If group events scheduling transaction was started,
1156          * skip the schedulability test here, it will be performed
1157          * at commit time (->commit_txn) as a whole.
1158          */
1159         if (cpuc->group_flag & PERF_EVENT_TXN)
1160                 goto done_collect;
1161
1162         ret = x86_pmu.schedule_events(cpuc, n, assign);
1163         if (ret)
1164                 goto out;
1165         /*
1166          * copy new assignment, now we know it is possible
1167          * will be used by hw_perf_enable()
1168          */
1169         memcpy(cpuc->assign, assign, n*sizeof(int));
1170
1171 done_collect:
1172         /*
1173          * Commit the collect_events() state. See x86_pmu_del() and
1174          * x86_pmu_*_txn().
1175          */
1176         cpuc->n_events = n;
1177         cpuc->n_added += n - n0;
1178         cpuc->n_txn += n - n0;
1179
1180         ret = 0;
1181 out:
1182         return ret;
1183 }
1184
1185 static void x86_pmu_start(struct perf_event *event, int flags)
1186 {
1187         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1188         int idx = event->hw.idx;
1189
1190         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1191                 return;
1192
1193         if (WARN_ON_ONCE(idx == -1))
1194                 return;
1195
1196         if (flags & PERF_EF_RELOAD) {
1197                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1198                 x86_perf_event_set_period(event);
1199         }
1200
1201         event->hw.state = 0;
1202
1203         cpuc->events[idx] = event;
1204         __set_bit(idx, cpuc->active_mask);
1205         __set_bit(idx, cpuc->running);
1206         x86_pmu.enable(event);
1207         perf_event_update_userpage(event);
1208 }
1209
1210 void perf_event_print_debug(void)
1211 {
1212         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1213         u64 pebs, debugctl;
1214         struct cpu_hw_events *cpuc;
1215         unsigned long flags;
1216         int cpu, idx;
1217
1218         if (!x86_pmu.num_counters)
1219                 return;
1220
1221         local_irq_save(flags);
1222
1223         cpu = smp_processor_id();
1224         cpuc = &per_cpu(cpu_hw_events, cpu);
1225
1226         if (x86_pmu.version >= 2) {
1227                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1228                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1229                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1230                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1231
1232                 pr_info("\n");
1233                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1234                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1235                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1236                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1237                 if (x86_pmu.pebs_constraints) {
1238                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1239                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1240                 }
1241                 if (x86_pmu.lbr_nr) {
1242                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1243                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1244                 }
1245         }
1246         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1247
1248         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1249                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1250                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1251
1252                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1253
1254                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1255                         cpu, idx, pmc_ctrl);
1256                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1257                         cpu, idx, pmc_count);
1258                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1259                         cpu, idx, prev_left);
1260         }
1261         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1262                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1263
1264                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1265                         cpu, idx, pmc_count);
1266         }
1267         local_irq_restore(flags);
1268 }
1269
1270 void x86_pmu_stop(struct perf_event *event, int flags)
1271 {
1272         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1273         struct hw_perf_event *hwc = &event->hw;
1274
1275         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1276                 x86_pmu.disable(event);
1277                 cpuc->events[hwc->idx] = NULL;
1278                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1279                 hwc->state |= PERF_HES_STOPPED;
1280         }
1281
1282         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1283                 /*
1284                  * Drain the remaining delta count out of a event
1285                  * that we are disabling:
1286                  */
1287                 x86_perf_event_update(event);
1288                 hwc->state |= PERF_HES_UPTODATE;
1289         }
1290 }
1291
1292 static void x86_pmu_del(struct perf_event *event, int flags)
1293 {
1294         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1295         int i;
1296
1297         /*
1298          * event is descheduled
1299          */
1300         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1301
1302         /*
1303          * If we're called during a txn, we don't need to do anything.
1304          * The events never got scheduled and ->cancel_txn will truncate
1305          * the event_list.
1306          *
1307          * XXX assumes any ->del() called during a TXN will only be on
1308          * an event added during that same TXN.
1309          */
1310         if (cpuc->group_flag & PERF_EVENT_TXN)
1311                 return;
1312
1313         /*
1314          * Not a TXN, therefore cleanup properly.
1315          */
1316         x86_pmu_stop(event, PERF_EF_UPDATE);
1317
1318         for (i = 0; i < cpuc->n_events; i++) {
1319                 if (event == cpuc->event_list[i])
1320                         break;
1321         }
1322
1323         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1324                 return;
1325
1326         /* If we have a newly added event; make sure to decrease n_added. */
1327         if (i >= cpuc->n_events - cpuc->n_added)
1328                 --cpuc->n_added;
1329
1330         if (x86_pmu.put_event_constraints)
1331                 x86_pmu.put_event_constraints(cpuc, event);
1332
1333         /* Delete the array entry. */
1334         while (++i < cpuc->n_events) {
1335                 cpuc->event_list[i-1] = cpuc->event_list[i];
1336                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1337         }
1338         --cpuc->n_events;
1339
1340         perf_event_update_userpage(event);
1341 }
1342
1343 int x86_pmu_handle_irq(struct pt_regs *regs)
1344 {
1345         struct perf_sample_data data;
1346         struct cpu_hw_events *cpuc;
1347         struct perf_event *event;
1348         int idx, handled = 0;
1349         u64 val;
1350
1351         cpuc = this_cpu_ptr(&cpu_hw_events);
1352
1353         /*
1354          * Some chipsets need to unmask the LVTPC in a particular spot
1355          * inside the nmi handler.  As a result, the unmasking was pushed
1356          * into all the nmi handlers.
1357          *
1358          * This generic handler doesn't seem to have any issues where the
1359          * unmasking occurs so it was left at the top.
1360          */
1361         apic_write(APIC_LVTPC, APIC_DM_NMI);
1362
1363         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1364                 if (!test_bit(idx, cpuc->active_mask)) {
1365                         /*
1366                          * Though we deactivated the counter some cpus
1367                          * might still deliver spurious interrupts still
1368                          * in flight. Catch them:
1369                          */
1370                         if (__test_and_clear_bit(idx, cpuc->running))
1371                                 handled++;
1372                         continue;
1373                 }
1374
1375                 event = cpuc->events[idx];
1376
1377                 val = x86_perf_event_update(event);
1378                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1379                         continue;
1380
1381                 /*
1382                  * event overflow
1383                  */
1384                 handled++;
1385                 perf_sample_data_init(&data, 0, event->hw.last_period);
1386
1387                 if (!x86_perf_event_set_period(event))
1388                         continue;
1389
1390                 if (perf_event_overflow(event, &data, regs))
1391                         x86_pmu_stop(event, 0);
1392         }
1393
1394         if (handled)
1395                 inc_irq_stat(apic_perf_irqs);
1396
1397         return handled;
1398 }
1399
1400 void perf_events_lapic_init(void)
1401 {
1402         if (!x86_pmu.apic || !x86_pmu_initialized())
1403                 return;
1404
1405         /*
1406          * Always use NMI for PMU
1407          */
1408         apic_write(APIC_LVTPC, APIC_DM_NMI);
1409 }
1410
1411 static int
1412 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1413 {
1414         u64 start_clock;
1415         u64 finish_clock;
1416         int ret;
1417
1418         if (!atomic_read(&active_events))
1419                 return NMI_DONE;
1420
1421         start_clock = sched_clock();
1422         ret = x86_pmu.handle_irq(regs);
1423         finish_clock = sched_clock();
1424
1425         perf_sample_event_took(finish_clock - start_clock);
1426
1427         return ret;
1428 }
1429 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1430
1431 struct event_constraint emptyconstraint;
1432 struct event_constraint unconstrained;
1433
1434 static int
1435 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1436 {
1437         unsigned int cpu = (long)hcpu;
1438         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1439         int i, ret = NOTIFY_OK;
1440
1441         switch (action & ~CPU_TASKS_FROZEN) {
1442         case CPU_UP_PREPARE:
1443                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1444                         cpuc->kfree_on_online[i] = NULL;
1445                 if (x86_pmu.cpu_prepare)
1446                         ret = x86_pmu.cpu_prepare(cpu);
1447                 break;
1448
1449         case CPU_STARTING:
1450                 if (x86_pmu.cpu_starting)
1451                         x86_pmu.cpu_starting(cpu);
1452                 break;
1453
1454         case CPU_ONLINE:
1455                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1456                         kfree(cpuc->kfree_on_online[i]);
1457                         cpuc->kfree_on_online[i] = NULL;
1458                 }
1459                 break;
1460
1461         case CPU_DYING:
1462                 if (x86_pmu.cpu_dying)
1463                         x86_pmu.cpu_dying(cpu);
1464                 break;
1465
1466         case CPU_UP_CANCELED:
1467         case CPU_DEAD:
1468                 if (x86_pmu.cpu_dead)
1469                         x86_pmu.cpu_dead(cpu);
1470                 break;
1471
1472         default:
1473                 break;
1474         }
1475
1476         return ret;
1477 }
1478
1479 static void __init pmu_check_apic(void)
1480 {
1481         if (cpu_has_apic)
1482                 return;
1483
1484         x86_pmu.apic = 0;
1485         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1486         pr_info("no hardware sampling interrupt available.\n");
1487
1488         /*
1489          * If we have a PMU initialized but no APIC
1490          * interrupts, we cannot sample hardware
1491          * events (user-space has to fall back and
1492          * sample via a hrtimer based software event):
1493          */
1494         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1495
1496 }
1497
1498 static struct attribute_group x86_pmu_format_group = {
1499         .name = "format",
1500         .attrs = NULL,
1501 };
1502
1503 /*
1504  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1505  * out of events_attr attributes.
1506  */
1507 static void __init filter_events(struct attribute **attrs)
1508 {
1509         struct device_attribute *d;
1510         struct perf_pmu_events_attr *pmu_attr;
1511         int i, j;
1512
1513         for (i = 0; attrs[i]; i++) {
1514                 d = (struct device_attribute *)attrs[i];
1515                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1516                 /* str trumps id */
1517                 if (pmu_attr->event_str)
1518                         continue;
1519                 if (x86_pmu.event_map(i))
1520                         continue;
1521
1522                 for (j = i; attrs[j]; j++)
1523                         attrs[j] = attrs[j + 1];
1524
1525                 /* Check the shifted attr. */
1526                 i--;
1527         }
1528 }
1529
1530 /* Merge two pointer arrays */
1531 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1532 {
1533         struct attribute **new;
1534         int j, i;
1535
1536         for (j = 0; a[j]; j++)
1537                 ;
1538         for (i = 0; b[i]; i++)
1539                 j++;
1540         j++;
1541
1542         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1543         if (!new)
1544                 return NULL;
1545
1546         j = 0;
1547         for (i = 0; a[i]; i++)
1548                 new[j++] = a[i];
1549         for (i = 0; b[i]; i++)
1550                 new[j++] = b[i];
1551         new[j] = NULL;
1552
1553         return new;
1554 }
1555
1556 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1557                           char *page)
1558 {
1559         struct perf_pmu_events_attr *pmu_attr = \
1560                 container_of(attr, struct perf_pmu_events_attr, attr);
1561         u64 config = x86_pmu.event_map(pmu_attr->id);
1562
1563         /* string trumps id */
1564         if (pmu_attr->event_str)
1565                 return sprintf(page, "%s", pmu_attr->event_str);
1566
1567         return x86_pmu.events_sysfs_show(page, config);
1568 }
1569
1570 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1571 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1572 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1573 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1574 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1575 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1576 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1577 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1578 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1579 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1580
1581 static struct attribute *empty_attrs;
1582
1583 static struct attribute *events_attr[] = {
1584         EVENT_PTR(CPU_CYCLES),
1585         EVENT_PTR(INSTRUCTIONS),
1586         EVENT_PTR(CACHE_REFERENCES),
1587         EVENT_PTR(CACHE_MISSES),
1588         EVENT_PTR(BRANCH_INSTRUCTIONS),
1589         EVENT_PTR(BRANCH_MISSES),
1590         EVENT_PTR(BUS_CYCLES),
1591         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1592         EVENT_PTR(STALLED_CYCLES_BACKEND),
1593         EVENT_PTR(REF_CPU_CYCLES),
1594         NULL,
1595 };
1596
1597 static struct attribute_group x86_pmu_events_group = {
1598         .name = "events",
1599         .attrs = events_attr,
1600 };
1601
1602 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1603 {
1604         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1605         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1606         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1607         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1608         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1609         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1610         ssize_t ret;
1611
1612         /*
1613         * We have whole page size to spend and just little data
1614         * to write, so we can safely use sprintf.
1615         */
1616         ret = sprintf(page, "event=0x%02llx", event);
1617
1618         if (umask)
1619                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1620
1621         if (edge)
1622                 ret += sprintf(page + ret, ",edge");
1623
1624         if (pc)
1625                 ret += sprintf(page + ret, ",pc");
1626
1627         if (any)
1628                 ret += sprintf(page + ret, ",any");
1629
1630         if (inv)
1631                 ret += sprintf(page + ret, ",inv");
1632
1633         if (cmask)
1634                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1635
1636         ret += sprintf(page + ret, "\n");
1637
1638         return ret;
1639 }
1640
1641 static int __init init_hw_perf_events(void)
1642 {
1643         struct x86_pmu_quirk *quirk;
1644         int err;
1645
1646         pr_info("Performance Events: ");
1647
1648         switch (boot_cpu_data.x86_vendor) {
1649         case X86_VENDOR_INTEL:
1650                 err = intel_pmu_init();
1651                 break;
1652         case X86_VENDOR_AMD:
1653                 err = amd_pmu_init();
1654                 break;
1655         default:
1656                 err = -ENOTSUPP;
1657         }
1658         if (err != 0) {
1659                 pr_cont("no PMU driver, software events only.\n");
1660                 return 0;
1661         }
1662
1663         pmu_check_apic();
1664
1665         /* sanity check that the hardware exists or is emulated */
1666         if (!check_hw_exists())
1667                 return 0;
1668
1669         pr_cont("%s PMU driver.\n", x86_pmu.name);
1670
1671         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1672
1673         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1674                 quirk->func();
1675
1676         if (!x86_pmu.intel_ctrl)
1677                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1678
1679         perf_events_lapic_init();
1680         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1681
1682         unconstrained = (struct event_constraint)
1683                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1684                                    0, x86_pmu.num_counters, 0, 0);
1685
1686         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1687
1688         if (x86_pmu.event_attrs)
1689                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1690
1691         if (!x86_pmu.events_sysfs_show)
1692                 x86_pmu_events_group.attrs = &empty_attrs;
1693         else
1694                 filter_events(x86_pmu_events_group.attrs);
1695
1696         if (x86_pmu.cpu_events) {
1697                 struct attribute **tmp;
1698
1699                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1700                 if (!WARN_ON(!tmp))
1701                         x86_pmu_events_group.attrs = tmp;
1702         }
1703
1704         pr_info("... version:                %d\n",     x86_pmu.version);
1705         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1706         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1707         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1708         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1709         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1710         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1711
1712         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1713         perf_cpu_notifier(x86_pmu_notifier);
1714
1715         return 0;
1716 }
1717 early_initcall(init_hw_perf_events);
1718
1719 static inline void x86_pmu_read(struct perf_event *event)
1720 {
1721         x86_perf_event_update(event);
1722 }
1723
1724 /*
1725  * Start group events scheduling transaction
1726  * Set the flag to make pmu::enable() not perform the
1727  * schedulability test, it will be performed at commit time
1728  */
1729 static void x86_pmu_start_txn(struct pmu *pmu)
1730 {
1731         perf_pmu_disable(pmu);
1732         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1733         __this_cpu_write(cpu_hw_events.n_txn, 0);
1734 }
1735
1736 /*
1737  * Stop group events scheduling transaction
1738  * Clear the flag and pmu::enable() will perform the
1739  * schedulability test.
1740  */
1741 static void x86_pmu_cancel_txn(struct pmu *pmu)
1742 {
1743         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1744         /*
1745          * Truncate collected array by the number of events added in this
1746          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1747          */
1748         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1749         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1750         perf_pmu_enable(pmu);
1751 }
1752
1753 /*
1754  * Commit group events scheduling transaction
1755  * Perform the group schedulability test as a whole
1756  * Return 0 if success
1757  *
1758  * Does not cancel the transaction on failure; expects the caller to do this.
1759  */
1760 static int x86_pmu_commit_txn(struct pmu *pmu)
1761 {
1762         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1763         int assign[X86_PMC_IDX_MAX];
1764         int n, ret;
1765
1766         n = cpuc->n_events;
1767
1768         if (!x86_pmu_initialized())
1769                 return -EAGAIN;
1770
1771         ret = x86_pmu.schedule_events(cpuc, n, assign);
1772         if (ret)
1773                 return ret;
1774
1775         /*
1776          * copy new assignment, now we know it is possible
1777          * will be used by hw_perf_enable()
1778          */
1779         memcpy(cpuc->assign, assign, n*sizeof(int));
1780
1781         cpuc->group_flag &= ~PERF_EVENT_TXN;
1782         perf_pmu_enable(pmu);
1783         return 0;
1784 }
1785 /*
1786  * a fake_cpuc is used to validate event groups. Due to
1787  * the extra reg logic, we need to also allocate a fake
1788  * per_core and per_cpu structure. Otherwise, group events
1789  * using extra reg may conflict without the kernel being
1790  * able to catch this when the last event gets added to
1791  * the group.
1792  */
1793 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1794 {
1795         kfree(cpuc->shared_regs);
1796         kfree(cpuc);
1797 }
1798
1799 static struct cpu_hw_events *allocate_fake_cpuc(void)
1800 {
1801         struct cpu_hw_events *cpuc;
1802         int cpu = raw_smp_processor_id();
1803
1804         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1805         if (!cpuc)
1806                 return ERR_PTR(-ENOMEM);
1807
1808         /* only needed, if we have extra_regs */
1809         if (x86_pmu.extra_regs) {
1810                 cpuc->shared_regs = allocate_shared_regs(cpu);
1811                 if (!cpuc->shared_regs)
1812                         goto error;
1813         }
1814         cpuc->is_fake = 1;
1815         return cpuc;
1816 error:
1817         free_fake_cpuc(cpuc);
1818         return ERR_PTR(-ENOMEM);
1819 }
1820
1821 /*
1822  * validate that we can schedule this event
1823  */
1824 static int validate_event(struct perf_event *event)
1825 {
1826         struct cpu_hw_events *fake_cpuc;
1827         struct event_constraint *c;
1828         int ret = 0;
1829
1830         fake_cpuc = allocate_fake_cpuc();
1831         if (IS_ERR(fake_cpuc))
1832                 return PTR_ERR(fake_cpuc);
1833
1834         c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1835
1836         if (!c || !c->weight)
1837                 ret = -EINVAL;
1838
1839         if (x86_pmu.put_event_constraints)
1840                 x86_pmu.put_event_constraints(fake_cpuc, event);
1841
1842         free_fake_cpuc(fake_cpuc);
1843
1844         return ret;
1845 }
1846
1847 /*
1848  * validate a single event group
1849  *
1850  * validation include:
1851  *      - check events are compatible which each other
1852  *      - events do not compete for the same counter
1853  *      - number of events <= number of counters
1854  *
1855  * validation ensures the group can be loaded onto the
1856  * PMU if it was the only group available.
1857  */
1858 static int validate_group(struct perf_event *event)
1859 {
1860         struct perf_event *leader = event->group_leader;
1861         struct cpu_hw_events *fake_cpuc;
1862         int ret = -EINVAL, n;
1863
1864         fake_cpuc = allocate_fake_cpuc();
1865         if (IS_ERR(fake_cpuc))
1866                 return PTR_ERR(fake_cpuc);
1867         /*
1868          * the event is not yet connected with its
1869          * siblings therefore we must first collect
1870          * existing siblings, then add the new event
1871          * before we can simulate the scheduling
1872          */
1873         n = collect_events(fake_cpuc, leader, true);
1874         if (n < 0)
1875                 goto out;
1876
1877         fake_cpuc->n_events = n;
1878         n = collect_events(fake_cpuc, event, false);
1879         if (n < 0)
1880                 goto out;
1881
1882         fake_cpuc->n_events = n;
1883
1884         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1885
1886 out:
1887         free_fake_cpuc(fake_cpuc);
1888         return ret;
1889 }
1890
1891 static int x86_pmu_event_init(struct perf_event *event)
1892 {
1893         struct pmu *tmp;
1894         int err;
1895
1896         switch (event->attr.type) {
1897         case PERF_TYPE_RAW:
1898         case PERF_TYPE_HARDWARE:
1899         case PERF_TYPE_HW_CACHE:
1900                 break;
1901
1902         default:
1903                 return -ENOENT;
1904         }
1905
1906         err = __x86_pmu_event_init(event);
1907         if (!err) {
1908                 /*
1909                  * we temporarily connect event to its pmu
1910                  * such that validate_group() can classify
1911                  * it as an x86 event using is_x86_event()
1912                  */
1913                 tmp = event->pmu;
1914                 event->pmu = &pmu;
1915
1916                 if (event->group_leader != event)
1917                         err = validate_group(event);
1918                 else
1919                         err = validate_event(event);
1920
1921                 event->pmu = tmp;
1922         }
1923         if (err) {
1924                 if (event->destroy)
1925                         event->destroy(event);
1926         }
1927
1928         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1929                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1930
1931         return err;
1932 }
1933
1934 static void refresh_pce(void *ignored)
1935 {
1936         if (current->mm)
1937                 load_mm_cr4(current->mm);
1938 }
1939
1940 static void x86_pmu_event_mapped(struct perf_event *event)
1941 {
1942         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1943                 return;
1944
1945         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
1946                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1947 }
1948
1949 static void x86_pmu_event_unmapped(struct perf_event *event)
1950 {
1951         if (!current->mm)
1952                 return;
1953
1954         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1955                 return;
1956
1957         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
1958                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1959 }
1960
1961 static int x86_pmu_event_idx(struct perf_event *event)
1962 {
1963         int idx = event->hw.idx;
1964
1965         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1966                 return 0;
1967
1968         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1969                 idx -= INTEL_PMC_IDX_FIXED;
1970                 idx |= 1 << 30;
1971         }
1972
1973         return idx + 1;
1974 }
1975
1976 static ssize_t get_attr_rdpmc(struct device *cdev,
1977                               struct device_attribute *attr,
1978                               char *buf)
1979 {
1980         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1981 }
1982
1983 static ssize_t set_attr_rdpmc(struct device *cdev,
1984                               struct device_attribute *attr,
1985                               const char *buf, size_t count)
1986 {
1987         unsigned long val;
1988         ssize_t ret;
1989
1990         ret = kstrtoul(buf, 0, &val);
1991         if (ret)
1992                 return ret;
1993
1994         if (val > 2)
1995                 return -EINVAL;
1996
1997         if (x86_pmu.attr_rdpmc_broken)
1998                 return -ENOTSUPP;
1999
2000         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2001                 /*
2002                  * Changing into or out of always available, aka
2003                  * perf-event-bypassing mode.  This path is extremely slow,
2004                  * but only root can trigger it, so it's okay.
2005                  */
2006                 if (val == 2)
2007                         static_key_slow_inc(&rdpmc_always_available);
2008                 else
2009                         static_key_slow_dec(&rdpmc_always_available);
2010                 on_each_cpu(refresh_pce, NULL, 1);
2011         }
2012
2013         x86_pmu.attr_rdpmc = val;
2014
2015         return count;
2016 }
2017
2018 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2019
2020 static struct attribute *x86_pmu_attrs[] = {
2021         &dev_attr_rdpmc.attr,
2022         NULL,
2023 };
2024
2025 static struct attribute_group x86_pmu_attr_group = {
2026         .attrs = x86_pmu_attrs,
2027 };
2028
2029 static const struct attribute_group *x86_pmu_attr_groups[] = {
2030         &x86_pmu_attr_group,
2031         &x86_pmu_format_group,
2032         &x86_pmu_events_group,
2033         NULL,
2034 };
2035
2036 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2037 {
2038         if (x86_pmu.sched_task)
2039                 x86_pmu.sched_task(ctx, sched_in);
2040 }
2041
2042 void perf_check_microcode(void)
2043 {
2044         if (x86_pmu.check_microcode)
2045                 x86_pmu.check_microcode();
2046 }
2047 EXPORT_SYMBOL_GPL(perf_check_microcode);
2048
2049 static struct pmu pmu = {
2050         .pmu_enable             = x86_pmu_enable,
2051         .pmu_disable            = x86_pmu_disable,
2052
2053         .attr_groups            = x86_pmu_attr_groups,
2054
2055         .event_init             = x86_pmu_event_init,
2056
2057         .event_mapped           = x86_pmu_event_mapped,
2058         .event_unmapped         = x86_pmu_event_unmapped,
2059
2060         .add                    = x86_pmu_add,
2061         .del                    = x86_pmu_del,
2062         .start                  = x86_pmu_start,
2063         .stop                   = x86_pmu_stop,
2064         .read                   = x86_pmu_read,
2065
2066         .start_txn              = x86_pmu_start_txn,
2067         .cancel_txn             = x86_pmu_cancel_txn,
2068         .commit_txn             = x86_pmu_commit_txn,
2069
2070         .event_idx              = x86_pmu_event_idx,
2071         .sched_task             = x86_pmu_sched_task,
2072         .task_ctx_size          = sizeof(struct x86_perf_task_context),
2073 };
2074
2075 void arch_perf_update_userpage(struct perf_event *event,
2076                                struct perf_event_mmap_page *userpg, u64 now)
2077 {
2078         struct cyc2ns_data *data;
2079
2080         userpg->cap_user_time = 0;
2081         userpg->cap_user_time_zero = 0;
2082         userpg->cap_user_rdpmc =
2083                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2084         userpg->pmc_width = x86_pmu.cntval_bits;
2085
2086         if (!sched_clock_stable())
2087                 return;
2088
2089         data = cyc2ns_read_begin();
2090
2091         /*
2092          * Internal timekeeping for enabled/running/stopped times
2093          * is always in the local_clock domain.
2094          */
2095         userpg->cap_user_time = 1;
2096         userpg->time_mult = data->cyc2ns_mul;
2097         userpg->time_shift = data->cyc2ns_shift;
2098         userpg->time_offset = data->cyc2ns_offset - now;
2099
2100         /*
2101          * cap_user_time_zero doesn't make sense when we're using a different
2102          * time base for the records.
2103          */
2104         if (event->clock == &local_clock) {
2105                 userpg->cap_user_time_zero = 1;
2106                 userpg->time_zero = data->cyc2ns_offset;
2107         }
2108
2109         cyc2ns_read_end(data);
2110 }
2111
2112 /*
2113  * callchain support
2114  */
2115
2116 static int backtrace_stack(void *data, char *name)
2117 {
2118         return 0;
2119 }
2120
2121 static void backtrace_address(void *data, unsigned long addr, int reliable)
2122 {
2123         struct perf_callchain_entry *entry = data;
2124
2125         perf_callchain_store(entry, addr);
2126 }
2127
2128 static const struct stacktrace_ops backtrace_ops = {
2129         .stack                  = backtrace_stack,
2130         .address                = backtrace_address,
2131         .walk_stack             = print_context_stack_bp,
2132 };
2133
2134 void
2135 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2136 {
2137         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2138                 /* TODO: We don't support guest os callchain now */
2139                 return;
2140         }
2141
2142         perf_callchain_store(entry, regs->ip);
2143
2144         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2145 }
2146
2147 static inline int
2148 valid_user_frame(const void __user *fp, unsigned long size)
2149 {
2150         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2151 }
2152
2153 static unsigned long get_segment_base(unsigned int segment)
2154 {
2155         struct desc_struct *desc;
2156         int idx = segment >> 3;
2157
2158         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2159                 if (idx > LDT_ENTRIES)
2160                         return 0;
2161
2162                 if (idx > current->active_mm->context.size)
2163                         return 0;
2164
2165                 desc = current->active_mm->context.ldt;
2166         } else {
2167                 if (idx > GDT_ENTRIES)
2168                         return 0;
2169
2170                 desc = raw_cpu_ptr(gdt_page.gdt);
2171         }
2172
2173         return get_desc_base(desc + idx);
2174 }
2175
2176 #ifdef CONFIG_COMPAT
2177
2178 #include <asm/compat.h>
2179
2180 static inline int
2181 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2182 {
2183         /* 32-bit process in 64-bit kernel. */
2184         unsigned long ss_base, cs_base;
2185         struct stack_frame_ia32 frame;
2186         const void __user *fp;
2187
2188         if (!test_thread_flag(TIF_IA32))
2189                 return 0;
2190
2191         cs_base = get_segment_base(regs->cs);
2192         ss_base = get_segment_base(regs->ss);
2193
2194         fp = compat_ptr(ss_base + regs->bp);
2195         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2196                 unsigned long bytes;
2197                 frame.next_frame     = 0;
2198                 frame.return_address = 0;
2199
2200                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2201                 if (bytes != 0)
2202                         break;
2203
2204                 if (!valid_user_frame(fp, sizeof(frame)))
2205                         break;
2206
2207                 perf_callchain_store(entry, cs_base + frame.return_address);
2208                 fp = compat_ptr(ss_base + frame.next_frame);
2209         }
2210         return 1;
2211 }
2212 #else
2213 static inline int
2214 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2215 {
2216     return 0;
2217 }
2218 #endif
2219
2220 void
2221 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2222 {
2223         struct stack_frame frame;
2224         const void __user *fp;
2225
2226         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2227                 /* TODO: We don't support guest os callchain now */
2228                 return;
2229         }
2230
2231         /*
2232          * We don't know what to do with VM86 stacks.. ignore them for now.
2233          */
2234         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2235                 return;
2236
2237         fp = (void __user *)regs->bp;
2238
2239         perf_callchain_store(entry, regs->ip);
2240
2241         if (!current->mm)
2242                 return;
2243
2244         if (perf_callchain_user32(regs, entry))
2245                 return;
2246
2247         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2248                 unsigned long bytes;
2249                 frame.next_frame             = NULL;
2250                 frame.return_address = 0;
2251
2252                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2253                 if (bytes != 0)
2254                         break;
2255
2256                 if (!valid_user_frame(fp, sizeof(frame)))
2257                         break;
2258
2259                 perf_callchain_store(entry, frame.return_address);
2260                 fp = frame.next_frame;
2261         }
2262 }
2263
2264 /*
2265  * Deal with code segment offsets for the various execution modes:
2266  *
2267  *   VM86 - the good olde 16 bit days, where the linear address is
2268  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2269  *
2270  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2271  *          to figure out what the 32bit base address is.
2272  *
2273  *    X32 - has TIF_X32 set, but is running in x86_64
2274  *
2275  * X86_64 - CS,DS,SS,ES are all zero based.
2276  */
2277 static unsigned long code_segment_base(struct pt_regs *regs)
2278 {
2279         /*
2280          * For IA32 we look at the GDT/LDT segment base to convert the
2281          * effective IP to a linear address.
2282          */
2283
2284 #ifdef CONFIG_X86_32
2285         /*
2286          * If we are in VM86 mode, add the segment offset to convert to a
2287          * linear address.
2288          */
2289         if (regs->flags & X86_VM_MASK)
2290                 return 0x10 * regs->cs;
2291
2292         if (user_mode(regs) && regs->cs != __USER_CS)
2293                 return get_segment_base(regs->cs);
2294 #else
2295         if (user_mode(regs) && !user_64bit_mode(regs) &&
2296             regs->cs != __USER32_CS)
2297                 return get_segment_base(regs->cs);
2298 #endif
2299         return 0;
2300 }
2301
2302 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2303 {
2304         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2305                 return perf_guest_cbs->get_guest_ip();
2306
2307         return regs->ip + code_segment_base(regs);
2308 }
2309
2310 unsigned long perf_misc_flags(struct pt_regs *regs)
2311 {
2312         int misc = 0;
2313
2314         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2315                 if (perf_guest_cbs->is_user_mode())
2316                         misc |= PERF_RECORD_MISC_GUEST_USER;
2317                 else
2318                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2319         } else {
2320                 if (user_mode(regs))
2321                         misc |= PERF_RECORD_MISC_USER;
2322                 else
2323                         misc |= PERF_RECORD_MISC_KERNEL;
2324         }
2325
2326         if (regs->flags & PERF_EFLAGS_EXACT)
2327                 misc |= PERF_RECORD_MISC_EXACT_IP;
2328
2329         return misc;
2330 }
2331
2332 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2333 {
2334         cap->version            = x86_pmu.version;
2335         cap->num_counters_gp    = x86_pmu.num_counters;
2336         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2337         cap->bit_width_gp       = x86_pmu.cntval_bits;
2338         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2339         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2340         cap->events_mask_len    = x86_pmu.events_mask_len;
2341 }
2342 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);