arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/timer.h>
  35 #include <asm/desc.h>
  36 #include <asm/ldt.h>
  37
  38 #include "perf_event.h"
  39
  40 struct x86_pmu x86_pmu __read_mostly;
  41
  42 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  43         .enabled = 1,
  44 };
  45
  46 u64 __read_mostly hw_cache_event_ids
  47                                 [PERF_COUNT_HW_CACHE_MAX]
  48                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  49                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  50 u64 __read_mostly hw_cache_extra_regs
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54
  55 /*
  56  * Propagate event elapsed time into the generic event.
  57  * Can only be executed on the CPU where the event is active.
  58  * Returns the delta events processed.
  59  */
  60 u64 x86_perf_event_update(struct perf_event *event)
  61 {
  62         struct hw_perf_event *hwc = &event->hw;
  63         int shift = 64 - x86_pmu.cntval_bits;
  64         u64 prev_raw_count, new_raw_count;
  65         int idx = hwc->idx;
  66         s64 delta;
  67
  68         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  69                 return 0;
  70
  71         /*
  72          * Careful: an NMI might modify the previous event value.
  73          *
  74          * Our tactic to handle this is to first atomically read and
  75          * exchange a new raw count - then add that new-prev delta
  76          * count to the generic event atomically:
  77          */
  78 again:
  79         prev_raw_count = local64_read(&hwc->prev_count);
  80         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  81
  82         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  83                                         new_raw_count) != prev_raw_count)
  84                 goto again;
  85
  86         /*
  87          * Now we have the new raw value and have updated the prev
  88          * timestamp already. We can now calculate the elapsed delta
  89          * (event-)time and add that to the generic event.
  90          *
  91          * Careful, not all hw sign-extends above the physical width
  92          * of the count.
  93          */
  94         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  95         delta >>= shift;
  96
  97         local64_add(delta, &event->count);
  98         local64_sub(delta, &hwc->period_left);
  99
 100         return new_raw_count;
 101 }
 102
 103 /*
 104  * Find and validate any extra registers to set up.
 105  */
 106 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 107 {
 108         struct hw_perf_event_extra *reg;
 109         struct extra_reg *er;
 110
 111         reg = &event->hw.extra_reg;
 112
 113         if (!x86_pmu.extra_regs)
 114                 return 0;
 115
 116         for (er = x86_pmu.extra_regs; er->msr; er++) {
 117                 if (er->event != (config & er->config_mask))
 118                         continue;
 119                 if (event->attr.config1 & ~er->valid_mask)
 120                         return -EINVAL;
 121                 /* Check if the extra msrs can be safely accessed*/
 122                 if (!er->extra_msr_access)
 123                         return -ENXIO;
 124
 125                 reg->idx = er->idx;
 126                 reg->config = event->attr.config1;
 127                 reg->reg = er->msr;
 128                 break;
 129         }
 130         return 0;
 131 }
 132
 133 static atomic_t active_events;
 134 static DEFINE_MUTEX(pmc_reserve_mutex);
 135
 136 #ifdef CONFIG_X86_LOCAL_APIC
 137
 138 static bool reserve_pmc_hardware(void)
 139 {
 140         int i;
 141
 142         for (i = 0; i < x86_pmu.num_counters; i++) {
 143                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 144                         goto perfctr_fail;
 145         }
 146
 147         for (i = 0; i < x86_pmu.num_counters; i++) {
 148                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 149                         goto eventsel_fail;
 150         }
 151
 152         return true;
 153
 154 eventsel_fail:
 155         for (i--; i >= 0; i--)
 156                 release_evntsel_nmi(x86_pmu_config_addr(i));
 157
 158         i = x86_pmu.num_counters;
 159
 160 perfctr_fail:
 161         for (i--; i >= 0; i--)
 162                 release_perfctr_nmi(x86_pmu_event_addr(i));
 163
 164         return false;
 165 }
 166
 167 static void release_pmc_hardware(void)
 168 {
 169         int i;
 170
 171         for (i = 0; i < x86_pmu.num_counters; i++) {
 172                 release_perfctr_nmi(x86_pmu_event_addr(i));
 173                 release_evntsel_nmi(x86_pmu_config_addr(i));
 174         }
 175 }
 176
 177 #else
 178
 179 static bool reserve_pmc_hardware(void) { return true; }
 180 static void release_pmc_hardware(void) {}
 181
 182 #endif
 183
 184 static bool check_hw_exists(void)
 185 {
 186         u64 val, val_fail, val_new= ~0;
 187         int i, reg, reg_fail, ret = 0;
 188         int bios_fail = 0;
 189
 190         /*
 191          * Check to see if the BIOS enabled any of the counters, if so
 192          * complain and bail.
 193          */
 194         for (i = 0; i < x86_pmu.num_counters; i++) {
 195                 reg = x86_pmu_config_addr(i);
 196                 ret = rdmsrl_safe(reg, &val);
 197                 if (ret)
 198                         goto msr_fail;
 199                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 200                         bios_fail = 1;
 201                         val_fail = val;
 202                         reg_fail = reg;
 203                 }
 204         }
 205
 206         if (x86_pmu.num_counters_fixed) {
 207                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 208                 ret = rdmsrl_safe(reg, &val);
 209                 if (ret)
 210                         goto msr_fail;
 211                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 212                         if (val & (0x03 << i*4)) {
 213                                 bios_fail = 1;
 214                                 val_fail = val;
 215                                 reg_fail = reg;
 216                         }
 217                 }
 218         }
 219
 220         /*
 221          * Read the current value, change it and read it back to see if it
 222          * matches, this is needed to detect certain hardware emulators
 223          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 224          */
 225         reg = x86_pmu_event_addr(0);
 226         if (rdmsrl_safe(reg, &val))
 227                 goto msr_fail;
 228         val ^= 0xffffUL;
 229         ret = wrmsrl_safe(reg, val);
 230         ret |= rdmsrl_safe(reg, &val_new);
 231         if (ret || val != val_new)
 232                 goto msr_fail;
 233
 234         /*
 235          * We still allow the PMU driver to operate:
 236          */
 237         if (bios_fail) {
 238                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 239                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 240         }
 241
 242         return true;
 243
 244 msr_fail:
 245         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 246         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 247                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 248                 reg, val_new);
 249
 250         return false;
 251 }
 252
 253 static void hw_perf_event_destroy(struct perf_event *event)
 254 {
 255         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 256                 release_pmc_hardware();
 257                 release_ds_buffers();
 258                 mutex_unlock(&pmc_reserve_mutex);
 259         }
 260 }
 261
 262 static inline int x86_pmu_initialized(void)
 263 {
 264         return x86_pmu.handle_irq != NULL;
 265 }
 266
 267 static inline int
 268 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 269 {
 270         struct perf_event_attr *attr = &event->attr;
 271         unsigned int cache_type, cache_op, cache_result;
 272         u64 config, val;
 273
 274         config = attr->config;
 275
 276         cache_type = (config >>  0) & 0xff;
 277         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 278                 return -EINVAL;
 279
 280         cache_op = (config >>  8) & 0xff;
 281         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 282                 return -EINVAL;
 283
 284         cache_result = (config >> 16) & 0xff;
 285         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 286                 return -EINVAL;
 287
 288         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 289
 290         if (val == 0)
 291                 return -ENOENT;
 292
 293         if (val == -1)
 294                 return -EINVAL;
 295
 296         hwc->config |= val;
 297         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 298         return x86_pmu_extra_regs(val, event);
 299 }
 300
 301 int x86_setup_perfctr(struct perf_event *event)
 302 {
 303         struct perf_event_attr *attr = &event->attr;
 304         struct hw_perf_event *hwc = &event->hw;
 305         u64 config;
 306
 307         if (!is_sampling_event(event)) {
 308                 hwc->sample_period = x86_pmu.max_period;
 309                 hwc->last_period = hwc->sample_period;
 310                 local64_set(&hwc->period_left, hwc->sample_period);
 311         }
 312
 313         if (attr->type == PERF_TYPE_RAW)
 314                 return x86_pmu_extra_regs(event->attr.config, event);
 315
 316         if (attr->type == PERF_TYPE_HW_CACHE)
 317                 return set_ext_hw_attr(hwc, event);
 318
 319         if (attr->config >= x86_pmu.max_events)
 320                 return -EINVAL;
 321
 322         /*
 323          * The generic map:
 324          */
 325         config = x86_pmu.event_map(attr->config);
 326
 327         if (config == 0)
 328                 return -ENOENT;
 329
 330         if (config == -1LL)
 331                 return -EINVAL;
 332
 333         /*
 334          * Branch tracing:
 335          */
 336         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 337             !attr->freq && hwc->sample_period == 1) {
 338                 /* BTS is not supported by this architecture. */
 339                 if (!x86_pmu.bts_active)
 340                         return -EOPNOTSUPP;
 341
 342                 /* BTS is currently only allowed for user-mode. */
 343                 if (!attr->exclude_kernel)
 344                         return -EOPNOTSUPP;
 345         }
 346
 347         hwc->config |= config;
 348
 349         return 0;
 350 }
 351
 352 /*
 353  * check that branch_sample_type is compatible with
 354  * settings needed for precise_ip > 1 which implies
 355  * using the LBR to capture ALL taken branches at the
 356  * priv levels of the measurement
 357  */
 358 static inline int precise_br_compat(struct perf_event *event)
 359 {
 360         u64 m = event->attr.branch_sample_type;
 361         u64 b = 0;
 362
 363         /* must capture all branches */
 364         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 365                 return 0;
 366
 367         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 368
 369         if (!event->attr.exclude_user)
 370                 b |= PERF_SAMPLE_BRANCH_USER;
 371
 372         if (!event->attr.exclude_kernel)
 373                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 374
 375         /*
 376          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 377          */
 378
 379         return m == b;
 380 }
 381
 382 int x86_pmu_hw_config(struct perf_event *event)
 383 {
 384         if (event->attr.precise_ip) {
 385                 int precise = 0;
 386
 387                 /* Support for constant skid */
 388                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 389                         precise++;
 390
 391                         /* Support for IP fixup */
 392                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 393                                 precise++;
 394                 }
 395
 396                 if (event->attr.precise_ip > precise)
 397                         return -EOPNOTSUPP;
 398                 /*
 399                  * check that PEBS LBR correction does not conflict with
 400                  * whatever the user is asking with attr->branch_sample_type
 401                  */
 402                 if (event->attr.precise_ip > 1 &&
 403                     x86_pmu.intel_cap.pebs_format < 2) {
 404                         u64 *br_type = &event->attr.branch_sample_type;
 405
 406                         if (has_branch_stack(event)) {
 407                                 if (!precise_br_compat(event))
 408                                         return -EOPNOTSUPP;
 409
 410                                 /* branch_sample_type is compatible */
 411
 412                         } else {
 413                                 /*
 414                                  * user did not specify  branch_sample_type
 415                                  *
 416                                  * For PEBS fixups, we capture all
 417                                  * the branches at the priv level of the
 418                                  * event.
 419                                  */
 420                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 421
 422                                 if (!event->attr.exclude_user)
 423                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 424
 425                                 if (!event->attr.exclude_kernel)
 426                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 427                         }
 428                 }
 429         }
 430
 431         /*
 432          * Generate PMC IRQs:
 433          * (keep 'enabled' bit clear for now)
 434          */
 435         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 436
 437         /*
 438          * Count user and OS events unless requested not to
 439          */
 440         if (!event->attr.exclude_user)
 441                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 442         if (!event->attr.exclude_kernel)
 443                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 444
 445         if (event->attr.type == PERF_TYPE_RAW)
 446                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 447
 448         if (event->attr.sample_period && x86_pmu.limit_period) {
 449                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 450                                 event->attr.sample_period)
 451                         return -EINVAL;
 452         }
 453
 454         return x86_setup_perfctr(event);
 455 }
 456
 457 /*
 458  * Setup the hardware configuration for a given attr_type
 459  */
 460 static int __x86_pmu_event_init(struct perf_event *event)
 461 {
 462         int err;
 463
 464         if (!x86_pmu_initialized())
 465                 return -ENODEV;
 466
 467         err = 0;
 468         if (!atomic_inc_not_zero(&active_events)) {
 469                 mutex_lock(&pmc_reserve_mutex);
 470                 if (atomic_read(&active_events) == 0) {
 471                         if (!reserve_pmc_hardware())
 472                                 err = -EBUSY;
 473                         else
 474                                 reserve_ds_buffers();
 475                 }
 476                 if (!err)
 477                         atomic_inc(&active_events);
 478                 mutex_unlock(&pmc_reserve_mutex);
 479         }
 480         if (err)
 481                 return err;
 482
 483         event->destroy = hw_perf_event_destroy;
 484
 485         event->hw.idx = -1;
 486         event->hw.last_cpu = -1;
 487         event->hw.last_tag = ~0ULL;
 488
 489         /* mark unused */
 490         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 491         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 492
 493         return x86_pmu.hw_config(event);
 494 }
 495
 496 void x86_pmu_disable_all(void)
 497 {
 498         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 499         int idx;
 500
 501         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 502                 u64 val;
 503
 504                 if (!test_bit(idx, cpuc->active_mask))
 505                         continue;
 506                 rdmsrl(x86_pmu_config_addr(idx), val);
 507                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 508                         continue;
 509                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 510                 wrmsrl(x86_pmu_config_addr(idx), val);
 511         }
 512 }
 513
 514 static void x86_pmu_disable(struct pmu *pmu)
 515 {
 516         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 517
 518         if (!x86_pmu_initialized())
 519                 return;
 520
 521         if (!cpuc->enabled)
 522                 return;
 523
 524         cpuc->n_added = 0;
 525         cpuc->enabled = 0;
 526         barrier();
 527
 528         x86_pmu.disable_all();
 529 }
 530
 531 void x86_pmu_enable_all(int added)
 532 {
 533         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 534         int idx;
 535
 536         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 537                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 538
 539                 if (!test_bit(idx, cpuc->active_mask))
 540                         continue;
 541
 542                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 543         }
 544 }
 545
 546 static struct pmu pmu;
 547
 548 static inline int is_x86_event(struct perf_event *event)
 549 {
 550         return event->pmu == &pmu;
 551 }
 552
 553 /*
 554  * Event scheduler state:
 555  *
 556  * Assign events iterating over all events and counters, beginning
 557  * with events with least weights first. Keep the current iterator
 558  * state in struct sched_state.
 559  */
 560 struct sched_state {
 561         int     weight;
 562         int     event;          /* event index */
 563         int     counter;        /* counter index */
 564         int     unassigned;     /* number of events to be assigned left */
 565         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 566 };
 567
 568 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 569 #define SCHED_STATES_MAX        2
 570
 571 struct perf_sched {
 572         int                     max_weight;
 573         int                     max_events;
 574         struct perf_event       **events;
 575         struct sched_state      state;
 576         int                     saved_states;
 577         struct sched_state      saved[SCHED_STATES_MAX];
 578 };
 579
 580 /*
 581  * Initialize interator that runs through all events and counters.
 582  */
 583 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
 584                             int num, int wmin, int wmax)
 585 {
 586         int idx;
 587
 588         memset(sched, 0, sizeof(*sched));
 589         sched->max_events       = num;
 590         sched->max_weight       = wmax;
 591         sched->events           = events;
 592
 593         for (idx = 0; idx < num; idx++) {
 594                 if (events[idx]->hw.constraint->weight == wmin)
 595                         break;
 596         }
 597
 598         sched->state.event      = idx;          /* start with min weight */
 599         sched->state.weight     = wmin;
 600         sched->state.unassigned = num;
 601 }
 602
 603 static void perf_sched_save_state(struct perf_sched *sched)
 604 {
 605         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 606                 return;
 607
 608         sched->saved[sched->saved_states] = sched->state;
 609         sched->saved_states++;
 610 }
 611
 612 static bool perf_sched_restore_state(struct perf_sched *sched)
 613 {
 614         if (!sched->saved_states)
 615                 return false;
 616
 617         sched->saved_states--;
 618         sched->state = sched->saved[sched->saved_states];
 619
 620         /* continue with next counter: */
 621         clear_bit(sched->state.counter++, sched->state.used);
 622
 623         return true;
 624 }
 625
 626 /*
 627  * Select a counter for the current event to schedule. Return true on
 628  * success.
 629  */
 630 static bool __perf_sched_find_counter(struct perf_sched *sched)
 631 {
 632         struct event_constraint *c;
 633         int idx;
 634
 635         if (!sched->state.unassigned)
 636                 return false;
 637
 638         if (sched->state.event >= sched->max_events)
 639                 return false;
 640
 641         c = sched->events[sched->state.event]->hw.constraint;
 642         /* Prefer fixed purpose counters */
 643         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 644                 idx = INTEL_PMC_IDX_FIXED;
 645                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 646                         if (!__test_and_set_bit(idx, sched->state.used))
 647                                 goto done;
 648                 }
 649         }
 650         /* Grab the first unused counter starting with idx */
 651         idx = sched->state.counter;
 652         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 653                 if (!__test_and_set_bit(idx, sched->state.used))
 654                         goto done;
 655         }
 656
 657         return false;
 658
 659 done:
 660         sched->state.counter = idx;
 661
 662         if (c->overlap)
 663                 perf_sched_save_state(sched);
 664
 665         return true;
 666 }
 667
 668 static bool perf_sched_find_counter(struct perf_sched *sched)
 669 {
 670         while (!__perf_sched_find_counter(sched)) {
 671                 if (!perf_sched_restore_state(sched))
 672                         return false;
 673         }
 674
 675         return true;
 676 }
 677
 678 /*
 679  * Go through all unassigned events and find the next one to schedule.
 680  * Take events with the least weight first. Return true on success.
 681  */
 682 static bool perf_sched_next_event(struct perf_sched *sched)
 683 {
 684         struct event_constraint *c;
 685
 686         if (!sched->state.unassigned || !--sched->state.unassigned)
 687                 return false;
 688
 689         do {
 690                 /* next event */
 691                 sched->state.event++;
 692                 if (sched->state.event >= sched->max_events) {
 693                         /* next weight */
 694                         sched->state.event = 0;
 695                         sched->state.weight++;
 696                         if (sched->state.weight > sched->max_weight)
 697                                 return false;
 698                 }
 699                 c = sched->events[sched->state.event]->hw.constraint;
 700         } while (c->weight != sched->state.weight);
 701
 702         sched->state.counter = 0;       /* start with first counter */
 703
 704         return true;
 705 }
 706
 707 /*
 708  * Assign a counter for each event.
 709  */
 710 int perf_assign_events(struct perf_event **events, int n,
 711                         int wmin, int wmax, int *assign)
 712 {
 713         struct perf_sched sched;
 714
 715         perf_sched_init(&sched, events, n, wmin, wmax);
 716
 717         do {
 718                 if (!perf_sched_find_counter(&sched))
 719                         break;  /* failed */
 720                 if (assign)
 721                         assign[sched.state.event] = sched.state.counter;
 722         } while (perf_sched_next_event(&sched));
 723
 724         return sched.state.unassigned;
 725 }
 726 EXPORT_SYMBOL_GPL(perf_assign_events);
 727
 728 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 729 {
 730         struct event_constraint *c;
 731         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 732         struct perf_event *e;
 733         int i, wmin, wmax, num = 0;
 734         struct hw_perf_event *hwc;
 735
 736         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 737
 738         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 739                 hwc = &cpuc->event_list[i]->hw;
 740                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 741                 hwc->constraint = c;
 742
 743                 wmin = min(wmin, c->weight);
 744                 wmax = max(wmax, c->weight);
 745         }
 746
 747         /*
 748          * fastpath, try to reuse previous register
 749          */
 750         for (i = 0; i < n; i++) {
 751                 hwc = &cpuc->event_list[i]->hw;
 752                 c = hwc->constraint;
 753
 754                 /* never assigned */
 755                 if (hwc->idx == -1)
 756                         break;
 757
 758                 /* constraint still honored */
 759                 if (!test_bit(hwc->idx, c->idxmsk))
 760                         break;
 761
 762                 /* not already used */
 763                 if (test_bit(hwc->idx, used_mask))
 764                         break;
 765
 766                 __set_bit(hwc->idx, used_mask);
 767                 if (assign)
 768                         assign[i] = hwc->idx;
 769         }
 770
 771         /* slow path */
 772         if (i != n)
 773                 num = perf_assign_events(cpuc->event_list, n, wmin,
 774                                          wmax, assign);
 775
 776         /*
 777          * Mark the event as committed, so we do not put_constraint()
 778          * in case new events are added and fail scheduling.
 779          */
 780         if (!num && assign) {
 781                 for (i = 0; i < n; i++) {
 782                         e = cpuc->event_list[i];
 783                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 784                 }
 785         }
 786         /*
 787          * scheduling failed or is just a simulation,
 788          * free resources if necessary
 789          */
 790         if (!assign || num) {
 791                 for (i = 0; i < n; i++) {
 792                         e = cpuc->event_list[i];
 793                         /*
 794                          * do not put_constraint() on comitted events,
 795                          * because they are good to go
 796                          */
 797                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 798                                 continue;
 799
 800                         if (x86_pmu.put_event_constraints)
 801                                 x86_pmu.put_event_constraints(cpuc, e);
 802                 }
 803         }
 804         return num ? -EINVAL : 0;
 805 }
 806
 807 /*
 808  * dogrp: true if must collect siblings events (group)
 809  * returns total number of events and error code
 810  */
 811 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 812 {
 813         struct perf_event *event;
 814         int n, max_count;
 815
 816         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 817
 818         /* current number of events already accepted */
 819         n = cpuc->n_events;
 820
 821         if (is_x86_event(leader)) {
 822                 if (n >= max_count)
 823                         return -EINVAL;
 824                 cpuc->event_list[n] = leader;
 825                 n++;
 826         }
 827         if (!dogrp)
 828                 return n;
 829
 830         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 831                 if (!is_x86_event(event) ||
 832                     event->state <= PERF_EVENT_STATE_OFF)
 833                         continue;
 834
 835                 if (n >= max_count)
 836                         return -EINVAL;
 837
 838                 cpuc->event_list[n] = event;
 839                 n++;
 840         }
 841         return n;
 842 }
 843
 844 static inline void x86_assign_hw_event(struct perf_event *event,
 845                                 struct cpu_hw_events *cpuc, int i)
 846 {
 847         struct hw_perf_event *hwc = &event->hw;
 848
 849         hwc->idx = cpuc->assign[i];
 850         hwc->last_cpu = smp_processor_id();
 851         hwc->last_tag = ++cpuc->tags[i];
 852
 853         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 854                 hwc->config_base = 0;
 855                 hwc->event_base = 0;
 856         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 857                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 858                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 859                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 860         } else {
 861                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 862                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 863                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 864         }
 865 }
 866
 867 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 868                                         struct cpu_hw_events *cpuc,
 869                                         int i)
 870 {
 871         return hwc->idx == cpuc->assign[i] &&
 872                 hwc->last_cpu == smp_processor_id() &&
 873                 hwc->last_tag == cpuc->tags[i];
 874 }
 875
 876 static void x86_pmu_start(struct perf_event *event, int flags);
 877
 878 static void x86_pmu_enable(struct pmu *pmu)
 879 {
 880         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 881         struct perf_event *event;
 882         struct hw_perf_event *hwc;
 883         int i, added = cpuc->n_added;
 884
 885         if (!x86_pmu_initialized())
 886                 return;
 887
 888         if (cpuc->enabled)
 889                 return;
 890
 891         if (cpuc->n_added) {
 892                 int n_running = cpuc->n_events - cpuc->n_added;
 893                 /*
 894                  * apply assignment obtained either from
 895                  * hw_perf_group_sched_in() or x86_pmu_enable()
 896                  *
 897                  * step1: save events moving to new counters
 898                  */
 899                 for (i = 0; i < n_running; i++) {
 900                         event = cpuc->event_list[i];
 901                         hwc = &event->hw;
 902
 903                         /*
 904                          * we can avoid reprogramming counter if:
 905                          * - assigned same counter as last time
 906                          * - running on same CPU as last time
 907                          * - no other event has used the counter since
 908                          */
 909                         if (hwc->idx == -1 ||
 910                             match_prev_assignment(hwc, cpuc, i))
 911                                 continue;
 912
 913                         /*
 914                          * Ensure we don't accidentally enable a stopped
 915                          * counter simply because we rescheduled.
 916                          */
 917                         if (hwc->state & PERF_HES_STOPPED)
 918                                 hwc->state |= PERF_HES_ARCH;
 919
 920                         x86_pmu_stop(event, PERF_EF_UPDATE);
 921                 }
 922
 923                 /*
 924                  * step2: reprogram moved events into new counters
 925                  */
 926                 for (i = 0; i < cpuc->n_events; i++) {
 927                         event = cpuc->event_list[i];
 928                         hwc = &event->hw;
 929
 930                         if (!match_prev_assignment(hwc, cpuc, i))
 931                                 x86_assign_hw_event(event, cpuc, i);
 932                         else if (i < n_running)
 933                                 continue;
 934
 935                         if (hwc->state & PERF_HES_ARCH)
 936                                 continue;
 937
 938                         x86_pmu_start(event, PERF_EF_RELOAD);
 939                 }
 940                 cpuc->n_added = 0;
 941                 perf_events_lapic_init();
 942         }
 943
 944         cpuc->enabled = 1;
 945         barrier();
 946
 947         x86_pmu.enable_all(added);
 948 }
 949
 950 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 951
 952 /*
 953  * Set the next IRQ period, based on the hwc->period_left value.
 954  * To be called with the event disabled in hw:
 955  */
 956 int x86_perf_event_set_period(struct perf_event *event)
 957 {
 958         struct hw_perf_event *hwc = &event->hw;
 959         s64 left = local64_read(&hwc->period_left);
 960         s64 period = hwc->sample_period;
 961         int ret = 0, idx = hwc->idx;
 962
 963         if (idx == INTEL_PMC_IDX_FIXED_BTS)
 964                 return 0;
 965
 966         /*
 967          * If we are way outside a reasonable range then just skip forward:
 968          */
 969         if (unlikely(left <= -period)) {
 970                 left = period;
 971                 local64_set(&hwc->period_left, left);
 972                 hwc->last_period = period;
 973                 ret = 1;
 974         }
 975
 976         if (unlikely(left <= 0)) {
 977                 left += period;
 978                 local64_set(&hwc->period_left, left);
 979                 hwc->last_period = period;
 980                 ret = 1;
 981         }
 982         /*
 983          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 984          */
 985         if (unlikely(left < 2))
 986                 left = 2;
 987
 988         if (left > x86_pmu.max_period)
 989                 left = x86_pmu.max_period;
 990
 991         if (x86_pmu.limit_period)
 992                 left = x86_pmu.limit_period(event, left);
 993
 994         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 995
 996         /*
 997          * The hw event starts counting from this event offset,
 998          * mark it to be able to extra future deltas:
 999          */
1000         local64_set(&hwc->prev_count, (u64)-left);
1001
1002         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1003
1004         /*
1005          * Due to erratum on certan cpu we need
1006          * a second write to be sure the register
1007          * is updated properly
1008          */
1009         if (x86_pmu.perfctr_second_write) {
1010                 wrmsrl(hwc->event_base,
1011                         (u64)(-left) & x86_pmu.cntval_mask);
1012         }
1013
1014         perf_event_update_userpage(event);
1015
1016         return ret;
1017 }
1018
1019 void x86_pmu_enable_event(struct perf_event *event)
1020 {
1021         if (__this_cpu_read(cpu_hw_events.enabled))
1022                 __x86_pmu_enable_event(&event->hw,
1023                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1024 }
1025
1026 /*
1027  * Add a single event to the PMU.
1028  *
1029  * The event is added to the group of enabled events
1030  * but only if it can be scehduled with existing events.
1031  */
1032 static int x86_pmu_add(struct perf_event *event, int flags)
1033 {
1034         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1035         struct hw_perf_event *hwc;
1036         int assign[X86_PMC_IDX_MAX];
1037         int n, n0, ret;
1038
1039         hwc = &event->hw;
1040
1041         perf_pmu_disable(event->pmu);
1042         n0 = cpuc->n_events;
1043         ret = n = collect_events(cpuc, event, false);
1044         if (ret < 0)
1045                 goto out;
1046
1047         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1048         if (!(flags & PERF_EF_START))
1049                 hwc->state |= PERF_HES_ARCH;
1050
1051         /*
1052          * If group events scheduling transaction was started,
1053          * skip the schedulability test here, it will be performed
1054          * at commit time (->commit_txn) as a whole.
1055          */
1056         if (cpuc->group_flag & PERF_EVENT_TXN)
1057                 goto done_collect;
1058
1059         ret = x86_pmu.schedule_events(cpuc, n, assign);
1060         if (ret)
1061                 goto out;
1062         /*
1063          * copy new assignment, now we know it is possible
1064          * will be used by hw_perf_enable()
1065          */
1066         memcpy(cpuc->assign, assign, n*sizeof(int));
1067
1068 done_collect:
1069         /*
1070          * Commit the collect_events() state. See x86_pmu_del() and
1071          * x86_pmu_*_txn().
1072          */
1073         cpuc->n_events = n;
1074         cpuc->n_added += n - n0;
1075         cpuc->n_txn += n - n0;
1076
1077         ret = 0;
1078 out:
1079         perf_pmu_enable(event->pmu);
1080         return ret;
1081 }
1082
1083 static void x86_pmu_start(struct perf_event *event, int flags)
1084 {
1085         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1086         int idx = event->hw.idx;
1087
1088         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1089                 return;
1090
1091         if (WARN_ON_ONCE(idx == -1))
1092                 return;
1093
1094         if (flags & PERF_EF_RELOAD) {
1095                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1096                 x86_perf_event_set_period(event);
1097         }
1098
1099         event->hw.state = 0;
1100
1101         cpuc->events[idx] = event;
1102         __set_bit(idx, cpuc->active_mask);
1103         __set_bit(idx, cpuc->running);
1104         x86_pmu.enable(event);
1105         perf_event_update_userpage(event);
1106 }
1107
1108 void perf_event_print_debug(void)
1109 {
1110         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1111         u64 pebs;
1112         struct cpu_hw_events *cpuc;
1113         unsigned long flags;
1114         int cpu, idx;
1115
1116         if (!x86_pmu.num_counters)
1117                 return;
1118
1119         local_irq_save(flags);
1120
1121         cpu = smp_processor_id();
1122         cpuc = &per_cpu(cpu_hw_events, cpu);
1123
1124         if (x86_pmu.version >= 2) {
1125                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1126                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1127                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1128                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1129                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1130
1131                 pr_info("\n");
1132                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1133                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1134                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1135                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1136                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1137         }
1138         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1139
1140         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1141                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1142                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1143
1144                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1145
1146                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1147                         cpu, idx, pmc_ctrl);
1148                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1149                         cpu, idx, pmc_count);
1150                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1151                         cpu, idx, prev_left);
1152         }
1153         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1154                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1155
1156                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1157                         cpu, idx, pmc_count);
1158         }
1159         local_irq_restore(flags);
1160 }
1161
1162 void x86_pmu_stop(struct perf_event *event, int flags)
1163 {
1164         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1165         struct hw_perf_event *hwc = &event->hw;
1166
1167         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1168                 x86_pmu.disable(event);
1169                 cpuc->events[hwc->idx] = NULL;
1170                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1171                 hwc->state |= PERF_HES_STOPPED;
1172         }
1173
1174         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1175                 /*
1176                  * Drain the remaining delta count out of a event
1177                  * that we are disabling:
1178                  */
1179                 x86_perf_event_update(event);
1180                 hwc->state |= PERF_HES_UPTODATE;
1181         }
1182 }
1183
1184 static void x86_pmu_del(struct perf_event *event, int flags)
1185 {
1186         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1187         int i;
1188
1189         /*
1190          * event is descheduled
1191          */
1192         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1193
1194         /*
1195          * If we're called during a txn, we don't need to do anything.
1196          * The events never got scheduled and ->cancel_txn will truncate
1197          * the event_list.
1198          *
1199          * XXX assumes any ->del() called during a TXN will only be on
1200          * an event added during that same TXN.
1201          */
1202         if (cpuc->group_flag & PERF_EVENT_TXN)
1203                 return;
1204
1205         /*
1206          * Not a TXN, therefore cleanup properly.
1207          */
1208         x86_pmu_stop(event, PERF_EF_UPDATE);
1209
1210         for (i = 0; i < cpuc->n_events; i++) {
1211                 if (event == cpuc->event_list[i])
1212                         break;
1213         }
1214
1215         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1216                 return;
1217
1218         /* If we have a newly added event; make sure to decrease n_added. */
1219         if (i >= cpuc->n_events - cpuc->n_added)
1220                 --cpuc->n_added;
1221
1222         if (x86_pmu.put_event_constraints)
1223                 x86_pmu.put_event_constraints(cpuc, event);
1224
1225         /* Delete the array entry. */
1226         while (++i < cpuc->n_events)
1227                 cpuc->event_list[i-1] = cpuc->event_list[i];
1228         --cpuc->n_events;
1229
1230         perf_event_update_userpage(event);
1231 }
1232
1233 int x86_pmu_handle_irq(struct pt_regs *regs)
1234 {
1235         struct perf_sample_data data;
1236         struct cpu_hw_events *cpuc;
1237         struct perf_event *event;
1238         int idx, handled = 0;
1239         u64 val;
1240
1241         cpuc = this_cpu_ptr(&cpu_hw_events);
1242
1243         /*
1244          * Some chipsets need to unmask the LVTPC in a particular spot
1245          * inside the nmi handler.  As a result, the unmasking was pushed
1246          * into all the nmi handlers.
1247          *
1248          * This generic handler doesn't seem to have any issues where the
1249          * unmasking occurs so it was left at the top.
1250          */
1251         apic_write(APIC_LVTPC, APIC_DM_NMI);
1252
1253         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1254                 if (!test_bit(idx, cpuc->active_mask)) {
1255                         /*
1256                          * Though we deactivated the counter some cpus
1257                          * might still deliver spurious interrupts still
1258                          * in flight. Catch them:
1259                          */
1260                         if (__test_and_clear_bit(idx, cpuc->running))
1261                                 handled++;
1262                         continue;
1263                 }
1264
1265                 event = cpuc->events[idx];
1266
1267                 val = x86_perf_event_update(event);
1268                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1269                         continue;
1270
1271                 /*
1272                  * event overflow
1273                  */
1274                 handled++;
1275                 perf_sample_data_init(&data, 0, event->hw.last_period);
1276
1277                 if (!x86_perf_event_set_period(event))
1278                         continue;
1279
1280                 if (perf_event_overflow(event, &data, regs))
1281                         x86_pmu_stop(event, 0);
1282         }
1283
1284         if (handled)
1285                 inc_irq_stat(apic_perf_irqs);
1286
1287         return handled;
1288 }
1289
1290 void perf_events_lapic_init(void)
1291 {
1292         if (!x86_pmu.apic || !x86_pmu_initialized())
1293                 return;
1294
1295         /*
1296          * Always use NMI for PMU
1297          */
1298         apic_write(APIC_LVTPC, APIC_DM_NMI);
1299 }
1300
1301 static int
1302 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1303 {
1304         u64 start_clock;
1305         u64 finish_clock;
1306         int ret;
1307
1308         if (!atomic_read(&active_events))
1309                 return NMI_DONE;
1310
1311         start_clock = sched_clock();
1312         ret = x86_pmu.handle_irq(regs);
1313         finish_clock = sched_clock();
1314
1315         perf_sample_event_took(finish_clock - start_clock);
1316
1317         return ret;
1318 }
1319 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1320
1321 struct event_constraint emptyconstraint;
1322 struct event_constraint unconstrained;
1323
1324 static int
1325 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1326 {
1327         unsigned int cpu = (long)hcpu;
1328         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1329         int ret = NOTIFY_OK;
1330
1331         switch (action & ~CPU_TASKS_FROZEN) {
1332         case CPU_UP_PREPARE:
1333                 cpuc->kfree_on_online = NULL;
1334                 if (x86_pmu.cpu_prepare)
1335                         ret = x86_pmu.cpu_prepare(cpu);
1336                 break;
1337
1338         case CPU_STARTING:
1339                 if (x86_pmu.attr_rdpmc)
1340                         set_in_cr4(X86_CR4_PCE);
1341                 if (x86_pmu.cpu_starting)
1342                         x86_pmu.cpu_starting(cpu);
1343                 break;
1344
1345         case CPU_ONLINE:
1346                 kfree(cpuc->kfree_on_online);
1347                 break;
1348
1349         case CPU_DYING:
1350                 if (x86_pmu.cpu_dying)
1351                         x86_pmu.cpu_dying(cpu);
1352                 break;
1353
1354         case CPU_UP_CANCELED:
1355         case CPU_DEAD:
1356                 if (x86_pmu.cpu_dead)
1357                         x86_pmu.cpu_dead(cpu);
1358                 break;
1359
1360         default:
1361                 break;
1362         }
1363
1364         return ret;
1365 }
1366
1367 static void __init pmu_check_apic(void)
1368 {
1369         if (cpu_has_apic)
1370                 return;
1371
1372         x86_pmu.apic = 0;
1373         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1374         pr_info("no hardware sampling interrupt available.\n");
1375
1376         /*
1377          * If we have a PMU initialized but no APIC
1378          * interrupts, we cannot sample hardware
1379          * events (user-space has to fall back and
1380          * sample via a hrtimer based software event):
1381          */
1382         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1383
1384 }
1385
1386 static struct attribute_group x86_pmu_format_group = {
1387         .name = "format",
1388         .attrs = NULL,
1389 };
1390
1391 /*
1392  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1393  * out of events_attr attributes.
1394  */
1395 static void __init filter_events(struct attribute **attrs)
1396 {
1397         struct device_attribute *d;
1398         struct perf_pmu_events_attr *pmu_attr;
1399         int i, j;
1400
1401         for (i = 0; attrs[i]; i++) {
1402                 d = (struct device_attribute *)attrs[i];
1403                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1404                 /* str trumps id */
1405                 if (pmu_attr->event_str)
1406                         continue;
1407                 if (x86_pmu.event_map(i))
1408                         continue;
1409
1410                 for (j = i; attrs[j]; j++)
1411                         attrs[j] = attrs[j + 1];
1412
1413                 /* Check the shifted attr. */
1414                 i--;
1415         }
1416 }
1417
1418 /* Merge two pointer arrays */
1419 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1420 {
1421         struct attribute **new;
1422         int j, i;
1423
1424         for (j = 0; a[j]; j++)
1425                 ;
1426         for (i = 0; b[i]; i++)
1427                 j++;
1428         j++;
1429
1430         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1431         if (!new)
1432                 return NULL;
1433
1434         j = 0;
1435         for (i = 0; a[i]; i++)
1436                 new[j++] = a[i];
1437         for (i = 0; b[i]; i++)
1438                 new[j++] = b[i];
1439         new[j] = NULL;
1440
1441         return new;
1442 }
1443
1444 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1445                           char *page)
1446 {
1447         struct perf_pmu_events_attr *pmu_attr = \
1448                 container_of(attr, struct perf_pmu_events_attr, attr);
1449         u64 config = x86_pmu.event_map(pmu_attr->id);
1450
1451         /* string trumps id */
1452         if (pmu_attr->event_str)
1453                 return sprintf(page, "%s", pmu_attr->event_str);
1454
1455         return x86_pmu.events_sysfs_show(page, config);
1456 }
1457
1458 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1459 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1460 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1461 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1462 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1463 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1464 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1465 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1466 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1467 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1468
1469 static struct attribute *empty_attrs;
1470
1471 static struct attribute *events_attr[] = {
1472         EVENT_PTR(CPU_CYCLES),
1473         EVENT_PTR(INSTRUCTIONS),
1474         EVENT_PTR(CACHE_REFERENCES),
1475         EVENT_PTR(CACHE_MISSES),
1476         EVENT_PTR(BRANCH_INSTRUCTIONS),
1477         EVENT_PTR(BRANCH_MISSES),
1478         EVENT_PTR(BUS_CYCLES),
1479         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1480         EVENT_PTR(STALLED_CYCLES_BACKEND),
1481         EVENT_PTR(REF_CPU_CYCLES),
1482         NULL,
1483 };
1484
1485 static struct attribute_group x86_pmu_events_group = {
1486         .name = "events",
1487         .attrs = events_attr,
1488 };
1489
1490 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1491 {
1492         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1493         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1494         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1495         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1496         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1497         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1498         ssize_t ret;
1499
1500         /*
1501         * We have whole page size to spend and just little data
1502         * to write, so we can safely use sprintf.
1503         */
1504         ret = sprintf(page, "event=0x%02llx", event);
1505
1506         if (umask)
1507                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1508
1509         if (edge)
1510                 ret += sprintf(page + ret, ",edge");
1511
1512         if (pc)
1513                 ret += sprintf(page + ret, ",pc");
1514
1515         if (any)
1516                 ret += sprintf(page + ret, ",any");
1517
1518         if (inv)
1519                 ret += sprintf(page + ret, ",inv");
1520
1521         if (cmask)
1522                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1523
1524         ret += sprintf(page + ret, "\n");
1525
1526         return ret;
1527 }
1528
1529 static int __init init_hw_perf_events(void)
1530 {
1531         struct x86_pmu_quirk *quirk;
1532         int err;
1533
1534         pr_info("Performance Events: ");
1535
1536         switch (boot_cpu_data.x86_vendor) {
1537         case X86_VENDOR_INTEL:
1538                 err = intel_pmu_init();
1539                 break;
1540         case X86_VENDOR_AMD:
1541                 err = amd_pmu_init();
1542                 break;
1543         default:
1544                 err = -ENOTSUPP;
1545         }
1546         if (err != 0) {
1547                 pr_cont("no PMU driver, software events only.\n");
1548                 return 0;
1549         }
1550
1551         pmu_check_apic();
1552
1553         /* sanity check that the hardware exists or is emulated */
1554         if (!check_hw_exists())
1555                 return 0;
1556
1557         pr_cont("%s PMU driver.\n", x86_pmu.name);
1558
1559         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1560
1561         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1562                 quirk->func();
1563
1564         if (!x86_pmu.intel_ctrl)
1565                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1566
1567         perf_events_lapic_init();
1568         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1569
1570         unconstrained = (struct event_constraint)
1571                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1572                                    0, x86_pmu.num_counters, 0, 0);
1573
1574         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1575
1576         if (x86_pmu.event_attrs)
1577                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1578
1579         if (!x86_pmu.events_sysfs_show)
1580                 x86_pmu_events_group.attrs = &empty_attrs;
1581         else
1582                 filter_events(x86_pmu_events_group.attrs);
1583
1584         if (x86_pmu.cpu_events) {
1585                 struct attribute **tmp;
1586
1587                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1588                 if (!WARN_ON(!tmp))
1589                         x86_pmu_events_group.attrs = tmp;
1590         }
1591
1592         pr_info("... version:                %d\n",     x86_pmu.version);
1593         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1594         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1595         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1596         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1597         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1598         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1599
1600         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1601         perf_cpu_notifier(x86_pmu_notifier);
1602
1603         return 0;
1604 }
1605 early_initcall(init_hw_perf_events);
1606
1607 static inline void x86_pmu_read(struct perf_event *event)
1608 {
1609         x86_perf_event_update(event);
1610 }
1611
1612 /*
1613  * Start group events scheduling transaction
1614  * Set the flag to make pmu::enable() not perform the
1615  * schedulability test, it will be performed at commit time
1616  */
1617 static void x86_pmu_start_txn(struct pmu *pmu)
1618 {
1619         perf_pmu_disable(pmu);
1620         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1621         __this_cpu_write(cpu_hw_events.n_txn, 0);
1622 }
1623
1624 /*
1625  * Stop group events scheduling transaction
1626  * Clear the flag and pmu::enable() will perform the
1627  * schedulability test.
1628  */
1629 static void x86_pmu_cancel_txn(struct pmu *pmu)
1630 {
1631         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1632         /*
1633          * Truncate collected array by the number of events added in this
1634          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1635          */
1636         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1637         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1638         perf_pmu_enable(pmu);
1639 }
1640
1641 /*
1642  * Commit group events scheduling transaction
1643  * Perform the group schedulability test as a whole
1644  * Return 0 if success
1645  *
1646  * Does not cancel the transaction on failure; expects the caller to do this.
1647  */
1648 static int x86_pmu_commit_txn(struct pmu *pmu)
1649 {
1650         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1651         int assign[X86_PMC_IDX_MAX];
1652         int n, ret;
1653
1654         n = cpuc->n_events;
1655
1656         if (!x86_pmu_initialized())
1657                 return -EAGAIN;
1658
1659         ret = x86_pmu.schedule_events(cpuc, n, assign);
1660         if (ret)
1661                 return ret;
1662
1663         /*
1664          * copy new assignment, now we know it is possible
1665          * will be used by hw_perf_enable()
1666          */
1667         memcpy(cpuc->assign, assign, n*sizeof(int));
1668
1669         cpuc->group_flag &= ~PERF_EVENT_TXN;
1670         perf_pmu_enable(pmu);
1671         return 0;
1672 }
1673 /*
1674  * a fake_cpuc is used to validate event groups. Due to
1675  * the extra reg logic, we need to also allocate a fake
1676  * per_core and per_cpu structure. Otherwise, group events
1677  * using extra reg may conflict without the kernel being
1678  * able to catch this when the last event gets added to
1679  * the group.
1680  */
1681 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1682 {
1683         kfree(cpuc->shared_regs);
1684         kfree(cpuc);
1685 }
1686
1687 static struct cpu_hw_events *allocate_fake_cpuc(void)
1688 {
1689         struct cpu_hw_events *cpuc;
1690         int cpu = raw_smp_processor_id();
1691
1692         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1693         if (!cpuc)
1694                 return ERR_PTR(-ENOMEM);
1695
1696         /* only needed, if we have extra_regs */
1697         if (x86_pmu.extra_regs) {
1698                 cpuc->shared_regs = allocate_shared_regs(cpu);
1699                 if (!cpuc->shared_regs)
1700                         goto error;
1701         }
1702         cpuc->is_fake = 1;
1703         return cpuc;
1704 error:
1705         free_fake_cpuc(cpuc);
1706         return ERR_PTR(-ENOMEM);
1707 }
1708
1709 /*
1710  * validate that we can schedule this event
1711  */
1712 static int validate_event(struct perf_event *event)
1713 {
1714         struct cpu_hw_events *fake_cpuc;
1715         struct event_constraint *c;
1716         int ret = 0;
1717
1718         fake_cpuc = allocate_fake_cpuc();
1719         if (IS_ERR(fake_cpuc))
1720                 return PTR_ERR(fake_cpuc);
1721
1722         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1723
1724         if (!c || !c->weight)
1725                 ret = -EINVAL;
1726
1727         if (x86_pmu.put_event_constraints)
1728                 x86_pmu.put_event_constraints(fake_cpuc, event);
1729
1730         free_fake_cpuc(fake_cpuc);
1731
1732         return ret;
1733 }
1734
1735 /*
1736  * validate a single event group
1737  *
1738  * validation include:
1739  *      - check events are compatible which each other
1740  *      - events do not compete for the same counter
1741  *      - number of events <= number of counters
1742  *
1743  * validation ensures the group can be loaded onto the
1744  * PMU if it was the only group available.
1745  */
1746 static int validate_group(struct perf_event *event)
1747 {
1748         struct perf_event *leader = event->group_leader;
1749         struct cpu_hw_events *fake_cpuc;
1750         int ret = -EINVAL, n;
1751
1752         fake_cpuc = allocate_fake_cpuc();
1753         if (IS_ERR(fake_cpuc))
1754                 return PTR_ERR(fake_cpuc);
1755         /*
1756          * the event is not yet connected with its
1757          * siblings therefore we must first collect
1758          * existing siblings, then add the new event
1759          * before we can simulate the scheduling
1760          */
1761         n = collect_events(fake_cpuc, leader, true);
1762         if (n < 0)
1763                 goto out;
1764
1765         fake_cpuc->n_events = n;
1766         n = collect_events(fake_cpuc, event, false);
1767         if (n < 0)
1768                 goto out;
1769
1770         fake_cpuc->n_events = n;
1771
1772         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1773
1774 out:
1775         free_fake_cpuc(fake_cpuc);
1776         return ret;
1777 }
1778
1779 static int x86_pmu_event_init(struct perf_event *event)
1780 {
1781         struct pmu *tmp;
1782         int err;
1783
1784         switch (event->attr.type) {
1785         case PERF_TYPE_RAW:
1786         case PERF_TYPE_HARDWARE:
1787         case PERF_TYPE_HW_CACHE:
1788                 break;
1789
1790         default:
1791                 return -ENOENT;
1792         }
1793
1794         err = __x86_pmu_event_init(event);
1795         if (!err) {
1796                 /*
1797                  * we temporarily connect event to its pmu
1798                  * such that validate_group() can classify
1799                  * it as an x86 event using is_x86_event()
1800                  */
1801                 tmp = event->pmu;
1802                 event->pmu = &pmu;
1803
1804                 if (event->group_leader != event)
1805                         err = validate_group(event);
1806                 else
1807                         err = validate_event(event);
1808
1809                 event->pmu = tmp;
1810         }
1811         if (err) {
1812                 if (event->destroy)
1813                         event->destroy(event);
1814         }
1815
1816         return err;
1817 }
1818
1819 static int x86_pmu_event_idx(struct perf_event *event)
1820 {
1821         int idx = event->hw.idx;
1822
1823         if (!x86_pmu.attr_rdpmc)
1824                 return 0;
1825
1826         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1827                 idx -= INTEL_PMC_IDX_FIXED;
1828                 idx |= 1 << 30;
1829         }
1830
1831         return idx + 1;
1832 }
1833
1834 static ssize_t get_attr_rdpmc(struct device *cdev,
1835                               struct device_attribute *attr,
1836                               char *buf)
1837 {
1838         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1839 }
1840
1841 static void change_rdpmc(void *info)
1842 {
1843         bool enable = !!(unsigned long)info;
1844
1845         if (enable)
1846                 set_in_cr4(X86_CR4_PCE);
1847         else
1848                 clear_in_cr4(X86_CR4_PCE);
1849 }
1850
1851 static ssize_t set_attr_rdpmc(struct device *cdev,
1852                               struct device_attribute *attr,
1853                               const char *buf, size_t count)
1854 {
1855         unsigned long val;
1856         ssize_t ret;
1857
1858         ret = kstrtoul(buf, 0, &val);
1859         if (ret)
1860                 return ret;
1861
1862         if (x86_pmu.attr_rdpmc_broken)
1863                 return -ENOTSUPP;
1864
1865         if (!!val != !!x86_pmu.attr_rdpmc) {
1866                 x86_pmu.attr_rdpmc = !!val;
1867                 on_each_cpu(change_rdpmc, (void *)val, 1);
1868         }
1869
1870         return count;
1871 }
1872
1873 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1874
1875 static struct attribute *x86_pmu_attrs[] = {
1876         &dev_attr_rdpmc.attr,
1877         NULL,
1878 };
1879
1880 static struct attribute_group x86_pmu_attr_group = {
1881         .attrs = x86_pmu_attrs,
1882 };
1883
1884 static const struct attribute_group *x86_pmu_attr_groups[] = {
1885         &x86_pmu_attr_group,
1886         &x86_pmu_format_group,
1887         &x86_pmu_events_group,
1888         NULL,
1889 };
1890
1891 static void x86_pmu_flush_branch_stack(void)
1892 {
1893         if (x86_pmu.flush_branch_stack)
1894                 x86_pmu.flush_branch_stack();
1895 }
1896
1897 void perf_check_microcode(void)
1898 {
1899         if (x86_pmu.check_microcode)
1900                 x86_pmu.check_microcode();
1901 }
1902 EXPORT_SYMBOL_GPL(perf_check_microcode);
1903
1904 static struct pmu pmu = {
1905         .pmu_enable             = x86_pmu_enable,
1906         .pmu_disable            = x86_pmu_disable,
1907
1908         .attr_groups            = x86_pmu_attr_groups,
1909
1910         .event_init             = x86_pmu_event_init,
1911
1912         .add                    = x86_pmu_add,
1913         .del                    = x86_pmu_del,
1914         .start                  = x86_pmu_start,
1915         .stop                   = x86_pmu_stop,
1916         .read                   = x86_pmu_read,
1917
1918         .start_txn              = x86_pmu_start_txn,
1919         .cancel_txn             = x86_pmu_cancel_txn,
1920         .commit_txn             = x86_pmu_commit_txn,
1921
1922         .event_idx              = x86_pmu_event_idx,
1923         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1924 };
1925
1926 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1927 {
1928         struct cyc2ns_data *data;
1929
1930         userpg->cap_user_time = 0;
1931         userpg->cap_user_time_zero = 0;
1932         userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1933         userpg->pmc_width = x86_pmu.cntval_bits;
1934
1935         if (!sched_clock_stable())
1936                 return;
1937
1938         data = cyc2ns_read_begin();
1939
1940         userpg->cap_user_time = 1;
1941         userpg->time_mult = data->cyc2ns_mul;
1942         userpg->time_shift = data->cyc2ns_shift;
1943         userpg->time_offset = data->cyc2ns_offset - now;
1944
1945         userpg->cap_user_time_zero = 1;
1946         userpg->time_zero = data->cyc2ns_offset;
1947
1948         cyc2ns_read_end(data);
1949 }
1950
1951 /*
1952  * callchain support
1953  */
1954
1955 static int backtrace_stack(void *data, char *name)
1956 {
1957         return 0;
1958 }
1959
1960 static void backtrace_address(void *data, unsigned long addr, int reliable)
1961 {
1962         struct perf_callchain_entry *entry = data;
1963
1964         perf_callchain_store(entry, addr);
1965 }
1966
1967 static const struct stacktrace_ops backtrace_ops = {
1968         .stack                  = backtrace_stack,
1969         .address                = backtrace_address,
1970         .walk_stack             = print_context_stack_bp,
1971 };
1972
1973 void
1974 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1975 {
1976         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1977                 /* TODO: We don't support guest os callchain now */
1978                 return;
1979         }
1980
1981         perf_callchain_store(entry, regs->ip);
1982
1983         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1984 }
1985
1986 static inline int
1987 valid_user_frame(const void __user *fp, unsigned long size)
1988 {
1989         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1990 }
1991
1992 static unsigned long get_segment_base(unsigned int segment)
1993 {
1994         struct desc_struct *desc;
1995         int idx = segment >> 3;
1996
1997         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1998                 if (idx > LDT_ENTRIES)
1999                         return 0;
2000
2001                 if (idx > current->active_mm->context.size)
2002                         return 0;
2003
2004                 desc = current->active_mm->context.ldt;
2005         } else {
2006                 if (idx > GDT_ENTRIES)
2007                         return 0;
2008
2009                 desc = raw_cpu_ptr(gdt_page.gdt);
2010         }
2011
2012         return get_desc_base(desc + idx);
2013 }
2014
2015 #ifdef CONFIG_COMPAT
2016
2017 #include <asm/compat.h>
2018
2019 static inline int
2020 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2021 {
2022         /* 32-bit process in 64-bit kernel. */
2023         unsigned long ss_base, cs_base;
2024         struct stack_frame_ia32 frame;
2025         const void __user *fp;
2026
2027         if (!test_thread_flag(TIF_IA32))
2028                 return 0;
2029
2030         cs_base = get_segment_base(regs->cs);
2031         ss_base = get_segment_base(regs->ss);
2032
2033         fp = compat_ptr(ss_base + regs->bp);
2034         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2035                 unsigned long bytes;
2036                 frame.next_frame     = 0;
2037                 frame.return_address = 0;
2038
2039                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2040                 if (bytes != 0)
2041                         break;
2042
2043                 if (!valid_user_frame(fp, sizeof(frame)))
2044                         break;
2045
2046                 perf_callchain_store(entry, cs_base + frame.return_address);
2047                 fp = compat_ptr(ss_base + frame.next_frame);
2048         }
2049         return 1;
2050 }
2051 #else
2052 static inline int
2053 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2054 {
2055     return 0;
2056 }
2057 #endif
2058
2059 void
2060 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2061 {
2062         struct stack_frame frame;
2063         const void __user *fp;
2064
2065         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2066                 /* TODO: We don't support guest os callchain now */
2067                 return;
2068         }
2069
2070         /*
2071          * We don't know what to do with VM86 stacks.. ignore them for now.
2072          */
2073         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2074                 return;
2075
2076         fp = (void __user *)regs->bp;
2077
2078         perf_callchain_store(entry, regs->ip);
2079
2080         if (!current->mm)
2081                 return;
2082
2083         if (perf_callchain_user32(regs, entry))
2084                 return;
2085
2086         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2087                 unsigned long bytes;
2088                 frame.next_frame             = NULL;
2089                 frame.return_address = 0;
2090
2091                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2092                 if (bytes != 0)
2093                         break;
2094
2095                 if (!valid_user_frame(fp, sizeof(frame)))
2096                         break;
2097
2098                 perf_callchain_store(entry, frame.return_address);
2099                 fp = frame.next_frame;
2100         }
2101 }
2102
2103 /*
2104  * Deal with code segment offsets for the various execution modes:
2105  *
2106  *   VM86 - the good olde 16 bit days, where the linear address is
2107  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2108  *
2109  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2110  *          to figure out what the 32bit base address is.
2111  *
2112  *    X32 - has TIF_X32 set, but is running in x86_64
2113  *
2114  * X86_64 - CS,DS,SS,ES are all zero based.
2115  */
2116 static unsigned long code_segment_base(struct pt_regs *regs)
2117 {
2118         /*
2119          * If we are in VM86 mode, add the segment offset to convert to a
2120          * linear address.
2121          */
2122         if (regs->flags & X86_VM_MASK)
2123                 return 0x10 * regs->cs;
2124
2125         /*
2126          * For IA32 we look at the GDT/LDT segment base to convert the
2127          * effective IP to a linear address.
2128          */
2129 #ifdef CONFIG_X86_32
2130         if (user_mode(regs) && regs->cs != __USER_CS)
2131                 return get_segment_base(regs->cs);
2132 #else
2133         if (test_thread_flag(TIF_IA32)) {
2134                 if (user_mode(regs) && regs->cs != __USER32_CS)
2135                         return get_segment_base(regs->cs);
2136         }
2137 #endif
2138         return 0;
2139 }
2140
2141 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2142 {
2143         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2144                 return perf_guest_cbs->get_guest_ip();
2145
2146         return regs->ip + code_segment_base(regs);
2147 }
2148
2149 unsigned long perf_misc_flags(struct pt_regs *regs)
2150 {
2151         int misc = 0;
2152
2153         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2154                 if (perf_guest_cbs->is_user_mode())
2155                         misc |= PERF_RECORD_MISC_GUEST_USER;
2156                 else
2157                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2158         } else {
2159                 if (user_mode(regs))
2160                         misc |= PERF_RECORD_MISC_USER;
2161                 else
2162                         misc |= PERF_RECORD_MISC_KERNEL;
2163         }
2164
2165         if (regs->flags & PERF_EFLAGS_EXACT)
2166                 misc |= PERF_RECORD_MISC_EXACT_IP;
2167
2168         return misc;
2169 }
2170
2171 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2172 {
2173         cap->version            = x86_pmu.version;
2174         cap->num_counters_gp    = x86_pmu.num_counters;
2175         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2176         cap->bit_width_gp       = x86_pmu.cntval_bits;
2177         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2178         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2179         cap->events_mask_len    = x86_pmu.events_mask_len;
2180 }
2181 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);