arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  15
  16 /*
  17  * pebs_record_32 for p4 and core not supported
  18
  19 struct pebs_record_32 {
  20         u32 flags, ip;
  21         u32 ax, bc, cx, dx;
  22         u32 si, di, bp, sp;
  23 };
  24
  25  */
  26
  27 union intel_x86_pebs_dse {
  28         u64 val;
  29         struct {
  30                 unsigned int ld_dse:4;
  31                 unsigned int ld_stlb_miss:1;
  32                 unsigned int ld_locked:1;
  33                 unsigned int ld_reserved:26;
  34         };
  35         struct {
  36                 unsigned int st_l1d_hit:1;
  37                 unsigned int st_reserved1:3;
  38                 unsigned int st_stlb_miss:1;
  39                 unsigned int st_locked:1;
  40                 unsigned int st_reserved2:26;
  41         };
  42 };
  43
  44
  45 /*
  46  * Map PEBS Load Latency Data Source encodings to generic
  47  * memory data source information
  48  */
  49 #define P(a, b) PERF_MEM_S(a, b)
  50 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  51 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  52
  53 static const u64 pebs_data_source[] = {
  54         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  55         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  56         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  57         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  58         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  62         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  64         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  65         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  66         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  67         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  68         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  69         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  70 };
  71
  72 static u64 precise_store_data(u64 status)
  73 {
  74         union intel_x86_pebs_dse dse;
  75         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  76
  77         dse.val = status;
  78
  79         /*
  80          * bit 4: TLB access
  81          * 1 = stored missed 2nd level TLB
  82          *
  83          * so it either hit the walker or the OS
  84          * otherwise hit 2nd level TLB
  85          */
  86         if (dse.st_stlb_miss)
  87                 val |= P(TLB, MISS);
  88         else
  89                 val |= P(TLB, HIT);
  90
  91         /*
  92          * bit 0: hit L1 data cache
  93          * if not set, then all we know is that
  94          * it missed L1D
  95          */
  96         if (dse.st_l1d_hit)
  97                 val |= P(LVL, HIT);
  98         else
  99                 val |= P(LVL, MISS);
 100
 101         /*
 102          * bit 5: Locked prefix
 103          */
 104         if (dse.st_locked)
 105                 val |= P(LOCK, LOCKED);
 106
 107         return val;
 108 }
 109
 110 static u64 precise_store_data_hsw(u64 status)
 111 {
 112         union perf_mem_data_src dse;
 113
 114         dse.val = 0;
 115         dse.mem_op = PERF_MEM_OP_STORE;
 116         dse.mem_lvl = PERF_MEM_LVL_NA;
 117         if (status & 1)
 118                 dse.mem_lvl = PERF_MEM_LVL_L1;
 119         /* Nothing else supported. Sorry. */
 120         return dse.val;
 121 }
 122
 123 static u64 load_latency_data(u64 status)
 124 {
 125         union intel_x86_pebs_dse dse;
 126         u64 val;
 127         int model = boot_cpu_data.x86_model;
 128         int fam = boot_cpu_data.x86;
 129
 130         dse.val = status;
 131
 132         /*
 133          * use the mapping table for bit 0-3
 134          */
 135         val = pebs_data_source[dse.ld_dse];
 136
 137         /*
 138          * Nehalem models do not support TLB, Lock infos
 139          */
 140         if (fam == 0x6 && (model == 26 || model == 30
 141             || model == 31 || model == 46)) {
 142                 val |= P(TLB, NA) | P(LOCK, NA);
 143                 return val;
 144         }
 145         /*
 146          * bit 4: TLB access
 147          * 0 = did not miss 2nd level TLB
 148          * 1 = missed 2nd level TLB
 149          */
 150         if (dse.ld_stlb_miss)
 151                 val |= P(TLB, MISS) | P(TLB, L2);
 152         else
 153                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 154
 155         /*
 156          * bit 5: locked prefix
 157          */
 158         if (dse.ld_locked)
 159                 val |= P(LOCK, LOCKED);
 160
 161         return val;
 162 }
 163
 164 struct pebs_record_core {
 165         u64 flags, ip;
 166         u64 ax, bx, cx, dx;
 167         u64 si, di, bp, sp;
 168         u64 r8,  r9,  r10, r11;
 169         u64 r12, r13, r14, r15;
 170 };
 171
 172 struct pebs_record_nhm {
 173         u64 flags, ip;
 174         u64 ax, bx, cx, dx;
 175         u64 si, di, bp, sp;
 176         u64 r8,  r9,  r10, r11;
 177         u64 r12, r13, r14, r15;
 178         u64 status, dla, dse, lat;
 179 };
 180
 181 /*
 182  * Same as pebs_record_nhm, with two additional fields.
 183  */
 184 struct pebs_record_hsw {
 185         u64 flags, ip;
 186         u64 ax, bx, cx, dx;
 187         u64 si, di, bp, sp;
 188         u64 r8,  r9,  r10, r11;
 189         u64 r12, r13, r14, r15;
 190         u64 status, dla, dse, lat;
 191         u64 real_ip; /* the actual eventing ip */
 192         u64 tsx_tuning; /* TSX abort cycles and flags */
 193 };
 194
 195 union hsw_tsx_tuning {
 196         struct {
 197                 u32 cycles_last_block     : 32,
 198                     hle_abort             : 1,
 199                     rtm_abort             : 1,
 200                     instruction_abort     : 1,
 201                     non_instruction_abort : 1,
 202                     retry                 : 1,
 203                     data_conflict         : 1,
 204                     capacity_writes       : 1,
 205                     capacity_reads        : 1;
 206         };
 207         u64         value;
 208 };
 209
 210 void init_debug_store_on_cpu(int cpu)
 211 {
 212         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 213
 214         if (!ds)
 215                 return;
 216
 217         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 218                      (u32)((u64)(unsigned long)ds),
 219                      (u32)((u64)(unsigned long)ds >> 32));
 220 }
 221
 222 void fini_debug_store_on_cpu(int cpu)
 223 {
 224         if (!per_cpu(cpu_hw_events, cpu).ds)
 225                 return;
 226
 227         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 228 }
 229
 230 static int alloc_pebs_buffer(int cpu)
 231 {
 232         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 233         int node = cpu_to_node(cpu);
 234         int max, thresh = 1; /* always use a single PEBS record */
 235         void *buffer;
 236
 237         if (!x86_pmu.pebs)
 238                 return 0;
 239
 240         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 241         if (unlikely(!buffer))
 242                 return -ENOMEM;
 243
 244         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 245
 246         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 247         ds->pebs_index = ds->pebs_buffer_base;
 248         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 249                 max * x86_pmu.pebs_record_size;
 250
 251         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 252                 thresh * x86_pmu.pebs_record_size;
 253
 254         return 0;
 255 }
 256
 257 static void release_pebs_buffer(int cpu)
 258 {
 259         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 260
 261         if (!ds || !x86_pmu.pebs)
 262                 return;
 263
 264         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 265         ds->pebs_buffer_base = 0;
 266 }
 267
 268 static int alloc_bts_buffer(int cpu)
 269 {
 270         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 271         int node = cpu_to_node(cpu);
 272         int max, thresh;
 273         void *buffer;
 274
 275         if (!x86_pmu.bts)
 276                 return 0;
 277
 278         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL, node);
 279         if (unlikely(!buffer))
 280                 return -ENOMEM;
 281
 282         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 283         thresh = max / 16;
 284
 285         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 286         ds->bts_index = ds->bts_buffer_base;
 287         ds->bts_absolute_maximum = ds->bts_buffer_base +
 288                 max * BTS_RECORD_SIZE;
 289         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 290                 thresh * BTS_RECORD_SIZE;
 291
 292         return 0;
 293 }
 294
 295 static void release_bts_buffer(int cpu)
 296 {
 297         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 298
 299         if (!ds || !x86_pmu.bts)
 300                 return;
 301
 302         kfree((void *)(unsigned long)ds->bts_buffer_base);
 303         ds->bts_buffer_base = 0;
 304 }
 305
 306 static int alloc_ds_buffer(int cpu)
 307 {
 308         int node = cpu_to_node(cpu);
 309         struct debug_store *ds;
 310
 311         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 312         if (unlikely(!ds))
 313                 return -ENOMEM;
 314
 315         per_cpu(cpu_hw_events, cpu).ds = ds;
 316
 317         return 0;
 318 }
 319
 320 static void release_ds_buffer(int cpu)
 321 {
 322         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 323
 324         if (!ds)
 325                 return;
 326
 327         per_cpu(cpu_hw_events, cpu).ds = NULL;
 328         kfree(ds);
 329 }
 330
 331 void release_ds_buffers(void)
 332 {
 333         int cpu;
 334
 335         if (!x86_pmu.bts && !x86_pmu.pebs)
 336                 return;
 337
 338         get_online_cpus();
 339         for_each_online_cpu(cpu)
 340                 fini_debug_store_on_cpu(cpu);
 341
 342         for_each_possible_cpu(cpu) {
 343                 release_pebs_buffer(cpu);
 344                 release_bts_buffer(cpu);
 345                 release_ds_buffer(cpu);
 346         }
 347         put_online_cpus();
 348 }
 349
 350 void reserve_ds_buffers(void)
 351 {
 352         int bts_err = 0, pebs_err = 0;
 353         int cpu;
 354
 355         x86_pmu.bts_active = 0;
 356         x86_pmu.pebs_active = 0;
 357
 358         if (!x86_pmu.bts && !x86_pmu.pebs)
 359                 return;
 360
 361         if (!x86_pmu.bts)
 362                 bts_err = 1;
 363
 364         if (!x86_pmu.pebs)
 365                 pebs_err = 1;
 366
 367         get_online_cpus();
 368
 369         for_each_possible_cpu(cpu) {
 370                 if (alloc_ds_buffer(cpu)) {
 371                         bts_err = 1;
 372                         pebs_err = 1;
 373                 }
 374
 375                 if (!bts_err && alloc_bts_buffer(cpu))
 376                         bts_err = 1;
 377
 378                 if (!pebs_err && alloc_pebs_buffer(cpu))
 379                         pebs_err = 1;
 380
 381                 if (bts_err && pebs_err)
 382                         break;
 383         }
 384
 385         if (bts_err) {
 386                 for_each_possible_cpu(cpu)
 387                         release_bts_buffer(cpu);
 388         }
 389
 390         if (pebs_err) {
 391                 for_each_possible_cpu(cpu)
 392                         release_pebs_buffer(cpu);
 393         }
 394
 395         if (bts_err && pebs_err) {
 396                 for_each_possible_cpu(cpu)
 397                         release_ds_buffer(cpu);
 398         } else {
 399                 if (x86_pmu.bts && !bts_err)
 400                         x86_pmu.bts_active = 1;
 401
 402                 if (x86_pmu.pebs && !pebs_err)
 403                         x86_pmu.pebs_active = 1;
 404
 405                 for_each_online_cpu(cpu)
 406                         init_debug_store_on_cpu(cpu);
 407         }
 408
 409         put_online_cpus();
 410 }
 411
 412 /*
 413  * BTS
 414  */
 415
 416 struct event_constraint bts_constraint =
 417         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 418
 419 void intel_pmu_enable_bts(u64 config)
 420 {
 421         unsigned long debugctlmsr;
 422
 423         debugctlmsr = get_debugctlmsr();
 424
 425         debugctlmsr |= DEBUGCTLMSR_TR;
 426         debugctlmsr |= DEBUGCTLMSR_BTS;
 427         debugctlmsr |= DEBUGCTLMSR_BTINT;
 428
 429         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 430                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 431
 432         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 433                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 434
 435         update_debugctlmsr(debugctlmsr);
 436 }
 437
 438 void intel_pmu_disable_bts(void)
 439 {
 440         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 441         unsigned long debugctlmsr;
 442
 443         if (!cpuc->ds)
 444                 return;
 445
 446         debugctlmsr = get_debugctlmsr();
 447
 448         debugctlmsr &=
 449                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 450                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 451
 452         update_debugctlmsr(debugctlmsr);
 453 }
 454
 455 int intel_pmu_drain_bts_buffer(void)
 456 {
 457         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 458         struct debug_store *ds = cpuc->ds;
 459         struct bts_record {
 460                 u64     from;
 461                 u64     to;
 462                 u64     flags;
 463         };
 464         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 465         struct bts_record *at, *top;
 466         struct perf_output_handle handle;
 467         struct perf_event_header header;
 468         struct perf_sample_data data;
 469         struct pt_regs regs;
 470
 471         if (!event)
 472                 return 0;
 473
 474         if (!x86_pmu.bts_active)
 475                 return 0;
 476
 477         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 478         top = (struct bts_record *)(unsigned long)ds->bts_index;
 479
 480         if (top <= at)
 481                 return 0;
 482
 483         memset(&regs, 0, sizeof(regs));
 484
 485         ds->bts_index = ds->bts_buffer_base;
 486
 487         perf_sample_data_init(&data, 0, event->hw.last_period);
 488
 489         /*
 490          * Prepare a generic sample, i.e. fill in the invariant fields.
 491          * We will overwrite the from and to address before we output
 492          * the sample.
 493          */
 494         perf_prepare_sample(&header, &data, event, &regs);
 495
 496         if (perf_output_begin(&handle, event, header.size * (top - at)))
 497                 return 1;
 498
 499         for (; at < top; at++) {
 500                 data.ip         = at->from;
 501                 data.addr       = at->to;
 502
 503                 perf_output_sample(&handle, &header, &data, event);
 504         }
 505
 506         perf_output_end(&handle);
 507
 508         /* There's new data available. */
 509         event->hw.interrupts++;
 510         event->pending_kill = POLL_IN;
 511         return 1;
 512 }
 513
 514 /*
 515  * PEBS
 516  */
 517 struct event_constraint intel_core2_pebs_event_constraints[] = {
 518         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 519         INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 520         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 521         INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 522         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 523         EVENT_CONSTRAINT_END
 524 };
 525
 526 struct event_constraint intel_atom_pebs_event_constraints[] = {
 527         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 528         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 529         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 530         EVENT_CONSTRAINT_END
 531 };
 532
 533 struct event_constraint intel_slm_pebs_event_constraints[] = {
 534         INTEL_UEVENT_CONSTRAINT(0x0103, 0x1), /* REHABQ.LD_BLOCK_ST_FORWARD_PS */
 535         INTEL_UEVENT_CONSTRAINT(0x0803, 0x1), /* REHABQ.LD_SPLITS_PS */
 536         INTEL_UEVENT_CONSTRAINT(0x0204, 0x1), /* MEM_UOPS_RETIRED.L2_HIT_LOADS_PS */
 537         INTEL_UEVENT_CONSTRAINT(0x0404, 0x1), /* MEM_UOPS_RETIRED.L2_MISS_LOADS_PS */
 538         INTEL_UEVENT_CONSTRAINT(0x0804, 0x1), /* MEM_UOPS_RETIRED.DTLB_MISS_LOADS_PS */
 539         INTEL_UEVENT_CONSTRAINT(0x2004, 0x1), /* MEM_UOPS_RETIRED.HITM_PS */
 540         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY_PS */
 541         INTEL_UEVENT_CONSTRAINT(0x00c4, 0x1), /* BR_INST_RETIRED.ALL_BRANCHES_PS */
 542         INTEL_UEVENT_CONSTRAINT(0x7ec4, 0x1), /* BR_INST_RETIRED.JCC_PS */
 543         INTEL_UEVENT_CONSTRAINT(0xbfc4, 0x1), /* BR_INST_RETIRED.FAR_BRANCH_PS */
 544         INTEL_UEVENT_CONSTRAINT(0xebc4, 0x1), /* BR_INST_RETIRED.NON_RETURN_IND_PS */
 545         INTEL_UEVENT_CONSTRAINT(0xf7c4, 0x1), /* BR_INST_RETIRED.RETURN_PS */
 546         INTEL_UEVENT_CONSTRAINT(0xf9c4, 0x1), /* BR_INST_RETIRED.CALL_PS */
 547         INTEL_UEVENT_CONSTRAINT(0xfbc4, 0x1), /* BR_INST_RETIRED.IND_CALL_PS */
 548         INTEL_UEVENT_CONSTRAINT(0xfdc4, 0x1), /* BR_INST_RETIRED.REL_CALL_PS */
 549         INTEL_UEVENT_CONSTRAINT(0xfec4, 0x1), /* BR_INST_RETIRED.TAKEN_JCC_PS */
 550         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_MISP_RETIRED.ALL_BRANCHES_PS */
 551         INTEL_UEVENT_CONSTRAINT(0x7ec5, 0x1), /* BR_INST_MISP_RETIRED.JCC_PS */
 552         INTEL_UEVENT_CONSTRAINT(0xebc5, 0x1), /* BR_INST_MISP_RETIRED.NON_RETURN_IND_PS */
 553         INTEL_UEVENT_CONSTRAINT(0xf7c5, 0x1), /* BR_INST_MISP_RETIRED.RETURN_PS */
 554         INTEL_UEVENT_CONSTRAINT(0xfbc5, 0x1), /* BR_INST_MISP_RETIRED.IND_CALL_PS */
 555         INTEL_UEVENT_CONSTRAINT(0xfec5, 0x1), /* BR_INST_MISP_RETIRED.TAKEN_JCC_PS */
 556         EVENT_CONSTRAINT_END
 557 };
 558
 559 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 560         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 561         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 562         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 563         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 564         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 565         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 566         INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 567         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 568         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 569         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 570         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 571         EVENT_CONSTRAINT_END
 572 };
 573
 574 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 575         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 576         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 577         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 578         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 579         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 580         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 581         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 582         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 583         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 584         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 585         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 586         EVENT_CONSTRAINT_END
 587 };
 588
 589 struct event_constraint intel_snb_pebs_event_constraints[] = {
 590         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 591         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 592         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 593         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 594         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 595         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 596         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 597         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 598         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 599         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 600         INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
 601         EVENT_CONSTRAINT_END
 602 };
 603
 604 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 605         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 606         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 607         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 608         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 609         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 610         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 611         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 612         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 613         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 614         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 615         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 616         EVENT_CONSTRAINT_END
 617 };
 618
 619 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 620         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 621         INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 622         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 623         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 624         INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
 625         INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
 626         INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
 627         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.* */
 628         /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 629         INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
 630         /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 631         INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
 632         INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 633         INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 634         /* MEM_UOPS_RETIRED.SPLIT_STORES */
 635         INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
 636         INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 637         INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 638         INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
 639         INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
 640         INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
 641         /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
 642         INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
 643         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
 644         INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
 645         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
 646         INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
 647         /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
 648         INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
 649         INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
 650         INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
 651
 652         EVENT_CONSTRAINT_END
 653 };
 654
 655 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 656 {
 657         struct event_constraint *c;
 658
 659         if (!event->attr.precise_ip)
 660                 return NULL;
 661
 662         if (x86_pmu.pebs_constraints) {
 663                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 664                         if ((event->hw.config & c->cmask) == c->code) {
 665                                 event->hw.flags |= c->flags;
 666                                 return c;
 667                         }
 668                 }
 669         }
 670
 671         return &emptyconstraint;
 672 }
 673
 674 void intel_pmu_pebs_enable(struct perf_event *event)
 675 {
 676         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 677         struct hw_perf_event *hwc = &event->hw;
 678
 679         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 680
 681         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 682
 683         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 684                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 685         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 686                 cpuc->pebs_enabled |= 1ULL << 63;
 687 }
 688
 689 void intel_pmu_pebs_disable(struct perf_event *event)
 690 {
 691         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 692         struct hw_perf_event *hwc = &event->hw;
 693
 694         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 695
 696         if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
 697                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 698         else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
 699                 cpuc->pebs_enabled &= ~(1ULL << 63);
 700
 701         if (cpuc->enabled)
 702                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 703
 704         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 705 }
 706
 707 void intel_pmu_pebs_enable_all(void)
 708 {
 709         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 710
 711         if (cpuc->pebs_enabled)
 712                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 713 }
 714
 715 void intel_pmu_pebs_disable_all(void)
 716 {
 717         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 718
 719         if (cpuc->pebs_enabled)
 720                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 721 }
 722
 723 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 724 {
 725         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 726         unsigned long from = cpuc->lbr_entries[0].from;
 727         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 728         unsigned long ip = regs->ip;
 729         int is_64bit = 0;
 730
 731         /*
 732          * We don't need to fixup if the PEBS assist is fault like
 733          */
 734         if (!x86_pmu.intel_cap.pebs_trap)
 735                 return 1;
 736
 737         /*
 738          * No LBR entry, no basic block, no rewinding
 739          */
 740         if (!cpuc->lbr_stack.nr || !from || !to)
 741                 return 0;
 742
 743         /*
 744          * Basic blocks should never cross user/kernel boundaries
 745          */
 746         if (kernel_ip(ip) != kernel_ip(to))
 747                 return 0;
 748
 749         /*
 750          * unsigned math, either ip is before the start (impossible) or
 751          * the basic block is larger than 1 page (sanity)
 752          */
 753         if ((ip - to) > PAGE_SIZE)
 754                 return 0;
 755
 756         /*
 757          * We sampled a branch insn, rewind using the LBR stack
 758          */
 759         if (ip == to) {
 760                 set_linear_ip(regs, from);
 761                 return 1;
 762         }
 763
 764         do {
 765                 struct insn insn;
 766                 u8 buf[MAX_INSN_SIZE];
 767                 void *kaddr;
 768
 769                 old_to = to;
 770                 if (!kernel_ip(ip)) {
 771                         int bytes, size = MAX_INSN_SIZE;
 772
 773                         bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 774                         if (bytes != size)
 775                                 return 0;
 776
 777                         kaddr = buf;
 778                 } else
 779                         kaddr = (void *)to;
 780
 781 #ifdef CONFIG_X86_64
 782                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 783 #endif
 784                 insn_init(&insn, kaddr, is_64bit);
 785                 insn_get_length(&insn);
 786                 to += insn.length;
 787         } while (to < ip);
 788
 789         if (to == ip) {
 790                 set_linear_ip(regs, old_to);
 791                 return 1;
 792         }
 793
 794         /*
 795          * Even though we decoded the basic block, the instruction stream
 796          * never matched the given IP, either the TO or the IP got corrupted.
 797          */
 798         return 0;
 799 }
 800
 801 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
 802 {
 803         if (pebs->tsx_tuning) {
 804                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 805                 return tsx.cycles_last_block;
 806         }
 807         return 0;
 808 }
 809
 810 static void __intel_pmu_pebs_event(struct perf_event *event,
 811                                    struct pt_regs *iregs, void *__pebs)
 812 {
 813         /*
 814          * We cast to pebs_record_nhm to get the load latency data
 815          * if extra_reg MSR_PEBS_LD_LAT_THRESHOLD used
 816          * We cast to the biggest PEBS record are careful not
 817          * to access out-of-bounds members.
 818          */
 819         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 820         struct pebs_record_hsw *pebs = __pebs;
 821         struct perf_sample_data data;
 822         struct pt_regs regs;
 823         u64 sample_type;
 824         int fll, fst;
 825
 826         if (!intel_pmu_save_and_restart(event))
 827                 return;
 828
 829         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
 830         fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
 831                                  PERF_X86_EVENT_PEBS_ST_HSW);
 832
 833         perf_sample_data_init(&data, 0, event->hw.last_period);
 834
 835         data.period = event->hw.last_period;
 836         sample_type = event->attr.sample_type;
 837
 838         /*
 839          * if PEBS-LL or PreciseStore
 840          */
 841         if (fll || fst) {
 842                 /*
 843                  * Use latency for weight (only avail with PEBS-LL)
 844                  */
 845                 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
 846                         data.weight = pebs->lat;
 847
 848                 /*
 849                  * data.data_src encodes the data source
 850                  */
 851                 if (sample_type & PERF_SAMPLE_DATA_SRC) {
 852                         if (fll)
 853                                 data.data_src.val = load_latency_data(pebs->dse);
 854                         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 855                                 data.data_src.val =
 856                                         precise_store_data_hsw(pebs->dse);
 857                         else
 858                                 data.data_src.val = precise_store_data(pebs->dse);
 859                 }
 860         }
 861
 862         /*
 863          * We use the interrupt regs as a base because the PEBS record
 864          * does not contain a full regs set, specifically it seems to
 865          * lack segment descriptors, which get used by things like
 866          * user_mode().
 867          *
 868          * In the simple case fix up only the IP and BP,SP regs, for
 869          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 870          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 871          */
 872         regs = *iregs;
 873         regs.flags = pebs->flags;
 874         set_linear_ip(&regs, pebs->ip);
 875         regs.bp = pebs->bp;
 876         regs.sp = pebs->sp;
 877
 878         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
 879                 regs.ip = pebs->real_ip;
 880                 regs.flags |= PERF_EFLAGS_EXACT;
 881         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
 882                 regs.flags |= PERF_EFLAGS_EXACT;
 883         else
 884                 regs.flags &= ~PERF_EFLAGS_EXACT;
 885
 886         if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
 887                 x86_pmu.intel_cap.pebs_format >= 1)
 888                 data.addr = pebs->dla;
 889
 890         /* Only set the TSX weight when no memory weight was requested. */
 891         if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) &&
 892             !fll &&
 893             (x86_pmu.intel_cap.pebs_format >= 2))
 894                 data.weight = intel_hsw_weight(pebs);
 895
 896         if (has_branch_stack(event))
 897                 data.br_stack = &cpuc->lbr_stack;
 898
 899         if (perf_event_overflow(event, &data, &regs))
 900                 x86_pmu_stop(event, 0);
 901 }
 902
 903 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 904 {
 905         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 906         struct debug_store *ds = cpuc->ds;
 907         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 908         struct pebs_record_core *at, *top;
 909         int n;
 910
 911         if (!x86_pmu.pebs_active)
 912                 return;
 913
 914         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 915         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 916
 917         /*
 918          * Whatever else happens, drain the thing
 919          */
 920         ds->pebs_index = ds->pebs_buffer_base;
 921
 922         if (!test_bit(0, cpuc->active_mask))
 923                 return;
 924
 925         WARN_ON_ONCE(!event);
 926
 927         if (!event->attr.precise_ip)
 928                 return;
 929
 930         n = top - at;
 931         if (n <= 0)
 932                 return;
 933
 934         /*
 935          * Should not happen, we program the threshold at 1 and do not
 936          * set a reset value.
 937          */
 938         WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
 939         at += n - 1;
 940
 941         __intel_pmu_pebs_event(event, iregs, at);
 942 }
 943
 944 static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
 945                                         void *top)
 946 {
 947         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 948         struct debug_store *ds = cpuc->ds;
 949         struct perf_event *event = NULL;
 950         u64 status = 0;
 951         int bit;
 952
 953         ds->pebs_index = ds->pebs_buffer_base;
 954
 955         for (; at < top; at += x86_pmu.pebs_record_size) {
 956                 struct pebs_record_nhm *p = at;
 957
 958                 for_each_set_bit(bit, (unsigned long *)&p->status,
 959                                  x86_pmu.max_pebs_events) {
 960                         event = cpuc->events[bit];
 961                         if (!test_bit(bit, cpuc->active_mask))
 962                                 continue;
 963
 964                         WARN_ON_ONCE(!event);
 965
 966                         if (!event->attr.precise_ip)
 967                                 continue;
 968
 969                         if (__test_and_set_bit(bit, (unsigned long *)&status))
 970                                 continue;
 971
 972                         break;
 973                 }
 974
 975                 if (!event || bit >= x86_pmu.max_pebs_events)
 976                         continue;
 977
 978                 __intel_pmu_pebs_event(event, iregs, at);
 979         }
 980 }
 981
 982 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 983 {
 984         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 985         struct debug_store *ds = cpuc->ds;
 986         struct pebs_record_nhm *at, *top;
 987         int n;
 988
 989         if (!x86_pmu.pebs_active)
 990                 return;
 991
 992         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
 993         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
 994
 995         ds->pebs_index = ds->pebs_buffer_base;
 996
 997         n = top - at;
 998         if (n <= 0)
 999                 return;
1000
1001         /*
1002          * Should not happen, we program the threshold at 1 and do not
1003          * set a reset value.
1004          */
1005         WARN_ONCE(n > x86_pmu.max_pebs_events,
1006                   "Unexpected number of pebs records %d\n", n);
1007
1008         return __intel_pmu_drain_pebs_nhm(iregs, at, top);
1009 }
1010
1011 static void intel_pmu_drain_pebs_hsw(struct pt_regs *iregs)
1012 {
1013         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1014         struct debug_store *ds = cpuc->ds;
1015         struct pebs_record_hsw *at, *top;
1016         int n;
1017
1018         if (!x86_pmu.pebs_active)
1019                 return;
1020
1021         at  = (struct pebs_record_hsw *)(unsigned long)ds->pebs_buffer_base;
1022         top = (struct pebs_record_hsw *)(unsigned long)ds->pebs_index;
1023
1024         n = top - at;
1025         if (n <= 0)
1026                 return;
1027         /*
1028          * Should not happen, we program the threshold at 1 and do not
1029          * set a reset value.
1030          */
1031         WARN_ONCE(n > x86_pmu.max_pebs_events,
1032                   "Unexpected number of pebs records %d\n", n);
1033
1034         return __intel_pmu_drain_pebs_nhm(iregs, at, top);
1035 }
1036
1037 /*
1038  * BTS, PEBS probe and setup
1039  */
1040
1041 void intel_ds_init(void)
1042 {
1043         /*
1044          * No support for 32bit formats
1045          */
1046         if (!boot_cpu_has(X86_FEATURE_DTES64))
1047                 return;
1048
1049         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1050         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1051         if (x86_pmu.pebs) {
1052                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1053                 int format = x86_pmu.intel_cap.pebs_format;
1054
1055                 switch (format) {
1056                 case 0:
1057                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1058                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1059                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1060                         break;
1061
1062                 case 1:
1063                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1064                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1065                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1066                         break;
1067
1068                 case 2:
1069                         pr_cont("PEBS fmt2%c, ", pebs_type);
1070                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1071                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_hsw;
1072                         break;
1073
1074                 default:
1075                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1076                         x86_pmu.pebs = 0;
1077                 }
1078         }
1079 }
1080
1081 void perf_restore_debug_store(void)
1082 {
1083         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1084
1085         if (!x86_pmu.bts && !x86_pmu.pebs)
1086                 return;
1087
1088         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1089 }