2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
8 #include <asm/fpu/internal.h>
9 #include <asm/fpu/regset.h>
10 #include <asm/fpu/signal.h>
11 #include <asm/traps.h>
13 #include <linux/hardirq.h>
16 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
17 * depending on the FPU hardware format:
19 union thread_xstate init_fpstate __read_mostly;
22 * Track whether the kernel is using the FPU state
27 * - by IRQ context code to potentially use the FPU
30 * - to debug kernel_fpu_begin()/end() correctness
32 static DEFINE_PER_CPU(bool, in_kernel_fpu);
35 * Track which context is using the FPU on the CPU:
37 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
39 static void kernel_fpu_disable(void)
41 WARN_ON(this_cpu_read(in_kernel_fpu));
42 this_cpu_write(in_kernel_fpu, true);
45 static void kernel_fpu_enable(void)
47 WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
48 this_cpu_write(in_kernel_fpu, false);
51 static bool kernel_fpu_disabled(void)
53 return this_cpu_read(in_kernel_fpu);
57 * Were we in an interrupt that interrupted kernel mode?
59 * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
60 * pair does nothing at all: the thread must not have fpu (so
61 * that we don't try to save the FPU state), and TS must
62 * be set (so that the clts/stts pair does nothing that is
63 * visible in the interrupted kernel thread).
65 * Except for the eagerfpu case when we return true; in the likely case
66 * the thread has FPU but we are not going to set/clear TS.
68 static bool interrupted_kernel_fpu_idle(void)
70 if (kernel_fpu_disabled())
76 return !current->thread.fpu.fpregs_active && (read_cr0() & X86_CR0_TS);
80 * Were we in user mode (or vm86 mode) when we were
83 * Doing kernel_fpu_begin/end() is ok if we are running
84 * in an interrupt context from user mode - we'll just
85 * save the FPU state as required.
87 static bool interrupted_user_mode(void)
89 struct pt_regs *regs = get_irq_regs();
90 return regs && user_mode(regs);
94 * Can we use the FPU in kernel mode with the
95 * whole "kernel_fpu_begin/end()" sequence?
97 * It's always ok in process context (ie "not interrupt")
98 * but it is sometimes ok even from an irq.
100 bool irq_fpu_usable(void)
102 return !in_interrupt() ||
103 interrupted_user_mode() ||
104 interrupted_kernel_fpu_idle();
106 EXPORT_SYMBOL(irq_fpu_usable);
108 void __kernel_fpu_begin(void)
110 struct fpu *fpu = ¤t->thread.fpu;
112 kernel_fpu_disable();
114 if (fpu->fpregs_active) {
115 copy_fpregs_to_fpstate(fpu);
117 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
118 __fpregs_activate_hw();
121 EXPORT_SYMBOL(__kernel_fpu_begin);
123 void __kernel_fpu_end(void)
125 struct fpu *fpu = ¤t->thread.fpu;
127 if (fpu->fpregs_active) {
128 if (WARN_ON(copy_fpstate_to_fpregs(fpu)))
131 __fpregs_deactivate_hw();
136 EXPORT_SYMBOL(__kernel_fpu_end);
138 void kernel_fpu_begin(void)
141 WARN_ON_ONCE(!irq_fpu_usable());
142 __kernel_fpu_begin();
144 EXPORT_SYMBOL_GPL(kernel_fpu_begin);
146 void kernel_fpu_end(void)
151 EXPORT_SYMBOL_GPL(kernel_fpu_end);
154 * CR0::TS save/restore functions:
156 int irq_ts_save(void)
159 * If in process context and not atomic, we can take a spurious DNA fault.
160 * Otherwise, doing clts() in process context requires disabling preemption
161 * or some heavy lifting like kernel_fpu_begin()
166 if (read_cr0() & X86_CR0_TS) {
173 EXPORT_SYMBOL_GPL(irq_ts_save);
175 void irq_ts_restore(int TS_state)
180 EXPORT_SYMBOL_GPL(irq_ts_restore);
183 * Save the FPU state (mark it for reload if necessary):
185 * This only ever gets called for the current task.
187 void fpu__save(struct fpu *fpu)
189 WARN_ON(fpu != ¤t->thread.fpu);
192 if (fpu->fpregs_active) {
193 if (!copy_fpregs_to_fpstate(fpu))
194 fpregs_deactivate(fpu);
198 EXPORT_SYMBOL_GPL(fpu__save);
201 * Legacy x87 fpstate state init:
203 static inline void fpstate_init_fstate(struct i387_fsave_struct *fp)
205 fp->cwd = 0xffff037fu;
206 fp->swd = 0xffff0000u;
207 fp->twd = 0xffffffffu;
208 fp->fos = 0xffff0000u;
211 void fpstate_init(union thread_xstate *state)
214 fpstate_init_soft(&state->soft);
218 memset(state, 0, xstate_size);
221 fpstate_init_fxstate(&state->fxsave);
223 fpstate_init_fstate(&state->fsave);
225 EXPORT_SYMBOL_GPL(fpstate_init);
228 * Copy the current task's FPU state to a new task's FPU context.
230 * In the 'eager' case we just save to the destination context.
232 * In the 'lazy' case we save to the source context, mark the FPU lazy
233 * via stts() and copy the source context into the destination context.
235 static void fpu_copy(struct fpu *dst_fpu, struct fpu *src_fpu)
237 WARN_ON(src_fpu != ¤t->thread.fpu);
240 * Don't let 'init optimized' areas of the XSAVE area
241 * leak into the child task:
244 memset(&dst_fpu->state.xsave, 0, xstate_size);
247 * Save current FPU registers directly into the child
248 * FPU context, without any memory-to-memory copying.
250 * If the FPU context got destroyed in the process (FNSAVE
251 * done on old CPUs) then copy it back into the source
252 * context and mark the current task for lazy restore.
254 * We have to do all this with preemption disabled,
255 * mostly because of the FNSAVE case, because in that
256 * case we must not allow preemption in the window
257 * between the FNSAVE and us marking the context lazy.
259 * It shouldn't be an issue as even FNSAVE is plenty
260 * fast in terms of critical section length.
263 if (!copy_fpregs_to_fpstate(dst_fpu)) {
264 memcpy(&src_fpu->state, &dst_fpu->state, xstate_size);
265 fpregs_deactivate(src_fpu);
270 int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
272 dst_fpu->counter = 0;
273 dst_fpu->fpregs_active = 0;
274 dst_fpu->last_cpu = -1;
276 if (src_fpu->fpstate_active)
277 fpu_copy(dst_fpu, src_fpu);
283 * Activate the current task's in-memory FPU context,
284 * if it has not been used before:
286 void fpu__activate_curr(struct fpu *fpu)
288 WARN_ON_ONCE(fpu != ¤t->thread.fpu);
290 if (!fpu->fpstate_active) {
291 fpstate_init(&fpu->state);
293 /* Safe to do for the current task: */
294 fpu->fpstate_active = 1;
297 EXPORT_SYMBOL_GPL(fpu__activate_curr);
300 * This function must be called before we modify a stopped child's
303 * If the child has not used the FPU before then initialize its
306 * If the child has used the FPU before then unlazy it.
308 * [ After this function call, after registers in the fpstate are
309 * modified and the child task has woken up, the child task will
310 * restore the modified FPU state from the modified context. If we
311 * didn't clear its lazy status here then the lazy in-registers
312 * state pending on its former CPU could be restored, corrupting
313 * the modifications. ]
315 * This function is also called before we read a stopped child's
316 * FPU state - to make sure it's initialized if the child has
317 * no active FPU state.
319 * TODO: A future optimization would be to skip the unlazying in
320 * the read-only case, it's not strictly necessary for
321 * read-only access to the context.
323 static void fpu__activate_stopped(struct fpu *child_fpu)
325 WARN_ON_ONCE(child_fpu == ¤t->thread.fpu);
327 if (child_fpu->fpstate_active) {
328 child_fpu->last_cpu = -1;
330 fpstate_init(&child_fpu->state);
332 /* Safe to do for stopped child tasks: */
333 child_fpu->fpstate_active = 1;
338 * 'fpu__restore()' is called to copy FPU registers from
339 * the FPU fpstate to the live hw registers and to activate
340 * access to the hardware registers, so that FPU instructions
341 * can be used afterwards.
343 * Must be called with kernel preemption disabled (for example
344 * with local interrupts disabled, as it is in the case of
345 * do_device_not_available()).
347 void fpu__restore(void)
349 struct task_struct *tsk = current;
350 struct fpu *fpu = &tsk->thread.fpu;
352 fpu__activate_curr(fpu);
354 /* Avoid __kernel_fpu_begin() right after fpregs_activate() */
355 kernel_fpu_disable();
356 fpregs_activate(fpu);
357 if (unlikely(copy_fpstate_to_fpregs(fpu))) {
359 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
361 tsk->thread.fpu.counter++;
365 EXPORT_SYMBOL_GPL(fpu__restore);
368 * Drops current FPU state: deactivates the fpregs and
369 * the fpstate. NOTE: it still leaves previous contents
370 * in the fpregs in the eager-FPU case.
372 * This function can be used in cases where we know that
373 * a state-restore is coming: either an explicit one,
376 void fpu__drop(struct fpu *fpu)
381 if (fpu->fpregs_active) {
382 /* Ignore delayed exceptions from user space */
383 asm volatile("1: fwait\n"
385 _ASM_EXTABLE(1b, 2b));
386 fpregs_deactivate(fpu);
389 fpu->fpstate_active = 0;
395 * Clear FPU registers by setting them up from
398 static inline void copy_init_fpstate_to_fpregs(void)
401 xrstor_state(&init_fpstate.xsave, -1);
403 fxrstor_checking(&init_fpstate.fxsave);
407 * Clear the FPU state back to init state.
409 * Called by sys_execve(), by the signal handler code and by various
412 void fpu__clear(struct fpu *fpu)
414 WARN_ON_ONCE(fpu != ¤t->thread.fpu); /* Almost certainly an anomaly */
416 if (!use_eager_fpu()) {
417 /* FPU state will be reallocated lazily at the first use. */
420 if (!fpu->fpstate_active) {
421 fpu__activate_curr(fpu);
424 copy_init_fpstate_to_fpregs();
429 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
430 * as the "regset->n" for the xstate regset will be updated based on the feature
431 * capabilites supported by the xsave.
433 int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
435 struct fpu *target_fpu = &target->thread.fpu;
437 return target_fpu->fpstate_active ? regset->n : 0;
440 int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
442 struct fpu *target_fpu = &target->thread.fpu;
444 return (cpu_has_fxsr && target_fpu->fpstate_active) ? regset->n : 0;
447 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
448 unsigned int pos, unsigned int count,
449 void *kbuf, void __user *ubuf)
451 struct fpu *fpu = &target->thread.fpu;
456 fpu__activate_stopped(fpu);
457 fpstate_sanitize_xstate(fpu);
459 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
460 &fpu->state.fxsave, 0, -1);
463 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
464 unsigned int pos, unsigned int count,
465 const void *kbuf, const void __user *ubuf)
467 struct fpu *fpu = &target->thread.fpu;
473 fpu__activate_stopped(fpu);
474 fpstate_sanitize_xstate(fpu);
476 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
477 &fpu->state.fxsave, 0, -1);
480 * mxcsr reserved bits must be masked to zero for security reasons.
482 fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
485 * update the header bits in the xsave header, indicating the
486 * presence of FP and SSE state.
489 fpu->state.xsave.header.xfeatures |= XSTATE_FPSSE;
494 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
495 unsigned int pos, unsigned int count,
496 void *kbuf, void __user *ubuf)
498 struct fpu *fpu = &target->thread.fpu;
499 struct xsave_struct *xsave;
505 fpu__activate_stopped(fpu);
507 xsave = &fpu->state.xsave;
510 * Copy the 48bytes defined by the software first into the xstate
511 * memory layout in the thread struct, so that we can copy the entire
512 * xstateregs to the user using one user_regset_copyout().
514 memcpy(&xsave->i387.sw_reserved,
515 xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
517 * Copy the xstate memory layout.
519 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
523 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
524 unsigned int pos, unsigned int count,
525 const void *kbuf, const void __user *ubuf)
527 struct fpu *fpu = &target->thread.fpu;
528 struct xsave_struct *xsave;
534 fpu__activate_stopped(fpu);
536 xsave = &fpu->state.xsave;
538 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
540 * mxcsr reserved bits must be masked to zero for security reasons.
542 xsave->i387.mxcsr &= mxcsr_feature_mask;
543 xsave->header.xfeatures &= xfeatures_mask;
545 * These bits must be zero.
547 memset(&xsave->header.reserved, 0, 48);
552 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
555 * FPU tag word conversions.
558 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
560 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
562 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
564 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
565 /* and move the valid bits to the lower byte. */
566 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
567 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
568 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
573 #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
574 #define FP_EXP_TAG_VALID 0
575 #define FP_EXP_TAG_ZERO 1
576 #define FP_EXP_TAG_SPECIAL 2
577 #define FP_EXP_TAG_EMPTY 3
579 static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
582 u32 tos = (fxsave->swd >> 11) & 7;
583 u32 twd = (unsigned long) fxsave->twd;
585 u32 ret = 0xffff0000u;
588 for (i = 0; i < 8; i++, twd >>= 1) {
590 st = FPREG_ADDR(fxsave, (i - tos) & 7);
592 switch (st->exponent & 0x7fff) {
594 tag = FP_EXP_TAG_SPECIAL;
597 if (!st->significand[0] &&
598 !st->significand[1] &&
599 !st->significand[2] &&
601 tag = FP_EXP_TAG_ZERO;
603 tag = FP_EXP_TAG_SPECIAL;
606 if (st->significand[3] & 0x8000)
607 tag = FP_EXP_TAG_VALID;
609 tag = FP_EXP_TAG_SPECIAL;
613 tag = FP_EXP_TAG_EMPTY;
615 ret |= tag << (2 * i);
621 * FXSR floating point environment conversions.
625 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
627 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state.fxsave;
628 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
629 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
632 env->cwd = fxsave->cwd | 0xffff0000u;
633 env->swd = fxsave->swd | 0xffff0000u;
634 env->twd = twd_fxsr_to_i387(fxsave);
637 env->fip = fxsave->rip;
638 env->foo = fxsave->rdp;
640 * should be actually ds/cs at fpu exception time, but
641 * that information is not available in 64bit mode.
643 env->fcs = task_pt_regs(tsk)->cs;
644 if (tsk == current) {
645 savesegment(ds, env->fos);
647 env->fos = tsk->thread.ds;
649 env->fos |= 0xffff0000;
651 env->fip = fxsave->fip;
652 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
653 env->foo = fxsave->foo;
654 env->fos = fxsave->fos;
657 for (i = 0; i < 8; ++i)
658 memcpy(&to[i], &from[i], sizeof(to[0]));
661 void convert_to_fxsr(struct task_struct *tsk,
662 const struct user_i387_ia32_struct *env)
665 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state.fxsave;
666 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
667 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
670 fxsave->cwd = env->cwd;
671 fxsave->swd = env->swd;
672 fxsave->twd = twd_i387_to_fxsr(env->twd);
673 fxsave->fop = (u16) ((u32) env->fcs >> 16);
675 fxsave->rip = env->fip;
676 fxsave->rdp = env->foo;
677 /* cs and ds ignored */
679 fxsave->fip = env->fip;
680 fxsave->fcs = (env->fcs & 0xffff);
681 fxsave->foo = env->foo;
682 fxsave->fos = env->fos;
685 for (i = 0; i < 8; ++i)
686 memcpy(&to[i], &from[i], sizeof(from[0]));
689 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
690 unsigned int pos, unsigned int count,
691 void *kbuf, void __user *ubuf)
693 struct fpu *fpu = &target->thread.fpu;
694 struct user_i387_ia32_struct env;
696 fpu__activate_stopped(fpu);
698 if (!static_cpu_has(X86_FEATURE_FPU))
699 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
702 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
703 &fpu->state.fsave, 0,
706 fpstate_sanitize_xstate(fpu);
708 if (kbuf && pos == 0 && count == sizeof(env)) {
709 convert_from_fxsr(kbuf, target);
713 convert_from_fxsr(&env, target);
715 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
718 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
719 unsigned int pos, unsigned int count,
720 const void *kbuf, const void __user *ubuf)
722 struct fpu *fpu = &target->thread.fpu;
723 struct user_i387_ia32_struct env;
726 fpu__activate_stopped(fpu);
727 fpstate_sanitize_xstate(fpu);
729 if (!static_cpu_has(X86_FEATURE_FPU))
730 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
733 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
734 &fpu->state.fsave, 0,
737 if (pos > 0 || count < sizeof(env))
738 convert_from_fxsr(&env, target);
740 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
742 convert_to_fxsr(target, &env);
745 * update the header bit in the xsave header, indicating the
749 fpu->state.xsave.header.xfeatures |= XSTATE_FP;
754 * FPU state for core dumps.
755 * This is only used for a.out dumps now.
756 * It is declared generically using elf_fpregset_t (which is
757 * struct user_i387_struct) but is in fact only used for 32-bit
758 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
760 int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu)
762 struct task_struct *tsk = current;
763 struct fpu *fpu = &tsk->thread.fpu;
766 fpvalid = fpu->fpstate_active;
768 fpvalid = !fpregs_get(tsk, NULL,
769 0, sizeof(struct user_i387_ia32_struct),
774 EXPORT_SYMBOL(dump_fpu);
776 #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
779 * x87 math exception handling:
782 static inline unsigned short get_fpu_cwd(struct fpu *fpu)
785 return fpu->state.fxsave.cwd;
787 return (unsigned short)fpu->state.fsave.cwd;
791 static inline unsigned short get_fpu_swd(struct fpu *fpu)
794 return fpu->state.fxsave.swd;
796 return (unsigned short)fpu->state.fsave.swd;
800 static inline unsigned short get_fpu_mxcsr(struct fpu *fpu)
803 return fpu->state.fxsave.mxcsr;
805 return MXCSR_DEFAULT;
809 int fpu__exception_code(struct fpu *fpu, int trap_nr)
813 if (trap_nr == X86_TRAP_MF) {
814 unsigned short cwd, swd;
816 * (~cwd & swd) will mask out exceptions that are not set to unmasked
817 * status. 0x3f is the exception bits in these regs, 0x200 is the
818 * C1 reg you need in case of a stack fault, 0x040 is the stack
819 * fault bit. We should only be taking one exception at a time,
820 * so if this combination doesn't produce any single exception,
821 * then we have a bad program that isn't synchronizing its FPU usage
822 * and it will suffer the consequences since we won't be able to
823 * fully reproduce the context of the exception
825 cwd = get_fpu_cwd(fpu);
826 swd = get_fpu_swd(fpu);
831 * The SIMD FPU exceptions are handled a little differently, as there
832 * is only a single status/control register. Thus, to determine which
833 * unmasked exception was caught we must mask the exception mask bits
834 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
836 unsigned short mxcsr = get_fpu_mxcsr(fpu);
837 err = ~(mxcsr >> 7) & mxcsr;
840 if (err & 0x001) { /* Invalid op */
842 * swd & 0x240 == 0x040: Stack Underflow
843 * swd & 0x240 == 0x240: Stack Overflow
844 * User must clear the SF bit (0x40) if set
847 } else if (err & 0x004) { /* Divide by Zero */
849 } else if (err & 0x008) { /* Overflow */
851 } else if (err & 0x012) { /* Denormal, Underflow */
853 } else if (err & 0x020) { /* Precision */
858 * If we're using IRQ 13, or supposedly even some trap
859 * X86_TRAP_MF implementations, it's possible
860 * we get a spurious trap, which is not an error.