2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
8 #include <asm/fpu/internal.h>
9 #include <asm/fpu/regset.h>
10 #include <asm/fpu/signal.h>
11 #include <asm/traps.h>
13 #include <linux/hardirq.h>
16 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
17 * depending on the FPU hardware format:
19 union fpregs_state init_fpstate __read_mostly;
22 * Track whether the kernel is using the FPU state
27 * - by IRQ context code to potentially use the FPU
30 * - to debug kernel_fpu_begin()/end() correctness
32 static DEFINE_PER_CPU(bool, in_kernel_fpu);
35 * Track which context is using the FPU on the CPU:
37 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
39 static void kernel_fpu_disable(void)
41 WARN_ON(this_cpu_read(in_kernel_fpu));
42 this_cpu_write(in_kernel_fpu, true);
45 static void kernel_fpu_enable(void)
47 WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
48 this_cpu_write(in_kernel_fpu, false);
51 static bool kernel_fpu_disabled(void)
53 return this_cpu_read(in_kernel_fpu);
57 * Were we in an interrupt that interrupted kernel mode?
59 * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
60 * pair does nothing at all: the thread must not have fpu (so
61 * that we don't try to save the FPU state), and TS must
62 * be set (so that the clts/stts pair does nothing that is
63 * visible in the interrupted kernel thread).
65 * Except for the eagerfpu case when we return true; in the likely case
66 * the thread has FPU but we are not going to set/clear TS.
68 static bool interrupted_kernel_fpu_idle(void)
70 if (kernel_fpu_disabled())
76 return !current->thread.fpu.fpregs_active && (read_cr0() & X86_CR0_TS);
80 * Were we in user mode (or vm86 mode) when we were
83 * Doing kernel_fpu_begin/end() is ok if we are running
84 * in an interrupt context from user mode - we'll just
85 * save the FPU state as required.
87 static bool interrupted_user_mode(void)
89 struct pt_regs *regs = get_irq_regs();
90 return regs && user_mode(regs);
94 * Can we use the FPU in kernel mode with the
95 * whole "kernel_fpu_begin/end()" sequence?
97 * It's always ok in process context (ie "not interrupt")
98 * but it is sometimes ok even from an irq.
100 bool irq_fpu_usable(void)
102 return !in_interrupt() ||
103 interrupted_user_mode() ||
104 interrupted_kernel_fpu_idle();
106 EXPORT_SYMBOL(irq_fpu_usable);
108 void __kernel_fpu_begin(void)
110 struct fpu *fpu = ¤t->thread.fpu;
112 kernel_fpu_disable();
114 if (fpu->fpregs_active) {
115 copy_fpregs_to_fpstate(fpu);
117 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
118 __fpregs_activate_hw();
121 EXPORT_SYMBOL(__kernel_fpu_begin);
123 void __kernel_fpu_end(void)
125 struct fpu *fpu = ¤t->thread.fpu;
127 if (fpu->fpregs_active) {
128 if (WARN_ON(copy_fpstate_to_fpregs(fpu)))
131 __fpregs_deactivate_hw();
136 EXPORT_SYMBOL(__kernel_fpu_end);
138 void kernel_fpu_begin(void)
141 WARN_ON_ONCE(!irq_fpu_usable());
142 __kernel_fpu_begin();
144 EXPORT_SYMBOL_GPL(kernel_fpu_begin);
146 void kernel_fpu_end(void)
151 EXPORT_SYMBOL_GPL(kernel_fpu_end);
154 * CR0::TS save/restore functions:
156 int irq_ts_save(void)
159 * If in process context and not atomic, we can take a spurious DNA fault.
160 * Otherwise, doing clts() in process context requires disabling preemption
161 * or some heavy lifting like kernel_fpu_begin()
166 if (read_cr0() & X86_CR0_TS) {
173 EXPORT_SYMBOL_GPL(irq_ts_save);
175 void irq_ts_restore(int TS_state)
180 EXPORT_SYMBOL_GPL(irq_ts_restore);
183 * Save the FPU state (mark it for reload if necessary):
185 * This only ever gets called for the current task.
187 void fpu__save(struct fpu *fpu)
189 WARN_ON(fpu != ¤t->thread.fpu);
192 if (fpu->fpregs_active) {
193 if (!copy_fpregs_to_fpstate(fpu))
194 fpregs_deactivate(fpu);
198 EXPORT_SYMBOL_GPL(fpu__save);
201 * Legacy x87 fpstate state init:
203 static inline void fpstate_init_fstate(struct fregs_state *fp)
205 fp->cwd = 0xffff037fu;
206 fp->swd = 0xffff0000u;
207 fp->twd = 0xffffffffu;
208 fp->fos = 0xffff0000u;
211 void fpstate_init(union fpregs_state *state)
214 fpstate_init_soft(&state->soft);
218 memset(state, 0, xstate_size);
221 fpstate_init_fxstate(&state->fxsave);
223 fpstate_init_fstate(&state->fsave);
225 EXPORT_SYMBOL_GPL(fpstate_init);
228 * Copy the current task's FPU state to a new task's FPU context.
230 * In both the 'eager' and the 'lazy' case we save hardware registers
231 * directly to the destination buffer.
233 static void fpu_copy(struct fpu *dst_fpu, struct fpu *src_fpu)
235 WARN_ON(src_fpu != ¤t->thread.fpu);
238 * Don't let 'init optimized' areas of the XSAVE area
239 * leak into the child task:
242 memset(&dst_fpu->state.xsave, 0, xstate_size);
245 * Save current FPU registers directly into the child
246 * FPU context, without any memory-to-memory copying.
248 * If the FPU context got destroyed in the process (FNSAVE
249 * done on old CPUs) then copy it back into the source
250 * context and mark the current task for lazy restore.
252 * We have to do all this with preemption disabled,
253 * mostly because of the FNSAVE case, because in that
254 * case we must not allow preemption in the window
255 * between the FNSAVE and us marking the context lazy.
257 * It shouldn't be an issue as even FNSAVE is plenty
258 * fast in terms of critical section length.
261 if (!copy_fpregs_to_fpstate(dst_fpu)) {
262 memcpy(&src_fpu->state, &dst_fpu->state, xstate_size);
263 fpregs_deactivate(src_fpu);
268 int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
270 dst_fpu->counter = 0;
271 dst_fpu->fpregs_active = 0;
272 dst_fpu->last_cpu = -1;
274 if (src_fpu->fpstate_active)
275 fpu_copy(dst_fpu, src_fpu);
281 * Activate the current task's in-memory FPU context,
282 * if it has not been used before:
284 void fpu__activate_curr(struct fpu *fpu)
286 WARN_ON_ONCE(fpu != ¤t->thread.fpu);
288 if (!fpu->fpstate_active) {
289 fpstate_init(&fpu->state);
291 /* Safe to do for the current task: */
292 fpu->fpstate_active = 1;
295 EXPORT_SYMBOL_GPL(fpu__activate_curr);
298 * This function must be called before we modify a stopped child's
301 * If the child has not used the FPU before then initialize its
304 * If the child has used the FPU before then unlazy it.
306 * [ After this function call, after registers in the fpstate are
307 * modified and the child task has woken up, the child task will
308 * restore the modified FPU state from the modified context. If we
309 * didn't clear its lazy status here then the lazy in-registers
310 * state pending on its former CPU could be restored, corrupting
311 * the modifications. ]
313 * This function is also called before we read a stopped child's
314 * FPU state - to make sure it's initialized if the child has
315 * no active FPU state.
317 * TODO: A future optimization would be to skip the unlazying in
318 * the read-only case, it's not strictly necessary for
319 * read-only access to the context.
321 void fpu__activate_stopped(struct fpu *child_fpu)
323 WARN_ON_ONCE(child_fpu == ¤t->thread.fpu);
325 if (child_fpu->fpstate_active) {
326 child_fpu->last_cpu = -1;
328 fpstate_init(&child_fpu->state);
330 /* Safe to do for stopped child tasks: */
331 child_fpu->fpstate_active = 1;
336 * 'fpu__restore()' is called to copy FPU registers from
337 * the FPU fpstate to the live hw registers and to activate
338 * access to the hardware registers, so that FPU instructions
339 * can be used afterwards.
341 * Must be called with kernel preemption disabled (for example
342 * with local interrupts disabled, as it is in the case of
343 * do_device_not_available()).
345 void fpu__restore(void)
347 struct task_struct *tsk = current;
348 struct fpu *fpu = &tsk->thread.fpu;
350 fpu__activate_curr(fpu);
352 /* Avoid __kernel_fpu_begin() right after fpregs_activate() */
353 kernel_fpu_disable();
354 fpregs_activate(fpu);
355 if (unlikely(copy_fpstate_to_fpregs(fpu))) {
357 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
359 tsk->thread.fpu.counter++;
363 EXPORT_SYMBOL_GPL(fpu__restore);
366 * Drops current FPU state: deactivates the fpregs and
367 * the fpstate. NOTE: it still leaves previous contents
368 * in the fpregs in the eager-FPU case.
370 * This function can be used in cases where we know that
371 * a state-restore is coming: either an explicit one,
374 void fpu__drop(struct fpu *fpu)
379 if (fpu->fpregs_active) {
380 /* Ignore delayed exceptions from user space */
381 asm volatile("1: fwait\n"
383 _ASM_EXTABLE(1b, 2b));
384 fpregs_deactivate(fpu);
387 fpu->fpstate_active = 0;
393 * Clear FPU registers by setting them up from
396 static inline void copy_init_fpstate_to_fpregs(void)
399 copy_kernel_to_xregs(&init_fpstate.xsave, -1);
401 copy_kernel_to_fxregs(&init_fpstate.fxsave);
405 * Clear the FPU state back to init state.
407 * Called by sys_execve(), by the signal handler code and by various
410 void fpu__clear(struct fpu *fpu)
412 WARN_ON_ONCE(fpu != ¤t->thread.fpu); /* Almost certainly an anomaly */
414 if (!use_eager_fpu()) {
415 /* FPU state will be reallocated lazily at the first use. */
418 if (!fpu->fpstate_active) {
419 fpu__activate_curr(fpu);
422 copy_init_fpstate_to_fpregs();
427 * x87 math exception handling:
430 static inline unsigned short get_fpu_cwd(struct fpu *fpu)
433 return fpu->state.fxsave.cwd;
435 return (unsigned short)fpu->state.fsave.cwd;
439 static inline unsigned short get_fpu_swd(struct fpu *fpu)
442 return fpu->state.fxsave.swd;
444 return (unsigned short)fpu->state.fsave.swd;
448 static inline unsigned short get_fpu_mxcsr(struct fpu *fpu)
451 return fpu->state.fxsave.mxcsr;
453 return MXCSR_DEFAULT;
457 int fpu__exception_code(struct fpu *fpu, int trap_nr)
461 if (trap_nr == X86_TRAP_MF) {
462 unsigned short cwd, swd;
464 * (~cwd & swd) will mask out exceptions that are not set to unmasked
465 * status. 0x3f is the exception bits in these regs, 0x200 is the
466 * C1 reg you need in case of a stack fault, 0x040 is the stack
467 * fault bit. We should only be taking one exception at a time,
468 * so if this combination doesn't produce any single exception,
469 * then we have a bad program that isn't synchronizing its FPU usage
470 * and it will suffer the consequences since we won't be able to
471 * fully reproduce the context of the exception
473 cwd = get_fpu_cwd(fpu);
474 swd = get_fpu_swd(fpu);
479 * The SIMD FPU exceptions are handled a little differently, as there
480 * is only a single status/control register. Thus, to determine which
481 * unmasked exception was caught we must mask the exception mask bits
482 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
484 unsigned short mxcsr = get_fpu_mxcsr(fpu);
485 err = ~(mxcsr >> 7) & mxcsr;
488 if (err & 0x001) { /* Invalid op */
490 * swd & 0x240 == 0x040: Stack Underflow
491 * swd & 0x240 == 0x240: Stack Overflow
492 * User must clear the SF bit (0x40) if set
495 } else if (err & 0x004) { /* Divide by Zero */
497 } else if (err & 0x008) { /* Overflow */
499 } else if (err & 0x012) { /* Denormal, Underflow */
501 } else if (err & 0x020) { /* Precision */
506 * If we're using IRQ 13, or supposedly even some trap
507 * X86_TRAP_MF implementations, it's possible
508 * we get a spurious trap, which is not an error.