2 * x86 FPU boot time init code:
4 #include <asm/fpu/internal.h>
5 #include <asm/tlbflush.h>
8 * Initialize the TS bit in CR0 according to the style of context-switches
11 static void fpu__init_cpu_ctx_switch(void)
13 if (!cpu_has_eager_fpu)
20 * Initialize the registers found in all CPUs, CR0 and CR4:
22 static void fpu__init_cpu_generic(void)
25 unsigned long cr4_mask = 0;
28 cr4_mask |= X86_CR4_OSFXSR;
30 cr4_mask |= X86_CR4_OSXMMEXCPT;
32 cr4_set_bits(cr4_mask);
35 cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
40 /* Flush out any pending x87 state: */
41 asm volatile ("fninit");
45 * Enable all supported FPU features. Called when a CPU is brought online:
47 void fpu__init_cpu(void)
49 fpu__init_cpu_generic();
50 fpu__init_cpu_xstate();
51 fpu__init_cpu_ctx_switch();
55 * The earliest FPU detection code.
57 * Set the X86_FEATURE_FPU CPU-capability bit based on
58 * trying to execute an actual sequence of FPU instructions:
60 static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
68 cr0 &= ~(X86_CR0_TS | X86_CR0_EM);
71 asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
72 : "+m" (fsw), "+m" (fcw));
74 if (fsw == 0 && (fcw & 0x103f) == 0x003f)
75 set_cpu_cap(c, X86_FEATURE_FPU);
77 clear_cpu_cap(c, X86_FEATURE_FPU);
79 #ifndef CONFIG_MATH_EMULATION
81 pr_emerg("x86/fpu: Giving up, no FPU found and no math emulation present\n");
89 * Boot time FPU feature detection code:
91 unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
93 static void __init fpu__init_system_mxcsr(void)
95 unsigned int mask = 0;
98 /* Static because GCC does not get 16-byte stack alignment right: */
99 static struct fxregs_state fxregs __initdata;
101 asm volatile("fxsave %0" : "+m" (fxregs));
103 mask = fxregs.mxcsr_mask;
106 * If zero then use the default features mask,
107 * which has all features set, except the
108 * denormals-are-zero feature bit:
113 mxcsr_feature_mask &= mask;
117 * Once per bootup FPU initialization sequences that will run on most x86 CPUs:
119 static void __init fpu__init_system_generic(void)
122 * Set up the legacy init FPU context. (xstate init might overwrite this
123 * with a more modern format, if the CPU supports it.)
125 fpstate_init_fxstate(&init_fpstate.fxsave);
127 fpu__init_system_mxcsr();
131 * Size of the FPU context state. All tasks in the system use the
132 * same context size, regardless of what portion they use.
133 * This is inherent to the XSAVE architecture which puts all state
134 * components into a single, continuous memory block:
136 unsigned int xstate_size;
137 EXPORT_SYMBOL_GPL(xstate_size);
140 * Set up the xstate_size based on the legacy FPU context size.
142 * We set this up first, and later it will be overwritten by
143 * fpu__init_system_xstate() if the CPU knows about xstates.
145 static void __init fpu__init_system_xstate_size_legacy(void)
147 static int on_boot_cpu = 1;
149 WARN_ON_FPU(!on_boot_cpu);
153 * Note that xstate_size might be overwriten later during
154 * fpu__init_system_xstate().
159 * Disable xsave as we do not support it if i387
160 * emulation is enabled.
162 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
163 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
164 xstate_size = sizeof(struct swregs_state);
167 xstate_size = sizeof(struct fxregs_state);
169 xstate_size = sizeof(struct fregs_state);
172 * Quirk: we don't yet handle the XSAVES* instructions
173 * correctly, as we don't correctly convert between
174 * standard and compacted format when interfacing
175 * with user-space - so disable it for now.
177 * The difference is small: with recent CPUs the
178 * compacted format is only marginally smaller than
179 * the standard FPU state format.
181 * ( This is easy to backport while we are fixing
184 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
188 * FPU context switching strategies:
190 * Against popular belief, we don't do lazy FPU saves, due to the
191 * task migration complications it brings on SMP - we only do
194 * 'lazy' is the traditional strategy, which is based on setting
195 * CR0::TS to 1 during context-switch (instead of doing a full
196 * restore of the FPU state), which causes the first FPU instruction
197 * after the context switch (whenever it is executed) to fault - at
198 * which point we lazily restore the FPU state into FPU registers.
200 * Tasks are of course under no obligation to execute FPU instructions,
201 * so it can easily happen that another context-switch occurs without
202 * a single FPU instruction being executed. If we eventually switch
203 * back to the original task (that still owns the FPU) then we have
204 * not only saved the restores along the way, but we also have the
205 * FPU ready to be used for the original task.
207 * 'eager' switching is used on modern CPUs, there we switch the FPU
208 * state during every context switch, regardless of whether the task
209 * has used FPU instructions in that time slice or not. This is done
210 * because modern FPU context saving instructions are able to optimize
211 * state saving and restoration in hardware: they can detect both
212 * unused and untouched FPU state and optimize accordingly.
214 * [ Note that even in 'lazy' mode we might optimize context switches
215 * to use 'eager' restores, if we detect that a task is using the FPU
216 * frequently. See the fpu->counter logic in fpu/internal.h for that. ]
218 static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO;
220 static int __init eager_fpu_setup(char *s)
222 if (!strcmp(s, "on"))
224 else if (!strcmp(s, "off"))
226 else if (!strcmp(s, "auto"))
230 __setup("eagerfpu=", eager_fpu_setup);
233 * Pick the FPU context switching strategy:
235 static void __init fpu__init_system_ctx_switch(void)
237 static bool on_boot_cpu = 1;
239 WARN_ON_FPU(!on_boot_cpu);
242 WARN_ON_FPU(current->thread.fpu.fpstate_active);
243 current_thread_info()->status = 0;
245 /* Auto enable eagerfpu for xsaveopt */
246 if (cpu_has_xsaveopt && eagerfpu != DISABLE)
249 if (xfeatures_mask & XSTATE_EAGER) {
250 if (eagerfpu == DISABLE) {
251 pr_err("x86/fpu: eagerfpu switching disabled, disabling the following xstate features: 0x%llx.\n",
252 xfeatures_mask & XSTATE_EAGER);
253 xfeatures_mask &= ~XSTATE_EAGER;
259 if (eagerfpu == ENABLE)
260 setup_force_cpu_cap(X86_FEATURE_EAGER_FPU);
262 printk(KERN_INFO "x86/fpu: Using '%s' FPU context switches.\n", eagerfpu == ENABLE ? "eager" : "lazy");
266 * Called on the boot CPU once per system bootup, to set up the initial
267 * FPU state that is later cloned into all processes:
269 void __init fpu__init_system(struct cpuinfo_x86 *c)
271 fpu__init_system_early_generic(c);
274 * The FPU has to be operational for some of the
275 * later FPU init activities:
280 * But don't leave CR0::TS set yet, as some of the FPU setup
281 * methods depend on being able to execute FPU instructions
282 * that will fault on a set TS, such as the FXSAVE in
283 * fpu__init_system_mxcsr().
287 fpu__init_system_generic();
288 fpu__init_system_xstate_size_legacy();
289 fpu__init_system_xstate();
291 fpu__init_system_ctx_switch();
295 * Boot parameter to turn off FPU support and fall back to math-emu:
297 static int __init no_387(char *s)
299 setup_clear_cpu_cap(X86_FEATURE_FPU);
302 __setup("no387", no_387);
305 * Disable all xstate CPU features:
307 static int __init x86_noxsave_setup(char *s)
312 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
313 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
314 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
315 setup_clear_cpu_cap(X86_FEATURE_AVX);
316 setup_clear_cpu_cap(X86_FEATURE_AVX2);
320 __setup("noxsave", x86_noxsave_setup);
323 * Disable the XSAVEOPT instruction specifically:
325 static int __init x86_noxsaveopt_setup(char *s)
327 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
331 __setup("noxsaveopt", x86_noxsaveopt_setup);
334 * Disable the XSAVES instruction:
336 static int __init x86_noxsaves_setup(char *s)
338 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
342 __setup("noxsaves", x86_noxsaves_setup);
345 * Disable FX save/restore and SSE support:
347 static int __init x86_nofxsr_setup(char *s)
349 setup_clear_cpu_cap(X86_FEATURE_FXSR);
350 setup_clear_cpu_cap(X86_FEATURE_FXSR_OPT);
351 setup_clear_cpu_cap(X86_FEATURE_XMM);
355 __setup("nofxsr", x86_nofxsr_setup);