1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/export.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/i8253.h>
8 #include <linux/slab.h>
9 #include <linux/hpet.h>
10 #include <linux/init.h>
11 #include <linux/cpu.h>
15 #include <asm/irqdomain.h>
16 #include <asm/fixmap.h>
20 #define HPET_MASK CLOCKSOURCE_MASK(32)
24 #define FSEC_PER_NSEC 1000000L
26 #define HPET_DEV_USED_BIT 2
27 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
28 #define HPET_DEV_VALID 0x8
29 #define HPET_DEV_FSB_CAP 0x1000
30 #define HPET_DEV_PERI_CAP 0x2000
32 #define HPET_MIN_CYCLES 128
33 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
36 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 unsigned long hpet_address;
39 u8 hpet_blockid; /* OS timer block num */
43 static unsigned long hpet_num_timers;
45 static void __iomem *hpet_virt_address;
48 struct clock_event_device evt;
56 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
58 return container_of(evtdev, struct hpet_dev, evt);
61 inline unsigned int hpet_readl(unsigned int a)
63 return readl(hpet_virt_address + a);
66 static inline void hpet_writel(unsigned int d, unsigned int a)
68 writel(d, hpet_virt_address + a);
72 #include <asm/pgtable.h>
75 static inline void hpet_set_mapping(void)
77 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
80 static inline void hpet_clear_mapping(void)
82 iounmap(hpet_virt_address);
83 hpet_virt_address = NULL;
87 * HPET command line enable / disable
89 int boot_hpet_disable;
91 static int hpet_verbose;
93 static int __init hpet_setup(char *str)
96 char *next = strchr(str, ',');
100 if (!strncmp("disable", str, 7))
101 boot_hpet_disable = 1;
102 if (!strncmp("force", str, 5))
104 if (!strncmp("verbose", str, 7))
110 __setup("hpet=", hpet_setup);
112 static int __init disable_hpet(char *str)
114 boot_hpet_disable = 1;
117 __setup("nohpet", disable_hpet);
119 static inline int is_hpet_capable(void)
121 return !boot_hpet_disable && hpet_address;
125 * HPET timer interrupt enable / disable
127 static int hpet_legacy_int_enabled;
130 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
132 int is_hpet_enabled(void)
134 return is_hpet_capable() && hpet_legacy_int_enabled;
136 EXPORT_SYMBOL_GPL(is_hpet_enabled);
138 static void _hpet_print_config(const char *function, int line)
141 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
142 l = hpet_readl(HPET_ID);
143 h = hpet_readl(HPET_PERIOD);
144 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
145 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
146 l = hpet_readl(HPET_CFG);
147 h = hpet_readl(HPET_STATUS);
148 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
149 l = hpet_readl(HPET_COUNTER);
150 h = hpet_readl(HPET_COUNTER+4);
151 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
153 for (i = 0; i < timers; i++) {
154 l = hpet_readl(HPET_Tn_CFG(i));
155 h = hpet_readl(HPET_Tn_CFG(i)+4);
156 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
158 l = hpet_readl(HPET_Tn_CMP(i));
159 h = hpet_readl(HPET_Tn_CMP(i)+4);
160 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
162 l = hpet_readl(HPET_Tn_ROUTE(i));
163 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
164 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
169 #define hpet_print_config() \
172 _hpet_print_config(__func__, __LINE__); \
176 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
177 * timer 0 and timer 1 in case of RTC emulation.
181 static void hpet_reserve_msi_timers(struct hpet_data *hd);
183 static void hpet_reserve_platform_timers(unsigned int id)
185 struct hpet __iomem *hpet = hpet_virt_address;
186 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
187 unsigned int nrtimers, i;
190 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
192 memset(&hd, 0, sizeof(hd));
193 hd.hd_phys_address = hpet_address;
194 hd.hd_address = hpet;
195 hd.hd_nirqs = nrtimers;
196 hpet_reserve_timer(&hd, 0);
198 #ifdef CONFIG_HPET_EMULATE_RTC
199 hpet_reserve_timer(&hd, 1);
203 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
204 * is wrong for i8259!) not the output IRQ. Many BIOS writers
205 * don't bother configuring *any* comparator interrupts.
207 hd.hd_irq[0] = HPET_LEGACY_8254;
208 hd.hd_irq[1] = HPET_LEGACY_RTC;
210 for (i = 2; i < nrtimers; timer++, i++) {
211 hd.hd_irq[i] = (readl(&timer->hpet_config) &
212 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
215 hpet_reserve_msi_timers(&hd);
221 static void hpet_reserve_platform_timers(unsigned int id) { }
227 static unsigned long hpet_freq;
229 static struct clock_event_device hpet_clockevent;
231 static void hpet_stop_counter(void)
233 unsigned long cfg = hpet_readl(HPET_CFG);
234 cfg &= ~HPET_CFG_ENABLE;
235 hpet_writel(cfg, HPET_CFG);
238 static void hpet_reset_counter(void)
240 hpet_writel(0, HPET_COUNTER);
241 hpet_writel(0, HPET_COUNTER + 4);
244 static void hpet_start_counter(void)
246 unsigned int cfg = hpet_readl(HPET_CFG);
247 cfg |= HPET_CFG_ENABLE;
248 hpet_writel(cfg, HPET_CFG);
251 static void hpet_restart_counter(void)
254 hpet_reset_counter();
255 hpet_start_counter();
258 static void hpet_resume_device(void)
263 static void hpet_resume_counter(struct clocksource *cs)
265 hpet_resume_device();
266 hpet_restart_counter();
269 static void hpet_enable_legacy_int(void)
271 unsigned int cfg = hpet_readl(HPET_CFG);
273 cfg |= HPET_CFG_LEGACY;
274 hpet_writel(cfg, HPET_CFG);
275 hpet_legacy_int_enabled = 1;
278 static void hpet_legacy_clockevent_register(void)
280 /* Start HPET legacy interrupts */
281 hpet_enable_legacy_int();
284 * Start hpet with the boot cpu mask and make it
285 * global after the IO_APIC has been initialized.
287 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
288 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
289 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
290 global_clock_event = &hpet_clockevent;
291 printk(KERN_DEBUG "hpet clockevent registered\n");
294 static int hpet_set_periodic(struct clock_event_device *evt, int timer)
296 unsigned int cfg, cmp, now;
300 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
301 delta >>= evt->shift;
302 now = hpet_readl(HPET_COUNTER);
303 cmp = now + (unsigned int)delta;
304 cfg = hpet_readl(HPET_Tn_CFG(timer));
305 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
307 hpet_writel(cfg, HPET_Tn_CFG(timer));
308 hpet_writel(cmp, HPET_Tn_CMP(timer));
311 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
312 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
313 * bit is automatically cleared after the first write.
314 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
315 * Publication # 24674)
317 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
318 hpet_start_counter();
324 static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
328 cfg = hpet_readl(HPET_Tn_CFG(timer));
329 cfg &= ~HPET_TN_PERIODIC;
330 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
331 hpet_writel(cfg, HPET_Tn_CFG(timer));
336 static int hpet_shutdown(struct clock_event_device *evt, int timer)
340 cfg = hpet_readl(HPET_Tn_CFG(timer));
341 cfg &= ~HPET_TN_ENABLE;
342 hpet_writel(cfg, HPET_Tn_CFG(timer));
347 static int hpet_resume(struct clock_event_device *evt, int timer)
350 hpet_enable_legacy_int();
352 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
354 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
355 disable_irq(hdev->irq);
356 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
357 enable_irq(hdev->irq);
364 static int hpet_next_event(unsigned long delta,
365 struct clock_event_device *evt, int timer)
370 cnt = hpet_readl(HPET_COUNTER);
372 hpet_writel(cnt, HPET_Tn_CMP(timer));
375 * HPETs are a complete disaster. The compare register is
376 * based on a equal comparison and neither provides a less
377 * than or equal functionality (which would require to take
378 * the wraparound into account) nor a simple count down event
379 * mode. Further the write to the comparator register is
380 * delayed internally up to two HPET clock cycles in certain
381 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
382 * longer delays. We worked around that by reading back the
383 * compare register, but that required another workaround for
384 * ICH9,10 chips where the first readout after write can
385 * return the old stale value. We already had a minimum
386 * programming delta of 5us enforced, but a NMI or SMI hitting
387 * between the counter readout and the comparator write can
388 * move us behind that point easily. Now instead of reading
389 * the compare register back several times, we make the ETIME
390 * decision based on the following: Return ETIME if the
391 * counter value after the write is less than HPET_MIN_CYCLES
392 * away from the event or if the counter is already ahead of
393 * the event. The minimum programming delta for the generic
394 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
396 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
398 return res < HPET_MIN_CYCLES ? -ETIME : 0;
401 static int hpet_legacy_shutdown(struct clock_event_device *evt)
403 return hpet_shutdown(evt, 0);
406 static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
408 return hpet_set_oneshot(evt, 0);
411 static int hpet_legacy_set_periodic(struct clock_event_device *evt)
413 return hpet_set_periodic(evt, 0);
416 static int hpet_legacy_resume(struct clock_event_device *evt)
418 return hpet_resume(evt, 0);
421 static int hpet_legacy_next_event(unsigned long delta,
422 struct clock_event_device *evt)
424 return hpet_next_event(delta, evt, 0);
428 * The hpet clock event device
430 static struct clock_event_device hpet_clockevent = {
432 .features = CLOCK_EVT_FEAT_PERIODIC |
433 CLOCK_EVT_FEAT_ONESHOT,
434 .set_state_periodic = hpet_legacy_set_periodic,
435 .set_state_oneshot = hpet_legacy_set_oneshot,
436 .set_state_shutdown = hpet_legacy_shutdown,
437 .tick_resume = hpet_legacy_resume,
438 .set_next_event = hpet_legacy_next_event,
446 #ifdef CONFIG_PCI_MSI
448 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
449 static struct hpet_dev *hpet_devs;
450 static struct irq_domain *hpet_domain;
452 void hpet_msi_unmask(struct irq_data *data)
454 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
458 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
459 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
460 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
463 void hpet_msi_mask(struct irq_data *data)
465 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
469 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
470 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
471 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
474 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
476 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
477 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
480 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
482 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
483 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
487 static int hpet_msi_shutdown(struct clock_event_device *evt)
489 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
491 return hpet_shutdown(evt, hdev->num);
494 static int hpet_msi_set_oneshot(struct clock_event_device *evt)
496 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
498 return hpet_set_oneshot(evt, hdev->num);
501 static int hpet_msi_set_periodic(struct clock_event_device *evt)
503 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
505 return hpet_set_periodic(evt, hdev->num);
508 static int hpet_msi_resume(struct clock_event_device *evt)
510 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
512 return hpet_resume(evt, hdev->num);
515 static int hpet_msi_next_event(unsigned long delta,
516 struct clock_event_device *evt)
518 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
519 return hpet_next_event(delta, evt, hdev->num);
522 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
524 struct hpet_dev *dev = (struct hpet_dev *)data;
525 struct clock_event_device *hevt = &dev->evt;
527 if (!hevt->event_handler) {
528 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
533 hevt->event_handler(hevt);
537 static int hpet_setup_irq(struct hpet_dev *dev)
540 if (request_irq(dev->irq, hpet_interrupt_handler,
541 IRQF_TIMER | IRQF_NOBALANCING,
545 disable_irq(dev->irq);
546 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
547 enable_irq(dev->irq);
549 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
550 dev->name, dev->irq);
555 /* This should be called in specific @cpu */
556 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
558 struct clock_event_device *evt = &hdev->evt;
560 WARN_ON(cpu != smp_processor_id());
561 if (!(hdev->flags & HPET_DEV_VALID))
565 per_cpu(cpu_hpet_dev, cpu) = hdev;
566 evt->name = hdev->name;
567 hpet_setup_irq(hdev);
568 evt->irq = hdev->irq;
571 evt->features = CLOCK_EVT_FEAT_ONESHOT;
572 if (hdev->flags & HPET_DEV_PERI_CAP) {
573 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
574 evt->set_state_periodic = hpet_msi_set_periodic;
577 evt->set_state_shutdown = hpet_msi_shutdown;
578 evt->set_state_oneshot = hpet_msi_set_oneshot;
579 evt->tick_resume = hpet_msi_resume;
580 evt->set_next_event = hpet_msi_next_event;
581 evt->cpumask = cpumask_of(hdev->cpu);
583 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
588 /* Reserve at least one timer for userspace (/dev/hpet) */
589 #define RESERVE_TIMERS 1
591 #define RESERVE_TIMERS 0
594 static void hpet_msi_capability_lookup(unsigned int start_timer)
597 unsigned int num_timers;
598 unsigned int num_timers_used = 0;
601 if (hpet_msi_disable)
604 if (boot_cpu_has(X86_FEATURE_ARAT))
606 id = hpet_readl(HPET_ID);
608 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
609 num_timers++; /* Value read out starts from 0 */
612 hpet_domain = hpet_create_irq_domain(hpet_blockid);
616 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
620 hpet_num_timers = num_timers;
622 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
623 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
624 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
626 /* Only consider HPET timer with MSI support */
627 if (!(cfg & HPET_TN_FSB_CAP))
631 if (cfg & HPET_TN_PERIODIC_CAP)
632 hdev->flags |= HPET_DEV_PERI_CAP;
633 sprintf(hdev->name, "hpet%d", i);
636 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
641 hdev->flags |= HPET_DEV_FSB_CAP;
642 hdev->flags |= HPET_DEV_VALID;
644 if (num_timers_used == num_possible_cpus())
648 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
649 num_timers, num_timers_used);
653 static void hpet_reserve_msi_timers(struct hpet_data *hd)
660 for (i = 0; i < hpet_num_timers; i++) {
661 struct hpet_dev *hdev = &hpet_devs[i];
663 if (!(hdev->flags & HPET_DEV_VALID))
666 hd->hd_irq[hdev->num] = hdev->irq;
667 hpet_reserve_timer(hd, hdev->num);
672 static struct hpet_dev *hpet_get_unused_timer(void)
679 for (i = 0; i < hpet_num_timers; i++) {
680 struct hpet_dev *hdev = &hpet_devs[i];
682 if (!(hdev->flags & HPET_DEV_VALID))
684 if (test_and_set_bit(HPET_DEV_USED_BIT,
685 (unsigned long *)&hdev->flags))
692 struct hpet_work_struct {
693 struct delayed_work work;
694 struct completion complete;
697 static void hpet_work(struct work_struct *w)
699 struct hpet_dev *hdev;
700 int cpu = smp_processor_id();
701 struct hpet_work_struct *hpet_work;
703 hpet_work = container_of(w, struct hpet_work_struct, work.work);
705 hdev = hpet_get_unused_timer();
707 init_one_hpet_msi_clockevent(hdev, cpu);
709 complete(&hpet_work->complete);
712 static int hpet_cpuhp_notify(struct notifier_block *n,
713 unsigned long action, void *hcpu)
715 unsigned long cpu = (unsigned long)hcpu;
716 struct hpet_work_struct work;
717 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
719 switch (action & 0xf) {
721 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
722 init_completion(&work.complete);
723 /* FIXME: add schedule_work_on() */
724 schedule_delayed_work_on(cpu, &work.work, 0);
725 wait_for_completion(&work.complete);
726 destroy_delayed_work_on_stack(&work.work);
730 free_irq(hdev->irq, hdev);
731 hdev->flags &= ~HPET_DEV_USED;
732 per_cpu(cpu_hpet_dev, cpu) = NULL;
740 static void hpet_msi_capability_lookup(unsigned int start_timer)
746 static void hpet_reserve_msi_timers(struct hpet_data *hd)
752 static int hpet_cpuhp_notify(struct notifier_block *n,
753 unsigned long action, void *hcpu)
761 * Clock source related code
763 static cycle_t read_hpet(struct clocksource *cs)
765 return (cycle_t)hpet_readl(HPET_COUNTER);
768 static struct clocksource clocksource_hpet = {
773 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
774 .resume = hpet_resume_counter,
775 .archdata = { .vclock_mode = VCLOCK_HPET },
778 static int hpet_clocksource_register(void)
783 /* Start the counter */
784 hpet_restart_counter();
786 /* Verify whether hpet counter works */
787 t1 = hpet_readl(HPET_COUNTER);
791 * We don't know the TSC frequency yet, but waiting for
792 * 200000 TSC cycles is safe:
799 } while ((now - start) < 200000UL);
801 if (t1 == hpet_readl(HPET_COUNTER)) {
803 "HPET counter not counting. HPET disabled\n");
807 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
811 static u32 *hpet_boot_cfg;
814 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
816 int __init hpet_enable(void)
818 u32 hpet_period, cfg, id;
820 unsigned int i, last;
822 if (!is_hpet_capable())
828 * Read the period and check for a sane value:
830 hpet_period = hpet_readl(HPET_PERIOD);
833 * AMD SB700 based systems with spread spectrum enabled use a
834 * SMM based HPET emulation to provide proper frequency
835 * setting. The SMM code is initialized with the first HPET
836 * register access and takes some time to complete. During
837 * this time the config register reads 0xffffffff. We check
838 * for max. 1000 loops whether the config register reads a non
839 * 0xffffffff value to make sure that HPET is up and running
840 * before we go further. A counting loop is safe, as the HPET
841 * access takes thousands of CPU cycles. On non SB700 based
842 * machines this check is only done once and has no side
845 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
848 "HPET config register value = 0xFFFFFFFF. "
854 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
858 * The period is a femto seconds value. Convert it to a
862 do_div(freq, hpet_period);
866 * Read the HPET ID register to retrieve the IRQ routing
867 * information and the number of channels
869 id = hpet_readl(HPET_ID);
872 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
874 #ifdef CONFIG_HPET_EMULATE_RTC
876 * The legacy routing mode needs at least two channels, tick timer
877 * and the rtc emulation channel.
883 cfg = hpet_readl(HPET_CFG);
884 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
887 *hpet_boot_cfg = cfg;
889 pr_warn("HPET initial state will not be saved\n");
890 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
891 hpet_writel(cfg, HPET_CFG);
893 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
896 for (i = 0; i <= last; ++i) {
897 cfg = hpet_readl(HPET_Tn_CFG(i));
899 hpet_boot_cfg[i + 1] = cfg;
900 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
901 hpet_writel(cfg, HPET_Tn_CFG(i));
902 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
903 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
904 | HPET_TN_FSB | HPET_TN_FSB_CAP);
906 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
911 if (hpet_clocksource_register())
914 if (id & HPET_ID_LEGSUP) {
915 hpet_legacy_clockevent_register();
921 hpet_clear_mapping();
927 * Needs to be late, as the reserve_timer code calls kalloc !
929 * Not a problem on i386 as hpet_enable is called from late_time_init,
930 * but on x86_64 it is necessary !
932 static __init int hpet_late_init(void)
936 if (boot_hpet_disable)
940 if (!force_hpet_address)
943 hpet_address = force_hpet_address;
947 if (!hpet_virt_address)
950 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
951 hpet_msi_capability_lookup(2);
953 hpet_msi_capability_lookup(0);
955 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
958 if (hpet_msi_disable)
961 if (boot_cpu_has(X86_FEATURE_ARAT))
964 cpu_notifier_register_begin();
965 for_each_online_cpu(cpu) {
966 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
969 /* This notifier should be called after workqueue is ready */
970 __hotcpu_notifier(hpet_cpuhp_notify, -20);
971 cpu_notifier_register_done();
975 fs_initcall(hpet_late_init);
977 void hpet_disable(void)
979 if (is_hpet_capable() && hpet_virt_address) {
980 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
983 cfg = *hpet_boot_cfg;
984 else if (hpet_legacy_int_enabled) {
985 cfg &= ~HPET_CFG_LEGACY;
986 hpet_legacy_int_enabled = 0;
988 cfg &= ~HPET_CFG_ENABLE;
989 hpet_writel(cfg, HPET_CFG);
994 id = hpet_readl(HPET_ID);
995 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
997 for (id = 0; id <= last; ++id)
998 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1000 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1001 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1005 #ifdef CONFIG_HPET_EMULATE_RTC
1007 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1008 * is enabled, we support RTC interrupt functionality in software.
1009 * RTC has 3 kinds of interrupts:
1010 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1012 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1013 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1014 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1015 * (1) and (2) above are implemented using polling at a frequency of
1016 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1017 * overhead. (DEFAULT_RTC_INT_FREQ)
1018 * For (3), we use interrupts at 64Hz or user specified periodic
1019 * frequency, whichever is higher.
1021 #include <linux/mc146818rtc.h>
1022 #include <linux/rtc.h>
1023 #include <asm/rtc.h>
1025 #define DEFAULT_RTC_INT_FREQ 64
1026 #define DEFAULT_RTC_SHIFT 6
1027 #define RTC_NUM_INTS 1
1029 static unsigned long hpet_rtc_flags;
1030 static int hpet_prev_update_sec;
1031 static struct rtc_time hpet_alarm_time;
1032 static unsigned long hpet_pie_count;
1033 static u32 hpet_t1_cmp;
1034 static u32 hpet_default_delta;
1035 static u32 hpet_pie_delta;
1036 static unsigned long hpet_pie_limit;
1038 static rtc_irq_handler irq_handler;
1041 * Check that the hpet counter c1 is ahead of the c2
1043 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1045 return (s32)(c2 - c1) < 0;
1049 * Registers a IRQ handler.
1051 int hpet_register_irq_handler(rtc_irq_handler handler)
1053 if (!is_hpet_enabled())
1058 irq_handler = handler;
1062 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1065 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1068 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1070 if (!is_hpet_enabled())
1076 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1079 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1080 * is not supported by all HPET implementations for timer 1.
1082 * hpet_rtc_timer_init() is called when the rtc is initialized.
1084 int hpet_rtc_timer_init(void)
1086 unsigned int cfg, cnt, delta;
1087 unsigned long flags;
1089 if (!is_hpet_enabled())
1092 if (!hpet_default_delta) {
1095 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1096 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1097 hpet_default_delta = clc;
1100 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1101 delta = hpet_default_delta;
1103 delta = hpet_pie_delta;
1105 local_irq_save(flags);
1107 cnt = delta + hpet_readl(HPET_COUNTER);
1108 hpet_writel(cnt, HPET_T1_CMP);
1111 cfg = hpet_readl(HPET_T1_CFG);
1112 cfg &= ~HPET_TN_PERIODIC;
1113 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1114 hpet_writel(cfg, HPET_T1_CFG);
1116 local_irq_restore(flags);
1120 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1122 static void hpet_disable_rtc_channel(void)
1125 cfg = hpet_readl(HPET_T1_CFG);
1126 cfg &= ~HPET_TN_ENABLE;
1127 hpet_writel(cfg, HPET_T1_CFG);
1131 * The functions below are called from rtc driver.
1132 * Return 0 if HPET is not being used.
1133 * Otherwise do the necessary changes and return 1.
1135 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1137 if (!is_hpet_enabled())
1140 hpet_rtc_flags &= ~bit_mask;
1141 if (unlikely(!hpet_rtc_flags))
1142 hpet_disable_rtc_channel();
1146 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1148 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1150 unsigned long oldbits = hpet_rtc_flags;
1152 if (!is_hpet_enabled())
1155 hpet_rtc_flags |= bit_mask;
1157 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1158 hpet_prev_update_sec = -1;
1161 hpet_rtc_timer_init();
1165 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1167 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1170 if (!is_hpet_enabled())
1173 hpet_alarm_time.tm_hour = hrs;
1174 hpet_alarm_time.tm_min = min;
1175 hpet_alarm_time.tm_sec = sec;
1179 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1181 int hpet_set_periodic_freq(unsigned long freq)
1185 if (!is_hpet_enabled())
1188 if (freq <= DEFAULT_RTC_INT_FREQ)
1189 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1191 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1193 clc >>= hpet_clockevent.shift;
1194 hpet_pie_delta = clc;
1199 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1201 int hpet_rtc_dropped_irq(void)
1203 return is_hpet_enabled();
1205 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1207 static void hpet_rtc_timer_reinit(void)
1212 if (unlikely(!hpet_rtc_flags))
1213 hpet_disable_rtc_channel();
1215 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1216 delta = hpet_default_delta;
1218 delta = hpet_pie_delta;
1221 * Increment the comparator value until we are ahead of the
1225 hpet_t1_cmp += delta;
1226 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1228 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1231 if (hpet_rtc_flags & RTC_PIE)
1232 hpet_pie_count += lost_ints;
1233 if (printk_ratelimit())
1234 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1239 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1241 struct rtc_time curr_time;
1242 unsigned long rtc_int_flag = 0;
1244 hpet_rtc_timer_reinit();
1245 memset(&curr_time, 0, sizeof(struct rtc_time));
1247 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1248 get_rtc_time(&curr_time);
1250 if (hpet_rtc_flags & RTC_UIE &&
1251 curr_time.tm_sec != hpet_prev_update_sec) {
1252 if (hpet_prev_update_sec >= 0)
1253 rtc_int_flag = RTC_UF;
1254 hpet_prev_update_sec = curr_time.tm_sec;
1257 if (hpet_rtc_flags & RTC_PIE &&
1258 ++hpet_pie_count >= hpet_pie_limit) {
1259 rtc_int_flag |= RTC_PF;
1263 if (hpet_rtc_flags & RTC_AIE &&
1264 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1265 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1266 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1267 rtc_int_flag |= RTC_AF;
1270 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1272 irq_handler(rtc_int_flag, dev_id);
1276 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);