2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 static int __init parse_noapic(char *str)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic);
113 struct irq_pin_list *irq_2_pin;
115 cpumask_t old_domain;
116 unsigned move_cleanup_count;
118 u8 move_in_progress : 1;
121 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
122 static struct irq_cfg irq_cfgx[NR_IRQS] = {
123 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
124 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
125 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
126 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
127 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
128 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
129 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
130 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
131 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
132 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
133 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
134 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
135 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
136 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
137 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
138 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
141 #define for_each_irq_cfg(irq, cfg) \
142 for (irq = 0, cfg = irq_cfgx; irq < nr_irqs; irq++, cfg++)
144 static struct irq_cfg *irq_cfg(unsigned int irq)
146 return irq < nr_irqs ? irq_cfgx + irq : NULL;
149 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
155 * Rough estimation of how many shared IRQs there are, can be changed
158 #define MAX_PLUS_SHARED_IRQS NR_IRQS
159 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
162 * This is performance-critical, we want to do it O(1)
164 * the indexing order of this array favors 1:1 mappings
165 * between pins and IRQs.
168 struct irq_pin_list {
170 struct irq_pin_list *next;
173 static struct irq_pin_list irq_2_pin_head[PIN_MAP_SIZE];
174 static struct irq_pin_list *irq_2_pin_ptr;
176 static void __init irq_2_pin_init(void)
178 struct irq_pin_list *pin = irq_2_pin_head;
181 for (i = 1; i < PIN_MAP_SIZE; i++)
182 pin[i-1].next = &pin[i];
184 irq_2_pin_ptr = &pin[0];
187 static struct irq_pin_list *get_one_free_irq_2_pin(void)
189 struct irq_pin_list *pin = irq_2_pin_ptr;
192 panic("can not get more irq_2_pin\n");
194 irq_2_pin_ptr = pin->next;
201 unsigned int unused[3];
205 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
207 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
208 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
211 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
213 struct io_apic __iomem *io_apic = io_apic_base(apic);
214 writel(reg, &io_apic->index);
215 return readl(&io_apic->data);
218 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
220 struct io_apic __iomem *io_apic = io_apic_base(apic);
221 writel(reg, &io_apic->index);
222 writel(value, &io_apic->data);
226 * Re-write a value: to be used for read-modify-write
227 * cycles where the read already set up the index register.
229 * Older SiS APIC requires we rewrite the index register
231 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
233 struct io_apic __iomem *io_apic = io_apic_base(apic);
236 writel(reg, &io_apic->index);
237 writel(value, &io_apic->data);
240 static bool io_apic_level_ack_pending(unsigned int irq)
242 struct irq_pin_list *entry;
244 struct irq_cfg *cfg = irq_cfg(irq);
246 spin_lock_irqsave(&ioapic_lock, flags);
247 entry = cfg->irq_2_pin;
255 reg = io_apic_read(entry->apic, 0x10 + pin*2);
256 /* Is the remote IRR bit set? */
257 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
258 spin_unlock_irqrestore(&ioapic_lock, flags);
265 spin_unlock_irqrestore(&ioapic_lock, flags);
271 struct { u32 w1, w2; };
272 struct IO_APIC_route_entry entry;
275 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
277 union entry_union eu;
279 spin_lock_irqsave(&ioapic_lock, flags);
280 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
281 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
282 spin_unlock_irqrestore(&ioapic_lock, flags);
287 * When we write a new IO APIC routing entry, we need to write the high
288 * word first! If the mask bit in the low word is clear, we will enable
289 * the interrupt, and we need to make sure the entry is fully populated
290 * before that happens.
293 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
295 union entry_union eu;
297 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
298 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
301 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
304 spin_lock_irqsave(&ioapic_lock, flags);
305 __ioapic_write_entry(apic, pin, e);
306 spin_unlock_irqrestore(&ioapic_lock, flags);
310 * When we mask an IO APIC routing entry, we need to write the low
311 * word first, in order to set the mask bit before we change the
314 static void ioapic_mask_entry(int apic, int pin)
317 union entry_union eu = { .entry.mask = 1 };
319 spin_lock_irqsave(&ioapic_lock, flags);
320 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
321 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
322 spin_unlock_irqrestore(&ioapic_lock, flags);
326 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
330 struct irq_pin_list *entry;
333 entry = cfg->irq_2_pin;
342 #ifdef CONFIG_INTR_REMAP
344 * With interrupt-remapping, destination information comes
345 * from interrupt-remapping table entry.
347 if (!irq_remapped(irq))
348 io_apic_write(apic, 0x11 + pin*2, dest);
350 io_apic_write(apic, 0x11 + pin*2, dest);
352 reg = io_apic_read(apic, 0x10 + pin*2);
353 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
355 io_apic_modify(apic, 0x10 + pin*2, reg);
362 static int assign_irq_vector(int irq, cpumask_t mask);
364 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
370 struct irq_desc *desc;
372 cpus_and(tmp, mask, cpu_online_map);
377 if (assign_irq_vector(irq, mask))
380 cpus_and(tmp, cfg->domain, mask);
381 dest = cpu_mask_to_apicid(tmp);
383 * Only the high 8 bits are valid.
385 dest = SET_APIC_LOGICAL_ID(dest);
387 desc = irq_to_desc(irq);
388 spin_lock_irqsave(&ioapic_lock, flags);
389 __target_IO_APIC_irq(irq, dest, cfg->vector);
390 desc->affinity = mask;
391 spin_unlock_irqrestore(&ioapic_lock, flags);
393 #endif /* CONFIG_SMP */
396 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
397 * shared ISA-space IRQs, so we have to support them. We are super
398 * fast in the common case, and fast for shared ISA-space IRQs.
400 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
403 struct irq_pin_list *entry;
405 /* first time to refer irq_cfg, so with new */
406 cfg = irq_cfg_alloc(irq);
407 entry = cfg->irq_2_pin;
409 entry = get_one_free_irq_2_pin();
410 cfg->irq_2_pin = entry;
416 while (entry->next) {
417 /* not again, please */
418 if (entry->apic == apic && entry->pin == pin)
424 entry->next = get_one_free_irq_2_pin();
431 * Reroute an IRQ to a different pin.
433 static void __init replace_pin_at_irq(unsigned int irq,
434 int oldapic, int oldpin,
435 int newapic, int newpin)
437 struct irq_cfg *cfg = irq_cfg(irq);
438 struct irq_pin_list *entry = cfg->irq_2_pin;
442 if (entry->apic == oldapic && entry->pin == oldpin) {
443 entry->apic = newapic;
446 /* every one is different, right? */
452 /* why? call replace before add? */
454 add_pin_to_irq(irq, newapic, newpin);
457 static inline void io_apic_modify_irq(unsigned int irq,
458 int mask_and, int mask_or,
459 void (*final)(struct irq_pin_list *entry))
463 struct irq_pin_list *entry;
466 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
469 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
472 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
478 static void __unmask_IO_APIC_irq(unsigned int irq)
480 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, 0, NULL);
484 void io_apic_sync(struct irq_pin_list *entry)
487 * Synchronize the IO-APIC and the CPU by doing
488 * a dummy read from the IO-APIC
490 struct io_apic __iomem *io_apic;
491 io_apic = io_apic_base(entry->apic);
492 readl(&io_apic->data);
495 static void __mask_IO_APIC_irq(unsigned int irq)
497 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
499 #else /* CONFIG_X86_32 */
500 static void __mask_IO_APIC_irq(unsigned int irq)
502 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, NULL);
505 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
507 io_apic_modify_irq(irq, ~IO_APIC_REDIR_LEVEL_TRIGGER,
508 IO_APIC_REDIR_MASKED, NULL);
511 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
513 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED,
514 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
516 #endif /* CONFIG_X86_32 */
518 static void mask_IO_APIC_irq (unsigned int irq)
522 spin_lock_irqsave(&ioapic_lock, flags);
523 __mask_IO_APIC_irq(irq);
524 spin_unlock_irqrestore(&ioapic_lock, flags);
527 static void unmask_IO_APIC_irq (unsigned int irq)
531 spin_lock_irqsave(&ioapic_lock, flags);
532 __unmask_IO_APIC_irq(irq);
533 spin_unlock_irqrestore(&ioapic_lock, flags);
536 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
538 struct IO_APIC_route_entry entry;
540 /* Check delivery_mode to be sure we're not clearing an SMI pin */
541 entry = ioapic_read_entry(apic, pin);
542 if (entry.delivery_mode == dest_SMI)
545 * Disable it in the IO-APIC irq-routing table:
547 ioapic_mask_entry(apic, pin);
550 static void clear_IO_APIC (void)
554 for (apic = 0; apic < nr_ioapics; apic++)
555 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
556 clear_IO_APIC_pin(apic, pin);
559 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
560 void send_IPI_self(int vector)
567 apic_wait_icr_idle();
568 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
570 * Send the IPI. The write to APIC_ICR fires this off.
572 apic_write(APIC_ICR, cfg);
574 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
578 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
579 * specific CPU-side IRQs.
583 static int pirq_entries [MAX_PIRQS];
584 static int pirqs_enabled;
586 static int __init ioapic_pirq_setup(char *str)
589 int ints[MAX_PIRQS+1];
591 get_options(str, ARRAY_SIZE(ints), ints);
593 for (i = 0; i < MAX_PIRQS; i++)
594 pirq_entries[i] = -1;
597 apic_printk(APIC_VERBOSE, KERN_INFO
598 "PIRQ redirection, working around broken MP-BIOS.\n");
600 if (ints[0] < MAX_PIRQS)
603 for (i = 0; i < max; i++) {
604 apic_printk(APIC_VERBOSE, KERN_DEBUG
605 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
607 * PIRQs are mapped upside down, usually.
609 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
614 __setup("pirq=", ioapic_pirq_setup);
615 #endif /* CONFIG_X86_32 */
617 #ifdef CONFIG_INTR_REMAP
618 /* I/O APIC RTE contents at the OS boot up */
619 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
622 * Saves and masks all the unmasked IO-APIC RTE's
624 int save_mask_IO_APIC_setup(void)
626 union IO_APIC_reg_01 reg_01;
631 * The number of IO-APIC IRQ registers (== #pins):
633 for (apic = 0; apic < nr_ioapics; apic++) {
634 spin_lock_irqsave(&ioapic_lock, flags);
635 reg_01.raw = io_apic_read(apic, 1);
636 spin_unlock_irqrestore(&ioapic_lock, flags);
637 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
640 for (apic = 0; apic < nr_ioapics; apic++) {
641 early_ioapic_entries[apic] =
642 kzalloc(sizeof(struct IO_APIC_route_entry) *
643 nr_ioapic_registers[apic], GFP_KERNEL);
644 if (!early_ioapic_entries[apic])
648 for (apic = 0; apic < nr_ioapics; apic++)
649 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
650 struct IO_APIC_route_entry entry;
652 entry = early_ioapic_entries[apic][pin] =
653 ioapic_read_entry(apic, pin);
656 ioapic_write_entry(apic, pin, entry);
664 kfree(early_ioapic_entries[apic--]);
665 memset(early_ioapic_entries, 0,
666 ARRAY_SIZE(early_ioapic_entries));
671 void restore_IO_APIC_setup(void)
675 for (apic = 0; apic < nr_ioapics; apic++) {
676 if (!early_ioapic_entries[apic])
678 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
679 ioapic_write_entry(apic, pin,
680 early_ioapic_entries[apic][pin]);
681 kfree(early_ioapic_entries[apic]);
682 early_ioapic_entries[apic] = NULL;
686 void reinit_intr_remapped_IO_APIC(int intr_remapping)
689 * for now plain restore of previous settings.
690 * TBD: In the case of OS enabling interrupt-remapping,
691 * IO-APIC RTE's need to be setup to point to interrupt-remapping
692 * table entries. for now, do a plain restore, and wait for
693 * the setup_IO_APIC_irqs() to do proper initialization.
695 restore_IO_APIC_setup();
700 * Find the IRQ entry number of a certain pin.
702 static int find_irq_entry(int apic, int pin, int type)
706 for (i = 0; i < mp_irq_entries; i++)
707 if (mp_irqs[i].mp_irqtype == type &&
708 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
709 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
710 mp_irqs[i].mp_dstirq == pin)
717 * Find the pin to which IRQ[irq] (ISA) is connected
719 static int __init find_isa_irq_pin(int irq, int type)
723 for (i = 0; i < mp_irq_entries; i++) {
724 int lbus = mp_irqs[i].mp_srcbus;
726 if (test_bit(lbus, mp_bus_not_pci) &&
727 (mp_irqs[i].mp_irqtype == type) &&
728 (mp_irqs[i].mp_srcbusirq == irq))
730 return mp_irqs[i].mp_dstirq;
735 static int __init find_isa_irq_apic(int irq, int type)
739 for (i = 0; i < mp_irq_entries; i++) {
740 int lbus = mp_irqs[i].mp_srcbus;
742 if (test_bit(lbus, mp_bus_not_pci) &&
743 (mp_irqs[i].mp_irqtype == type) &&
744 (mp_irqs[i].mp_srcbusirq == irq))
747 if (i < mp_irq_entries) {
749 for(apic = 0; apic < nr_ioapics; apic++) {
750 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
759 * Find a specific PCI IRQ entry.
760 * Not an __init, possibly needed by modules
762 static int pin_2_irq(int idx, int apic, int pin);
764 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
766 int apic, i, best_guess = -1;
768 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
770 if (test_bit(bus, mp_bus_not_pci)) {
771 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
774 for (i = 0; i < mp_irq_entries; i++) {
775 int lbus = mp_irqs[i].mp_srcbus;
777 for (apic = 0; apic < nr_ioapics; apic++)
778 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
779 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
782 if (!test_bit(lbus, mp_bus_not_pci) &&
783 !mp_irqs[i].mp_irqtype &&
785 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
786 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
788 if (!(apic || IO_APIC_IRQ(irq)))
791 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
794 * Use the first all-but-pin matching entry as a
795 * best-guess fuzzy result for broken mptables.
804 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
806 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
808 * EISA Edge/Level control register, ELCR
810 static int EISA_ELCR(unsigned int irq)
813 unsigned int port = 0x4d0 + (irq >> 3);
814 return (inb(port) >> (irq & 7)) & 1;
816 apic_printk(APIC_VERBOSE, KERN_INFO
817 "Broken MPtable reports ISA irq %d\n", irq);
823 /* ISA interrupts are always polarity zero edge triggered,
824 * when listed as conforming in the MP table. */
826 #define default_ISA_trigger(idx) (0)
827 #define default_ISA_polarity(idx) (0)
829 /* EISA interrupts are always polarity zero and can be edge or level
830 * trigger depending on the ELCR value. If an interrupt is listed as
831 * EISA conforming in the MP table, that means its trigger type must
832 * be read in from the ELCR */
834 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
835 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
837 /* PCI interrupts are always polarity one level triggered,
838 * when listed as conforming in the MP table. */
840 #define default_PCI_trigger(idx) (1)
841 #define default_PCI_polarity(idx) (1)
843 /* MCA interrupts are always polarity zero level triggered,
844 * when listed as conforming in the MP table. */
846 #define default_MCA_trigger(idx) (1)
847 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
849 static int MPBIOS_polarity(int idx)
851 int bus = mp_irqs[idx].mp_srcbus;
855 * Determine IRQ line polarity (high active or low active):
857 switch (mp_irqs[idx].mp_irqflag & 3)
859 case 0: /* conforms, ie. bus-type dependent polarity */
860 if (test_bit(bus, mp_bus_not_pci))
861 polarity = default_ISA_polarity(idx);
863 polarity = default_PCI_polarity(idx);
865 case 1: /* high active */
870 case 2: /* reserved */
872 printk(KERN_WARNING "broken BIOS!!\n");
876 case 3: /* low active */
881 default: /* invalid */
883 printk(KERN_WARNING "broken BIOS!!\n");
891 static int MPBIOS_trigger(int idx)
893 int bus = mp_irqs[idx].mp_srcbus;
897 * Determine IRQ trigger mode (edge or level sensitive):
899 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
901 case 0: /* conforms, ie. bus-type dependent */
902 if (test_bit(bus, mp_bus_not_pci))
903 trigger = default_ISA_trigger(idx);
905 trigger = default_PCI_trigger(idx);
906 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
907 switch (mp_bus_id_to_type[bus]) {
908 case MP_BUS_ISA: /* ISA pin */
910 /* set before the switch */
913 case MP_BUS_EISA: /* EISA pin */
915 trigger = default_EISA_trigger(idx);
918 case MP_BUS_PCI: /* PCI pin */
920 /* set before the switch */
923 case MP_BUS_MCA: /* MCA pin */
925 trigger = default_MCA_trigger(idx);
930 printk(KERN_WARNING "broken BIOS!!\n");
942 case 2: /* reserved */
944 printk(KERN_WARNING "broken BIOS!!\n");
953 default: /* invalid */
955 printk(KERN_WARNING "broken BIOS!!\n");
963 static inline int irq_polarity(int idx)
965 return MPBIOS_polarity(idx);
968 static inline int irq_trigger(int idx)
970 return MPBIOS_trigger(idx);
973 int (*ioapic_renumber_irq)(int ioapic, int irq);
974 static int pin_2_irq(int idx, int apic, int pin)
977 int bus = mp_irqs[idx].mp_srcbus;
980 * Debugging check, we are in big trouble if this message pops up!
982 if (mp_irqs[idx].mp_dstirq != pin)
983 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
985 if (test_bit(bus, mp_bus_not_pci)) {
986 irq = mp_irqs[idx].mp_srcbusirq;
989 * PCI IRQs are mapped in order
993 irq += nr_ioapic_registers[i++];
996 * For MPS mode, so far only needed by ES7000 platform
998 if (ioapic_renumber_irq)
999 irq = ioapic_renumber_irq(apic, irq);
1002 #ifdef CONFIG_X86_32
1004 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1006 if ((pin >= 16) && (pin <= 23)) {
1007 if (pirq_entries[pin-16] != -1) {
1008 if (!pirq_entries[pin-16]) {
1009 apic_printk(APIC_VERBOSE, KERN_DEBUG
1010 "disabling PIRQ%d\n", pin-16);
1012 irq = pirq_entries[pin-16];
1013 apic_printk(APIC_VERBOSE, KERN_DEBUG
1014 "using PIRQ%d -> IRQ %d\n",
1024 void lock_vector_lock(void)
1026 /* Used to the online set of cpus does not change
1027 * during assign_irq_vector.
1029 spin_lock(&vector_lock);
1032 void unlock_vector_lock(void)
1034 spin_unlock(&vector_lock);
1037 static int __assign_irq_vector(int irq, cpumask_t mask)
1040 * NOTE! The local APIC isn't very good at handling
1041 * multiple interrupts at the same interrupt level.
1042 * As the interrupt level is determined by taking the
1043 * vector number and shifting that right by 4, we
1044 * want to spread these out a bit so that they don't
1045 * all fall in the same interrupt level.
1047 * Also, we've got to be careful not to trash gate
1048 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1050 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1051 unsigned int old_vector;
1053 struct irq_cfg *cfg;
1057 /* Only try and allocate irqs on cpus that are present */
1058 cpus_and(mask, mask, cpu_online_map);
1060 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1063 old_vector = cfg->vector;
1066 cpus_and(tmp, cfg->domain, mask);
1067 if (!cpus_empty(tmp))
1071 for_each_cpu_mask_nr(cpu, mask) {
1072 cpumask_t domain, new_mask;
1076 domain = vector_allocation_domain(cpu);
1077 cpus_and(new_mask, domain, cpu_online_map);
1079 vector = current_vector;
1080 offset = current_offset;
1083 if (vector >= first_system_vector) {
1084 /* If we run out of vectors on large boxen, must share them. */
1085 offset = (offset + 1) % 8;
1086 vector = FIRST_DEVICE_VECTOR + offset;
1088 if (unlikely(current_vector == vector))
1090 #ifdef CONFIG_X86_64
1091 if (vector == IA32_SYSCALL_VECTOR)
1094 if (vector == SYSCALL_VECTOR)
1097 for_each_cpu_mask_nr(new_cpu, new_mask)
1098 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1101 current_vector = vector;
1102 current_offset = offset;
1104 cfg->move_in_progress = 1;
1105 cfg->old_domain = cfg->domain;
1107 for_each_cpu_mask_nr(new_cpu, new_mask)
1108 per_cpu(vector_irq, new_cpu)[vector] = irq;
1109 cfg->vector = vector;
1110 cfg->domain = domain;
1116 static int assign_irq_vector(int irq, cpumask_t mask)
1119 unsigned long flags;
1121 spin_lock_irqsave(&vector_lock, flags);
1122 err = __assign_irq_vector(irq, mask);
1123 spin_unlock_irqrestore(&vector_lock, flags);
1127 static void __clear_irq_vector(int irq)
1129 struct irq_cfg *cfg;
1134 BUG_ON(!cfg->vector);
1136 vector = cfg->vector;
1137 cpus_and(mask, cfg->domain, cpu_online_map);
1138 for_each_cpu_mask_nr(cpu, mask)
1139 per_cpu(vector_irq, cpu)[vector] = -1;
1142 cpus_clear(cfg->domain);
1144 if (likely(!cfg->move_in_progress))
1146 cpus_and(mask, cfg->old_domain, cpu_online_map);
1147 for_each_cpu_mask_nr(cpu, mask) {
1148 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1150 if (per_cpu(vector_irq, cpu)[vector] != irq)
1152 per_cpu(vector_irq, cpu)[vector] = -1;
1156 cfg->move_in_progress = 0;
1159 void __setup_vector_irq(int cpu)
1161 /* Initialize vector_irq on a new cpu */
1162 /* This function must be called with vector_lock held */
1164 struct irq_cfg *cfg;
1166 /* Mark the inuse vectors */
1167 for_each_irq_cfg(irq, cfg) {
1168 if (!cpu_isset(cpu, cfg->domain))
1170 vector = cfg->vector;
1171 per_cpu(vector_irq, cpu)[vector] = irq;
1173 /* Mark the free vectors */
1174 for (vector = 0; vector < NR_VECTORS; ++vector) {
1175 irq = per_cpu(vector_irq, cpu)[vector];
1180 if (!cpu_isset(cpu, cfg->domain))
1181 per_cpu(vector_irq, cpu)[vector] = -1;
1185 static struct irq_chip ioapic_chip;
1186 #ifdef CONFIG_INTR_REMAP
1187 static struct irq_chip ir_ioapic_chip;
1190 #define IOAPIC_AUTO -1
1191 #define IOAPIC_EDGE 0
1192 #define IOAPIC_LEVEL 1
1194 #ifdef CONFIG_X86_32
1195 static inline int IO_APIC_irq_trigger(int irq)
1199 for (apic = 0; apic < nr_ioapics; apic++) {
1200 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1201 idx = find_irq_entry(apic, pin, mp_INT);
1202 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1203 return irq_trigger(idx);
1207 * nonexistent IRQs are edge default
1212 static inline int IO_APIC_irq_trigger(int irq)
1218 static void ioapic_register_intr(int irq, unsigned long trigger)
1220 struct irq_desc *desc;
1222 desc = irq_to_desc(irq);
1224 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1225 trigger == IOAPIC_LEVEL)
1226 desc->status |= IRQ_LEVEL;
1228 desc->status &= ~IRQ_LEVEL;
1230 #ifdef CONFIG_INTR_REMAP
1231 if (irq_remapped(irq)) {
1232 desc->status |= IRQ_MOVE_PCNTXT;
1234 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1238 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1239 handle_edge_irq, "edge");
1243 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1244 trigger == IOAPIC_LEVEL)
1245 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1249 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1250 handle_edge_irq, "edge");
1253 static int setup_ioapic_entry(int apic, int irq,
1254 struct IO_APIC_route_entry *entry,
1255 unsigned int destination, int trigger,
1256 int polarity, int vector)
1259 * add it to the IO-APIC irq-routing table:
1261 memset(entry,0,sizeof(*entry));
1263 #ifdef CONFIG_INTR_REMAP
1264 if (intr_remapping_enabled) {
1265 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1267 struct IR_IO_APIC_route_entry *ir_entry =
1268 (struct IR_IO_APIC_route_entry *) entry;
1272 panic("No mapping iommu for ioapic %d\n", apic);
1274 index = alloc_irte(iommu, irq, 1);
1276 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1278 memset(&irte, 0, sizeof(irte));
1281 irte.dst_mode = INT_DEST_MODE;
1282 irte.trigger_mode = trigger;
1283 irte.dlvry_mode = INT_DELIVERY_MODE;
1284 irte.vector = vector;
1285 irte.dest_id = IRTE_DEST(destination);
1287 modify_irte(irq, &irte);
1289 ir_entry->index2 = (index >> 15) & 0x1;
1291 ir_entry->format = 1;
1292 ir_entry->index = (index & 0x7fff);
1296 entry->delivery_mode = INT_DELIVERY_MODE;
1297 entry->dest_mode = INT_DEST_MODE;
1298 entry->dest = destination;
1301 entry->mask = 0; /* enable IRQ */
1302 entry->trigger = trigger;
1303 entry->polarity = polarity;
1304 entry->vector = vector;
1306 /* Mask level triggered irqs.
1307 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1314 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1315 int trigger, int polarity)
1317 struct irq_cfg *cfg;
1318 struct IO_APIC_route_entry entry;
1321 if (!IO_APIC_IRQ(irq))
1327 if (assign_irq_vector(irq, mask))
1330 cpus_and(mask, cfg->domain, mask);
1332 apic_printk(APIC_VERBOSE,KERN_DEBUG
1333 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1334 "IRQ %d Mode:%i Active:%i)\n",
1335 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1336 irq, trigger, polarity);
1339 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1340 cpu_mask_to_apicid(mask), trigger, polarity,
1342 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1343 mp_ioapics[apic].mp_apicid, pin);
1344 __clear_irq_vector(irq);
1348 ioapic_register_intr(irq, trigger);
1350 disable_8259A_irq(irq);
1352 ioapic_write_entry(apic, pin, entry);
1355 static void __init setup_IO_APIC_irqs(void)
1357 int apic, pin, idx, irq;
1360 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1362 for (apic = 0; apic < nr_ioapics; apic++) {
1363 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1365 idx = find_irq_entry(apic, pin, mp_INT);
1369 apic_printk(APIC_VERBOSE,
1370 KERN_DEBUG " %d-%d",
1371 mp_ioapics[apic].mp_apicid,
1374 apic_printk(APIC_VERBOSE, " %d-%d",
1375 mp_ioapics[apic].mp_apicid,
1380 apic_printk(APIC_VERBOSE,
1381 " (apicid-pin) not connected\n");
1385 irq = pin_2_irq(idx, apic, pin);
1386 #ifdef CONFIG_X86_32
1387 if (multi_timer_check(apic, irq))
1390 add_pin_to_irq(irq, apic, pin);
1392 setup_IO_APIC_irq(apic, pin, irq,
1393 irq_trigger(idx), irq_polarity(idx));
1398 apic_printk(APIC_VERBOSE,
1399 " (apicid-pin) not connected\n");
1403 * Set up the timer pin, possibly with the 8259A-master behind.
1405 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1408 struct IO_APIC_route_entry entry;
1410 #ifdef CONFIG_INTR_REMAP
1411 if (intr_remapping_enabled)
1415 memset(&entry, 0, sizeof(entry));
1418 * We use logical delivery to get the timer IRQ
1421 entry.dest_mode = INT_DEST_MODE;
1422 entry.mask = 1; /* mask IRQ now */
1423 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1424 entry.delivery_mode = INT_DELIVERY_MODE;
1427 entry.vector = vector;
1430 * The timer IRQ doesn't have to know that behind the
1431 * scene we may have a 8259A-master in AEOI mode ...
1433 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1436 * Add it to the IO-APIC irq-routing table:
1438 ioapic_write_entry(apic, pin, entry);
1442 __apicdebuginit(void) print_IO_APIC(void)
1445 union IO_APIC_reg_00 reg_00;
1446 union IO_APIC_reg_01 reg_01;
1447 union IO_APIC_reg_02 reg_02;
1448 union IO_APIC_reg_03 reg_03;
1449 unsigned long flags;
1450 struct irq_cfg *cfg;
1453 if (apic_verbosity == APIC_QUIET)
1456 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1457 for (i = 0; i < nr_ioapics; i++)
1458 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1459 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1462 * We are a bit conservative about what we expect. We have to
1463 * know about every hardware change ASAP.
1465 printk(KERN_INFO "testing the IO APIC.......................\n");
1467 for (apic = 0; apic < nr_ioapics; apic++) {
1469 spin_lock_irqsave(&ioapic_lock, flags);
1470 reg_00.raw = io_apic_read(apic, 0);
1471 reg_01.raw = io_apic_read(apic, 1);
1472 if (reg_01.bits.version >= 0x10)
1473 reg_02.raw = io_apic_read(apic, 2);
1474 if (reg_01.bits.version >= 0x20)
1475 reg_03.raw = io_apic_read(apic, 3);
1476 spin_unlock_irqrestore(&ioapic_lock, flags);
1479 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1480 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1481 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1482 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1483 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1485 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1486 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1488 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1489 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1492 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1493 * but the value of reg_02 is read as the previous read register
1494 * value, so ignore it if reg_02 == reg_01.
1496 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1497 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1498 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1502 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1503 * or reg_03, but the value of reg_0[23] is read as the previous read
1504 * register value, so ignore it if reg_03 == reg_0[12].
1506 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1507 reg_03.raw != reg_01.raw) {
1508 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1509 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1512 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1514 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1515 " Stat Dmod Deli Vect: \n");
1517 for (i = 0; i <= reg_01.bits.entries; i++) {
1518 struct IO_APIC_route_entry entry;
1520 entry = ioapic_read_entry(apic, i);
1522 printk(KERN_DEBUG " %02x %03X ",
1527 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1532 entry.delivery_status,
1534 entry.delivery_mode,
1539 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1540 for_each_irq_cfg(irq, cfg) {
1541 struct irq_pin_list *entry = cfg->irq_2_pin;
1544 printk(KERN_DEBUG "IRQ%d ", irq);
1546 printk("-> %d:%d", entry->apic, entry->pin);
1549 entry = entry->next;
1554 printk(KERN_INFO ".................................... done.\n");
1559 __apicdebuginit(void) print_APIC_bitfield(int base)
1564 if (apic_verbosity == APIC_QUIET)
1567 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1568 for (i = 0; i < 8; i++) {
1569 v = apic_read(base + i*0x10);
1570 for (j = 0; j < 32; j++) {
1580 __apicdebuginit(void) print_local_APIC(void *dummy)
1582 unsigned int v, ver, maxlvt;
1585 if (apic_verbosity == APIC_QUIET)
1588 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1589 smp_processor_id(), hard_smp_processor_id());
1590 v = apic_read(APIC_ID);
1591 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1592 v = apic_read(APIC_LVR);
1593 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1594 ver = GET_APIC_VERSION(v);
1595 maxlvt = lapic_get_maxlvt();
1597 v = apic_read(APIC_TASKPRI);
1598 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1600 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1601 if (!APIC_XAPIC(ver)) {
1602 v = apic_read(APIC_ARBPRI);
1603 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1604 v & APIC_ARBPRI_MASK);
1606 v = apic_read(APIC_PROCPRI);
1607 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1611 * Remote read supported only in the 82489DX and local APIC for
1612 * Pentium processors.
1614 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1615 v = apic_read(APIC_RRR);
1616 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1619 v = apic_read(APIC_LDR);
1620 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1621 if (!x2apic_enabled()) {
1622 v = apic_read(APIC_DFR);
1623 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1625 v = apic_read(APIC_SPIV);
1626 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1628 printk(KERN_DEBUG "... APIC ISR field:\n");
1629 print_APIC_bitfield(APIC_ISR);
1630 printk(KERN_DEBUG "... APIC TMR field:\n");
1631 print_APIC_bitfield(APIC_TMR);
1632 printk(KERN_DEBUG "... APIC IRR field:\n");
1633 print_APIC_bitfield(APIC_IRR);
1635 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1636 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1637 apic_write(APIC_ESR, 0);
1639 v = apic_read(APIC_ESR);
1640 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1643 icr = apic_icr_read();
1644 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1645 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1647 v = apic_read(APIC_LVTT);
1648 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1650 if (maxlvt > 3) { /* PC is LVT#4. */
1651 v = apic_read(APIC_LVTPC);
1652 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1654 v = apic_read(APIC_LVT0);
1655 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1656 v = apic_read(APIC_LVT1);
1657 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1659 if (maxlvt > 2) { /* ERR is LVT#3. */
1660 v = apic_read(APIC_LVTERR);
1661 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1664 v = apic_read(APIC_TMICT);
1665 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1666 v = apic_read(APIC_TMCCT);
1667 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1668 v = apic_read(APIC_TDCR);
1669 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1673 __apicdebuginit(void) print_all_local_APICs(void)
1678 for_each_online_cpu(cpu)
1679 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1683 __apicdebuginit(void) print_PIC(void)
1686 unsigned long flags;
1688 if (apic_verbosity == APIC_QUIET)
1691 printk(KERN_DEBUG "\nprinting PIC contents\n");
1693 spin_lock_irqsave(&i8259A_lock, flags);
1695 v = inb(0xa1) << 8 | inb(0x21);
1696 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1698 v = inb(0xa0) << 8 | inb(0x20);
1699 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1703 v = inb(0xa0) << 8 | inb(0x20);
1707 spin_unlock_irqrestore(&i8259A_lock, flags);
1709 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1711 v = inb(0x4d1) << 8 | inb(0x4d0);
1712 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1715 __apicdebuginit(int) print_all_ICs(void)
1718 print_all_local_APICs();
1724 fs_initcall(print_all_ICs);
1727 /* Where if anywhere is the i8259 connect in external int mode */
1728 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1730 void __init enable_IO_APIC(void)
1732 union IO_APIC_reg_01 reg_01;
1733 int i8259_apic, i8259_pin;
1735 unsigned long flags;
1737 #ifdef CONFIG_X86_32
1740 for (i = 0; i < MAX_PIRQS; i++)
1741 pirq_entries[i] = -1;
1745 * The number of IO-APIC IRQ registers (== #pins):
1747 for (apic = 0; apic < nr_ioapics; apic++) {
1748 spin_lock_irqsave(&ioapic_lock, flags);
1749 reg_01.raw = io_apic_read(apic, 1);
1750 spin_unlock_irqrestore(&ioapic_lock, flags);
1751 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1753 for(apic = 0; apic < nr_ioapics; apic++) {
1755 /* See if any of the pins is in ExtINT mode */
1756 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1757 struct IO_APIC_route_entry entry;
1758 entry = ioapic_read_entry(apic, pin);
1760 /* If the interrupt line is enabled and in ExtInt mode
1761 * I have found the pin where the i8259 is connected.
1763 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1764 ioapic_i8259.apic = apic;
1765 ioapic_i8259.pin = pin;
1771 /* Look to see what if the MP table has reported the ExtINT */
1772 /* If we could not find the appropriate pin by looking at the ioapic
1773 * the i8259 probably is not connected the ioapic but give the
1774 * mptable a chance anyway.
1776 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1777 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1778 /* Trust the MP table if nothing is setup in the hardware */
1779 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1780 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1781 ioapic_i8259.pin = i8259_pin;
1782 ioapic_i8259.apic = i8259_apic;
1784 /* Complain if the MP table and the hardware disagree */
1785 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1786 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1788 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1792 * Do not trust the IO-APIC being empty at bootup
1798 * Not an __init, needed by the reboot code
1800 void disable_IO_APIC(void)
1803 * Clear the IO-APIC before rebooting:
1808 * If the i8259 is routed through an IOAPIC
1809 * Put that IOAPIC in virtual wire mode
1810 * so legacy interrupts can be delivered.
1812 if (ioapic_i8259.pin != -1) {
1813 struct IO_APIC_route_entry entry;
1815 memset(&entry, 0, sizeof(entry));
1816 entry.mask = 0; /* Enabled */
1817 entry.trigger = 0; /* Edge */
1819 entry.polarity = 0; /* High */
1820 entry.delivery_status = 0;
1821 entry.dest_mode = 0; /* Physical */
1822 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1824 entry.dest = read_apic_id();
1827 * Add it to the IO-APIC irq-routing table:
1829 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1832 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1835 #ifdef CONFIG_X86_32
1837 * function to set the IO-APIC physical IDs based on the
1838 * values stored in the MPC table.
1840 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1843 static void __init setup_ioapic_ids_from_mpc(void)
1845 union IO_APIC_reg_00 reg_00;
1846 physid_mask_t phys_id_present_map;
1849 unsigned char old_id;
1850 unsigned long flags;
1852 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1856 * Don't check I/O APIC IDs for xAPIC systems. They have
1857 * no meaning without the serial APIC bus.
1859 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1860 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1863 * This is broken; anything with a real cpu count has to
1864 * circumvent this idiocy regardless.
1866 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1869 * Set the IOAPIC ID to the value stored in the MPC table.
1871 for (apic = 0; apic < nr_ioapics; apic++) {
1873 /* Read the register 0 value */
1874 spin_lock_irqsave(&ioapic_lock, flags);
1875 reg_00.raw = io_apic_read(apic, 0);
1876 spin_unlock_irqrestore(&ioapic_lock, flags);
1878 old_id = mp_ioapics[apic].mp_apicid;
1880 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1881 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1882 apic, mp_ioapics[apic].mp_apicid);
1883 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1885 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1889 * Sanity check, is the ID really free? Every APIC in a
1890 * system must have a unique ID or we get lots of nice
1891 * 'stuck on smp_invalidate_needed IPI wait' messages.
1893 if (check_apicid_used(phys_id_present_map,
1894 mp_ioapics[apic].mp_apicid)) {
1895 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1896 apic, mp_ioapics[apic].mp_apicid);
1897 for (i = 0; i < get_physical_broadcast(); i++)
1898 if (!physid_isset(i, phys_id_present_map))
1900 if (i >= get_physical_broadcast())
1901 panic("Max APIC ID exceeded!\n");
1902 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1904 physid_set(i, phys_id_present_map);
1905 mp_ioapics[apic].mp_apicid = i;
1908 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1909 apic_printk(APIC_VERBOSE, "Setting %d in the "
1910 "phys_id_present_map\n",
1911 mp_ioapics[apic].mp_apicid);
1912 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1917 * We need to adjust the IRQ routing table
1918 * if the ID changed.
1920 if (old_id != mp_ioapics[apic].mp_apicid)
1921 for (i = 0; i < mp_irq_entries; i++)
1922 if (mp_irqs[i].mp_dstapic == old_id)
1923 mp_irqs[i].mp_dstapic
1924 = mp_ioapics[apic].mp_apicid;
1927 * Read the right value from the MPC table and
1928 * write it into the ID register.
1930 apic_printk(APIC_VERBOSE, KERN_INFO
1931 "...changing IO-APIC physical APIC ID to %d ...",
1932 mp_ioapics[apic].mp_apicid);
1934 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1935 spin_lock_irqsave(&ioapic_lock, flags);
1936 io_apic_write(apic, 0, reg_00.raw);
1937 spin_unlock_irqrestore(&ioapic_lock, flags);
1942 spin_lock_irqsave(&ioapic_lock, flags);
1943 reg_00.raw = io_apic_read(apic, 0);
1944 spin_unlock_irqrestore(&ioapic_lock, flags);
1945 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1946 printk("could not set ID!\n");
1948 apic_printk(APIC_VERBOSE, " ok.\n");
1953 int no_timer_check __initdata;
1955 static int __init notimercheck(char *s)
1960 __setup("no_timer_check", notimercheck);
1963 * There is a nasty bug in some older SMP boards, their mptable lies
1964 * about the timer IRQ. We do the following to work around the situation:
1966 * - timer IRQ defaults to IO-APIC IRQ
1967 * - if this function detects that timer IRQs are defunct, then we fall
1968 * back to ISA timer IRQs
1970 static int __init timer_irq_works(void)
1972 unsigned long t1 = jiffies;
1973 unsigned long flags;
1978 local_save_flags(flags);
1980 /* Let ten ticks pass... */
1981 mdelay((10 * 1000) / HZ);
1982 local_irq_restore(flags);
1985 * Expect a few ticks at least, to be sure some possible
1986 * glue logic does not lock up after one or two first
1987 * ticks in a non-ExtINT mode. Also the local APIC
1988 * might have cached one ExtINT interrupt. Finally, at
1989 * least one tick may be lost due to delays.
1993 if (time_after(jiffies, t1 + 4))
1999 * In the SMP+IOAPIC case it might happen that there are an unspecified
2000 * number of pending IRQ events unhandled. These cases are very rare,
2001 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2002 * better to do it this way as thus we do not have to be aware of
2003 * 'pending' interrupts in the IRQ path, except at this point.
2006 * Edge triggered needs to resend any interrupt
2007 * that was delayed but this is now handled in the device
2012 * Starting up a edge-triggered IO-APIC interrupt is
2013 * nasty - we need to make sure that we get the edge.
2014 * If it is already asserted for some reason, we need
2015 * return 1 to indicate that is was pending.
2017 * This is not complete - we should be able to fake
2018 * an edge even if it isn't on the 8259A...
2021 static unsigned int startup_ioapic_irq(unsigned int irq)
2023 int was_pending = 0;
2024 unsigned long flags;
2026 spin_lock_irqsave(&ioapic_lock, flags);
2028 disable_8259A_irq(irq);
2029 if (i8259A_irq_pending(irq))
2032 __unmask_IO_APIC_irq(irq);
2033 spin_unlock_irqrestore(&ioapic_lock, flags);
2038 #ifdef CONFIG_X86_64
2039 static int ioapic_retrigger_irq(unsigned int irq)
2042 struct irq_cfg *cfg = irq_cfg(irq);
2043 unsigned long flags;
2045 spin_lock_irqsave(&vector_lock, flags);
2046 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2047 spin_unlock_irqrestore(&vector_lock, flags);
2052 static int ioapic_retrigger_irq(unsigned int irq)
2054 send_IPI_self(irq_cfg(irq)->vector);
2061 * Level and edge triggered IO-APIC interrupts need different handling,
2062 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2063 * handled with the level-triggered descriptor, but that one has slightly
2064 * more overhead. Level-triggered interrupts cannot be handled with the
2065 * edge-triggered handler, without risking IRQ storms and other ugly
2071 #ifdef CONFIG_INTR_REMAP
2072 static void ir_irq_migration(struct work_struct *work);
2074 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2077 * Migrate the IO-APIC irq in the presence of intr-remapping.
2079 * For edge triggered, irq migration is a simple atomic update(of vector
2080 * and cpu destination) of IRTE and flush the hardware cache.
2082 * For level triggered, we need to modify the io-apic RTE aswell with the update
2083 * vector information, along with modifying IRTE with vector and destination.
2084 * So irq migration for level triggered is little bit more complex compared to
2085 * edge triggered migration. But the good news is, we use the same algorithm
2086 * for level triggered migration as we have today, only difference being,
2087 * we now initiate the irq migration from process context instead of the
2088 * interrupt context.
2090 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2091 * suppression) to the IO-APIC, level triggered irq migration will also be
2092 * as simple as edge triggered migration and we can do the irq migration
2093 * with a simple atomic update to IO-APIC RTE.
2095 static void migrate_ioapic_irq(int irq, cpumask_t mask)
2097 struct irq_cfg *cfg;
2098 struct irq_desc *desc;
2099 cpumask_t tmp, cleanup_mask;
2101 int modify_ioapic_rte;
2103 unsigned long flags;
2105 cpus_and(tmp, mask, cpu_online_map);
2106 if (cpus_empty(tmp))
2109 if (get_irte(irq, &irte))
2112 if (assign_irq_vector(irq, mask))
2116 cpus_and(tmp, cfg->domain, mask);
2117 dest = cpu_mask_to_apicid(tmp);
2119 desc = irq_to_desc(irq);
2120 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2121 if (modify_ioapic_rte) {
2122 spin_lock_irqsave(&ioapic_lock, flags);
2123 __target_IO_APIC_irq(irq, dest, cfg->vector);
2124 spin_unlock_irqrestore(&ioapic_lock, flags);
2127 irte.vector = cfg->vector;
2128 irte.dest_id = IRTE_DEST(dest);
2131 * Modified the IRTE and flushes the Interrupt entry cache.
2133 modify_irte(irq, &irte);
2135 if (cfg->move_in_progress) {
2136 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2137 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2138 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2139 cfg->move_in_progress = 0;
2142 desc->affinity = mask;
2145 static int migrate_irq_remapped_level(int irq)
2148 struct irq_desc *desc = irq_to_desc(irq);
2150 mask_IO_APIC_irq(irq);
2152 if (io_apic_level_ack_pending(irq)) {
2154 * Interrupt in progress. Migrating irq now will change the
2155 * vector information in the IO-APIC RTE and that will confuse
2156 * the EOI broadcast performed by cpu.
2157 * So, delay the irq migration to the next instance.
2159 schedule_delayed_work(&ir_migration_work, 1);
2163 /* everthing is clear. we have right of way */
2164 migrate_ioapic_irq(irq, desc->pending_mask);
2167 desc->status &= ~IRQ_MOVE_PENDING;
2168 cpus_clear(desc->pending_mask);
2171 unmask_IO_APIC_irq(irq);
2175 static void ir_irq_migration(struct work_struct *work)
2178 struct irq_desc *desc;
2180 for_each_irq_desc(irq, desc) {
2181 if (desc->status & IRQ_MOVE_PENDING) {
2182 unsigned long flags;
2184 spin_lock_irqsave(&desc->lock, flags);
2185 if (!desc->chip->set_affinity ||
2186 !(desc->status & IRQ_MOVE_PENDING)) {
2187 desc->status &= ~IRQ_MOVE_PENDING;
2188 spin_unlock_irqrestore(&desc->lock, flags);
2192 desc->chip->set_affinity(irq, desc->pending_mask);
2193 spin_unlock_irqrestore(&desc->lock, flags);
2199 * Migrates the IRQ destination in the process context.
2201 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2203 struct irq_desc *desc = irq_to_desc(irq);
2205 if (desc->status & IRQ_LEVEL) {
2206 desc->status |= IRQ_MOVE_PENDING;
2207 desc->pending_mask = mask;
2208 migrate_irq_remapped_level(irq);
2212 migrate_ioapic_irq(irq, mask);
2216 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2218 unsigned vector, me;
2224 me = smp_processor_id();
2225 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2227 struct irq_desc *desc;
2228 struct irq_cfg *cfg;
2229 irq = __get_cpu_var(vector_irq)[vector];
2231 desc = irq_to_desc(irq);
2236 spin_lock(&desc->lock);
2237 if (!cfg->move_cleanup_count)
2240 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2243 __get_cpu_var(vector_irq)[vector] = -1;
2244 cfg->move_cleanup_count--;
2246 spin_unlock(&desc->lock);
2252 static void irq_complete_move(unsigned int irq)
2254 struct irq_cfg *cfg = irq_cfg(irq);
2255 unsigned vector, me;
2257 if (likely(!cfg->move_in_progress))
2260 vector = ~get_irq_regs()->orig_ax;
2261 me = smp_processor_id();
2262 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2263 cpumask_t cleanup_mask;
2265 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2266 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2267 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2268 cfg->move_in_progress = 0;
2272 static inline void irq_complete_move(unsigned int irq) {}
2274 #ifdef CONFIG_INTR_REMAP
2275 static void ack_x2apic_level(unsigned int irq)
2280 static void ack_x2apic_edge(unsigned int irq)
2286 static void ack_apic_edge(unsigned int irq)
2288 irq_complete_move(irq);
2289 move_native_irq(irq);
2293 atomic_t irq_mis_count;
2295 static void ack_apic_level(unsigned int irq)
2297 #ifdef CONFIG_X86_32
2301 int do_unmask_irq = 0;
2303 irq_complete_move(irq);
2304 #ifdef CONFIG_GENERIC_PENDING_IRQ
2305 /* If we are moving the irq we need to mask it */
2306 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2308 mask_IO_APIC_irq(irq);
2312 #ifdef CONFIG_X86_32
2314 * It appears there is an erratum which affects at least version 0x11
2315 * of I/O APIC (that's the 82093AA and cores integrated into various
2316 * chipsets). Under certain conditions a level-triggered interrupt is
2317 * erroneously delivered as edge-triggered one but the respective IRR
2318 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2319 * message but it will never arrive and further interrupts are blocked
2320 * from the source. The exact reason is so far unknown, but the
2321 * phenomenon was observed when two consecutive interrupt requests
2322 * from a given source get delivered to the same CPU and the source is
2323 * temporarily disabled in between.
2325 * A workaround is to simulate an EOI message manually. We achieve it
2326 * by setting the trigger mode to edge and then to level when the edge
2327 * trigger mode gets detected in the TMR of a local APIC for a
2328 * level-triggered interrupt. We mask the source for the time of the
2329 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2330 * The idea is from Manfred Spraul. --macro
2332 i = irq_cfg(irq)->vector;
2334 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2338 * We must acknowledge the irq before we move it or the acknowledge will
2339 * not propagate properly.
2343 /* Now we can move and renable the irq */
2344 if (unlikely(do_unmask_irq)) {
2345 /* Only migrate the irq if the ack has been received.
2347 * On rare occasions the broadcast level triggered ack gets
2348 * delayed going to ioapics, and if we reprogram the
2349 * vector while Remote IRR is still set the irq will never
2352 * To prevent this scenario we read the Remote IRR bit
2353 * of the ioapic. This has two effects.
2354 * - On any sane system the read of the ioapic will
2355 * flush writes (and acks) going to the ioapic from
2357 * - We get to see if the ACK has actually been delivered.
2359 * Based on failed experiments of reprogramming the
2360 * ioapic entry from outside of irq context starting
2361 * with masking the ioapic entry and then polling until
2362 * Remote IRR was clear before reprogramming the
2363 * ioapic I don't trust the Remote IRR bit to be
2364 * completey accurate.
2366 * However there appears to be no other way to plug
2367 * this race, so if the Remote IRR bit is not
2368 * accurate and is causing problems then it is a hardware bug
2369 * and you can go talk to the chipset vendor about it.
2371 if (!io_apic_level_ack_pending(irq))
2372 move_masked_irq(irq);
2373 unmask_IO_APIC_irq(irq);
2376 #ifdef CONFIG_X86_32
2377 if (!(v & (1 << (i & 0x1f)))) {
2378 atomic_inc(&irq_mis_count);
2379 spin_lock(&ioapic_lock);
2380 __mask_and_edge_IO_APIC_irq(irq);
2381 __unmask_and_level_IO_APIC_irq(irq);
2382 spin_unlock(&ioapic_lock);
2387 static struct irq_chip ioapic_chip __read_mostly = {
2389 .startup = startup_ioapic_irq,
2390 .mask = mask_IO_APIC_irq,
2391 .unmask = unmask_IO_APIC_irq,
2392 .ack = ack_apic_edge,
2393 .eoi = ack_apic_level,
2395 .set_affinity = set_ioapic_affinity_irq,
2397 .retrigger = ioapic_retrigger_irq,
2400 #ifdef CONFIG_INTR_REMAP
2401 static struct irq_chip ir_ioapic_chip __read_mostly = {
2402 .name = "IR-IO-APIC",
2403 .startup = startup_ioapic_irq,
2404 .mask = mask_IO_APIC_irq,
2405 .unmask = unmask_IO_APIC_irq,
2406 .ack = ack_x2apic_edge,
2407 .eoi = ack_x2apic_level,
2409 .set_affinity = set_ir_ioapic_affinity_irq,
2411 .retrigger = ioapic_retrigger_irq,
2415 static inline void init_IO_APIC_traps(void)
2418 struct irq_desc *desc;
2419 struct irq_cfg *cfg;
2422 * NOTE! The local APIC isn't very good at handling
2423 * multiple interrupts at the same interrupt level.
2424 * As the interrupt level is determined by taking the
2425 * vector number and shifting that right by 4, we
2426 * want to spread these out a bit so that they don't
2427 * all fall in the same interrupt level.
2429 * Also, we've got to be careful not to trash gate
2430 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2432 for_each_irq_cfg(irq, cfg) {
2433 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2435 * Hmm.. We don't have an entry for this,
2436 * so default to an old-fashioned 8259
2437 * interrupt if we can..
2440 make_8259A_irq(irq);
2442 desc = irq_to_desc(irq);
2443 /* Strange. Oh, well.. */
2444 desc->chip = &no_irq_chip;
2451 * The local APIC irq-chip implementation:
2454 static void mask_lapic_irq(unsigned int irq)
2458 v = apic_read(APIC_LVT0);
2459 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2462 static void unmask_lapic_irq(unsigned int irq)
2466 v = apic_read(APIC_LVT0);
2467 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2470 static void ack_lapic_irq (unsigned int irq)
2475 static struct irq_chip lapic_chip __read_mostly = {
2476 .name = "local-APIC",
2477 .mask = mask_lapic_irq,
2478 .unmask = unmask_lapic_irq,
2479 .ack = ack_lapic_irq,
2482 static void lapic_register_intr(int irq)
2484 struct irq_desc *desc;
2486 desc = irq_to_desc(irq);
2487 desc->status &= ~IRQ_LEVEL;
2488 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2492 static void __init setup_nmi(void)
2495 * Dirty trick to enable the NMI watchdog ...
2496 * We put the 8259A master into AEOI mode and
2497 * unmask on all local APICs LVT0 as NMI.
2499 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2500 * is from Maciej W. Rozycki - so we do not have to EOI from
2501 * the NMI handler or the timer interrupt.
2503 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2505 enable_NMI_through_LVT0();
2507 apic_printk(APIC_VERBOSE, " done.\n");
2511 * This looks a bit hackish but it's about the only one way of sending
2512 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2513 * not support the ExtINT mode, unfortunately. We need to send these
2514 * cycles as some i82489DX-based boards have glue logic that keeps the
2515 * 8259A interrupt line asserted until INTA. --macro
2517 static inline void __init unlock_ExtINT_logic(void)
2520 struct IO_APIC_route_entry entry0, entry1;
2521 unsigned char save_control, save_freq_select;
2523 pin = find_isa_irq_pin(8, mp_INT);
2528 apic = find_isa_irq_apic(8, mp_INT);
2534 entry0 = ioapic_read_entry(apic, pin);
2535 clear_IO_APIC_pin(apic, pin);
2537 memset(&entry1, 0, sizeof(entry1));
2539 entry1.dest_mode = 0; /* physical delivery */
2540 entry1.mask = 0; /* unmask IRQ now */
2541 entry1.dest = hard_smp_processor_id();
2542 entry1.delivery_mode = dest_ExtINT;
2543 entry1.polarity = entry0.polarity;
2547 ioapic_write_entry(apic, pin, entry1);
2549 save_control = CMOS_READ(RTC_CONTROL);
2550 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2551 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2553 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2558 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2562 CMOS_WRITE(save_control, RTC_CONTROL);
2563 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2564 clear_IO_APIC_pin(apic, pin);
2566 ioapic_write_entry(apic, pin, entry0);
2569 static int disable_timer_pin_1 __initdata;
2570 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2571 static int __init disable_timer_pin_setup(char *arg)
2573 disable_timer_pin_1 = 1;
2576 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2578 int timer_through_8259 __initdata;
2581 * This code may look a bit paranoid, but it's supposed to cooperate with
2582 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2583 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2584 * fanatically on his truly buggy board.
2586 * FIXME: really need to revamp this for all platforms.
2588 static inline void __init check_timer(void)
2590 struct irq_cfg *cfg = irq_cfg(0);
2591 int apic1, pin1, apic2, pin2;
2592 unsigned long flags;
2596 local_irq_save(flags);
2598 ver = apic_read(APIC_LVR);
2599 ver = GET_APIC_VERSION(ver);
2602 * get/set the timer IRQ vector:
2604 disable_8259A_irq(0);
2605 assign_irq_vector(0, TARGET_CPUS);
2608 * As IRQ0 is to be enabled in the 8259A, the virtual
2609 * wire has to be disabled in the local APIC. Also
2610 * timer interrupts need to be acknowledged manually in
2611 * the 8259A for the i82489DX when using the NMI
2612 * watchdog as that APIC treats NMIs as level-triggered.
2613 * The AEOI mode will finish them in the 8259A
2616 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2618 #ifdef CONFIG_X86_32
2619 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2622 pin1 = find_isa_irq_pin(0, mp_INT);
2623 apic1 = find_isa_irq_apic(0, mp_INT);
2624 pin2 = ioapic_i8259.pin;
2625 apic2 = ioapic_i8259.apic;
2627 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2628 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2629 cfg->vector, apic1, pin1, apic2, pin2);
2632 * Some BIOS writers are clueless and report the ExtINTA
2633 * I/O APIC input from the cascaded 8259A as the timer
2634 * interrupt input. So just in case, if only one pin
2635 * was found above, try it both directly and through the
2639 #ifdef CONFIG_INTR_REMAP
2640 if (intr_remapping_enabled)
2641 panic("BIOS bug: timer not connected to IO-APIC");
2646 } else if (pin2 == -1) {
2653 * Ok, does IRQ0 through the IOAPIC work?
2656 add_pin_to_irq(0, apic1, pin1);
2657 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2659 unmask_IO_APIC_irq(0);
2660 if (timer_irq_works()) {
2661 if (nmi_watchdog == NMI_IO_APIC) {
2663 enable_8259A_irq(0);
2665 if (disable_timer_pin_1 > 0)
2666 clear_IO_APIC_pin(0, pin1);
2669 #ifdef CONFIG_INTR_REMAP
2670 if (intr_remapping_enabled)
2671 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2673 clear_IO_APIC_pin(apic1, pin1);
2675 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2676 "8254 timer not connected to IO-APIC\n");
2678 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2679 "(IRQ0) through the 8259A ...\n");
2680 apic_printk(APIC_QUIET, KERN_INFO
2681 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2683 * legacy devices should be connected to IO APIC #0
2685 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2686 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2687 unmask_IO_APIC_irq(0);
2688 enable_8259A_irq(0);
2689 if (timer_irq_works()) {
2690 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2691 timer_through_8259 = 1;
2692 if (nmi_watchdog == NMI_IO_APIC) {
2693 disable_8259A_irq(0);
2695 enable_8259A_irq(0);
2700 * Cleanup, just in case ...
2702 disable_8259A_irq(0);
2703 clear_IO_APIC_pin(apic2, pin2);
2704 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2707 if (nmi_watchdog == NMI_IO_APIC) {
2708 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2709 "through the IO-APIC - disabling NMI Watchdog!\n");
2710 nmi_watchdog = NMI_NONE;
2712 #ifdef CONFIG_X86_32
2716 apic_printk(APIC_QUIET, KERN_INFO
2717 "...trying to set up timer as Virtual Wire IRQ...\n");
2719 lapic_register_intr(0);
2720 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2721 enable_8259A_irq(0);
2723 if (timer_irq_works()) {
2724 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2727 disable_8259A_irq(0);
2728 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2729 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2731 apic_printk(APIC_QUIET, KERN_INFO
2732 "...trying to set up timer as ExtINT IRQ...\n");
2736 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2738 unlock_ExtINT_logic();
2740 if (timer_irq_works()) {
2741 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2744 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2745 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2746 "report. Then try booting with the 'noapic' option.\n");
2748 local_irq_restore(flags);
2752 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2753 * to devices. However there may be an I/O APIC pin available for
2754 * this interrupt regardless. The pin may be left unconnected, but
2755 * typically it will be reused as an ExtINT cascade interrupt for
2756 * the master 8259A. In the MPS case such a pin will normally be
2757 * reported as an ExtINT interrupt in the MP table. With ACPI
2758 * there is no provision for ExtINT interrupts, and in the absence
2759 * of an override it would be treated as an ordinary ISA I/O APIC
2760 * interrupt, that is edge-triggered and unmasked by default. We
2761 * used to do this, but it caused problems on some systems because
2762 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2763 * the same ExtINT cascade interrupt to drive the local APIC of the
2764 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2765 * the I/O APIC in all cases now. No actual device should request
2766 * it anyway. --macro
2768 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2770 void __init setup_IO_APIC(void)
2773 #ifdef CONFIG_X86_32
2777 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2781 io_apic_irqs = ~PIC_IRQS;
2783 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2785 * Set up IO-APIC IRQ routing.
2787 #ifdef CONFIG_X86_32
2789 setup_ioapic_ids_from_mpc();
2792 setup_IO_APIC_irqs();
2793 init_IO_APIC_traps();
2798 * Called after all the initialization is done. If we didnt find any
2799 * APIC bugs then we can allow the modify fast path
2802 static int __init io_apic_bug_finalize(void)
2804 if (sis_apic_bug == -1)
2809 late_initcall(io_apic_bug_finalize);
2811 struct sysfs_ioapic_data {
2812 struct sys_device dev;
2813 struct IO_APIC_route_entry entry[0];
2815 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2817 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2819 struct IO_APIC_route_entry *entry;
2820 struct sysfs_ioapic_data *data;
2823 data = container_of(dev, struct sysfs_ioapic_data, dev);
2824 entry = data->entry;
2825 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2826 *entry = ioapic_read_entry(dev->id, i);
2831 static int ioapic_resume(struct sys_device *dev)
2833 struct IO_APIC_route_entry *entry;
2834 struct sysfs_ioapic_data *data;
2835 unsigned long flags;
2836 union IO_APIC_reg_00 reg_00;
2839 data = container_of(dev, struct sysfs_ioapic_data, dev);
2840 entry = data->entry;
2842 spin_lock_irqsave(&ioapic_lock, flags);
2843 reg_00.raw = io_apic_read(dev->id, 0);
2844 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2845 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2846 io_apic_write(dev->id, 0, reg_00.raw);
2848 spin_unlock_irqrestore(&ioapic_lock, flags);
2849 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2850 ioapic_write_entry(dev->id, i, entry[i]);
2855 static struct sysdev_class ioapic_sysdev_class = {
2857 .suspend = ioapic_suspend,
2858 .resume = ioapic_resume,
2861 static int __init ioapic_init_sysfs(void)
2863 struct sys_device * dev;
2866 error = sysdev_class_register(&ioapic_sysdev_class);
2870 for (i = 0; i < nr_ioapics; i++ ) {
2871 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2872 * sizeof(struct IO_APIC_route_entry);
2873 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2874 if (!mp_ioapic_data[i]) {
2875 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2878 dev = &mp_ioapic_data[i]->dev;
2880 dev->cls = &ioapic_sysdev_class;
2881 error = sysdev_register(dev);
2883 kfree(mp_ioapic_data[i]);
2884 mp_ioapic_data[i] = NULL;
2885 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2893 device_initcall(ioapic_init_sysfs);
2896 * Dynamic irq allocate and deallocation
2898 unsigned int create_irq_nr(unsigned int irq_want)
2900 /* Allocate an unused irq */
2903 unsigned long flags;
2904 struct irq_cfg *cfg_new;
2906 irq_want = nr_irqs - 1;
2909 spin_lock_irqsave(&vector_lock, flags);
2910 for (new = irq_want; new > 0; new--) {
2911 if (platform_legacy_irq(new))
2913 cfg_new = irq_cfg(new);
2914 if (cfg_new && cfg_new->vector != 0)
2916 /* check if need to create one */
2918 cfg_new = irq_cfg_alloc(new);
2919 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2923 spin_unlock_irqrestore(&vector_lock, flags);
2926 dynamic_irq_init(irq);
2931 int create_irq(void)
2935 irq = create_irq_nr(nr_irqs - 1);
2943 void destroy_irq(unsigned int irq)
2945 unsigned long flags;
2947 dynamic_irq_cleanup(irq);
2949 #ifdef CONFIG_INTR_REMAP
2952 spin_lock_irqsave(&vector_lock, flags);
2953 __clear_irq_vector(irq);
2954 spin_unlock_irqrestore(&vector_lock, flags);
2958 * MSI message composition
2960 #ifdef CONFIG_PCI_MSI
2961 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2963 struct irq_cfg *cfg;
2969 err = assign_irq_vector(irq, tmp);
2974 cpus_and(tmp, cfg->domain, tmp);
2975 dest = cpu_mask_to_apicid(tmp);
2977 #ifdef CONFIG_INTR_REMAP
2978 if (irq_remapped(irq)) {
2983 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2984 BUG_ON(ir_index == -1);
2986 memset (&irte, 0, sizeof(irte));
2989 irte.dst_mode = INT_DEST_MODE;
2990 irte.trigger_mode = 0; /* edge */
2991 irte.dlvry_mode = INT_DELIVERY_MODE;
2992 irte.vector = cfg->vector;
2993 irte.dest_id = IRTE_DEST(dest);
2995 modify_irte(irq, &irte);
2997 msg->address_hi = MSI_ADDR_BASE_HI;
2998 msg->data = sub_handle;
2999 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3001 MSI_ADDR_IR_INDEX1(ir_index) |
3002 MSI_ADDR_IR_INDEX2(ir_index);
3006 msg->address_hi = MSI_ADDR_BASE_HI;
3009 ((INT_DEST_MODE == 0) ?
3010 MSI_ADDR_DEST_MODE_PHYSICAL:
3011 MSI_ADDR_DEST_MODE_LOGICAL) |
3012 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3013 MSI_ADDR_REDIRECTION_CPU:
3014 MSI_ADDR_REDIRECTION_LOWPRI) |
3015 MSI_ADDR_DEST_ID(dest);
3018 MSI_DATA_TRIGGER_EDGE |
3019 MSI_DATA_LEVEL_ASSERT |
3020 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3021 MSI_DATA_DELIVERY_FIXED:
3022 MSI_DATA_DELIVERY_LOWPRI) |
3023 MSI_DATA_VECTOR(cfg->vector);
3029 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3031 struct irq_cfg *cfg;
3035 struct irq_desc *desc;
3037 cpus_and(tmp, mask, cpu_online_map);
3038 if (cpus_empty(tmp))
3041 if (assign_irq_vector(irq, mask))
3045 cpus_and(tmp, cfg->domain, mask);
3046 dest = cpu_mask_to_apicid(tmp);
3048 read_msi_msg(irq, &msg);
3050 msg.data &= ~MSI_DATA_VECTOR_MASK;
3051 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3052 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3053 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3055 write_msi_msg(irq, &msg);
3056 desc = irq_to_desc(irq);
3057 desc->affinity = mask;
3060 #ifdef CONFIG_INTR_REMAP
3062 * Migrate the MSI irq to another cpumask. This migration is
3063 * done in the process context using interrupt-remapping hardware.
3065 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3067 struct irq_cfg *cfg;
3069 cpumask_t tmp, cleanup_mask;
3071 struct irq_desc *desc;
3073 cpus_and(tmp, mask, cpu_online_map);
3074 if (cpus_empty(tmp))
3077 if (get_irte(irq, &irte))
3080 if (assign_irq_vector(irq, mask))
3084 cpus_and(tmp, cfg->domain, mask);
3085 dest = cpu_mask_to_apicid(tmp);
3087 irte.vector = cfg->vector;
3088 irte.dest_id = IRTE_DEST(dest);
3091 * atomically update the IRTE with the new destination and vector.
3093 modify_irte(irq, &irte);
3096 * After this point, all the interrupts will start arriving
3097 * at the new destination. So, time to cleanup the previous
3098 * vector allocation.
3100 if (cfg->move_in_progress) {
3101 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3102 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3103 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3104 cfg->move_in_progress = 0;
3107 desc = irq_to_desc(irq);
3108 desc->affinity = mask;
3111 #endif /* CONFIG_SMP */
3114 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3115 * which implement the MSI or MSI-X Capability Structure.
3117 static struct irq_chip msi_chip = {
3119 .unmask = unmask_msi_irq,
3120 .mask = mask_msi_irq,
3121 .ack = ack_apic_edge,
3123 .set_affinity = set_msi_irq_affinity,
3125 .retrigger = ioapic_retrigger_irq,
3128 #ifdef CONFIG_INTR_REMAP
3129 static struct irq_chip msi_ir_chip = {
3130 .name = "IR-PCI-MSI",
3131 .unmask = unmask_msi_irq,
3132 .mask = mask_msi_irq,
3133 .ack = ack_x2apic_edge,
3135 .set_affinity = ir_set_msi_irq_affinity,
3137 .retrigger = ioapic_retrigger_irq,
3141 * Map the PCI dev to the corresponding remapping hardware unit
3142 * and allocate 'nvec' consecutive interrupt-remapping table entries
3145 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3147 struct intel_iommu *iommu;
3150 iommu = map_dev_to_ir(dev);
3153 "Unable to map PCI %s to iommu\n", pci_name(dev));
3157 index = alloc_irte(iommu, irq, nvec);
3160 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3168 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3173 ret = msi_compose_msg(dev, irq, &msg);
3177 set_irq_msi(irq, desc);
3178 write_msi_msg(irq, &msg);
3180 #ifdef CONFIG_INTR_REMAP
3181 if (irq_remapped(irq)) {
3182 struct irq_desc *desc = irq_to_desc(irq);
3184 * irq migration in process context
3186 desc->status |= IRQ_MOVE_PCNTXT;
3187 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3190 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3192 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3197 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3201 irq = dev->bus->number;
3209 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3213 unsigned int irq_want;
3215 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3217 irq = create_irq_nr(irq_want);
3221 #ifdef CONFIG_INTR_REMAP
3222 if (!intr_remapping_enabled)
3225 ret = msi_alloc_irte(dev, irq, 1);
3230 ret = setup_msi_irq(dev, desc, irq);
3237 #ifdef CONFIG_INTR_REMAP
3244 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3247 int ret, sub_handle;
3248 struct msi_desc *desc;
3249 unsigned int irq_want;
3251 #ifdef CONFIG_INTR_REMAP
3252 struct intel_iommu *iommu = 0;
3256 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3258 list_for_each_entry(desc, &dev->msi_list, list) {
3259 irq = create_irq_nr(irq_want--);
3262 #ifdef CONFIG_INTR_REMAP
3263 if (!intr_remapping_enabled)
3268 * allocate the consecutive block of IRTE's
3271 index = msi_alloc_irte(dev, irq, nvec);
3277 iommu = map_dev_to_ir(dev);
3283 * setup the mapping between the irq and the IRTE
3284 * base index, the sub_handle pointing to the
3285 * appropriate interrupt remap table entry.
3287 set_irte_irq(irq, iommu, index, sub_handle);
3291 ret = setup_msi_irq(dev, desc, irq);
3303 void arch_teardown_msi_irq(unsigned int irq)
3310 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3312 struct irq_cfg *cfg;
3316 struct irq_desc *desc;
3318 cpus_and(tmp, mask, cpu_online_map);
3319 if (cpus_empty(tmp))
3322 if (assign_irq_vector(irq, mask))
3326 cpus_and(tmp, cfg->domain, mask);
3327 dest = cpu_mask_to_apicid(tmp);
3329 dmar_msi_read(irq, &msg);
3331 msg.data &= ~MSI_DATA_VECTOR_MASK;
3332 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3333 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3334 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3336 dmar_msi_write(irq, &msg);
3337 desc = irq_to_desc(irq);
3338 desc->affinity = mask;
3340 #endif /* CONFIG_SMP */
3342 struct irq_chip dmar_msi_type = {
3344 .unmask = dmar_msi_unmask,
3345 .mask = dmar_msi_mask,
3346 .ack = ack_apic_edge,
3348 .set_affinity = dmar_msi_set_affinity,
3350 .retrigger = ioapic_retrigger_irq,
3353 int arch_setup_dmar_msi(unsigned int irq)
3358 ret = msi_compose_msg(NULL, irq, &msg);
3361 dmar_msi_write(irq, &msg);
3362 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3368 #ifdef CONFIG_HPET_TIMER
3371 static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask)
3373 struct irq_cfg *cfg;
3374 struct irq_desc *desc;
3379 cpus_and(tmp, mask, cpu_online_map);
3380 if (cpus_empty(tmp))
3383 if (assign_irq_vector(irq, mask))
3387 cpus_and(tmp, cfg->domain, mask);
3388 dest = cpu_mask_to_apicid(tmp);
3390 hpet_msi_read(irq, &msg);
3392 msg.data &= ~MSI_DATA_VECTOR_MASK;
3393 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3394 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3395 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3397 hpet_msi_write(irq, &msg);
3398 desc = irq_to_desc(irq);
3399 desc->affinity = mask;
3401 #endif /* CONFIG_SMP */
3403 struct irq_chip hpet_msi_type = {
3405 .unmask = hpet_msi_unmask,
3406 .mask = hpet_msi_mask,
3407 .ack = ack_apic_edge,
3409 .set_affinity = hpet_msi_set_affinity,
3411 .retrigger = ioapic_retrigger_irq,
3414 int arch_setup_hpet_msi(unsigned int irq)
3419 ret = msi_compose_msg(NULL, irq, &msg);
3423 hpet_msi_write(irq, &msg);
3424 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3431 #endif /* CONFIG_PCI_MSI */
3433 * Hypertransport interrupt support
3435 #ifdef CONFIG_HT_IRQ
3439 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3441 struct ht_irq_msg msg;
3442 fetch_ht_irq_msg(irq, &msg);
3444 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3445 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3447 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3448 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3450 write_ht_irq_msg(irq, &msg);
3453 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3455 struct irq_cfg *cfg;
3458 struct irq_desc *desc;
3460 cpus_and(tmp, mask, cpu_online_map);
3461 if (cpus_empty(tmp))
3464 if (assign_irq_vector(irq, mask))
3468 cpus_and(tmp, cfg->domain, mask);
3469 dest = cpu_mask_to_apicid(tmp);
3471 target_ht_irq(irq, dest, cfg->vector);
3472 desc = irq_to_desc(irq);
3473 desc->affinity = mask;
3477 static struct irq_chip ht_irq_chip = {
3479 .mask = mask_ht_irq,
3480 .unmask = unmask_ht_irq,
3481 .ack = ack_apic_edge,
3483 .set_affinity = set_ht_irq_affinity,
3485 .retrigger = ioapic_retrigger_irq,
3488 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3490 struct irq_cfg *cfg;
3495 err = assign_irq_vector(irq, tmp);
3497 struct ht_irq_msg msg;
3501 cpus_and(tmp, cfg->domain, tmp);
3502 dest = cpu_mask_to_apicid(tmp);
3504 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3508 HT_IRQ_LOW_DEST_ID(dest) |
3509 HT_IRQ_LOW_VECTOR(cfg->vector) |
3510 ((INT_DEST_MODE == 0) ?
3511 HT_IRQ_LOW_DM_PHYSICAL :
3512 HT_IRQ_LOW_DM_LOGICAL) |
3513 HT_IRQ_LOW_RQEOI_EDGE |
3514 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3515 HT_IRQ_LOW_MT_FIXED :
3516 HT_IRQ_LOW_MT_ARBITRATED) |
3517 HT_IRQ_LOW_IRQ_MASKED;
3519 write_ht_irq_msg(irq, &msg);
3521 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3522 handle_edge_irq, "edge");
3524 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3528 #endif /* CONFIG_HT_IRQ */
3530 #ifdef CONFIG_X86_64
3532 * Re-target the irq to the specified CPU and enable the specified MMR located
3533 * on the specified blade to allow the sending of MSIs to the specified CPU.
3535 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3536 unsigned long mmr_offset)
3538 const cpumask_t *eligible_cpu = get_cpu_mask(cpu);
3539 struct irq_cfg *cfg;
3541 unsigned long mmr_value;
3542 struct uv_IO_APIC_route_entry *entry;
3543 unsigned long flags;
3546 err = assign_irq_vector(irq, *eligible_cpu);
3550 spin_lock_irqsave(&vector_lock, flags);
3551 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3553 spin_unlock_irqrestore(&vector_lock, flags);
3558 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3559 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3561 entry->vector = cfg->vector;
3562 entry->delivery_mode = INT_DELIVERY_MODE;
3563 entry->dest_mode = INT_DEST_MODE;
3564 entry->polarity = 0;
3567 entry->dest = cpu_mask_to_apicid(*eligible_cpu);
3569 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3570 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3576 * Disable the specified MMR located on the specified blade so that MSIs are
3577 * longer allowed to be sent.
3579 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3581 unsigned long mmr_value;
3582 struct uv_IO_APIC_route_entry *entry;
3586 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3587 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3591 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3592 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3594 #endif /* CONFIG_X86_64 */
3596 int __init io_apic_get_redir_entries (int ioapic)
3598 union IO_APIC_reg_01 reg_01;
3599 unsigned long flags;
3601 spin_lock_irqsave(&ioapic_lock, flags);
3602 reg_01.raw = io_apic_read(ioapic, 1);
3603 spin_unlock_irqrestore(&ioapic_lock, flags);
3605 return reg_01.bits.entries;
3608 int __init probe_nr_irqs(void)
3613 /* --------------------------------------------------------------------------
3614 ACPI-based IOAPIC Configuration
3615 -------------------------------------------------------------------------- */
3619 #ifdef CONFIG_X86_32
3620 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3622 union IO_APIC_reg_00 reg_00;
3623 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3625 unsigned long flags;
3629 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3630 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3631 * supports up to 16 on one shared APIC bus.
3633 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3634 * advantage of new APIC bus architecture.
3637 if (physids_empty(apic_id_map))
3638 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3640 spin_lock_irqsave(&ioapic_lock, flags);
3641 reg_00.raw = io_apic_read(ioapic, 0);
3642 spin_unlock_irqrestore(&ioapic_lock, flags);
3644 if (apic_id >= get_physical_broadcast()) {
3645 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3646 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3647 apic_id = reg_00.bits.ID;
3651 * Every APIC in a system must have a unique ID or we get lots of nice
3652 * 'stuck on smp_invalidate_needed IPI wait' messages.
3654 if (check_apicid_used(apic_id_map, apic_id)) {
3656 for (i = 0; i < get_physical_broadcast(); i++) {
3657 if (!check_apicid_used(apic_id_map, i))
3661 if (i == get_physical_broadcast())
3662 panic("Max apic_id exceeded!\n");
3664 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3665 "trying %d\n", ioapic, apic_id, i);
3670 tmp = apicid_to_cpu_present(apic_id);
3671 physids_or(apic_id_map, apic_id_map, tmp);
3673 if (reg_00.bits.ID != apic_id) {
3674 reg_00.bits.ID = apic_id;
3676 spin_lock_irqsave(&ioapic_lock, flags);
3677 io_apic_write(ioapic, 0, reg_00.raw);
3678 reg_00.raw = io_apic_read(ioapic, 0);
3679 spin_unlock_irqrestore(&ioapic_lock, flags);
3682 if (reg_00.bits.ID != apic_id) {
3683 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3688 apic_printk(APIC_VERBOSE, KERN_INFO
3689 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3694 int __init io_apic_get_version(int ioapic)
3696 union IO_APIC_reg_01 reg_01;
3697 unsigned long flags;
3699 spin_lock_irqsave(&ioapic_lock, flags);
3700 reg_01.raw = io_apic_read(ioapic, 1);
3701 spin_unlock_irqrestore(&ioapic_lock, flags);
3703 return reg_01.bits.version;
3707 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3709 if (!IO_APIC_IRQ(irq)) {
3710 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3716 * IRQs < 16 are already in the irq_2_pin[] map
3719 add_pin_to_irq(irq, ioapic, pin);
3721 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3727 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3731 if (skip_ioapic_setup)
3734 for (i = 0; i < mp_irq_entries; i++)
3735 if (mp_irqs[i].mp_irqtype == mp_INT &&
3736 mp_irqs[i].mp_srcbusirq == bus_irq)
3738 if (i >= mp_irq_entries)
3741 *trigger = irq_trigger(i);
3742 *polarity = irq_polarity(i);
3746 #endif /* CONFIG_ACPI */
3749 * This function currently is only a helper for the i386 smp boot process where
3750 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3751 * so mask in all cases should simply be TARGET_CPUS
3754 void __init setup_ioapic_dest(void)
3756 int pin, ioapic, irq, irq_entry;
3757 struct irq_desc *desc;
3758 struct irq_cfg *cfg;
3761 if (skip_ioapic_setup == 1)
3764 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3765 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3766 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3767 if (irq_entry == -1)
3769 irq = pin_2_irq(irq_entry, ioapic, pin);
3771 /* setup_IO_APIC_irqs could fail to get vector for some device
3772 * when you have too many devices, because at that time only boot
3777 setup_IO_APIC_irq(ioapic, pin, irq,
3778 irq_trigger(irq_entry),
3779 irq_polarity(irq_entry));
3785 * Honour affinities which have been set in early boot
3787 desc = irq_to_desc(irq);
3789 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
3790 mask = desc->affinity;
3794 #ifdef CONFIG_INTR_REMAP
3795 if (intr_remapping_enabled)
3796 set_ir_ioapic_affinity_irq(irq, mask);
3799 set_ioapic_affinity_irq(irq, mask);
3806 #define IOAPIC_RESOURCE_NAME_SIZE 11
3808 static struct resource *ioapic_resources;
3810 static struct resource * __init ioapic_setup_resources(void)
3813 struct resource *res;
3817 if (nr_ioapics <= 0)
3820 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3823 mem = alloc_bootmem(n);
3827 mem += sizeof(struct resource) * nr_ioapics;
3829 for (i = 0; i < nr_ioapics; i++) {
3831 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3832 sprintf(mem, "IOAPIC %u", i);
3833 mem += IOAPIC_RESOURCE_NAME_SIZE;
3837 ioapic_resources = res;
3842 void __init ioapic_init_mappings(void)
3844 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3845 struct resource *ioapic_res;
3849 ioapic_res = ioapic_setup_resources();
3850 for (i = 0; i < nr_ioapics; i++) {
3851 if (smp_found_config) {
3852 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3853 #ifdef CONFIG_X86_32
3856 "WARNING: bogus zero IO-APIC "
3857 "address found in MPTABLE, "
3858 "disabling IO/APIC support!\n");
3859 smp_found_config = 0;
3860 skip_ioapic_setup = 1;
3861 goto fake_ioapic_page;
3865 #ifdef CONFIG_X86_32
3868 ioapic_phys = (unsigned long)
3869 alloc_bootmem_pages(PAGE_SIZE);
3870 ioapic_phys = __pa(ioapic_phys);
3872 set_fixmap_nocache(idx, ioapic_phys);
3873 apic_printk(APIC_VERBOSE,
3874 "mapped IOAPIC to %08lx (%08lx)\n",
3875 __fix_to_virt(idx), ioapic_phys);
3878 if (ioapic_res != NULL) {
3879 ioapic_res->start = ioapic_phys;
3880 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3886 static int __init ioapic_insert_resources(void)
3889 struct resource *r = ioapic_resources;
3893 "IO APIC resources could be not be allocated.\n");
3897 for (i = 0; i < nr_ioapics; i++) {
3898 insert_resource(&iomem_resource, r);
3905 /* Insert the IO APIC resources after PCI initialization has occured to handle
3906 * IO APICS that are mapped in on a BAR in PCI space. */
3907 late_initcall(ioapic_insert_resources);