2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 static int __init parse_noapic(char *str)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list {
121 struct irq_pin_list *next;
124 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
126 struct irq_pin_list *pin;
129 node = cpu_to_node(cpu);
131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132 printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node);
138 struct irq_pin_list *irq_2_pin;
140 cpumask_t old_domain;
141 unsigned move_cleanup_count;
143 u8 move_in_progress : 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending : 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
155 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
156 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
157 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
158 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
159 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
160 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
161 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
162 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
163 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
164 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
165 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
166 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
167 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
168 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
169 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
170 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
173 void __init arch_early_irq_init(void)
176 struct irq_desc *desc;
181 count = ARRAY_SIZE(irq_cfgx);
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
189 #ifdef CONFIG_SPARSE_IRQ
190 static struct irq_cfg *irq_cfg(unsigned int irq)
192 struct irq_cfg *cfg = NULL;
193 struct irq_desc *desc;
195 desc = irq_to_desc(irq);
197 cfg = desc->chip_data;
202 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
207 node = cpu_to_node(cpu);
209 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
210 printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
215 void arch_init_chip_data(struct irq_desc *desc, int cpu)
219 cfg = desc->chip_data;
221 desc->chip_data = get_one_free_irq_cfg(cpu);
222 if (!desc->chip_data) {
223 printk(KERN_ERR "can not alloc irq_cfg\n");
229 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
232 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
234 struct irq_pin_list *old_entry, *head, *tail, *entry;
236 cfg->irq_2_pin = NULL;
237 old_entry = old_cfg->irq_2_pin;
241 entry = get_one_free_irq_2_pin(cpu);
245 entry->apic = old_entry->apic;
246 entry->pin = old_entry->pin;
249 old_entry = old_entry->next;
251 entry = get_one_free_irq_2_pin(cpu);
259 /* still use the old one */
262 entry->apic = old_entry->apic;
263 entry->pin = old_entry->pin;
266 old_entry = old_entry->next;
270 cfg->irq_2_pin = head;
273 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
275 struct irq_pin_list *entry, *next;
277 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
280 entry = old_cfg->irq_2_pin;
287 old_cfg->irq_2_pin = NULL;
290 void arch_init_copy_chip_data(struct irq_desc *old_desc,
291 struct irq_desc *desc, int cpu)
294 struct irq_cfg *old_cfg;
296 cfg = get_one_free_irq_cfg(cpu);
301 desc->chip_data = cfg;
303 old_cfg = old_desc->chip_data;
305 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
307 init_copy_irq_2_pin(old_cfg, cfg, cpu);
310 static void free_irq_cfg(struct irq_cfg *old_cfg)
315 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
317 struct irq_cfg *old_cfg, *cfg;
319 old_cfg = old_desc->chip_data;
320 cfg = desc->chip_data;
326 free_irq_2_pin(old_cfg, cfg);
327 free_irq_cfg(old_cfg);
328 old_desc->chip_data = NULL;
332 static void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
334 struct irq_cfg *cfg = desc->chip_data;
336 if (!cfg->move_in_progress) {
337 /* it means that domain is not changed */
338 if (!cpus_intersects(desc->affinity, mask))
339 cfg->move_desc_pending = 1;
345 static struct irq_cfg *irq_cfg(unsigned int irq)
347 return irq < nr_irqs ? irq_cfgx + irq : NULL;
352 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
353 static inline void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
360 unsigned int unused[3];
364 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
366 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
367 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
370 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
372 struct io_apic __iomem *io_apic = io_apic_base(apic);
373 writel(reg, &io_apic->index);
374 return readl(&io_apic->data);
377 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
379 struct io_apic __iomem *io_apic = io_apic_base(apic);
380 writel(reg, &io_apic->index);
381 writel(value, &io_apic->data);
385 * Re-write a value: to be used for read-modify-write
386 * cycles where the read already set up the index register.
388 * Older SiS APIC requires we rewrite the index register
390 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
392 struct io_apic __iomem *io_apic = io_apic_base(apic);
395 writel(reg, &io_apic->index);
396 writel(value, &io_apic->data);
399 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
401 struct irq_pin_list *entry;
404 spin_lock_irqsave(&ioapic_lock, flags);
405 entry = cfg->irq_2_pin;
413 reg = io_apic_read(entry->apic, 0x10 + pin*2);
414 /* Is the remote IRR bit set? */
415 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
416 spin_unlock_irqrestore(&ioapic_lock, flags);
423 spin_unlock_irqrestore(&ioapic_lock, flags);
429 struct { u32 w1, w2; };
430 struct IO_APIC_route_entry entry;
433 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
435 union entry_union eu;
437 spin_lock_irqsave(&ioapic_lock, flags);
438 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
439 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
440 spin_unlock_irqrestore(&ioapic_lock, flags);
445 * When we write a new IO APIC routing entry, we need to write the high
446 * word first! If the mask bit in the low word is clear, we will enable
447 * the interrupt, and we need to make sure the entry is fully populated
448 * before that happens.
451 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
453 union entry_union eu;
455 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
456 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
459 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
462 spin_lock_irqsave(&ioapic_lock, flags);
463 __ioapic_write_entry(apic, pin, e);
464 spin_unlock_irqrestore(&ioapic_lock, flags);
468 * When we mask an IO APIC routing entry, we need to write the low
469 * word first, in order to set the mask bit before we change the
472 static void ioapic_mask_entry(int apic, int pin)
475 union entry_union eu = { .entry.mask = 1 };
477 spin_lock_irqsave(&ioapic_lock, flags);
478 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
479 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
480 spin_unlock_irqrestore(&ioapic_lock, flags);
484 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
487 struct irq_pin_list *entry;
488 u8 vector = cfg->vector;
490 entry = cfg->irq_2_pin;
499 #ifdef CONFIG_INTR_REMAP
501 * With interrupt-remapping, destination information comes
502 * from interrupt-remapping table entry.
504 if (!irq_remapped(irq))
505 io_apic_write(apic, 0x11 + pin*2, dest);
507 io_apic_write(apic, 0x11 + pin*2, dest);
509 reg = io_apic_read(apic, 0x10 + pin*2);
510 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
512 io_apic_modify(apic, 0x10 + pin*2, reg);
519 static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask);
521 static void set_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask)
529 cpus_and(tmp, mask, cpu_online_map);
534 cfg = desc->chip_data;
535 if (assign_irq_vector(irq, cfg, mask))
538 set_extra_move_desc(desc, mask);
540 cpus_and(tmp, cfg->domain, mask);
541 dest = cpu_mask_to_apicid(tmp);
543 * Only the high 8 bits are valid.
545 dest = SET_APIC_LOGICAL_ID(dest);
547 spin_lock_irqsave(&ioapic_lock, flags);
548 __target_IO_APIC_irq(irq, dest, cfg);
549 desc->affinity = mask;
550 spin_unlock_irqrestore(&ioapic_lock, flags);
553 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
555 struct irq_desc *desc;
557 desc = irq_to_desc(irq);
559 set_ioapic_affinity_irq_desc(desc, mask);
561 #endif /* CONFIG_SMP */
564 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
565 * shared ISA-space IRQs, so we have to support them. We are super
566 * fast in the common case, and fast for shared ISA-space IRQs.
568 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
570 struct irq_pin_list *entry;
572 entry = cfg->irq_2_pin;
574 entry = get_one_free_irq_2_pin(cpu);
576 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
580 cfg->irq_2_pin = entry;
586 while (entry->next) {
587 /* not again, please */
588 if (entry->apic == apic && entry->pin == pin)
594 entry->next = get_one_free_irq_2_pin(cpu);
601 * Reroute an IRQ to a different pin.
603 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
604 int oldapic, int oldpin,
605 int newapic, int newpin)
607 struct irq_pin_list *entry = cfg->irq_2_pin;
611 if (entry->apic == oldapic && entry->pin == oldpin) {
612 entry->apic = newapic;
615 /* every one is different, right? */
621 /* why? call replace before add? */
623 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
626 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
627 int mask_and, int mask_or,
628 void (*final)(struct irq_pin_list *entry))
631 struct irq_pin_list *entry;
633 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
636 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
639 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
645 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
647 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
651 void io_apic_sync(struct irq_pin_list *entry)
654 * Synchronize the IO-APIC and the CPU by doing
655 * a dummy read from the IO-APIC
657 struct io_apic __iomem *io_apic;
658 io_apic = io_apic_base(entry->apic);
659 readl(&io_apic->data);
662 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
664 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
666 #else /* CONFIG_X86_32 */
667 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
669 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
672 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
674 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
675 IO_APIC_REDIR_MASKED, NULL);
678 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
680 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
681 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
683 #endif /* CONFIG_X86_32 */
685 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
687 struct irq_cfg *cfg = desc->chip_data;
692 spin_lock_irqsave(&ioapic_lock, flags);
693 __mask_IO_APIC_irq(cfg);
694 spin_unlock_irqrestore(&ioapic_lock, flags);
697 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
699 struct irq_cfg *cfg = desc->chip_data;
702 spin_lock_irqsave(&ioapic_lock, flags);
703 __unmask_IO_APIC_irq(cfg);
704 spin_unlock_irqrestore(&ioapic_lock, flags);
707 static void mask_IO_APIC_irq(unsigned int irq)
709 struct irq_desc *desc = irq_to_desc(irq);
711 mask_IO_APIC_irq_desc(desc);
713 static void unmask_IO_APIC_irq(unsigned int irq)
715 struct irq_desc *desc = irq_to_desc(irq);
717 unmask_IO_APIC_irq_desc(desc);
720 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
722 struct IO_APIC_route_entry entry;
724 /* Check delivery_mode to be sure we're not clearing an SMI pin */
725 entry = ioapic_read_entry(apic, pin);
726 if (entry.delivery_mode == dest_SMI)
729 * Disable it in the IO-APIC irq-routing table:
731 ioapic_mask_entry(apic, pin);
734 static void clear_IO_APIC (void)
738 for (apic = 0; apic < nr_ioapics; apic++)
739 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
740 clear_IO_APIC_pin(apic, pin);
743 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
744 void send_IPI_self(int vector)
751 apic_wait_icr_idle();
752 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
754 * Send the IPI. The write to APIC_ICR fires this off.
756 apic_write(APIC_ICR, cfg);
758 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
762 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
763 * specific CPU-side IRQs.
767 static int pirq_entries [MAX_PIRQS];
768 static int pirqs_enabled;
770 static int __init ioapic_pirq_setup(char *str)
773 int ints[MAX_PIRQS+1];
775 get_options(str, ARRAY_SIZE(ints), ints);
777 for (i = 0; i < MAX_PIRQS; i++)
778 pirq_entries[i] = -1;
781 apic_printk(APIC_VERBOSE, KERN_INFO
782 "PIRQ redirection, working around broken MP-BIOS.\n");
784 if (ints[0] < MAX_PIRQS)
787 for (i = 0; i < max; i++) {
788 apic_printk(APIC_VERBOSE, KERN_DEBUG
789 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
791 * PIRQs are mapped upside down, usually.
793 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
798 __setup("pirq=", ioapic_pirq_setup);
799 #endif /* CONFIG_X86_32 */
801 #ifdef CONFIG_INTR_REMAP
802 /* I/O APIC RTE contents at the OS boot up */
803 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
806 * Saves and masks all the unmasked IO-APIC RTE's
808 int save_mask_IO_APIC_setup(void)
810 union IO_APIC_reg_01 reg_01;
815 * The number of IO-APIC IRQ registers (== #pins):
817 for (apic = 0; apic < nr_ioapics; apic++) {
818 spin_lock_irqsave(&ioapic_lock, flags);
819 reg_01.raw = io_apic_read(apic, 1);
820 spin_unlock_irqrestore(&ioapic_lock, flags);
821 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
824 for (apic = 0; apic < nr_ioapics; apic++) {
825 early_ioapic_entries[apic] =
826 kzalloc(sizeof(struct IO_APIC_route_entry) *
827 nr_ioapic_registers[apic], GFP_KERNEL);
828 if (!early_ioapic_entries[apic])
832 for (apic = 0; apic < nr_ioapics; apic++)
833 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
834 struct IO_APIC_route_entry entry;
836 entry = early_ioapic_entries[apic][pin] =
837 ioapic_read_entry(apic, pin);
840 ioapic_write_entry(apic, pin, entry);
848 kfree(early_ioapic_entries[apic--]);
849 memset(early_ioapic_entries, 0,
850 ARRAY_SIZE(early_ioapic_entries));
855 void restore_IO_APIC_setup(void)
859 for (apic = 0; apic < nr_ioapics; apic++) {
860 if (!early_ioapic_entries[apic])
862 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
863 ioapic_write_entry(apic, pin,
864 early_ioapic_entries[apic][pin]);
865 kfree(early_ioapic_entries[apic]);
866 early_ioapic_entries[apic] = NULL;
870 void reinit_intr_remapped_IO_APIC(int intr_remapping)
873 * for now plain restore of previous settings.
874 * TBD: In the case of OS enabling interrupt-remapping,
875 * IO-APIC RTE's need to be setup to point to interrupt-remapping
876 * table entries. for now, do a plain restore, and wait for
877 * the setup_IO_APIC_irqs() to do proper initialization.
879 restore_IO_APIC_setup();
884 * Find the IRQ entry number of a certain pin.
886 static int find_irq_entry(int apic, int pin, int type)
890 for (i = 0; i < mp_irq_entries; i++)
891 if (mp_irqs[i].mp_irqtype == type &&
892 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
893 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
894 mp_irqs[i].mp_dstirq == pin)
901 * Find the pin to which IRQ[irq] (ISA) is connected
903 static int __init find_isa_irq_pin(int irq, int type)
907 for (i = 0; i < mp_irq_entries; i++) {
908 int lbus = mp_irqs[i].mp_srcbus;
910 if (test_bit(lbus, mp_bus_not_pci) &&
911 (mp_irqs[i].mp_irqtype == type) &&
912 (mp_irqs[i].mp_srcbusirq == irq))
914 return mp_irqs[i].mp_dstirq;
919 static int __init find_isa_irq_apic(int irq, int type)
923 for (i = 0; i < mp_irq_entries; i++) {
924 int lbus = mp_irqs[i].mp_srcbus;
926 if (test_bit(lbus, mp_bus_not_pci) &&
927 (mp_irqs[i].mp_irqtype == type) &&
928 (mp_irqs[i].mp_srcbusirq == irq))
931 if (i < mp_irq_entries) {
933 for(apic = 0; apic < nr_ioapics; apic++) {
934 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
943 * Find a specific PCI IRQ entry.
944 * Not an __init, possibly needed by modules
946 static int pin_2_irq(int idx, int apic, int pin);
948 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
950 int apic, i, best_guess = -1;
952 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
954 if (test_bit(bus, mp_bus_not_pci)) {
955 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
958 for (i = 0; i < mp_irq_entries; i++) {
959 int lbus = mp_irqs[i].mp_srcbus;
961 for (apic = 0; apic < nr_ioapics; apic++)
962 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
963 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
966 if (!test_bit(lbus, mp_bus_not_pci) &&
967 !mp_irqs[i].mp_irqtype &&
969 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
970 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
972 if (!(apic || IO_APIC_IRQ(irq)))
975 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
978 * Use the first all-but-pin matching entry as a
979 * best-guess fuzzy result for broken mptables.
988 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
990 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
992 * EISA Edge/Level control register, ELCR
994 static int EISA_ELCR(unsigned int irq)
996 if (irq < NR_IRQS_LEGACY) {
997 unsigned int port = 0x4d0 + (irq >> 3);
998 return (inb(port) >> (irq & 7)) & 1;
1000 apic_printk(APIC_VERBOSE, KERN_INFO
1001 "Broken MPtable reports ISA irq %d\n", irq);
1007 /* ISA interrupts are always polarity zero edge triggered,
1008 * when listed as conforming in the MP table. */
1010 #define default_ISA_trigger(idx) (0)
1011 #define default_ISA_polarity(idx) (0)
1013 /* EISA interrupts are always polarity zero and can be edge or level
1014 * trigger depending on the ELCR value. If an interrupt is listed as
1015 * EISA conforming in the MP table, that means its trigger type must
1016 * be read in from the ELCR */
1018 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1019 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1021 /* PCI interrupts are always polarity one level triggered,
1022 * when listed as conforming in the MP table. */
1024 #define default_PCI_trigger(idx) (1)
1025 #define default_PCI_polarity(idx) (1)
1027 /* MCA interrupts are always polarity zero level triggered,
1028 * when listed as conforming in the MP table. */
1030 #define default_MCA_trigger(idx) (1)
1031 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1033 static int MPBIOS_polarity(int idx)
1035 int bus = mp_irqs[idx].mp_srcbus;
1039 * Determine IRQ line polarity (high active or low active):
1041 switch (mp_irqs[idx].mp_irqflag & 3)
1043 case 0: /* conforms, ie. bus-type dependent polarity */
1044 if (test_bit(bus, mp_bus_not_pci))
1045 polarity = default_ISA_polarity(idx);
1047 polarity = default_PCI_polarity(idx);
1049 case 1: /* high active */
1054 case 2: /* reserved */
1056 printk(KERN_WARNING "broken BIOS!!\n");
1060 case 3: /* low active */
1065 default: /* invalid */
1067 printk(KERN_WARNING "broken BIOS!!\n");
1075 static int MPBIOS_trigger(int idx)
1077 int bus = mp_irqs[idx].mp_srcbus;
1081 * Determine IRQ trigger mode (edge or level sensitive):
1083 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1085 case 0: /* conforms, ie. bus-type dependent */
1086 if (test_bit(bus, mp_bus_not_pci))
1087 trigger = default_ISA_trigger(idx);
1089 trigger = default_PCI_trigger(idx);
1090 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1091 switch (mp_bus_id_to_type[bus]) {
1092 case MP_BUS_ISA: /* ISA pin */
1094 /* set before the switch */
1097 case MP_BUS_EISA: /* EISA pin */
1099 trigger = default_EISA_trigger(idx);
1102 case MP_BUS_PCI: /* PCI pin */
1104 /* set before the switch */
1107 case MP_BUS_MCA: /* MCA pin */
1109 trigger = default_MCA_trigger(idx);
1114 printk(KERN_WARNING "broken BIOS!!\n");
1126 case 2: /* reserved */
1128 printk(KERN_WARNING "broken BIOS!!\n");
1137 default: /* invalid */
1139 printk(KERN_WARNING "broken BIOS!!\n");
1147 static inline int irq_polarity(int idx)
1149 return MPBIOS_polarity(idx);
1152 static inline int irq_trigger(int idx)
1154 return MPBIOS_trigger(idx);
1157 int (*ioapic_renumber_irq)(int ioapic, int irq);
1158 static int pin_2_irq(int idx, int apic, int pin)
1161 int bus = mp_irqs[idx].mp_srcbus;
1164 * Debugging check, we are in big trouble if this message pops up!
1166 if (mp_irqs[idx].mp_dstirq != pin)
1167 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1169 if (test_bit(bus, mp_bus_not_pci)) {
1170 irq = mp_irqs[idx].mp_srcbusirq;
1173 * PCI IRQs are mapped in order
1177 irq += nr_ioapic_registers[i++];
1180 * For MPS mode, so far only needed by ES7000 platform
1182 if (ioapic_renumber_irq)
1183 irq = ioapic_renumber_irq(apic, irq);
1186 #ifdef CONFIG_X86_32
1188 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1190 if ((pin >= 16) && (pin <= 23)) {
1191 if (pirq_entries[pin-16] != -1) {
1192 if (!pirq_entries[pin-16]) {
1193 apic_printk(APIC_VERBOSE, KERN_DEBUG
1194 "disabling PIRQ%d\n", pin-16);
1196 irq = pirq_entries[pin-16];
1197 apic_printk(APIC_VERBOSE, KERN_DEBUG
1198 "using PIRQ%d -> IRQ %d\n",
1208 void lock_vector_lock(void)
1210 /* Used to the online set of cpus does not change
1211 * during assign_irq_vector.
1213 spin_lock(&vector_lock);
1216 void unlock_vector_lock(void)
1218 spin_unlock(&vector_lock);
1221 static int __assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask)
1224 * NOTE! The local APIC isn't very good at handling
1225 * multiple interrupts at the same interrupt level.
1226 * As the interrupt level is determined by taking the
1227 * vector number and shifting that right by 4, we
1228 * want to spread these out a bit so that they don't
1229 * all fall in the same interrupt level.
1231 * Also, we've got to be careful not to trash gate
1232 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1234 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1235 unsigned int old_vector;
1238 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1241 /* Only try and allocate irqs on cpus that are present */
1242 cpus_and(mask, mask, cpu_online_map);
1244 old_vector = cfg->vector;
1247 cpus_and(tmp, cfg->domain, mask);
1248 if (!cpus_empty(tmp))
1252 for_each_cpu_mask_nr(cpu, mask) {
1253 cpumask_t domain, new_mask;
1257 domain = vector_allocation_domain(cpu);
1258 cpus_and(new_mask, domain, cpu_online_map);
1260 vector = current_vector;
1261 offset = current_offset;
1264 if (vector >= first_system_vector) {
1265 /* If we run out of vectors on large boxen, must share them. */
1266 offset = (offset + 1) % 8;
1267 vector = FIRST_DEVICE_VECTOR + offset;
1269 if (unlikely(current_vector == vector))
1271 #ifdef CONFIG_X86_64
1272 if (vector == IA32_SYSCALL_VECTOR)
1275 if (vector == SYSCALL_VECTOR)
1278 for_each_cpu_mask_nr(new_cpu, new_mask)
1279 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1282 current_vector = vector;
1283 current_offset = offset;
1285 cfg->move_in_progress = 1;
1286 cfg->old_domain = cfg->domain;
1288 for_each_cpu_mask_nr(new_cpu, new_mask)
1289 per_cpu(vector_irq, new_cpu)[vector] = irq;
1290 cfg->vector = vector;
1291 cfg->domain = domain;
1297 static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask)
1300 unsigned long flags;
1302 spin_lock_irqsave(&vector_lock, flags);
1303 err = __assign_irq_vector(irq, cfg, mask);
1304 spin_unlock_irqrestore(&vector_lock, flags);
1308 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1313 BUG_ON(!cfg->vector);
1315 vector = cfg->vector;
1316 cpus_and(mask, cfg->domain, cpu_online_map);
1317 for_each_cpu_mask_nr(cpu, mask)
1318 per_cpu(vector_irq, cpu)[vector] = -1;
1321 cpus_clear(cfg->domain);
1323 if (likely(!cfg->move_in_progress))
1325 cpus_and(mask, cfg->old_domain, cpu_online_map);
1326 for_each_cpu_mask_nr(cpu, mask) {
1327 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1329 if (per_cpu(vector_irq, cpu)[vector] != irq)
1331 per_cpu(vector_irq, cpu)[vector] = -1;
1335 cfg->move_in_progress = 0;
1338 void __setup_vector_irq(int cpu)
1340 /* Initialize vector_irq on a new cpu */
1341 /* This function must be called with vector_lock held */
1343 struct irq_cfg *cfg;
1344 struct irq_desc *desc;
1346 /* Mark the inuse vectors */
1347 for_each_irq_desc(irq, desc) {
1350 cfg = desc->chip_data;
1351 if (!cpu_isset(cpu, cfg->domain))
1353 vector = cfg->vector;
1354 per_cpu(vector_irq, cpu)[vector] = irq;
1356 /* Mark the free vectors */
1357 for (vector = 0; vector < NR_VECTORS; ++vector) {
1358 irq = per_cpu(vector_irq, cpu)[vector];
1363 if (!cpu_isset(cpu, cfg->domain))
1364 per_cpu(vector_irq, cpu)[vector] = -1;
1368 static struct irq_chip ioapic_chip;
1369 #ifdef CONFIG_INTR_REMAP
1370 static struct irq_chip ir_ioapic_chip;
1373 #define IOAPIC_AUTO -1
1374 #define IOAPIC_EDGE 0
1375 #define IOAPIC_LEVEL 1
1377 #ifdef CONFIG_X86_32
1378 static inline int IO_APIC_irq_trigger(int irq)
1382 for (apic = 0; apic < nr_ioapics; apic++) {
1383 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1384 idx = find_irq_entry(apic, pin, mp_INT);
1385 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1386 return irq_trigger(idx);
1390 * nonexistent IRQs are edge default
1395 static inline int IO_APIC_irq_trigger(int irq)
1401 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1404 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1405 trigger == IOAPIC_LEVEL)
1406 desc->status |= IRQ_LEVEL;
1408 desc->status &= ~IRQ_LEVEL;
1410 #ifdef CONFIG_INTR_REMAP
1411 if (irq_remapped(irq)) {
1412 desc->status |= IRQ_MOVE_PCNTXT;
1414 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1418 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1419 handle_edge_irq, "edge");
1423 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1424 trigger == IOAPIC_LEVEL)
1425 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1429 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1430 handle_edge_irq, "edge");
1433 static int setup_ioapic_entry(int apic, int irq,
1434 struct IO_APIC_route_entry *entry,
1435 unsigned int destination, int trigger,
1436 int polarity, int vector)
1439 * add it to the IO-APIC irq-routing table:
1441 memset(entry,0,sizeof(*entry));
1443 #ifdef CONFIG_INTR_REMAP
1444 if (intr_remapping_enabled) {
1445 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1447 struct IR_IO_APIC_route_entry *ir_entry =
1448 (struct IR_IO_APIC_route_entry *) entry;
1452 panic("No mapping iommu for ioapic %d\n", apic);
1454 index = alloc_irte(iommu, irq, 1);
1456 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1458 memset(&irte, 0, sizeof(irte));
1461 irte.dst_mode = INT_DEST_MODE;
1462 irte.trigger_mode = trigger;
1463 irte.dlvry_mode = INT_DELIVERY_MODE;
1464 irte.vector = vector;
1465 irte.dest_id = IRTE_DEST(destination);
1467 modify_irte(irq, &irte);
1469 ir_entry->index2 = (index >> 15) & 0x1;
1471 ir_entry->format = 1;
1472 ir_entry->index = (index & 0x7fff);
1476 entry->delivery_mode = INT_DELIVERY_MODE;
1477 entry->dest_mode = INT_DEST_MODE;
1478 entry->dest = destination;
1481 entry->mask = 0; /* enable IRQ */
1482 entry->trigger = trigger;
1483 entry->polarity = polarity;
1484 entry->vector = vector;
1486 /* Mask level triggered irqs.
1487 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1494 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
1495 int trigger, int polarity)
1497 struct irq_cfg *cfg;
1498 struct IO_APIC_route_entry entry;
1501 if (!IO_APIC_IRQ(irq))
1504 cfg = desc->chip_data;
1507 if (assign_irq_vector(irq, cfg, mask))
1510 cpus_and(mask, cfg->domain, mask);
1512 apic_printk(APIC_VERBOSE,KERN_DEBUG
1513 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1514 "IRQ %d Mode:%i Active:%i)\n",
1515 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1516 irq, trigger, polarity);
1519 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1520 cpu_mask_to_apicid(mask), trigger, polarity,
1522 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1523 mp_ioapics[apic].mp_apicid, pin);
1524 __clear_irq_vector(irq, cfg);
1528 ioapic_register_intr(irq, desc, trigger);
1529 if (irq < NR_IRQS_LEGACY)
1530 disable_8259A_irq(irq);
1532 ioapic_write_entry(apic, pin, entry);
1535 static void __init setup_IO_APIC_irqs(void)
1537 int apic, pin, idx, irq;
1539 struct irq_desc *desc;
1540 struct irq_cfg *cfg;
1541 int cpu = boot_cpu_id;
1543 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1545 for (apic = 0; apic < nr_ioapics; apic++) {
1546 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1548 idx = find_irq_entry(apic, pin, mp_INT);
1552 apic_printk(APIC_VERBOSE,
1553 KERN_DEBUG " %d-%d",
1554 mp_ioapics[apic].mp_apicid,
1557 apic_printk(APIC_VERBOSE, " %d-%d",
1558 mp_ioapics[apic].mp_apicid,
1563 apic_printk(APIC_VERBOSE,
1564 " (apicid-pin) not connected\n");
1568 irq = pin_2_irq(idx, apic, pin);
1569 #ifdef CONFIG_X86_32
1570 if (multi_timer_check(apic, irq))
1573 desc = irq_to_desc_alloc_cpu(irq, cpu);
1575 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1578 cfg = desc->chip_data;
1579 add_pin_to_irq_cpu(cfg, cpu, apic, pin);
1581 setup_IO_APIC_irq(apic, pin, irq, desc,
1582 irq_trigger(idx), irq_polarity(idx));
1587 apic_printk(APIC_VERBOSE,
1588 " (apicid-pin) not connected\n");
1592 * Set up the timer pin, possibly with the 8259A-master behind.
1594 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1597 struct IO_APIC_route_entry entry;
1599 #ifdef CONFIG_INTR_REMAP
1600 if (intr_remapping_enabled)
1604 memset(&entry, 0, sizeof(entry));
1607 * We use logical delivery to get the timer IRQ
1610 entry.dest_mode = INT_DEST_MODE;
1611 entry.mask = 1; /* mask IRQ now */
1612 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1613 entry.delivery_mode = INT_DELIVERY_MODE;
1616 entry.vector = vector;
1619 * The timer IRQ doesn't have to know that behind the
1620 * scene we may have a 8259A-master in AEOI mode ...
1622 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1625 * Add it to the IO-APIC irq-routing table:
1627 ioapic_write_entry(apic, pin, entry);
1631 __apicdebuginit(void) print_IO_APIC(void)
1634 union IO_APIC_reg_00 reg_00;
1635 union IO_APIC_reg_01 reg_01;
1636 union IO_APIC_reg_02 reg_02;
1637 union IO_APIC_reg_03 reg_03;
1638 unsigned long flags;
1639 struct irq_cfg *cfg;
1640 struct irq_desc *desc;
1643 if (apic_verbosity == APIC_QUIET)
1646 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1647 for (i = 0; i < nr_ioapics; i++)
1648 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1649 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1652 * We are a bit conservative about what we expect. We have to
1653 * know about every hardware change ASAP.
1655 printk(KERN_INFO "testing the IO APIC.......................\n");
1657 for (apic = 0; apic < nr_ioapics; apic++) {
1659 spin_lock_irqsave(&ioapic_lock, flags);
1660 reg_00.raw = io_apic_read(apic, 0);
1661 reg_01.raw = io_apic_read(apic, 1);
1662 if (reg_01.bits.version >= 0x10)
1663 reg_02.raw = io_apic_read(apic, 2);
1664 if (reg_01.bits.version >= 0x20)
1665 reg_03.raw = io_apic_read(apic, 3);
1666 spin_unlock_irqrestore(&ioapic_lock, flags);
1669 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1670 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1671 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1672 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1673 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1675 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1676 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1678 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1679 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1682 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1683 * but the value of reg_02 is read as the previous read register
1684 * value, so ignore it if reg_02 == reg_01.
1686 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1687 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1688 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1692 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1693 * or reg_03, but the value of reg_0[23] is read as the previous read
1694 * register value, so ignore it if reg_03 == reg_0[12].
1696 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1697 reg_03.raw != reg_01.raw) {
1698 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1699 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1702 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1704 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1705 " Stat Dmod Deli Vect: \n");
1707 for (i = 0; i <= reg_01.bits.entries; i++) {
1708 struct IO_APIC_route_entry entry;
1710 entry = ioapic_read_entry(apic, i);
1712 printk(KERN_DEBUG " %02x %03X ",
1717 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1722 entry.delivery_status,
1724 entry.delivery_mode,
1729 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1730 for_each_irq_desc(irq, desc) {
1731 struct irq_pin_list *entry;
1735 cfg = desc->chip_data;
1736 entry = cfg->irq_2_pin;
1739 printk(KERN_DEBUG "IRQ%d ", irq);
1741 printk("-> %d:%d", entry->apic, entry->pin);
1744 entry = entry->next;
1749 printk(KERN_INFO ".................................... done.\n");
1754 __apicdebuginit(void) print_APIC_bitfield(int base)
1759 if (apic_verbosity == APIC_QUIET)
1762 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1763 for (i = 0; i < 8; i++) {
1764 v = apic_read(base + i*0x10);
1765 for (j = 0; j < 32; j++) {
1775 __apicdebuginit(void) print_local_APIC(void *dummy)
1777 unsigned int v, ver, maxlvt;
1780 if (apic_verbosity == APIC_QUIET)
1783 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1784 smp_processor_id(), hard_smp_processor_id());
1785 v = apic_read(APIC_ID);
1786 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1787 v = apic_read(APIC_LVR);
1788 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1789 ver = GET_APIC_VERSION(v);
1790 maxlvt = lapic_get_maxlvt();
1792 v = apic_read(APIC_TASKPRI);
1793 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1795 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1796 if (!APIC_XAPIC(ver)) {
1797 v = apic_read(APIC_ARBPRI);
1798 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1799 v & APIC_ARBPRI_MASK);
1801 v = apic_read(APIC_PROCPRI);
1802 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1806 * Remote read supported only in the 82489DX and local APIC for
1807 * Pentium processors.
1809 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1810 v = apic_read(APIC_RRR);
1811 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1814 v = apic_read(APIC_LDR);
1815 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1816 if (!x2apic_enabled()) {
1817 v = apic_read(APIC_DFR);
1818 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1820 v = apic_read(APIC_SPIV);
1821 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1823 printk(KERN_DEBUG "... APIC ISR field:\n");
1824 print_APIC_bitfield(APIC_ISR);
1825 printk(KERN_DEBUG "... APIC TMR field:\n");
1826 print_APIC_bitfield(APIC_TMR);
1827 printk(KERN_DEBUG "... APIC IRR field:\n");
1828 print_APIC_bitfield(APIC_IRR);
1830 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1831 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1832 apic_write(APIC_ESR, 0);
1834 v = apic_read(APIC_ESR);
1835 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1838 icr = apic_icr_read();
1839 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1840 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1842 v = apic_read(APIC_LVTT);
1843 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1845 if (maxlvt > 3) { /* PC is LVT#4. */
1846 v = apic_read(APIC_LVTPC);
1847 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1849 v = apic_read(APIC_LVT0);
1850 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1851 v = apic_read(APIC_LVT1);
1852 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1854 if (maxlvt > 2) { /* ERR is LVT#3. */
1855 v = apic_read(APIC_LVTERR);
1856 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1859 v = apic_read(APIC_TMICT);
1860 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1861 v = apic_read(APIC_TMCCT);
1862 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1863 v = apic_read(APIC_TDCR);
1864 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1868 __apicdebuginit(void) print_all_local_APICs(void)
1873 for_each_online_cpu(cpu)
1874 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1878 __apicdebuginit(void) print_PIC(void)
1881 unsigned long flags;
1883 if (apic_verbosity == APIC_QUIET)
1886 printk(KERN_DEBUG "\nprinting PIC contents\n");
1888 spin_lock_irqsave(&i8259A_lock, flags);
1890 v = inb(0xa1) << 8 | inb(0x21);
1891 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1893 v = inb(0xa0) << 8 | inb(0x20);
1894 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1898 v = inb(0xa0) << 8 | inb(0x20);
1902 spin_unlock_irqrestore(&i8259A_lock, flags);
1904 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1906 v = inb(0x4d1) << 8 | inb(0x4d0);
1907 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1910 __apicdebuginit(int) print_all_ICs(void)
1913 print_all_local_APICs();
1919 fs_initcall(print_all_ICs);
1922 /* Where if anywhere is the i8259 connect in external int mode */
1923 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1925 void __init enable_IO_APIC(void)
1927 union IO_APIC_reg_01 reg_01;
1928 int i8259_apic, i8259_pin;
1930 unsigned long flags;
1932 #ifdef CONFIG_X86_32
1935 for (i = 0; i < MAX_PIRQS; i++)
1936 pirq_entries[i] = -1;
1940 * The number of IO-APIC IRQ registers (== #pins):
1942 for (apic = 0; apic < nr_ioapics; apic++) {
1943 spin_lock_irqsave(&ioapic_lock, flags);
1944 reg_01.raw = io_apic_read(apic, 1);
1945 spin_unlock_irqrestore(&ioapic_lock, flags);
1946 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1948 for(apic = 0; apic < nr_ioapics; apic++) {
1950 /* See if any of the pins is in ExtINT mode */
1951 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1952 struct IO_APIC_route_entry entry;
1953 entry = ioapic_read_entry(apic, pin);
1955 /* If the interrupt line is enabled and in ExtInt mode
1956 * I have found the pin where the i8259 is connected.
1958 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1959 ioapic_i8259.apic = apic;
1960 ioapic_i8259.pin = pin;
1966 /* Look to see what if the MP table has reported the ExtINT */
1967 /* If we could not find the appropriate pin by looking at the ioapic
1968 * the i8259 probably is not connected the ioapic but give the
1969 * mptable a chance anyway.
1971 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1972 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1973 /* Trust the MP table if nothing is setup in the hardware */
1974 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1975 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1976 ioapic_i8259.pin = i8259_pin;
1977 ioapic_i8259.apic = i8259_apic;
1979 /* Complain if the MP table and the hardware disagree */
1980 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1981 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1983 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1987 * Do not trust the IO-APIC being empty at bootup
1993 * Not an __init, needed by the reboot code
1995 void disable_IO_APIC(void)
1998 * Clear the IO-APIC before rebooting:
2003 * If the i8259 is routed through an IOAPIC
2004 * Put that IOAPIC in virtual wire mode
2005 * so legacy interrupts can be delivered.
2007 if (ioapic_i8259.pin != -1) {
2008 struct IO_APIC_route_entry entry;
2010 memset(&entry, 0, sizeof(entry));
2011 entry.mask = 0; /* Enabled */
2012 entry.trigger = 0; /* Edge */
2014 entry.polarity = 0; /* High */
2015 entry.delivery_status = 0;
2016 entry.dest_mode = 0; /* Physical */
2017 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2019 entry.dest = read_apic_id();
2022 * Add it to the IO-APIC irq-routing table:
2024 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2027 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2030 #ifdef CONFIG_X86_32
2032 * function to set the IO-APIC physical IDs based on the
2033 * values stored in the MPC table.
2035 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2038 static void __init setup_ioapic_ids_from_mpc(void)
2040 union IO_APIC_reg_00 reg_00;
2041 physid_mask_t phys_id_present_map;
2044 unsigned char old_id;
2045 unsigned long flags;
2047 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2051 * Don't check I/O APIC IDs for xAPIC systems. They have
2052 * no meaning without the serial APIC bus.
2054 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2055 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2058 * This is broken; anything with a real cpu count has to
2059 * circumvent this idiocy regardless.
2061 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2064 * Set the IOAPIC ID to the value stored in the MPC table.
2066 for (apic = 0; apic < nr_ioapics; apic++) {
2068 /* Read the register 0 value */
2069 spin_lock_irqsave(&ioapic_lock, flags);
2070 reg_00.raw = io_apic_read(apic, 0);
2071 spin_unlock_irqrestore(&ioapic_lock, flags);
2073 old_id = mp_ioapics[apic].mp_apicid;
2075 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
2076 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2077 apic, mp_ioapics[apic].mp_apicid);
2078 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2080 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
2084 * Sanity check, is the ID really free? Every APIC in a
2085 * system must have a unique ID or we get lots of nice
2086 * 'stuck on smp_invalidate_needed IPI wait' messages.
2088 if (check_apicid_used(phys_id_present_map,
2089 mp_ioapics[apic].mp_apicid)) {
2090 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2091 apic, mp_ioapics[apic].mp_apicid);
2092 for (i = 0; i < get_physical_broadcast(); i++)
2093 if (!physid_isset(i, phys_id_present_map))
2095 if (i >= get_physical_broadcast())
2096 panic("Max APIC ID exceeded!\n");
2097 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2099 physid_set(i, phys_id_present_map);
2100 mp_ioapics[apic].mp_apicid = i;
2103 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2104 apic_printk(APIC_VERBOSE, "Setting %d in the "
2105 "phys_id_present_map\n",
2106 mp_ioapics[apic].mp_apicid);
2107 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2112 * We need to adjust the IRQ routing table
2113 * if the ID changed.
2115 if (old_id != mp_ioapics[apic].mp_apicid)
2116 for (i = 0; i < mp_irq_entries; i++)
2117 if (mp_irqs[i].mp_dstapic == old_id)
2118 mp_irqs[i].mp_dstapic
2119 = mp_ioapics[apic].mp_apicid;
2122 * Read the right value from the MPC table and
2123 * write it into the ID register.
2125 apic_printk(APIC_VERBOSE, KERN_INFO
2126 "...changing IO-APIC physical APIC ID to %d ...",
2127 mp_ioapics[apic].mp_apicid);
2129 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2130 spin_lock_irqsave(&ioapic_lock, flags);
2131 io_apic_write(apic, 0, reg_00.raw);
2132 spin_unlock_irqrestore(&ioapic_lock, flags);
2137 spin_lock_irqsave(&ioapic_lock, flags);
2138 reg_00.raw = io_apic_read(apic, 0);
2139 spin_unlock_irqrestore(&ioapic_lock, flags);
2140 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2141 printk("could not set ID!\n");
2143 apic_printk(APIC_VERBOSE, " ok.\n");
2148 int no_timer_check __initdata;
2150 static int __init notimercheck(char *s)
2155 __setup("no_timer_check", notimercheck);
2158 * There is a nasty bug in some older SMP boards, their mptable lies
2159 * about the timer IRQ. We do the following to work around the situation:
2161 * - timer IRQ defaults to IO-APIC IRQ
2162 * - if this function detects that timer IRQs are defunct, then we fall
2163 * back to ISA timer IRQs
2165 static int __init timer_irq_works(void)
2167 unsigned long t1 = jiffies;
2168 unsigned long flags;
2173 local_save_flags(flags);
2175 /* Let ten ticks pass... */
2176 mdelay((10 * 1000) / HZ);
2177 local_irq_restore(flags);
2180 * Expect a few ticks at least, to be sure some possible
2181 * glue logic does not lock up after one or two first
2182 * ticks in a non-ExtINT mode. Also the local APIC
2183 * might have cached one ExtINT interrupt. Finally, at
2184 * least one tick may be lost due to delays.
2188 if (time_after(jiffies, t1 + 4))
2194 * In the SMP+IOAPIC case it might happen that there are an unspecified
2195 * number of pending IRQ events unhandled. These cases are very rare,
2196 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2197 * better to do it this way as thus we do not have to be aware of
2198 * 'pending' interrupts in the IRQ path, except at this point.
2201 * Edge triggered needs to resend any interrupt
2202 * that was delayed but this is now handled in the device
2207 * Starting up a edge-triggered IO-APIC interrupt is
2208 * nasty - we need to make sure that we get the edge.
2209 * If it is already asserted for some reason, we need
2210 * return 1 to indicate that is was pending.
2212 * This is not complete - we should be able to fake
2213 * an edge even if it isn't on the 8259A...
2216 static unsigned int startup_ioapic_irq(unsigned int irq)
2218 int was_pending = 0;
2219 unsigned long flags;
2220 struct irq_cfg *cfg;
2222 spin_lock_irqsave(&ioapic_lock, flags);
2223 if (irq < NR_IRQS_LEGACY) {
2224 disable_8259A_irq(irq);
2225 if (i8259A_irq_pending(irq))
2229 __unmask_IO_APIC_irq(cfg);
2230 spin_unlock_irqrestore(&ioapic_lock, flags);
2235 #ifdef CONFIG_X86_64
2236 static int ioapic_retrigger_irq(unsigned int irq)
2239 struct irq_cfg *cfg = irq_cfg(irq);
2240 unsigned long flags;
2242 spin_lock_irqsave(&vector_lock, flags);
2243 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2244 spin_unlock_irqrestore(&vector_lock, flags);
2249 static int ioapic_retrigger_irq(unsigned int irq)
2251 send_IPI_self(irq_cfg(irq)->vector);
2258 * Level and edge triggered IO-APIC interrupts need different handling,
2259 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2260 * handled with the level-triggered descriptor, but that one has slightly
2261 * more overhead. Level-triggered interrupts cannot be handled with the
2262 * edge-triggered handler, without risking IRQ storms and other ugly
2268 #ifdef CONFIG_INTR_REMAP
2269 static void ir_irq_migration(struct work_struct *work);
2271 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2274 * Migrate the IO-APIC irq in the presence of intr-remapping.
2276 * For edge triggered, irq migration is a simple atomic update(of vector
2277 * and cpu destination) of IRTE and flush the hardware cache.
2279 * For level triggered, we need to modify the io-apic RTE aswell with the update
2280 * vector information, along with modifying IRTE with vector and destination.
2281 * So irq migration for level triggered is little bit more complex compared to
2282 * edge triggered migration. But the good news is, we use the same algorithm
2283 * for level triggered migration as we have today, only difference being,
2284 * we now initiate the irq migration from process context instead of the
2285 * interrupt context.
2287 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2288 * suppression) to the IO-APIC, level triggered irq migration will also be
2289 * as simple as edge triggered migration and we can do the irq migration
2290 * with a simple atomic update to IO-APIC RTE.
2292 static void migrate_ioapic_irq_desc(struct irq_desc *desc, cpumask_t mask)
2294 struct irq_cfg *cfg;
2295 cpumask_t tmp, cleanup_mask;
2297 int modify_ioapic_rte;
2299 unsigned long flags;
2302 cpus_and(tmp, mask, cpu_online_map);
2303 if (cpus_empty(tmp))
2307 if (get_irte(irq, &irte))
2310 cfg = desc->chip_data;
2311 if (assign_irq_vector(irq, cfg, mask))
2314 set_extra_move_desc(desc, mask);
2316 cpus_and(tmp, cfg->domain, mask);
2317 dest = cpu_mask_to_apicid(tmp);
2319 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2320 if (modify_ioapic_rte) {
2321 spin_lock_irqsave(&ioapic_lock, flags);
2322 __target_IO_APIC_irq(irq, dest, cfg);
2323 spin_unlock_irqrestore(&ioapic_lock, flags);
2326 irte.vector = cfg->vector;
2327 irte.dest_id = IRTE_DEST(dest);
2330 * Modified the IRTE and flushes the Interrupt entry cache.
2332 modify_irte(irq, &irte);
2334 if (cfg->move_in_progress) {
2335 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2336 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2337 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2338 cfg->move_in_progress = 0;
2341 desc->affinity = mask;
2344 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2347 struct irq_cfg *cfg = desc->chip_data;
2349 mask_IO_APIC_irq_desc(desc);
2351 if (io_apic_level_ack_pending(cfg)) {
2353 * Interrupt in progress. Migrating irq now will change the
2354 * vector information in the IO-APIC RTE and that will confuse
2355 * the EOI broadcast performed by cpu.
2356 * So, delay the irq migration to the next instance.
2358 schedule_delayed_work(&ir_migration_work, 1);
2362 /* everthing is clear. we have right of way */
2363 migrate_ioapic_irq_desc(desc, desc->pending_mask);
2366 desc->status &= ~IRQ_MOVE_PENDING;
2367 cpus_clear(desc->pending_mask);
2370 unmask_IO_APIC_irq_desc(desc);
2375 static void ir_irq_migration(struct work_struct *work)
2378 struct irq_desc *desc;
2380 for_each_irq_desc(irq, desc) {
2384 if (desc->status & IRQ_MOVE_PENDING) {
2385 unsigned long flags;
2387 spin_lock_irqsave(&desc->lock, flags);
2388 if (!desc->chip->set_affinity ||
2389 !(desc->status & IRQ_MOVE_PENDING)) {
2390 desc->status &= ~IRQ_MOVE_PENDING;
2391 spin_unlock_irqrestore(&desc->lock, flags);
2395 desc->chip->set_affinity(irq, desc->pending_mask);
2396 spin_unlock_irqrestore(&desc->lock, flags);
2402 * Migrates the IRQ destination in the process context.
2404 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask)
2406 if (desc->status & IRQ_LEVEL) {
2407 desc->status |= IRQ_MOVE_PENDING;
2408 desc->pending_mask = mask;
2409 migrate_irq_remapped_level_desc(desc);
2413 migrate_ioapic_irq_desc(desc, mask);
2415 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2417 struct irq_desc *desc = irq_to_desc(irq);
2419 set_ir_ioapic_affinity_irq_desc(desc, mask);
2423 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2425 unsigned vector, me;
2431 me = smp_processor_id();
2432 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2434 struct irq_desc *desc;
2435 struct irq_cfg *cfg;
2436 irq = __get_cpu_var(vector_irq)[vector];
2441 desc = irq_to_desc(irq);
2446 spin_lock(&desc->lock);
2447 if (!cfg->move_cleanup_count)
2450 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2453 __get_cpu_var(vector_irq)[vector] = -1;
2454 cfg->move_cleanup_count--;
2456 spin_unlock(&desc->lock);
2462 static void irq_complete_move(struct irq_desc **descp)
2464 struct irq_desc *desc = *descp;
2465 struct irq_cfg *cfg = desc->chip_data;
2466 unsigned vector, me;
2468 if (likely(!cfg->move_in_progress)) {
2469 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2470 if (likely(!cfg->move_desc_pending))
2473 /* domain has not changed, but affinity did */
2474 me = smp_processor_id();
2475 if (cpu_isset(me, desc->affinity)) {
2476 *descp = desc = move_irq_desc(desc, me);
2477 /* get the new one */
2478 cfg = desc->chip_data;
2479 cfg->move_desc_pending = 0;
2485 vector = ~get_irq_regs()->orig_ax;
2486 me = smp_processor_id();
2487 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2488 cpumask_t cleanup_mask;
2490 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2491 *descp = desc = move_irq_desc(desc, me);
2492 /* get the new one */
2493 cfg = desc->chip_data;
2496 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2497 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2498 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2499 cfg->move_in_progress = 0;
2503 static inline void irq_complete_move(struct irq_desc **descp) {}
2506 #ifdef CONFIG_INTR_REMAP
2507 static void ack_x2apic_level(unsigned int irq)
2512 static void ack_x2apic_edge(unsigned int irq)
2519 static void ack_apic_edge(unsigned int irq)
2521 struct irq_desc *desc = irq_to_desc(irq);
2523 irq_complete_move(&desc);
2524 move_native_irq(irq);
2528 atomic_t irq_mis_count;
2530 static void ack_apic_level(unsigned int irq)
2532 struct irq_desc *desc = irq_to_desc(irq);
2534 #ifdef CONFIG_X86_32
2538 struct irq_cfg *cfg;
2539 int do_unmask_irq = 0;
2541 irq_complete_move(&desc);
2542 #ifdef CONFIG_GENERIC_PENDING_IRQ
2543 /* If we are moving the irq we need to mask it */
2544 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2546 mask_IO_APIC_irq_desc(desc);
2550 #ifdef CONFIG_X86_32
2552 * It appears there is an erratum which affects at least version 0x11
2553 * of I/O APIC (that's the 82093AA and cores integrated into various
2554 * chipsets). Under certain conditions a level-triggered interrupt is
2555 * erroneously delivered as edge-triggered one but the respective IRR
2556 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2557 * message but it will never arrive and further interrupts are blocked
2558 * from the source. The exact reason is so far unknown, but the
2559 * phenomenon was observed when two consecutive interrupt requests
2560 * from a given source get delivered to the same CPU and the source is
2561 * temporarily disabled in between.
2563 * A workaround is to simulate an EOI message manually. We achieve it
2564 * by setting the trigger mode to edge and then to level when the edge
2565 * trigger mode gets detected in the TMR of a local APIC for a
2566 * level-triggered interrupt. We mask the source for the time of the
2567 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2568 * The idea is from Manfred Spraul. --macro
2570 cfg = desc->chip_data;
2573 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2577 * We must acknowledge the irq before we move it or the acknowledge will
2578 * not propagate properly.
2582 /* Now we can move and renable the irq */
2583 if (unlikely(do_unmask_irq)) {
2584 /* Only migrate the irq if the ack has been received.
2586 * On rare occasions the broadcast level triggered ack gets
2587 * delayed going to ioapics, and if we reprogram the
2588 * vector while Remote IRR is still set the irq will never
2591 * To prevent this scenario we read the Remote IRR bit
2592 * of the ioapic. This has two effects.
2593 * - On any sane system the read of the ioapic will
2594 * flush writes (and acks) going to the ioapic from
2596 * - We get to see if the ACK has actually been delivered.
2598 * Based on failed experiments of reprogramming the
2599 * ioapic entry from outside of irq context starting
2600 * with masking the ioapic entry and then polling until
2601 * Remote IRR was clear before reprogramming the
2602 * ioapic I don't trust the Remote IRR bit to be
2603 * completey accurate.
2605 * However there appears to be no other way to plug
2606 * this race, so if the Remote IRR bit is not
2607 * accurate and is causing problems then it is a hardware bug
2608 * and you can go talk to the chipset vendor about it.
2610 cfg = desc->chip_data;
2611 if (!io_apic_level_ack_pending(cfg))
2612 move_masked_irq(irq);
2613 unmask_IO_APIC_irq_desc(desc);
2616 #ifdef CONFIG_X86_32
2617 if (!(v & (1 << (i & 0x1f)))) {
2618 atomic_inc(&irq_mis_count);
2619 spin_lock(&ioapic_lock);
2620 __mask_and_edge_IO_APIC_irq(cfg);
2621 __unmask_and_level_IO_APIC_irq(cfg);
2622 spin_unlock(&ioapic_lock);
2627 static struct irq_chip ioapic_chip __read_mostly = {
2629 .startup = startup_ioapic_irq,
2630 .mask = mask_IO_APIC_irq,
2631 .unmask = unmask_IO_APIC_irq,
2632 .ack = ack_apic_edge,
2633 .eoi = ack_apic_level,
2635 .set_affinity = set_ioapic_affinity_irq,
2637 .retrigger = ioapic_retrigger_irq,
2640 #ifdef CONFIG_INTR_REMAP
2641 static struct irq_chip ir_ioapic_chip __read_mostly = {
2642 .name = "IR-IO-APIC",
2643 .startup = startup_ioapic_irq,
2644 .mask = mask_IO_APIC_irq,
2645 .unmask = unmask_IO_APIC_irq,
2646 .ack = ack_x2apic_edge,
2647 .eoi = ack_x2apic_level,
2649 .set_affinity = set_ir_ioapic_affinity_irq,
2651 .retrigger = ioapic_retrigger_irq,
2655 static inline void init_IO_APIC_traps(void)
2658 struct irq_desc *desc;
2659 struct irq_cfg *cfg;
2662 * NOTE! The local APIC isn't very good at handling
2663 * multiple interrupts at the same interrupt level.
2664 * As the interrupt level is determined by taking the
2665 * vector number and shifting that right by 4, we
2666 * want to spread these out a bit so that they don't
2667 * all fall in the same interrupt level.
2669 * Also, we've got to be careful not to trash gate
2670 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2672 for_each_irq_desc(irq, desc) {
2676 cfg = desc->chip_data;
2677 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2679 * Hmm.. We don't have an entry for this,
2680 * so default to an old-fashioned 8259
2681 * interrupt if we can..
2683 if (irq < NR_IRQS_LEGACY)
2684 make_8259A_irq(irq);
2686 /* Strange. Oh, well.. */
2687 desc->chip = &no_irq_chip;
2693 * The local APIC irq-chip implementation:
2696 static void mask_lapic_irq(unsigned int irq)
2700 v = apic_read(APIC_LVT0);
2701 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2704 static void unmask_lapic_irq(unsigned int irq)
2708 v = apic_read(APIC_LVT0);
2709 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2712 static void ack_lapic_irq(unsigned int irq)
2717 static struct irq_chip lapic_chip __read_mostly = {
2718 .name = "local-APIC",
2719 .mask = mask_lapic_irq,
2720 .unmask = unmask_lapic_irq,
2721 .ack = ack_lapic_irq,
2724 static void lapic_register_intr(int irq, struct irq_desc *desc)
2726 desc->status &= ~IRQ_LEVEL;
2727 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2731 static void __init setup_nmi(void)
2734 * Dirty trick to enable the NMI watchdog ...
2735 * We put the 8259A master into AEOI mode and
2736 * unmask on all local APICs LVT0 as NMI.
2738 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2739 * is from Maciej W. Rozycki - so we do not have to EOI from
2740 * the NMI handler or the timer interrupt.
2742 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2744 enable_NMI_through_LVT0();
2746 apic_printk(APIC_VERBOSE, " done.\n");
2750 * This looks a bit hackish but it's about the only one way of sending
2751 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2752 * not support the ExtINT mode, unfortunately. We need to send these
2753 * cycles as some i82489DX-based boards have glue logic that keeps the
2754 * 8259A interrupt line asserted until INTA. --macro
2756 static inline void __init unlock_ExtINT_logic(void)
2759 struct IO_APIC_route_entry entry0, entry1;
2760 unsigned char save_control, save_freq_select;
2762 pin = find_isa_irq_pin(8, mp_INT);
2767 apic = find_isa_irq_apic(8, mp_INT);
2773 entry0 = ioapic_read_entry(apic, pin);
2774 clear_IO_APIC_pin(apic, pin);
2776 memset(&entry1, 0, sizeof(entry1));
2778 entry1.dest_mode = 0; /* physical delivery */
2779 entry1.mask = 0; /* unmask IRQ now */
2780 entry1.dest = hard_smp_processor_id();
2781 entry1.delivery_mode = dest_ExtINT;
2782 entry1.polarity = entry0.polarity;
2786 ioapic_write_entry(apic, pin, entry1);
2788 save_control = CMOS_READ(RTC_CONTROL);
2789 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2790 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2792 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2797 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2801 CMOS_WRITE(save_control, RTC_CONTROL);
2802 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2803 clear_IO_APIC_pin(apic, pin);
2805 ioapic_write_entry(apic, pin, entry0);
2808 static int disable_timer_pin_1 __initdata;
2809 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2810 static int __init disable_timer_pin_setup(char *arg)
2812 disable_timer_pin_1 = 1;
2815 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2817 int timer_through_8259 __initdata;
2820 * This code may look a bit paranoid, but it's supposed to cooperate with
2821 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2822 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2823 * fanatically on his truly buggy board.
2825 * FIXME: really need to revamp this for all platforms.
2827 static inline void __init check_timer(void)
2829 struct irq_desc *desc = irq_to_desc(0);
2830 struct irq_cfg *cfg = desc->chip_data;
2831 int cpu = boot_cpu_id;
2832 int apic1, pin1, apic2, pin2;
2833 unsigned long flags;
2837 local_irq_save(flags);
2839 ver = apic_read(APIC_LVR);
2840 ver = GET_APIC_VERSION(ver);
2843 * get/set the timer IRQ vector:
2845 disable_8259A_irq(0);
2846 assign_irq_vector(0, cfg, TARGET_CPUS);
2849 * As IRQ0 is to be enabled in the 8259A, the virtual
2850 * wire has to be disabled in the local APIC. Also
2851 * timer interrupts need to be acknowledged manually in
2852 * the 8259A for the i82489DX when using the NMI
2853 * watchdog as that APIC treats NMIs as level-triggered.
2854 * The AEOI mode will finish them in the 8259A
2857 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2859 #ifdef CONFIG_X86_32
2860 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2863 pin1 = find_isa_irq_pin(0, mp_INT);
2864 apic1 = find_isa_irq_apic(0, mp_INT);
2865 pin2 = ioapic_i8259.pin;
2866 apic2 = ioapic_i8259.apic;
2868 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2869 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2870 cfg->vector, apic1, pin1, apic2, pin2);
2873 * Some BIOS writers are clueless and report the ExtINTA
2874 * I/O APIC input from the cascaded 8259A as the timer
2875 * interrupt input. So just in case, if only one pin
2876 * was found above, try it both directly and through the
2880 #ifdef CONFIG_INTR_REMAP
2881 if (intr_remapping_enabled)
2882 panic("BIOS bug: timer not connected to IO-APIC");
2887 } else if (pin2 == -1) {
2894 * Ok, does IRQ0 through the IOAPIC work?
2897 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2898 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2900 unmask_IO_APIC_irq_desc(desc);
2901 if (timer_irq_works()) {
2902 if (nmi_watchdog == NMI_IO_APIC) {
2904 enable_8259A_irq(0);
2906 if (disable_timer_pin_1 > 0)
2907 clear_IO_APIC_pin(0, pin1);
2910 #ifdef CONFIG_INTR_REMAP
2911 if (intr_remapping_enabled)
2912 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2914 clear_IO_APIC_pin(apic1, pin1);
2916 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2917 "8254 timer not connected to IO-APIC\n");
2919 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2920 "(IRQ0) through the 8259A ...\n");
2921 apic_printk(APIC_QUIET, KERN_INFO
2922 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2924 * legacy devices should be connected to IO APIC #0
2926 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2927 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2928 unmask_IO_APIC_irq_desc(desc);
2929 enable_8259A_irq(0);
2930 if (timer_irq_works()) {
2931 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2932 timer_through_8259 = 1;
2933 if (nmi_watchdog == NMI_IO_APIC) {
2934 disable_8259A_irq(0);
2936 enable_8259A_irq(0);
2941 * Cleanup, just in case ...
2943 disable_8259A_irq(0);
2944 clear_IO_APIC_pin(apic2, pin2);
2945 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2948 if (nmi_watchdog == NMI_IO_APIC) {
2949 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2950 "through the IO-APIC - disabling NMI Watchdog!\n");
2951 nmi_watchdog = NMI_NONE;
2953 #ifdef CONFIG_X86_32
2957 apic_printk(APIC_QUIET, KERN_INFO
2958 "...trying to set up timer as Virtual Wire IRQ...\n");
2960 lapic_register_intr(0, desc);
2961 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2962 enable_8259A_irq(0);
2964 if (timer_irq_works()) {
2965 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2968 disable_8259A_irq(0);
2969 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2970 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2972 apic_printk(APIC_QUIET, KERN_INFO
2973 "...trying to set up timer as ExtINT IRQ...\n");
2977 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2979 unlock_ExtINT_logic();
2981 if (timer_irq_works()) {
2982 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2985 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2986 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2987 "report. Then try booting with the 'noapic' option.\n");
2989 local_irq_restore(flags);
2993 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2994 * to devices. However there may be an I/O APIC pin available for
2995 * this interrupt regardless. The pin may be left unconnected, but
2996 * typically it will be reused as an ExtINT cascade interrupt for
2997 * the master 8259A. In the MPS case such a pin will normally be
2998 * reported as an ExtINT interrupt in the MP table. With ACPI
2999 * there is no provision for ExtINT interrupts, and in the absence
3000 * of an override it would be treated as an ordinary ISA I/O APIC
3001 * interrupt, that is edge-triggered and unmasked by default. We
3002 * used to do this, but it caused problems on some systems because
3003 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3004 * the same ExtINT cascade interrupt to drive the local APIC of the
3005 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3006 * the I/O APIC in all cases now. No actual device should request
3007 * it anyway. --macro
3009 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3011 void __init setup_IO_APIC(void)
3014 #ifdef CONFIG_X86_32
3018 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3022 io_apic_irqs = ~PIC_IRQS;
3024 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3026 * Set up IO-APIC IRQ routing.
3028 #ifdef CONFIG_X86_32
3030 setup_ioapic_ids_from_mpc();
3033 setup_IO_APIC_irqs();
3034 init_IO_APIC_traps();
3039 * Called after all the initialization is done. If we didnt find any
3040 * APIC bugs then we can allow the modify fast path
3043 static int __init io_apic_bug_finalize(void)
3045 if (sis_apic_bug == -1)
3050 late_initcall(io_apic_bug_finalize);
3052 struct sysfs_ioapic_data {
3053 struct sys_device dev;
3054 struct IO_APIC_route_entry entry[0];
3056 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3058 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3060 struct IO_APIC_route_entry *entry;
3061 struct sysfs_ioapic_data *data;
3064 data = container_of(dev, struct sysfs_ioapic_data, dev);
3065 entry = data->entry;
3066 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3067 *entry = ioapic_read_entry(dev->id, i);
3072 static int ioapic_resume(struct sys_device *dev)
3074 struct IO_APIC_route_entry *entry;
3075 struct sysfs_ioapic_data *data;
3076 unsigned long flags;
3077 union IO_APIC_reg_00 reg_00;
3080 data = container_of(dev, struct sysfs_ioapic_data, dev);
3081 entry = data->entry;
3083 spin_lock_irqsave(&ioapic_lock, flags);
3084 reg_00.raw = io_apic_read(dev->id, 0);
3085 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
3086 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
3087 io_apic_write(dev->id, 0, reg_00.raw);
3089 spin_unlock_irqrestore(&ioapic_lock, flags);
3090 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3091 ioapic_write_entry(dev->id, i, entry[i]);
3096 static struct sysdev_class ioapic_sysdev_class = {
3098 .suspend = ioapic_suspend,
3099 .resume = ioapic_resume,
3102 static int __init ioapic_init_sysfs(void)
3104 struct sys_device * dev;
3107 error = sysdev_class_register(&ioapic_sysdev_class);
3111 for (i = 0; i < nr_ioapics; i++ ) {
3112 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3113 * sizeof(struct IO_APIC_route_entry);
3114 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3115 if (!mp_ioapic_data[i]) {
3116 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3119 dev = &mp_ioapic_data[i]->dev;
3121 dev->cls = &ioapic_sysdev_class;
3122 error = sysdev_register(dev);
3124 kfree(mp_ioapic_data[i]);
3125 mp_ioapic_data[i] = NULL;
3126 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3134 device_initcall(ioapic_init_sysfs);
3137 * Dynamic irq allocate and deallocation
3139 unsigned int create_irq_nr(unsigned int irq_want)
3141 /* Allocate an unused irq */
3144 unsigned long flags;
3145 struct irq_cfg *cfg_new = NULL;
3146 int cpu = boot_cpu_id;
3147 struct irq_desc *desc_new = NULL;
3150 spin_lock_irqsave(&vector_lock, flags);
3151 for (new = irq_want; new < NR_IRQS; new++) {
3152 if (platform_legacy_irq(new))
3155 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3157 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3160 cfg_new = desc_new->chip_data;
3162 if (cfg_new->vector != 0)
3164 if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0)
3168 spin_unlock_irqrestore(&vector_lock, flags);
3171 dynamic_irq_init(irq);
3172 /* restore it, in case dynamic_irq_init clear it */
3174 desc_new->chip_data = cfg_new;
3179 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3180 int create_irq(void)
3182 unsigned int irq_want;
3185 irq_want = nr_irqs_gsi;
3186 irq = create_irq_nr(irq_want);
3194 void destroy_irq(unsigned int irq)
3196 unsigned long flags;
3197 struct irq_cfg *cfg;
3198 struct irq_desc *desc;
3200 /* store it, in case dynamic_irq_cleanup clear it */
3201 desc = irq_to_desc(irq);
3202 cfg = desc->chip_data;
3203 dynamic_irq_cleanup(irq);
3204 /* connect back irq_cfg */
3206 desc->chip_data = cfg;
3208 #ifdef CONFIG_INTR_REMAP
3211 spin_lock_irqsave(&vector_lock, flags);
3212 __clear_irq_vector(irq, cfg);
3213 spin_unlock_irqrestore(&vector_lock, flags);
3217 * MSI message composition
3219 #ifdef CONFIG_PCI_MSI
3220 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3222 struct irq_cfg *cfg;
3229 err = assign_irq_vector(irq, cfg, tmp);
3233 cpus_and(tmp, cfg->domain, tmp);
3234 dest = cpu_mask_to_apicid(tmp);
3236 #ifdef CONFIG_INTR_REMAP
3237 if (irq_remapped(irq)) {
3242 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3243 BUG_ON(ir_index == -1);
3245 memset (&irte, 0, sizeof(irte));
3248 irte.dst_mode = INT_DEST_MODE;
3249 irte.trigger_mode = 0; /* edge */
3250 irte.dlvry_mode = INT_DELIVERY_MODE;
3251 irte.vector = cfg->vector;
3252 irte.dest_id = IRTE_DEST(dest);
3254 modify_irte(irq, &irte);
3256 msg->address_hi = MSI_ADDR_BASE_HI;
3257 msg->data = sub_handle;
3258 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3260 MSI_ADDR_IR_INDEX1(ir_index) |
3261 MSI_ADDR_IR_INDEX2(ir_index);
3265 msg->address_hi = MSI_ADDR_BASE_HI;
3268 ((INT_DEST_MODE == 0) ?
3269 MSI_ADDR_DEST_MODE_PHYSICAL:
3270 MSI_ADDR_DEST_MODE_LOGICAL) |
3271 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3272 MSI_ADDR_REDIRECTION_CPU:
3273 MSI_ADDR_REDIRECTION_LOWPRI) |
3274 MSI_ADDR_DEST_ID(dest);
3277 MSI_DATA_TRIGGER_EDGE |
3278 MSI_DATA_LEVEL_ASSERT |
3279 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3280 MSI_DATA_DELIVERY_FIXED:
3281 MSI_DATA_DELIVERY_LOWPRI) |
3282 MSI_DATA_VECTOR(cfg->vector);
3288 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3290 struct irq_desc *desc = irq_to_desc(irq);
3291 struct irq_cfg *cfg;
3296 cpus_and(tmp, mask, cpu_online_map);
3297 if (cpus_empty(tmp))
3300 cfg = desc->chip_data;
3301 if (assign_irq_vector(irq, cfg, mask))
3304 set_extra_move_desc(desc, mask);
3306 cpus_and(tmp, cfg->domain, mask);
3307 dest = cpu_mask_to_apicid(tmp);
3309 read_msi_msg_desc(desc, &msg);
3311 msg.data &= ~MSI_DATA_VECTOR_MASK;
3312 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3313 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3314 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3316 write_msi_msg_desc(desc, &msg);
3317 desc->affinity = mask;
3319 #ifdef CONFIG_INTR_REMAP
3321 * Migrate the MSI irq to another cpumask. This migration is
3322 * done in the process context using interrupt-remapping hardware.
3324 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3326 struct irq_desc *desc = irq_to_desc(irq);
3327 struct irq_cfg *cfg;
3329 cpumask_t tmp, cleanup_mask;
3332 cpus_and(tmp, mask, cpu_online_map);
3333 if (cpus_empty(tmp))
3336 if (get_irte(irq, &irte))
3339 cfg = desc->chip_data;
3340 if (assign_irq_vector(irq, cfg, mask))
3343 set_extra_move_desc(desc, mask);
3345 cpus_and(tmp, cfg->domain, mask);
3346 dest = cpu_mask_to_apicid(tmp);
3348 irte.vector = cfg->vector;
3349 irte.dest_id = IRTE_DEST(dest);
3352 * atomically update the IRTE with the new destination and vector.
3354 modify_irte(irq, &irte);
3357 * After this point, all the interrupts will start arriving
3358 * at the new destination. So, time to cleanup the previous
3359 * vector allocation.
3361 if (cfg->move_in_progress) {
3362 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3363 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3364 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3365 cfg->move_in_progress = 0;
3368 desc->affinity = mask;
3372 #endif /* CONFIG_SMP */
3375 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3376 * which implement the MSI or MSI-X Capability Structure.
3378 static struct irq_chip msi_chip = {
3380 .unmask = unmask_msi_irq,
3381 .mask = mask_msi_irq,
3382 .ack = ack_apic_edge,
3384 .set_affinity = set_msi_irq_affinity,
3386 .retrigger = ioapic_retrigger_irq,
3389 #ifdef CONFIG_INTR_REMAP
3390 static struct irq_chip msi_ir_chip = {
3391 .name = "IR-PCI-MSI",
3392 .unmask = unmask_msi_irq,
3393 .mask = mask_msi_irq,
3394 .ack = ack_x2apic_edge,
3396 .set_affinity = ir_set_msi_irq_affinity,
3398 .retrigger = ioapic_retrigger_irq,
3402 * Map the PCI dev to the corresponding remapping hardware unit
3403 * and allocate 'nvec' consecutive interrupt-remapping table entries
3406 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3408 struct intel_iommu *iommu;
3411 iommu = map_dev_to_ir(dev);
3414 "Unable to map PCI %s to iommu\n", pci_name(dev));
3418 index = alloc_irte(iommu, irq, nvec);
3421 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3429 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3434 ret = msi_compose_msg(dev, irq, &msg);
3438 set_irq_msi(irq, msidesc);
3439 write_msi_msg(irq, &msg);
3441 #ifdef CONFIG_INTR_REMAP
3442 if (irq_remapped(irq)) {
3443 struct irq_desc *desc = irq_to_desc(irq);
3445 * irq migration in process context
3447 desc->status |= IRQ_MOVE_PCNTXT;
3448 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3451 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3453 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3458 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc)
3462 unsigned int irq_want;
3464 irq_want = nr_irqs_gsi;
3465 irq = create_irq_nr(irq_want);
3469 #ifdef CONFIG_INTR_REMAP
3470 if (!intr_remapping_enabled)
3473 ret = msi_alloc_irte(dev, irq, 1);
3478 ret = setup_msi_irq(dev, msidesc, irq);
3485 #ifdef CONFIG_INTR_REMAP
3492 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3495 int ret, sub_handle;
3496 struct msi_desc *msidesc;
3497 unsigned int irq_want;
3499 #ifdef CONFIG_INTR_REMAP
3500 struct intel_iommu *iommu = 0;
3504 irq_want = nr_irqs_gsi;
3506 list_for_each_entry(msidesc, &dev->msi_list, list) {
3507 irq = create_irq_nr(irq_want);
3511 #ifdef CONFIG_INTR_REMAP
3512 if (!intr_remapping_enabled)
3517 * allocate the consecutive block of IRTE's
3520 index = msi_alloc_irte(dev, irq, nvec);
3526 iommu = map_dev_to_ir(dev);
3532 * setup the mapping between the irq and the IRTE
3533 * base index, the sub_handle pointing to the
3534 * appropriate interrupt remap table entry.
3536 set_irte_irq(irq, iommu, index, sub_handle);
3540 ret = setup_msi_irq(dev, msidesc, irq);
3552 void arch_teardown_msi_irq(unsigned int irq)
3559 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3561 struct irq_desc *desc = irq_to_desc(irq);
3562 struct irq_cfg *cfg;
3567 cpus_and(tmp, mask, cpu_online_map);
3568 if (cpus_empty(tmp))
3571 cfg = desc->chip_data;
3572 if (assign_irq_vector(irq, cfg, mask))
3575 set_extra_move_desc(desc, mask);
3577 cpus_and(tmp, cfg->domain, mask);
3578 dest = cpu_mask_to_apicid(tmp);
3580 dmar_msi_read(irq, &msg);
3582 msg.data &= ~MSI_DATA_VECTOR_MASK;
3583 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3584 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3585 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3587 dmar_msi_write(irq, &msg);
3588 desc->affinity = mask;
3591 #endif /* CONFIG_SMP */
3593 struct irq_chip dmar_msi_type = {
3595 .unmask = dmar_msi_unmask,
3596 .mask = dmar_msi_mask,
3597 .ack = ack_apic_edge,
3599 .set_affinity = dmar_msi_set_affinity,
3601 .retrigger = ioapic_retrigger_irq,
3604 int arch_setup_dmar_msi(unsigned int irq)
3609 ret = msi_compose_msg(NULL, irq, &msg);
3612 dmar_msi_write(irq, &msg);
3613 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3619 #ifdef CONFIG_HPET_TIMER
3622 static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask)
3624 struct irq_desc *desc = irq_to_desc(irq);
3625 struct irq_cfg *cfg;
3630 cpus_and(tmp, mask, cpu_online_map);
3631 if (cpus_empty(tmp))
3634 cfg = desc->chip_data;
3635 if (assign_irq_vector(irq, cfg, mask))
3638 set_extra_move_desc(desc, mask);
3640 cpus_and(tmp, cfg->domain, mask);
3641 dest = cpu_mask_to_apicid(tmp);
3643 hpet_msi_read(irq, &msg);
3645 msg.data &= ~MSI_DATA_VECTOR_MASK;
3646 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3647 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3648 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3650 hpet_msi_write(irq, &msg);
3651 desc->affinity = mask;
3654 #endif /* CONFIG_SMP */
3656 struct irq_chip hpet_msi_type = {
3658 .unmask = hpet_msi_unmask,
3659 .mask = hpet_msi_mask,
3660 .ack = ack_apic_edge,
3662 .set_affinity = hpet_msi_set_affinity,
3664 .retrigger = ioapic_retrigger_irq,
3667 int arch_setup_hpet_msi(unsigned int irq)
3672 ret = msi_compose_msg(NULL, irq, &msg);
3676 hpet_msi_write(irq, &msg);
3677 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3684 #endif /* CONFIG_PCI_MSI */
3686 * Hypertransport interrupt support
3688 #ifdef CONFIG_HT_IRQ
3692 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3694 struct ht_irq_msg msg;
3695 fetch_ht_irq_msg(irq, &msg);
3697 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3698 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3700 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3701 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3703 write_ht_irq_msg(irq, &msg);
3706 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3708 struct irq_desc *desc = irq_to_desc(irq);
3709 struct irq_cfg *cfg;
3713 cpus_and(tmp, mask, cpu_online_map);
3714 if (cpus_empty(tmp))
3717 cfg = desc->chip_data;
3718 if (assign_irq_vector(irq, cfg, mask))
3721 set_extra_move_desc(desc, mask);
3723 cpus_and(tmp, cfg->domain, mask);
3724 dest = cpu_mask_to_apicid(tmp);
3726 target_ht_irq(irq, dest, cfg->vector);
3727 desc->affinity = mask;
3732 static struct irq_chip ht_irq_chip = {
3734 .mask = mask_ht_irq,
3735 .unmask = unmask_ht_irq,
3736 .ack = ack_apic_edge,
3738 .set_affinity = set_ht_irq_affinity,
3740 .retrigger = ioapic_retrigger_irq,
3743 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3745 struct irq_cfg *cfg;
3751 err = assign_irq_vector(irq, cfg, tmp);
3753 struct ht_irq_msg msg;
3756 cpus_and(tmp, cfg->domain, tmp);
3757 dest = cpu_mask_to_apicid(tmp);
3759 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3763 HT_IRQ_LOW_DEST_ID(dest) |
3764 HT_IRQ_LOW_VECTOR(cfg->vector) |
3765 ((INT_DEST_MODE == 0) ?
3766 HT_IRQ_LOW_DM_PHYSICAL :
3767 HT_IRQ_LOW_DM_LOGICAL) |
3768 HT_IRQ_LOW_RQEOI_EDGE |
3769 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3770 HT_IRQ_LOW_MT_FIXED :
3771 HT_IRQ_LOW_MT_ARBITRATED) |
3772 HT_IRQ_LOW_IRQ_MASKED;
3774 write_ht_irq_msg(irq, &msg);
3776 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3777 handle_edge_irq, "edge");
3779 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3783 #endif /* CONFIG_HT_IRQ */
3785 #ifdef CONFIG_X86_64
3787 * Re-target the irq to the specified CPU and enable the specified MMR located
3788 * on the specified blade to allow the sending of MSIs to the specified CPU.
3790 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3791 unsigned long mmr_offset)
3793 const cpumask_t *eligible_cpu = get_cpu_mask(cpu);
3794 struct irq_cfg *cfg;
3796 unsigned long mmr_value;
3797 struct uv_IO_APIC_route_entry *entry;
3798 unsigned long flags;
3803 err = assign_irq_vector(irq, cfg, *eligible_cpu);
3807 spin_lock_irqsave(&vector_lock, flags);
3808 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3810 spin_unlock_irqrestore(&vector_lock, flags);
3813 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3814 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3816 entry->vector = cfg->vector;
3817 entry->delivery_mode = INT_DELIVERY_MODE;
3818 entry->dest_mode = INT_DEST_MODE;
3819 entry->polarity = 0;
3822 entry->dest = cpu_mask_to_apicid(*eligible_cpu);
3824 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3825 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3831 * Disable the specified MMR located on the specified blade so that MSIs are
3832 * longer allowed to be sent.
3834 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3836 unsigned long mmr_value;
3837 struct uv_IO_APIC_route_entry *entry;
3841 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3842 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3846 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3847 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3849 #endif /* CONFIG_X86_64 */
3851 int __init io_apic_get_redir_entries (int ioapic)
3853 union IO_APIC_reg_01 reg_01;
3854 unsigned long flags;
3856 spin_lock_irqsave(&ioapic_lock, flags);
3857 reg_01.raw = io_apic_read(ioapic, 1);
3858 spin_unlock_irqrestore(&ioapic_lock, flags);
3860 return reg_01.bits.entries;
3863 void __init probe_nr_irqs_gsi(void)
3868 for (idx = 0; idx < nr_ioapics; idx++)
3869 nr += io_apic_get_redir_entries(idx) + 1;
3871 if (nr > nr_irqs_gsi)
3875 /* --------------------------------------------------------------------------
3876 ACPI-based IOAPIC Configuration
3877 -------------------------------------------------------------------------- */
3881 #ifdef CONFIG_X86_32
3882 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3884 union IO_APIC_reg_00 reg_00;
3885 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3887 unsigned long flags;
3891 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3892 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3893 * supports up to 16 on one shared APIC bus.
3895 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3896 * advantage of new APIC bus architecture.
3899 if (physids_empty(apic_id_map))
3900 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3902 spin_lock_irqsave(&ioapic_lock, flags);
3903 reg_00.raw = io_apic_read(ioapic, 0);
3904 spin_unlock_irqrestore(&ioapic_lock, flags);
3906 if (apic_id >= get_physical_broadcast()) {
3907 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3908 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3909 apic_id = reg_00.bits.ID;
3913 * Every APIC in a system must have a unique ID or we get lots of nice
3914 * 'stuck on smp_invalidate_needed IPI wait' messages.
3916 if (check_apicid_used(apic_id_map, apic_id)) {
3918 for (i = 0; i < get_physical_broadcast(); i++) {
3919 if (!check_apicid_used(apic_id_map, i))
3923 if (i == get_physical_broadcast())
3924 panic("Max apic_id exceeded!\n");
3926 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3927 "trying %d\n", ioapic, apic_id, i);
3932 tmp = apicid_to_cpu_present(apic_id);
3933 physids_or(apic_id_map, apic_id_map, tmp);
3935 if (reg_00.bits.ID != apic_id) {
3936 reg_00.bits.ID = apic_id;
3938 spin_lock_irqsave(&ioapic_lock, flags);
3939 io_apic_write(ioapic, 0, reg_00.raw);
3940 reg_00.raw = io_apic_read(ioapic, 0);
3941 spin_unlock_irqrestore(&ioapic_lock, flags);
3944 if (reg_00.bits.ID != apic_id) {
3945 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3950 apic_printk(APIC_VERBOSE, KERN_INFO
3951 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3956 int __init io_apic_get_version(int ioapic)
3958 union IO_APIC_reg_01 reg_01;
3959 unsigned long flags;
3961 spin_lock_irqsave(&ioapic_lock, flags);
3962 reg_01.raw = io_apic_read(ioapic, 1);
3963 spin_unlock_irqrestore(&ioapic_lock, flags);
3965 return reg_01.bits.version;
3969 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3971 struct irq_desc *desc;
3972 struct irq_cfg *cfg;
3973 int cpu = boot_cpu_id;
3975 if (!IO_APIC_IRQ(irq)) {
3976 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3981 desc = irq_to_desc_alloc_cpu(irq, cpu);
3983 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3988 * IRQs < 16 are already in the irq_2_pin[] map
3990 if (irq >= NR_IRQS_LEGACY) {
3991 cfg = desc->chip_data;
3992 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3995 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
4001 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4005 if (skip_ioapic_setup)
4008 for (i = 0; i < mp_irq_entries; i++)
4009 if (mp_irqs[i].mp_irqtype == mp_INT &&
4010 mp_irqs[i].mp_srcbusirq == bus_irq)
4012 if (i >= mp_irq_entries)
4015 *trigger = irq_trigger(i);
4016 *polarity = irq_polarity(i);
4020 #endif /* CONFIG_ACPI */
4023 * This function currently is only a helper for the i386 smp boot process where
4024 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4025 * so mask in all cases should simply be TARGET_CPUS
4028 void __init setup_ioapic_dest(void)
4030 int pin, ioapic, irq, irq_entry;
4031 struct irq_desc *desc;
4032 struct irq_cfg *cfg;
4035 if (skip_ioapic_setup == 1)
4038 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4039 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4040 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4041 if (irq_entry == -1)
4043 irq = pin_2_irq(irq_entry, ioapic, pin);
4045 /* setup_IO_APIC_irqs could fail to get vector for some device
4046 * when you have too many devices, because at that time only boot
4049 desc = irq_to_desc(irq);
4050 cfg = desc->chip_data;
4052 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4053 irq_trigger(irq_entry),
4054 irq_polarity(irq_entry));
4060 * Honour affinities which have been set in early boot
4063 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4064 mask = desc->affinity;
4068 #ifdef CONFIG_INTR_REMAP
4069 if (intr_remapping_enabled)
4070 set_ir_ioapic_affinity_irq_desc(desc, mask);
4073 set_ioapic_affinity_irq_desc(desc, mask);
4080 #define IOAPIC_RESOURCE_NAME_SIZE 11
4082 static struct resource *ioapic_resources;
4084 static struct resource * __init ioapic_setup_resources(void)
4087 struct resource *res;
4091 if (nr_ioapics <= 0)
4094 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4097 mem = alloc_bootmem(n);
4101 mem += sizeof(struct resource) * nr_ioapics;
4103 for (i = 0; i < nr_ioapics; i++) {
4105 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4106 sprintf(mem, "IOAPIC %u", i);
4107 mem += IOAPIC_RESOURCE_NAME_SIZE;
4111 ioapic_resources = res;
4116 void __init ioapic_init_mappings(void)
4118 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4119 struct resource *ioapic_res;
4122 ioapic_res = ioapic_setup_resources();
4123 for (i = 0; i < nr_ioapics; i++) {
4124 if (smp_found_config) {
4125 ioapic_phys = mp_ioapics[i].mp_apicaddr;
4126 #ifdef CONFIG_X86_32
4129 "WARNING: bogus zero IO-APIC "
4130 "address found in MPTABLE, "
4131 "disabling IO/APIC support!\n");
4132 smp_found_config = 0;
4133 skip_ioapic_setup = 1;
4134 goto fake_ioapic_page;
4138 #ifdef CONFIG_X86_32
4141 ioapic_phys = (unsigned long)
4142 alloc_bootmem_pages(PAGE_SIZE);
4143 ioapic_phys = __pa(ioapic_phys);
4145 set_fixmap_nocache(idx, ioapic_phys);
4146 apic_printk(APIC_VERBOSE,
4147 "mapped IOAPIC to %08lx (%08lx)\n",
4148 __fix_to_virt(idx), ioapic_phys);
4151 if (ioapic_res != NULL) {
4152 ioapic_res->start = ioapic_phys;
4153 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4159 static int __init ioapic_insert_resources(void)
4162 struct resource *r = ioapic_resources;
4166 "IO APIC resources could be not be allocated.\n");
4170 for (i = 0; i < nr_ioapics; i++) {
4171 insert_resource(&iomem_resource, r);
4178 /* Insert the IO APIC resources after PCI initialization has occured to handle
4179 * IO APICS that are mapped in on a BAR in PCI space. */
4180 late_initcall(ioapic_insert_resources);