arch/x86/kernel/irq.c

   1 /*
   2  * Common interrupt code for 32 and 64 bit
   3  */
   4 #include <linux/cpu.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel_stat.h>
   7 #include <linux/of.h>
   8 #include <linux/seq_file.h>
   9 #include <linux/smp.h>
  10 #include <linux/ftrace.h>
  11 #include <linux/delay.h>
  12 #include <linux/export.h>
  13
  14 #include <asm/apic.h>
  15 #include <asm/io_apic.h>
  16 #include <asm/irq.h>
  17 #include <asm/idle.h>
  18 #include <asm/mce.h>
  19 #include <asm/hw_irq.h>
  20 #include <asm/desc.h>
  21
  22 #define CREATE_TRACE_POINTS
  23 #include <asm/trace/irq_vectors.h>
  24
  25 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
  26 EXPORT_PER_CPU_SYMBOL(irq_stat);
  27
  28 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
  29 EXPORT_PER_CPU_SYMBOL(irq_regs);
  30
  31 atomic_t irq_err_count;
  32
  33 /* Function pointer for generic interrupt vector handling */
  34 void (*x86_platform_ipi_callback)(void) = NULL;
  35
  36 /*
  37  * 'what should we do if we get a hw irq event on an illegal vector'.
  38  * each architecture has to answer this themselves.
  39  */
  40 void ack_bad_irq(unsigned int irq)
  41 {
  42         if (printk_ratelimit())
  43                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
  44
  45         /*
  46          * Currently unexpected vectors happen only on SMP and APIC.
  47          * We _must_ ack these because every local APIC has only N
  48          * irq slots per priority level, and a 'hanging, unacked' IRQ
  49          * holds up an irq slot - in excessive cases (when multiple
  50          * unexpected vectors occur) that might lock up the APIC
  51          * completely.
  52          * But only ack when the APIC is enabled -AK
  53          */
  54         ack_APIC_irq();
  55 }
  56
  57 #define irq_stats(x)            (&per_cpu(irq_stat, x))
  58 /*
  59  * /proc/interrupts printing for arch specific interrupts
  60  */
  61 int arch_show_interrupts(struct seq_file *p, int prec)
  62 {
  63         int j;
  64
  65         seq_printf(p, "%*s: ", prec, "NMI");
  66         for_each_online_cpu(j)
  67                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
  68         seq_puts(p, "  Non-maskable interrupts\n");
  69 #ifdef CONFIG_X86_LOCAL_APIC
  70         seq_printf(p, "%*s: ", prec, "LOC");
  71         for_each_online_cpu(j)
  72                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
  73         seq_puts(p, "  Local timer interrupts\n");
  74
  75         seq_printf(p, "%*s: ", prec, "SPU");
  76         for_each_online_cpu(j)
  77                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
  78         seq_puts(p, "  Spurious interrupts\n");
  79         seq_printf(p, "%*s: ", prec, "PMI");
  80         for_each_online_cpu(j)
  81                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
  82         seq_puts(p, "  Performance monitoring interrupts\n");
  83         seq_printf(p, "%*s: ", prec, "IWI");
  84         for_each_online_cpu(j)
  85                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
  86         seq_puts(p, "  IRQ work interrupts\n");
  87         seq_printf(p, "%*s: ", prec, "RTR");
  88         for_each_online_cpu(j)
  89                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
  90         seq_puts(p, "  APIC ICR read retries\n");
  91 #endif
  92         if (x86_platform_ipi_callback) {
  93                 seq_printf(p, "%*s: ", prec, "PLT");
  94                 for_each_online_cpu(j)
  95                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
  96                 seq_puts(p, "  Platform interrupts\n");
  97         }
  98 #ifdef CONFIG_SMP
  99         seq_printf(p, "%*s: ", prec, "RES");
 100         for_each_online_cpu(j)
 101                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
 102         seq_puts(p, "  Rescheduling interrupts\n");
 103         seq_printf(p, "%*s: ", prec, "CAL");
 104         for_each_online_cpu(j)
 105                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
 106                                         irq_stats(j)->irq_tlb_count);
 107         seq_puts(p, "  Function call interrupts\n");
 108         seq_printf(p, "%*s: ", prec, "TLB");
 109         for_each_online_cpu(j)
 110                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
 111         seq_puts(p, "  TLB shootdowns\n");
 112 #endif
 113 #ifdef CONFIG_X86_THERMAL_VECTOR
 114         seq_printf(p, "%*s: ", prec, "TRM");
 115         for_each_online_cpu(j)
 116                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
 117         seq_puts(p, "  Thermal event interrupts\n");
 118 #endif
 119 #ifdef CONFIG_X86_MCE_THRESHOLD
 120         seq_printf(p, "%*s: ", prec, "THR");
 121         for_each_online_cpu(j)
 122                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
 123         seq_puts(p, "  Threshold APIC interrupts\n");
 124 #endif
 125 #ifdef CONFIG_X86_MCE_AMD
 126         seq_printf(p, "%*s: ", prec, "DFR");
 127         for_each_online_cpu(j)
 128                 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
 129         seq_puts(p, "  Deferred Error APIC interrupts\n");
 130 #endif
 131 #ifdef CONFIG_X86_MCE
 132         seq_printf(p, "%*s: ", prec, "MCE");
 133         for_each_online_cpu(j)
 134                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
 135         seq_puts(p, "  Machine check exceptions\n");
 136         seq_printf(p, "%*s: ", prec, "MCP");
 137         for_each_online_cpu(j)
 138                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
 139         seq_puts(p, "  Machine check polls\n");
 140 #endif
 141 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
 142         seq_printf(p, "%*s: ", prec, "HYP");
 143         for_each_online_cpu(j)
 144                 seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
 145         seq_puts(p, "  Hypervisor callback interrupts\n");
 146 #endif
 147         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
 148 #if defined(CONFIG_X86_IO_APIC)
 149         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
 150 #endif
 151 #ifdef CONFIG_HAVE_KVM
 152         seq_printf(p, "%*s: ", prec, "PIN");
 153         for_each_online_cpu(j)
 154                 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
 155         seq_puts(p, "  Posted-interrupt notification event\n");
 156
 157         seq_printf(p, "%*s: ", prec, "PIW");
 158         for_each_online_cpu(j)
 159                 seq_printf(p, "%10u ",
 160                            irq_stats(j)->kvm_posted_intr_wakeup_ipis);
 161         seq_puts(p, "  Posted-interrupt wakeup event\n");
 162 #endif
 163         return 0;
 164 }
 165
 166 /*
 167  * /proc/stat helpers
 168  */
 169 u64 arch_irq_stat_cpu(unsigned int cpu)
 170 {
 171         u64 sum = irq_stats(cpu)->__nmi_count;
 172
 173 #ifdef CONFIG_X86_LOCAL_APIC
 174         sum += irq_stats(cpu)->apic_timer_irqs;
 175         sum += irq_stats(cpu)->irq_spurious_count;
 176         sum += irq_stats(cpu)->apic_perf_irqs;
 177         sum += irq_stats(cpu)->apic_irq_work_irqs;
 178         sum += irq_stats(cpu)->icr_read_retry_count;
 179 #endif
 180         if (x86_platform_ipi_callback)
 181                 sum += irq_stats(cpu)->x86_platform_ipis;
 182 #ifdef CONFIG_SMP
 183         sum += irq_stats(cpu)->irq_resched_count;
 184         sum += irq_stats(cpu)->irq_call_count;
 185 #endif
 186 #ifdef CONFIG_X86_THERMAL_VECTOR
 187         sum += irq_stats(cpu)->irq_thermal_count;
 188 #endif
 189 #ifdef CONFIG_X86_MCE_THRESHOLD
 190         sum += irq_stats(cpu)->irq_threshold_count;
 191 #endif
 192 #ifdef CONFIG_X86_MCE
 193         sum += per_cpu(mce_exception_count, cpu);
 194         sum += per_cpu(mce_poll_count, cpu);
 195 #endif
 196         return sum;
 197 }
 198
 199 u64 arch_irq_stat(void)
 200 {
 201         u64 sum = atomic_read(&irq_err_count);
 202         return sum;
 203 }
 204
 205
 206 /*
 207  * do_IRQ handles all normal device IRQ's (the special
 208  * SMP cross-CPU interrupts have their own specific
 209  * handlers).
 210  */
 211 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
 212 {
 213         struct pt_regs *old_regs = set_irq_regs(regs);
 214
 215         /* high bit used in ret_from_ code  */
 216         unsigned vector = ~regs->orig_ax;
 217         unsigned irq;
 218
 219         /*
 220          * NB: Unlike exception entries, IRQ entries do not reliably
 221          * handle context tracking in the low-level entry code.  This is
 222          * because syscall entries execute briefly with IRQs on before
 223          * updating context tracking state, so we can take an IRQ from
 224          * kernel mode with CONTEXT_USER.  The low-level entry code only
 225          * updates the context if we came from user mode, so we won't
 226          * switch to CONTEXT_KERNEL.  We'll fix that once the syscall
 227          * code is cleaned up enough that we can cleanly defer enabling
 228          * IRQs.
 229          */
 230
 231         entering_irq();
 232
 233         /* entering_irq() tells RCU that we're not quiescent.  Check it. */
 234         RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
 235
 236         irq = __this_cpu_read(vector_irq[vector]);
 237
 238         if (!handle_irq(irq, regs)) {
 239                 ack_APIC_irq();
 240
 241                 if (irq != VECTOR_RETRIGGERED) {
 242                         pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n",
 243                                              __func__, smp_processor_id(),
 244                                              vector, irq);
 245                 } else {
 246                         __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
 247                 }
 248         }
 249
 250         exiting_irq();
 251
 252         set_irq_regs(old_regs);
 253         return 1;
 254 }
 255
 256 /*
 257  * Handler for X86_PLATFORM_IPI_VECTOR.
 258  */
 259 void __smp_x86_platform_ipi(void)
 260 {
 261         inc_irq_stat(x86_platform_ipis);
 262
 263         if (x86_platform_ipi_callback)
 264                 x86_platform_ipi_callback();
 265 }
 266
 267 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
 268 {
 269         struct pt_regs *old_regs = set_irq_regs(regs);
 270
 271         entering_ack_irq();
 272         __smp_x86_platform_ipi();
 273         exiting_irq();
 274         set_irq_regs(old_regs);
 275 }
 276
 277 #ifdef CONFIG_HAVE_KVM
 278 static void dummy_handler(void) {}
 279 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
 280
 281 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
 282 {
 283         if (handler)
 284                 kvm_posted_intr_wakeup_handler = handler;
 285         else
 286                 kvm_posted_intr_wakeup_handler = dummy_handler;
 287 }
 288 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
 289
 290 /*
 291  * Handler for POSTED_INTERRUPT_VECTOR.
 292  */
 293 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
 294 {
 295         struct pt_regs *old_regs = set_irq_regs(regs);
 296
 297         entering_ack_irq();
 298         inc_irq_stat(kvm_posted_intr_ipis);
 299         exiting_irq();
 300         set_irq_regs(old_regs);
 301 }
 302
 303 /*
 304  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
 305  */
 306 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
 307 {
 308         struct pt_regs *old_regs = set_irq_regs(regs);
 309
 310         entering_ack_irq();
 311         inc_irq_stat(kvm_posted_intr_wakeup_ipis);
 312         kvm_posted_intr_wakeup_handler();
 313         exiting_irq();
 314         set_irq_regs(old_regs);
 315 }
 316 #endif
 317
 318 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
 319 {
 320         struct pt_regs *old_regs = set_irq_regs(regs);
 321
 322         entering_ack_irq();
 323         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
 324         __smp_x86_platform_ipi();
 325         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
 326         exiting_irq();
 327         set_irq_regs(old_regs);
 328 }
 329
 330 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 331
 332 #ifdef CONFIG_HOTPLUG_CPU
 333
 334 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
 335  * below, which is protected by stop_machine().  Putting them on the stack
 336  * results in a stack frame overflow.  Dynamically allocating could result in a
 337  * failure so declare these two cpumasks as global.
 338  */
 339 static struct cpumask affinity_new, online_new;
 340
 341 /*
 342  * This cpu is going to be removed and its vectors migrated to the remaining
 343  * online cpus.  Check to see if there are enough vectors in the remaining cpus.
 344  * This function is protected by stop_machine().
 345  */
 346 int check_irq_vectors_for_cpu_disable(void)
 347 {
 348         int irq, cpu;
 349         unsigned int this_cpu, vector, this_count, count;
 350         struct irq_desc *desc;
 351         struct irq_data *data;
 352
 353         this_cpu = smp_processor_id();
 354         cpumask_copy(&online_new, cpu_online_mask);
 355         cpumask_clear_cpu(this_cpu, &online_new);
 356
 357         this_count = 0;
 358         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 359                 irq = __this_cpu_read(vector_irq[vector]);
 360                 if (irq >= 0) {
 361                         desc = irq_to_desc(irq);
 362                         if (!desc)
 363                                 continue;
 364
 365                         /*
 366                          * Protect against concurrent action removal,
 367                          * affinity changes etc.
 368                          */
 369                         raw_spin_lock(&desc->lock);
 370                         data = irq_desc_get_irq_data(desc);
 371                         cpumask_copy(&affinity_new, data->affinity);
 372                         cpumask_clear_cpu(this_cpu, &affinity_new);
 373
 374                         /* Do not count inactive or per-cpu irqs. */
 375                         if (!irq_has_action(irq) || irqd_is_per_cpu(data)) {
 376                                 raw_spin_unlock(&desc->lock);
 377                                 continue;
 378                         }
 379
 380                         raw_spin_unlock(&desc->lock);
 381                         /*
 382                          * A single irq may be mapped to multiple
 383                          * cpu's vector_irq[] (for example IOAPIC cluster
 384                          * mode).  In this case we have two
 385                          * possibilities:
 386                          *
 387                          * 1) the resulting affinity mask is empty; that is
 388                          * this the down'd cpu is the last cpu in the irq's
 389                          * affinity mask, or
 390                          *
 391                          * 2) the resulting affinity mask is no longer
 392                          * a subset of the online cpus but the affinity
 393                          * mask is not zero; that is the down'd cpu is the
 394                          * last online cpu in a user set affinity mask.
 395                          */
 396                         if (cpumask_empty(&affinity_new) ||
 397                             !cpumask_subset(&affinity_new, &online_new))
 398                                 this_count++;
 399                 }
 400         }
 401
 402         count = 0;
 403         for_each_online_cpu(cpu) {
 404                 if (cpu == this_cpu)
 405                         continue;
 406                 /*
 407                  * We scan from FIRST_EXTERNAL_VECTOR to first system
 408                  * vector. If the vector is marked in the used vectors
 409                  * bitmap or an irq is assigned to it, we don't count
 410                  * it as available.
 411                  *
 412                  * As this is an inaccurate snapshot anyway, we can do
 413                  * this w/o holding vector_lock.
 414                  */
 415                 for (vector = FIRST_EXTERNAL_VECTOR;
 416                      vector < first_system_vector; vector++) {
 417                         if (!test_bit(vector, used_vectors) &&
 418                             per_cpu(vector_irq, cpu)[vector] < 0)
 419                                         count++;
 420                 }
 421         }
 422
 423         if (count < this_count) {
 424                 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
 425                         this_cpu, this_count, count);
 426                 return -ERANGE;
 427         }
 428         return 0;
 429 }
 430
 431 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
 432 void fixup_irqs(void)
 433 {
 434         unsigned int irq, vector;
 435         static int warned;
 436         struct irq_desc *desc;
 437         struct irq_data *data;
 438         struct irq_chip *chip;
 439         int ret;
 440
 441         for_each_irq_desc(irq, desc) {
 442                 int break_affinity = 0;
 443                 int set_affinity = 1;
 444                 const struct cpumask *affinity;
 445
 446                 if (!desc)
 447                         continue;
 448                 if (irq == 2)
 449                         continue;
 450
 451                 /* interrupt's are disabled at this point */
 452                 raw_spin_lock(&desc->lock);
 453
 454                 data = irq_desc_get_irq_data(desc);
 455                 affinity = data->affinity;
 456                 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
 457                     cpumask_subset(affinity, cpu_online_mask)) {
 458                         raw_spin_unlock(&desc->lock);
 459                         continue;
 460                 }
 461
 462                 /*
 463                  * Complete the irq move. This cpu is going down and for
 464                  * non intr-remapping case, we can't wait till this interrupt
 465                  * arrives at this cpu before completing the irq move.
 466                  */
 467                 irq_force_complete_move(irq);
 468
 469                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
 470                         break_affinity = 1;
 471                         affinity = cpu_online_mask;
 472                 }
 473
 474                 chip = irq_data_get_irq_chip(data);
 475                 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
 476                         chip->irq_mask(data);
 477
 478                 if (chip->irq_set_affinity) {
 479                         ret = chip->irq_set_affinity(data, affinity, true);
 480                         if (ret == -ENOSPC)
 481                                 pr_crit("IRQ %d set affinity failed because there are no available vectors.  The device assigned to this IRQ is unstable.\n", irq);
 482                 } else {
 483                         if (!(warned++))
 484                                 set_affinity = 0;
 485                 }
 486
 487                 /*
 488                  * We unmask if the irq was not marked masked by the
 489                  * core code. That respects the lazy irq disable
 490                  * behaviour.
 491                  */
 492                 if (!irqd_can_move_in_process_context(data) &&
 493                     !irqd_irq_masked(data) && chip->irq_unmask)
 494                         chip->irq_unmask(data);
 495
 496                 raw_spin_unlock(&desc->lock);
 497
 498                 if (break_affinity && set_affinity)
 499                         pr_notice("Broke affinity for irq %i\n", irq);
 500                 else if (!set_affinity)
 501                         pr_notice("Cannot set affinity for irq %i\n", irq);
 502         }
 503
 504         /*
 505          * We can remove mdelay() and then send spuriuous interrupts to
 506          * new cpu targets for all the irqs that were handled previously by
 507          * this cpu. While it works, I have seen spurious interrupt messages
 508          * (nothing wrong but still...).
 509          *
 510          * So for now, retain mdelay(1) and check the IRR and then send those
 511          * interrupts to new targets as this cpu is already offlined...
 512          */
 513         mdelay(1);
 514
 515         /*
 516          * We can walk the vector array of this cpu without holding
 517          * vector_lock because the cpu is already marked !online, so
 518          * nothing else will touch it.
 519          */
 520         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 521                 unsigned int irr;
 522
 523                 if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNDEFINED)
 524                         continue;
 525
 526                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
 527                 if (irr  & (1 << (vector % 32))) {
 528                         irq = __this_cpu_read(vector_irq[vector]);
 529
 530                         desc = irq_to_desc(irq);
 531                         raw_spin_lock(&desc->lock);
 532                         data = irq_desc_get_irq_data(desc);
 533                         chip = irq_data_get_irq_chip(data);
 534                         if (chip->irq_retrigger) {
 535                                 chip->irq_retrigger(data);
 536                                 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
 537                         }
 538                         raw_spin_unlock(&desc->lock);
 539                 }
 540                 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
 541                         __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
 542         }
 543 }
 544 #endif