1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/module.h>
12 #include <linux/clockchips.h>
13 #include <linux/random.h>
14 #include <linux/user-return-notifier.h>
15 #include <linux/dmi.h>
16 #include <linux/utsname.h>
17 #include <linux/stackprotector.h>
18 #include <linux/tick.h>
19 #include <linux/cpuidle.h>
20 #include <trace/events/power.h>
21 #include <linux/hw_breakpoint.h>
24 #include <asm/syscalls.h>
26 #include <asm/uaccess.h>
28 #include <asm/fpu-internal.h>
29 #include <asm/debugreg.h>
33 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
34 * no more per-task TSS's. The TSS size is kept cacheline-aligned
35 * so they are allowed to end up in the .data..cacheline_aligned
36 * section. Since TSS's are completely CPU-local, we want them
37 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
39 DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
42 static DEFINE_PER_CPU(unsigned char, is_idle);
45 struct kmem_cache *task_xstate_cachep;
46 EXPORT_SYMBOL_GPL(task_xstate_cachep);
49 * this gets called so that we can store lazy state into memory and copy the
50 * current task into the new thread.
52 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
57 if (fpu_allocated(&src->thread.fpu)) {
58 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
59 ret = fpu_alloc(&dst->thread.fpu);
67 void free_thread_xstate(struct task_struct *tsk)
69 fpu_free(&tsk->thread.fpu);
72 void arch_release_task_struct(struct task_struct *tsk)
74 free_thread_xstate(tsk);
77 void arch_task_cache_init(void)
80 kmem_cache_create("task_xstate", xstate_size,
81 __alignof__(union thread_xstate),
82 SLAB_PANIC | SLAB_NOTRACK, NULL);
86 * Free current thread data structures etc..
88 void exit_thread(void)
90 struct task_struct *me = current;
91 struct thread_struct *t = &me->thread;
92 unsigned long *bp = t->io_bitmap_ptr;
95 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
97 t->io_bitmap_ptr = NULL;
98 clear_thread_flag(TIF_IO_BITMAP);
100 * Careful, clear this in the TSS too:
102 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
103 t->io_bitmap_max = 0;
111 void flush_thread(void)
113 struct task_struct *tsk = current;
115 flush_ptrace_hw_breakpoint(tsk);
116 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
119 * Free the FPU state for non xsave platforms. They get reallocated
120 * lazily at the first use.
122 if (!use_eager_fpu())
123 free_thread_xstate(tsk);
126 static void hard_disable_TSC(void)
128 write_cr4(read_cr4() | X86_CR4_TSD);
131 void disable_TSC(void)
134 if (!test_and_set_thread_flag(TIF_NOTSC))
136 * Must flip the CPU state synchronously with
137 * TIF_NOTSC in the current running context.
143 static void hard_enable_TSC(void)
145 write_cr4(read_cr4() & ~X86_CR4_TSD);
148 static void enable_TSC(void)
151 if (test_and_clear_thread_flag(TIF_NOTSC))
153 * Must flip the CPU state synchronously with
154 * TIF_NOTSC in the current running context.
160 int get_tsc_mode(unsigned long adr)
164 if (test_thread_flag(TIF_NOTSC))
165 val = PR_TSC_SIGSEGV;
169 return put_user(val, (unsigned int __user *)adr);
172 int set_tsc_mode(unsigned int val)
174 if (val == PR_TSC_SIGSEGV)
176 else if (val == PR_TSC_ENABLE)
184 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
185 struct tss_struct *tss)
187 struct thread_struct *prev, *next;
189 prev = &prev_p->thread;
190 next = &next_p->thread;
192 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
193 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
194 unsigned long debugctl = get_debugctlmsr();
196 debugctl &= ~DEBUGCTLMSR_BTF;
197 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
198 debugctl |= DEBUGCTLMSR_BTF;
200 update_debugctlmsr(debugctl);
203 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
204 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
205 /* prev and next are different */
206 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
212 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
214 * Copy the relevant range of the IO bitmap.
215 * Normally this is 128 bytes or less:
217 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
218 max(prev->io_bitmap_max, next->io_bitmap_max));
219 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
221 * Clear any possible leftover bits:
223 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
225 propagate_user_return_notify(prev_p, next_p);
229 * Idle related variables and functions
231 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
232 EXPORT_SYMBOL(boot_option_idle_override);
234 static void (*x86_idle)(void);
237 static inline void play_dead(void)
244 void enter_idle(void)
246 this_cpu_write(is_idle, 1);
247 idle_notifier_call_chain(IDLE_START);
250 static void __exit_idle(void)
252 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
254 idle_notifier_call_chain(IDLE_END);
257 /* Called from interrupts to signify idle end */
260 /* idle loop has pid 0 */
267 void arch_cpu_idle_enter(void)
273 void arch_cpu_idle_exit(void)
278 void arch_cpu_idle_dead(void)
284 * Called from the generic idle code.
286 void arch_cpu_idle(void)
288 if (cpuidle_idle_call())
295 * We use this if we don't have any better idle routine..
297 void default_idle(void)
299 trace_cpu_idle_rcuidle(1, smp_processor_id());
301 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
303 #ifdef CONFIG_APM_MODULE
304 EXPORT_SYMBOL(default_idle);
308 bool xen_set_default_idle(void)
310 bool ret = !!x86_idle;
312 x86_idle = default_idle;
317 void stop_this_cpu(void *dummy)
323 set_cpu_online(smp_processor_id(), false);
324 disable_local_APIC();
330 bool amd_e400_c1e_detected;
331 EXPORT_SYMBOL(amd_e400_c1e_detected);
333 static cpumask_var_t amd_e400_c1e_mask;
335 void amd_e400_remove_cpu(int cpu)
337 if (amd_e400_c1e_mask != NULL)
338 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
342 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
343 * pending message MSR. If we detect C1E, then we handle it the same
344 * way as C3 power states (local apic timer and TSC stop)
346 static void amd_e400_idle(void)
348 if (!amd_e400_c1e_detected) {
351 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
353 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
354 amd_e400_c1e_detected = true;
355 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
356 mark_tsc_unstable("TSC halt in AMD C1E");
357 pr_info("System has AMD C1E enabled\n");
361 if (amd_e400_c1e_detected) {
362 int cpu = smp_processor_id();
364 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
365 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
367 * Force broadcast so ACPI can not interfere.
369 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
371 pr_info("Switch to broadcast mode on CPU%d\n", cpu);
373 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
378 * The switch back from broadcast mode needs to be
379 * called with interrupts disabled.
382 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
388 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
391 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
392 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
394 if (x86_idle || boot_option_idle_override == IDLE_POLL)
397 if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
398 /* E400: APIC timer interrupt does not wake up CPU from C1e */
399 pr_info("using AMD E400 aware idle routine\n");
400 x86_idle = amd_e400_idle;
402 x86_idle = default_idle;
405 void __init init_amd_e400_c1e_mask(void)
407 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
408 if (x86_idle == amd_e400_idle)
409 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
412 static int __init idle_setup(char *str)
417 if (!strcmp(str, "poll")) {
418 pr_info("using polling idle threads\n");
419 boot_option_idle_override = IDLE_POLL;
420 cpu_idle_poll_ctrl(true);
421 } else if (!strcmp(str, "halt")) {
423 * When the boot option of idle=halt is added, halt is
424 * forced to be used for CPU idle. In such case CPU C2/C3
425 * won't be used again.
426 * To continue to load the CPU idle driver, don't touch
427 * the boot_option_idle_override.
429 x86_idle = default_idle;
430 boot_option_idle_override = IDLE_HALT;
431 } else if (!strcmp(str, "nomwait")) {
433 * If the boot option of "idle=nomwait" is added,
434 * it means that mwait will be disabled for CPU C2/C3
435 * states. In such case it won't touch the variable
436 * of boot_option_idle_override.
438 boot_option_idle_override = IDLE_NOMWAIT;
444 early_param("idle", idle_setup);
446 unsigned long arch_align_stack(unsigned long sp)
448 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
449 sp -= get_random_int() % 8192;
453 unsigned long arch_randomize_brk(struct mm_struct *mm)
455 unsigned long range_end = mm->brk + 0x02000000;
456 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;