1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/module.h>
12 #include <linux/clockchips.h>
13 #include <linux/random.h>
14 #include <linux/user-return-notifier.h>
15 #include <linux/dmi.h>
16 #include <linux/utsname.h>
17 #include <linux/stackprotector.h>
18 #include <linux/tick.h>
19 #include <linux/cpuidle.h>
20 #include <trace/events/power.h>
21 #include <linux/hw_breakpoint.h>
24 #include <asm/syscalls.h>
26 #include <asm/uaccess.h>
28 #include <asm/fpu-internal.h>
29 #include <asm/debugreg.h>
33 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
34 * no more per-task TSS's. The TSS size is kept cacheline-aligned
35 * so they are allowed to end up in the .data..cacheline_aligned
36 * section. Since TSS's are completely CPU-local, we want them
37 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
39 DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
42 static DEFINE_PER_CPU(unsigned char, is_idle);
43 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
45 void idle_notifier_register(struct notifier_block *n)
47 atomic_notifier_chain_register(&idle_notifier, n);
49 EXPORT_SYMBOL_GPL(idle_notifier_register);
51 void idle_notifier_unregister(struct notifier_block *n)
53 atomic_notifier_chain_unregister(&idle_notifier, n);
55 EXPORT_SYMBOL_GPL(idle_notifier_unregister);
58 struct kmem_cache *task_xstate_cachep;
59 EXPORT_SYMBOL_GPL(task_xstate_cachep);
62 * this gets called so that we can store lazy state into memory and copy the
63 * current task into the new thread.
65 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
70 if (fpu_allocated(&src->thread.fpu)) {
71 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
72 ret = fpu_alloc(&dst->thread.fpu);
80 void free_thread_xstate(struct task_struct *tsk)
82 fpu_free(&tsk->thread.fpu);
85 void arch_release_task_struct(struct task_struct *tsk)
87 free_thread_xstate(tsk);
90 void arch_task_cache_init(void)
93 kmem_cache_create("task_xstate", xstate_size,
94 __alignof__(union thread_xstate),
95 SLAB_PANIC | SLAB_NOTRACK, NULL);
99 * Free current thread data structures etc..
101 void exit_thread(void)
103 struct task_struct *me = current;
104 struct thread_struct *t = &me->thread;
105 unsigned long *bp = t->io_bitmap_ptr;
108 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
110 t->io_bitmap_ptr = NULL;
111 clear_thread_flag(TIF_IO_BITMAP);
113 * Careful, clear this in the TSS too:
115 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
116 t->io_bitmap_max = 0;
124 void flush_thread(void)
126 struct task_struct *tsk = current;
128 flush_ptrace_hw_breakpoint(tsk);
129 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
132 * Free the FPU state for non xsave platforms. They get reallocated
133 * lazily at the first use.
135 if (!use_eager_fpu())
136 free_thread_xstate(tsk);
139 static void hard_disable_TSC(void)
141 write_cr4(read_cr4() | X86_CR4_TSD);
144 void disable_TSC(void)
147 if (!test_and_set_thread_flag(TIF_NOTSC))
149 * Must flip the CPU state synchronously with
150 * TIF_NOTSC in the current running context.
156 static void hard_enable_TSC(void)
158 write_cr4(read_cr4() & ~X86_CR4_TSD);
161 static void enable_TSC(void)
164 if (test_and_clear_thread_flag(TIF_NOTSC))
166 * Must flip the CPU state synchronously with
167 * TIF_NOTSC in the current running context.
173 int get_tsc_mode(unsigned long adr)
177 if (test_thread_flag(TIF_NOTSC))
178 val = PR_TSC_SIGSEGV;
182 return put_user(val, (unsigned int __user *)adr);
185 int set_tsc_mode(unsigned int val)
187 if (val == PR_TSC_SIGSEGV)
189 else if (val == PR_TSC_ENABLE)
197 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
198 struct tss_struct *tss)
200 struct thread_struct *prev, *next;
202 prev = &prev_p->thread;
203 next = &next_p->thread;
205 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
206 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
207 unsigned long debugctl = get_debugctlmsr();
209 debugctl &= ~DEBUGCTLMSR_BTF;
210 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
211 debugctl |= DEBUGCTLMSR_BTF;
213 update_debugctlmsr(debugctl);
216 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
217 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
218 /* prev and next are different */
219 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
225 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
227 * Copy the relevant range of the IO bitmap.
228 * Normally this is 128 bytes or less:
230 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
231 max(prev->io_bitmap_max, next->io_bitmap_max));
232 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
234 * Clear any possible leftover bits:
236 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
238 propagate_user_return_notify(prev_p, next_p);
242 * Idle related variables and functions
244 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
245 EXPORT_SYMBOL(boot_option_idle_override);
247 static void (*x86_idle)(void);
250 static inline void play_dead(void)
257 void enter_idle(void)
259 this_cpu_write(is_idle, 1);
260 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
263 static void __exit_idle(void)
265 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
267 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
270 /* Called from interrupts to signify idle end */
273 /* idle loop has pid 0 */
280 void arch_cpu_idle_prepare(void)
283 * If we're the non-boot CPU, nothing set the stack canary up
284 * for us. CPU0 already has it initialized but no harm in
285 * doing it again. This is a good place for updating it, as
286 * we wont ever return from this function (so the invalid
287 * canaries already on the stack wont ever trigger).
289 boot_init_stack_canary();
292 void arch_cpu_idle_enter(void)
298 void arch_cpu_idle_exit(void)
303 void arch_cpu_idle_dead(void)
309 * Called from the generic idle code.
311 void arch_cpu_idle(void)
313 if (cpuidle_idle_call())
320 * We use this if we don't have any better idle routine..
322 void default_idle(void)
324 trace_cpu_idle_rcuidle(1, smp_processor_id());
326 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
328 #ifdef CONFIG_APM_MODULE
329 EXPORT_SYMBOL(default_idle);
333 bool xen_set_default_idle(void)
335 bool ret = !!x86_idle;
337 x86_idle = default_idle;
342 void stop_this_cpu(void *dummy)
348 set_cpu_online(smp_processor_id(), false);
349 disable_local_APIC();
355 bool amd_e400_c1e_detected;
356 EXPORT_SYMBOL(amd_e400_c1e_detected);
358 static cpumask_var_t amd_e400_c1e_mask;
360 void amd_e400_remove_cpu(int cpu)
362 if (amd_e400_c1e_mask != NULL)
363 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
367 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
368 * pending message MSR. If we detect C1E, then we handle it the same
369 * way as C3 power states (local apic timer and TSC stop)
371 static void amd_e400_idle(void)
373 if (!amd_e400_c1e_detected) {
376 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
378 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
379 amd_e400_c1e_detected = true;
380 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
381 mark_tsc_unstable("TSC halt in AMD C1E");
382 pr_info("System has AMD C1E enabled\n");
386 if (amd_e400_c1e_detected) {
387 int cpu = smp_processor_id();
389 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
390 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
392 * Force broadcast so ACPI can not interfere.
394 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
396 pr_info("Switch to broadcast mode on CPU%d\n", cpu);
398 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
403 * The switch back from broadcast mode needs to be
404 * called with interrupts disabled.
407 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
413 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
416 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
417 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
419 if (x86_idle || boot_option_idle_override == IDLE_POLL)
422 if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
423 /* E400: APIC timer interrupt does not wake up CPU from C1e */
424 pr_info("using AMD E400 aware idle routine\n");
425 x86_idle = amd_e400_idle;
427 x86_idle = default_idle;
430 void __init init_amd_e400_c1e_mask(void)
432 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
433 if (x86_idle == amd_e400_idle)
434 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
437 static int __init idle_setup(char *str)
442 if (!strcmp(str, "poll")) {
443 pr_info("using polling idle threads\n");
444 boot_option_idle_override = IDLE_POLL;
445 cpu_idle_poll_ctrl(true);
446 } else if (!strcmp(str, "halt")) {
448 * When the boot option of idle=halt is added, halt is
449 * forced to be used for CPU idle. In such case CPU C2/C3
450 * won't be used again.
451 * To continue to load the CPU idle driver, don't touch
452 * the boot_option_idle_override.
454 x86_idle = default_idle;
455 boot_option_idle_override = IDLE_HALT;
456 } else if (!strcmp(str, "nomwait")) {
458 * If the boot option of "idle=nomwait" is added,
459 * it means that mwait will be disabled for CPU C2/C3
460 * states. In such case it won't touch the variable
461 * of boot_option_idle_override.
463 boot_option_idle_override = IDLE_NOMWAIT;
469 early_param("idle", idle_setup);
471 unsigned long arch_align_stack(unsigned long sp)
473 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
474 sp -= get_random_int() % 8192;
478 unsigned long arch_randomize_brk(struct mm_struct *mm)
480 unsigned long range_end = mm->brk + 0x02000000;
481 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;