1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <linux/dmi.h>
14 #include <linux/utsname.h>
15 #include <trace/events/power.h>
16 #include <linux/hw_breakpoint.h>
17 #include <asm/system.h>
19 #include <asm/syscalls.h>
21 #include <asm/uaccess.h>
23 #include <asm/debugreg.h>
25 unsigned long idle_halt;
26 EXPORT_SYMBOL(idle_halt);
27 unsigned long idle_nomwait;
28 EXPORT_SYMBOL(idle_nomwait);
30 struct kmem_cache *task_xstate_cachep;
32 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
37 if (fpu_allocated(&src->thread.fpu)) {
38 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
39 ret = fpu_alloc(&dst->thread.fpu);
42 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
47 void free_thread_xstate(struct task_struct *tsk)
49 fpu_free(&tsk->thread.fpu);
52 void free_thread_info(struct thread_info *ti)
54 free_thread_xstate(ti->task);
55 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
58 void arch_task_cache_init(void)
61 kmem_cache_create("task_xstate", xstate_size,
62 __alignof__(union thread_xstate),
63 SLAB_PANIC | SLAB_NOTRACK, NULL);
67 * Free current thread data structures etc..
69 void exit_thread(void)
71 struct task_struct *me = current;
72 struct thread_struct *t = &me->thread;
73 unsigned long *bp = t->io_bitmap_ptr;
76 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
78 t->io_bitmap_ptr = NULL;
79 clear_thread_flag(TIF_IO_BITMAP);
81 * Careful, clear this in the TSS too:
83 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
90 void show_regs(struct pt_regs *regs)
93 show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs),
97 void show_regs_common(void)
99 const char *board, *product;
101 board = dmi_get_system_info(DMI_BOARD_NAME);
104 product = dmi_get_system_info(DMI_PRODUCT_NAME);
108 printk(KERN_CONT "\n");
109 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
110 current->pid, current->comm, print_tainted(),
111 init_utsname()->release,
112 (int)strcspn(init_utsname()->version, " "),
113 init_utsname()->version, board, product);
116 void flush_thread(void)
118 struct task_struct *tsk = current;
120 flush_ptrace_hw_breakpoint(tsk);
121 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
123 * Forget coprocessor state..
125 tsk->fpu_counter = 0;
130 static void hard_disable_TSC(void)
132 write_cr4(read_cr4() | X86_CR4_TSD);
135 void disable_TSC(void)
138 if (!test_and_set_thread_flag(TIF_NOTSC))
140 * Must flip the CPU state synchronously with
141 * TIF_NOTSC in the current running context.
147 static void hard_enable_TSC(void)
149 write_cr4(read_cr4() & ~X86_CR4_TSD);
152 static void enable_TSC(void)
155 if (test_and_clear_thread_flag(TIF_NOTSC))
157 * Must flip the CPU state synchronously with
158 * TIF_NOTSC in the current running context.
164 int get_tsc_mode(unsigned long adr)
168 if (test_thread_flag(TIF_NOTSC))
169 val = PR_TSC_SIGSEGV;
173 return put_user(val, (unsigned int __user *)adr);
176 int set_tsc_mode(unsigned int val)
178 if (val == PR_TSC_SIGSEGV)
180 else if (val == PR_TSC_ENABLE)
188 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
189 struct tss_struct *tss)
191 struct thread_struct *prev, *next;
193 prev = &prev_p->thread;
194 next = &next_p->thread;
196 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
197 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
198 unsigned long debugctl = get_debugctlmsr();
200 debugctl &= ~DEBUGCTLMSR_BTF;
201 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
202 debugctl |= DEBUGCTLMSR_BTF;
204 update_debugctlmsr(debugctl);
207 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
208 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
209 /* prev and next are different */
210 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
216 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
218 * Copy the relevant range of the IO bitmap.
219 * Normally this is 128 bytes or less:
221 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
222 max(prev->io_bitmap_max, next->io_bitmap_max));
223 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
225 * Clear any possible leftover bits:
227 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
229 propagate_user_return_notify(prev_p, next_p);
232 int sys_fork(struct pt_regs *regs)
234 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
238 * This is trivial, and on the face of it looks like it
239 * could equally well be done in user mode.
241 * Not so, for quite unobvious reasons - register pressure.
242 * In user mode vfork() cannot have a stack frame, and if
243 * done by calling the "clone()" system call directly, you
244 * do not have enough call-clobbered registers to hold all
245 * the information you need.
247 int sys_vfork(struct pt_regs *regs)
249 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
254 sys_clone(unsigned long clone_flags, unsigned long newsp,
255 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
259 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
263 * This gets run with %si containing the
264 * function to call, and %di containing
267 extern void kernel_thread_helper(void);
270 * Create a kernel thread
272 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
276 memset(®s, 0, sizeof(regs));
278 regs.si = (unsigned long) fn;
279 regs.di = (unsigned long) arg;
284 regs.fs = __KERNEL_PERCPU;
285 regs.gs = __KERNEL_STACK_CANARY;
287 regs.ss = __KERNEL_DS;
291 regs.ip = (unsigned long) kernel_thread_helper;
292 regs.cs = __KERNEL_CS | get_kernel_rpl();
293 regs.flags = X86_EFLAGS_IF | 0x2;
295 /* Ok, create the new process.. */
296 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
298 EXPORT_SYMBOL(kernel_thread);
301 * sys_execve() executes a new program.
303 long sys_execve(char __user *name, char __user * __user *argv,
304 char __user * __user *envp, struct pt_regs *regs)
309 filename = getname(name);
310 error = PTR_ERR(filename);
311 if (IS_ERR(filename))
313 error = do_execve(filename, argv, envp, regs);
317 /* Make sure we don't return using sysenter.. */
318 set_thread_flag(TIF_IRET);
327 * Idle related variables and functions
329 unsigned long boot_option_idle_override = 0;
330 EXPORT_SYMBOL(boot_option_idle_override);
333 * Powermanagement idle function, if any..
335 void (*pm_idle)(void);
336 EXPORT_SYMBOL(pm_idle);
340 * This halt magic was a workaround for ancient floppy DMA
341 * wreckage. It should be safe to remove.
343 static int hlt_counter;
344 void disable_hlt(void)
348 EXPORT_SYMBOL(disable_hlt);
350 void enable_hlt(void)
354 EXPORT_SYMBOL(enable_hlt);
356 static inline int hlt_use_halt(void)
358 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
361 static inline int hlt_use_halt(void)
368 * We use this if we don't have any better
371 void default_idle(void)
373 if (hlt_use_halt()) {
374 trace_power_start(POWER_CSTATE, 1);
375 current_thread_info()->status &= ~TS_POLLING;
377 * TS_POLLING-cleared state must be visible before we
383 safe_halt(); /* enables interrupts racelessly */
386 current_thread_info()->status |= TS_POLLING;
389 /* loop is done by the caller */
393 #ifdef CONFIG_APM_MODULE
394 EXPORT_SYMBOL(default_idle);
397 void stop_this_cpu(void *dummy)
403 set_cpu_online(smp_processor_id(), false);
404 disable_local_APIC();
407 if (hlt_works(smp_processor_id()))
412 static void do_nothing(void *unused)
417 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
418 * pm_idle and update to new pm_idle value. Required while changing pm_idle
419 * handler on SMP systems.
421 * Caller must have changed pm_idle to the new value before the call. Old
422 * pm_idle value will not be used by any CPU after the return of this function.
424 void cpu_idle_wait(void)
427 /* kick all the CPUs so that they exit out of pm_idle */
428 smp_call_function(do_nothing, NULL, 1);
430 EXPORT_SYMBOL_GPL(cpu_idle_wait);
433 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
434 * which can obviate IPI to trigger checking of need_resched.
435 * We execute MONITOR against need_resched and enter optimized wait state
436 * through MWAIT. Whenever someone changes need_resched, we would be woken
437 * up from MWAIT (without an IPI).
439 * New with Core Duo processors, MWAIT can take some hints based on CPU
442 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
444 trace_power_start(POWER_CSTATE, (ax>>4)+1);
445 if (!need_resched()) {
446 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
447 clflush((void *)¤t_thread_info()->flags);
449 __monitor((void *)¤t_thread_info()->flags, 0, 0);
456 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
457 static void mwait_idle(void)
459 if (!need_resched()) {
460 trace_power_start(POWER_CSTATE, 1);
461 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
462 clflush((void *)¤t_thread_info()->flags);
464 __monitor((void *)¤t_thread_info()->flags, 0, 0);
475 * On SMP it's slightly faster (but much more power-consuming!)
476 * to poll the ->work.need_resched flag instead of waiting for the
477 * cross-CPU IPI to arrive. Use this option with caution.
479 static void poll_idle(void)
481 trace_power_start(POWER_CSTATE, 0);
483 while (!need_resched())
489 * mwait selection logic:
491 * It depends on the CPU. For AMD CPUs that support MWAIT this is
492 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
493 * then depend on a clock divisor and current Pstate of the core. If
494 * all cores of a processor are in halt state (C1) the processor can
495 * enter the C1E (C1 enhanced) state. If mwait is used this will never
498 * idle=mwait overrides this decision and forces the usage of mwait.
500 static int __cpuinitdata force_mwait;
502 #define MWAIT_INFO 0x05
503 #define MWAIT_ECX_EXTENDED_INFO 0x01
504 #define MWAIT_EDX_C1 0xf0
506 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
508 u32 eax, ebx, ecx, edx;
513 if (c->cpuid_level < MWAIT_INFO)
516 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
517 /* Check, whether EDX has extended info about MWAIT */
518 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
522 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
525 return (edx & MWAIT_EDX_C1);
529 * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e.
530 * For more information see
531 * - Erratum #400 for NPT family 0xf and family 0x10 CPUs
532 * - Erratum #365 for family 0x11 (not affected because C1e not in use)
534 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
537 if (c->x86_vendor != X86_VENDOR_AMD)
540 /* Family 0x0f models < rev F do not have C1E */
541 if (c->x86 == 0x0F && c->x86_model >= 0x40)
544 if (c->x86 == 0x10) {
546 * check OSVW bit for CPUs that are not affected
549 if (cpu_has(c, X86_FEATURE_OSVW)) {
550 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
552 rdmsrl(MSR_AMD64_OSVW_STATUS, val);
564 static cpumask_var_t c1e_mask;
565 static int c1e_detected;
567 void c1e_remove_cpu(int cpu)
569 if (c1e_mask != NULL)
570 cpumask_clear_cpu(cpu, c1e_mask);
574 * C1E aware idle routine. We check for C1E active in the interrupt
575 * pending message MSR. If we detect C1E, then we handle it the same
576 * way as C3 power states (local apic timer and TSC stop)
578 static void c1e_idle(void)
586 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
587 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
589 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
590 mark_tsc_unstable("TSC halt in AMD C1E");
591 printk(KERN_INFO "System has AMD C1E enabled\n");
592 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
597 int cpu = smp_processor_id();
599 if (!cpumask_test_cpu(cpu, c1e_mask)) {
600 cpumask_set_cpu(cpu, c1e_mask);
602 * Force broadcast so ACPI can not interfere.
604 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
606 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
609 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
614 * The switch back from broadcast mode needs to be
615 * called with interrupts disabled.
618 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
624 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
627 if (pm_idle == poll_idle && smp_num_siblings > 1) {
628 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
629 " performance may degrade.\n");
635 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
637 * One CPU supports mwait => All CPUs supports mwait
639 printk(KERN_INFO "using mwait in idle threads.\n");
640 pm_idle = mwait_idle;
641 } else if (check_c1e_idle(c)) {
642 printk(KERN_INFO "using C1E aware idle routine\n");
645 pm_idle = default_idle;
648 void __init init_c1e_mask(void)
650 /* If we're using c1e_idle, we need to allocate c1e_mask. */
651 if (pm_idle == c1e_idle)
652 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
655 static int __init idle_setup(char *str)
660 if (!strcmp(str, "poll")) {
661 printk("using polling idle threads.\n");
663 } else if (!strcmp(str, "mwait"))
665 else if (!strcmp(str, "halt")) {
667 * When the boot option of idle=halt is added, halt is
668 * forced to be used for CPU idle. In such case CPU C2/C3
669 * won't be used again.
670 * To continue to load the CPU idle driver, don't touch
671 * the boot_option_idle_override.
673 pm_idle = default_idle;
676 } else if (!strcmp(str, "nomwait")) {
678 * If the boot option of "idle=nomwait" is added,
679 * it means that mwait will be disabled for CPU C2/C3
680 * states. In such case it won't touch the variable
681 * of boot_option_idle_override.
688 boot_option_idle_override = 1;
691 early_param("idle", idle_setup);
693 unsigned long arch_align_stack(unsigned long sp)
695 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
696 sp -= get_random_int() % 8192;
700 unsigned long arch_randomize_brk(struct mm_struct *mm)
702 unsigned long range_end = mm->brk + 0x02000000;
703 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;