2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * CPU hotplug support - ashok.raj@intel.com
14 * This file handles the architecture-dependent parts of process handling..
17 #include <linux/cpu.h>
18 #include <linux/errno.h>
19 #include <linux/sched.h>
21 #include <linux/kernel.h>
23 #include <linux/elfcore.h>
24 #include <linux/smp.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/module.h>
30 #include <linux/ptrace.h>
31 #include <linux/notifier.h>
32 #include <linux/kprobes.h>
33 #include <linux/kdebug.h>
34 #include <linux/prctl.h>
35 #include <linux/uaccess.h>
37 #include <linux/ftrace.h>
39 #include <asm/pgtable.h>
40 #include <asm/processor.h>
41 #include <asm/fpu/internal.h>
42 #include <asm/mmu_context.h>
43 #include <asm/prctl.h>
45 #include <asm/proto.h>
48 #include <asm/syscalls.h>
49 #include <asm/debugreg.h>
50 #include <asm/switch_to.h>
52 asmlinkage extern void ret_from_fork(void);
54 __visible DEFINE_PER_CPU(unsigned long, rsp_scratch);
56 /* Prints also some state that isn't saved in the pt_regs */
57 void __show_regs(struct pt_regs *regs, int all)
59 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
60 unsigned long d0, d1, d2, d3, d6, d7;
61 unsigned int fsindex, gsindex;
62 unsigned int ds, cs, es;
64 printk(KERN_DEFAULT "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
65 printk_address(regs->ip);
66 printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss,
67 regs->sp, regs->flags);
68 printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
69 regs->ax, regs->bx, regs->cx);
70 printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
71 regs->dx, regs->si, regs->di);
72 printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
73 regs->bp, regs->r8, regs->r9);
74 printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
75 regs->r10, regs->r11, regs->r12);
76 printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
77 regs->r13, regs->r14, regs->r15);
79 asm("movl %%ds,%0" : "=r" (ds));
80 asm("movl %%cs,%0" : "=r" (cs));
81 asm("movl %%es,%0" : "=r" (es));
82 asm("movl %%fs,%0" : "=r" (fsindex));
83 asm("movl %%gs,%0" : "=r" (gsindex));
85 rdmsrl(MSR_FS_BASE, fs);
86 rdmsrl(MSR_GS_BASE, gs);
87 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
97 printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
98 fs, fsindex, gs, gsindex, shadowgs);
99 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
101 printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
111 /* Only print out debug registers if they are in their non-default state. */
112 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
113 (d6 == DR6_RESERVED) && (d7 == 0x400))
116 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
117 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
121 void release_thread(struct task_struct *dead_task)
124 #ifdef CONFIG_MODIFY_LDT_SYSCALL
125 if (dead_task->mm->context.ldt) {
126 pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
128 dead_task->mm->context.ldt,
129 dead_task->mm->context.ldt->size);
136 static inline void set_32bit_tls(struct task_struct *t, int tls, u32 addr)
138 struct user_desc ud = {
145 struct desc_struct *desc = t->thread.tls_array;
150 static inline u32 read_32bit_tls(struct task_struct *t, int tls)
152 return get_desc_base(&t->thread.tls_array[tls]);
155 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
156 unsigned long arg, struct task_struct *p, unsigned long tls)
159 struct pt_regs *childregs;
160 struct task_struct *me = current;
162 p->thread.sp0 = (unsigned long)task_stack_page(p) + THREAD_SIZE;
163 childregs = task_pt_regs(p);
164 p->thread.sp = (unsigned long) childregs;
165 set_tsk_thread_flag(p, TIF_FORK);
166 p->thread.io_bitmap_ptr = NULL;
168 savesegment(gs, p->thread.gsindex);
169 p->thread.gs = p->thread.gsindex ? 0 : me->thread.gs;
170 savesegment(fs, p->thread.fsindex);
171 p->thread.fs = p->thread.fsindex ? 0 : me->thread.fs;
172 savesegment(es, p->thread.es);
173 savesegment(ds, p->thread.ds);
174 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
176 if (unlikely(p->flags & PF_KTHREAD)) {
178 memset(childregs, 0, sizeof(struct pt_regs));
179 childregs->sp = (unsigned long)childregs;
180 childregs->ss = __KERNEL_DS;
181 childregs->bx = sp; /* function */
183 childregs->orig_ax = -1;
184 childregs->cs = __KERNEL_CS | get_kernel_rpl();
185 childregs->flags = X86_EFLAGS_IF | X86_EFLAGS_FIXED;
188 *childregs = *current_pt_regs();
195 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
196 p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr,
197 IO_BITMAP_BYTES, GFP_KERNEL);
198 if (!p->thread.io_bitmap_ptr) {
199 p->thread.io_bitmap_max = 0;
202 set_tsk_thread_flag(p, TIF_IO_BITMAP);
206 * Set a new TLS for the child thread?
208 if (clone_flags & CLONE_SETTLS) {
209 #ifdef CONFIG_IA32_EMULATION
211 err = do_set_thread_area(p, -1,
212 (struct user_desc __user *)tls, 0);
215 err = do_arch_prctl(p, ARCH_SET_FS, tls);
221 if (err && p->thread.io_bitmap_ptr) {
222 kfree(p->thread.io_bitmap_ptr);
223 p->thread.io_bitmap_max = 0;
230 start_thread_common(struct pt_regs *regs, unsigned long new_ip,
231 unsigned long new_sp,
232 unsigned int _cs, unsigned int _ss, unsigned int _ds)
235 loadsegment(es, _ds);
236 loadsegment(ds, _ds);
242 regs->flags = X86_EFLAGS_IF;
247 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
249 start_thread_common(regs, new_ip, new_sp,
250 __USER_CS, __USER_DS, 0);
254 void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp)
256 start_thread_common(regs, new_ip, new_sp,
257 test_thread_flag(TIF_X32)
258 ? __USER_CS : __USER32_CS,
259 __USER_DS, __USER_DS);
264 * switch_to(x,y) should switch tasks from x to y.
266 * This could still be optimized:
267 * - fold all the options into a flag word and test it with a single test.
268 * - could test fs/gs bitsliced
270 * Kprobes not supported here. Set the probe on schedule instead.
271 * Function graph tracer not supported too.
273 __visible __notrace_funcgraph struct task_struct *
274 __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
276 struct thread_struct *prev = &prev_p->thread;
277 struct thread_struct *next = &next_p->thread;
278 struct fpu *prev_fpu = &prev->fpu;
279 struct fpu *next_fpu = &next->fpu;
280 int cpu = smp_processor_id();
281 struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
282 unsigned fsindex, gsindex;
283 fpu_switch_t fpu_switch;
285 fpu_switch = switch_fpu_prepare(prev_fpu, next_fpu, cpu);
287 /* We must save %fs and %gs before load_TLS() because
288 * %fs and %gs may be cleared by load_TLS().
290 * (e.g. xen_load_tls())
292 savesegment(fs, fsindex);
293 savesegment(gs, gsindex);
296 * Load TLS before restoring any segments so that segment loads
297 * reference the correct GDT entries.
302 * Leave lazy mode, flushing any hypercalls made here. This
303 * must be done after loading TLS entries in the GDT but before
304 * loading segments that might reference them, and and it must
305 * be done before fpu__restore(), so the TS bit is up to
308 arch_end_context_switch(next_p);
312 * Reading them only returns the selectors, but writing them (if
313 * nonzero) loads the full descriptor from the GDT or LDT. The
314 * LDT for next is loaded in switch_mm, and the GDT is loaded
317 * We therefore need to write new values to the segment
318 * registers on every context switch unless both the new and old
321 * Note that we don't need to do anything for CS and SS, as
322 * those are saved and restored as part of pt_regs.
324 savesegment(es, prev->es);
325 if (unlikely(next->es | prev->es))
326 loadsegment(es, next->es);
328 savesegment(ds, prev->ds);
329 if (unlikely(next->ds | prev->ds))
330 loadsegment(ds, next->ds);
335 * These are even more complicated than FS and GS: they have
336 * 64-bit bases are that controlled by arch_prctl. Those bases
337 * only differ from the values in the GDT or LDT if the selector
340 * Loading the segment register resets the hidden base part of
341 * the register to 0 or the value from the GDT / LDT. If the
342 * next base address zero, writing 0 to the segment register is
343 * much faster than using wrmsr to explicitly zero the base.
345 * The thread_struct.fs and thread_struct.gs values are 0
346 * if the fs and gs bases respectively are not overridden
347 * from the values implied by fsindex and gsindex. They
348 * are nonzero, and store the nonzero base addresses, if
349 * the bases are overridden.
351 * (fs != 0 && fsindex != 0) || (gs != 0 && gsindex != 0) should
354 * Therefore we need to reload the segment registers if either
355 * the old or new selector is nonzero, and we need to override
356 * the base address if next thread expects it to be overridden.
358 * This code is unnecessarily slow in the case where the old and
359 * new indexes are zero and the new base is nonzero -- it will
360 * unnecessarily write 0 to the selector before writing the new
363 * Note: This all depends on arch_prctl being the only way that
364 * user code can override the segment base. Once wrfsbase and
365 * wrgsbase are enabled, most of this code will need to change.
367 if (unlikely(fsindex | next->fsindex | prev->fs)) {
368 loadsegment(fs, next->fsindex);
371 * If user code wrote a nonzero value to FS, then it also
372 * cleared the overridden base address.
374 * XXX: if user code wrote 0 to FS and cleared the base
375 * address itself, we won't notice and we'll incorrectly
376 * restore the prior base address next time we reschdule
383 wrmsrl(MSR_FS_BASE, next->fs);
384 prev->fsindex = fsindex;
386 if (unlikely(gsindex | next->gsindex | prev->gs)) {
387 load_gs_index(next->gsindex);
389 /* This works (and fails) the same way as fsindex above. */
394 wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
395 prev->gsindex = gsindex;
397 switch_fpu_finish(next_fpu, fpu_switch);
400 * Switch the PDA and FPU contexts.
402 this_cpu_write(current_task, next_p);
405 * If it were not for PREEMPT_ACTIVE we could guarantee that the
406 * preempt_count of all tasks was equal here and this would not be
409 task_thread_info(prev_p)->saved_preempt_count = this_cpu_read(__preempt_count);
410 this_cpu_write(__preempt_count, task_thread_info(next_p)->saved_preempt_count);
412 /* Reload esp0 and ss1. This changes current_thread_info(). */
416 * Now maybe reload the debug registers and handle I/O bitmaps
418 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
419 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
420 __switch_to_xtra(prev_p, next_p, tss);
422 if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) {
424 * AMD CPUs have a misfeature: SYSRET sets the SS selector but
425 * does not update the cached descriptor. As a result, if we
426 * do SYSRET while SS is NULL, we'll end up in user mode with
427 * SS apparently equal to __USER_DS but actually unusable.
429 * The straightforward workaround would be to fix it up just
430 * before SYSRET, but that would slow down the system call
431 * fast paths. Instead, we ensure that SS is never NULL in
432 * system call context. We do this by replacing NULL SS
433 * selectors at every context switch. SYSCALL sets up a valid
434 * SS, so the only way to get NULL is to re-enter the kernel
435 * from CPL 3 through an interrupt. Since that can't happen
436 * in the same task as a running syscall, we are guaranteed to
437 * context switch between every interrupt vector entry and a
440 * We read SS first because SS reads are much faster than
441 * writes. Out of caution, we force SS to __KERNEL_DS even if
442 * it previously had a different non-NULL value.
444 unsigned short ss_sel;
445 savesegment(ss, ss_sel);
446 if (ss_sel != __KERNEL_DS)
447 loadsegment(ss, __KERNEL_DS);
453 void set_personality_64bit(void)
455 /* inherit personality from parent */
457 /* Make sure to be in 64bit mode */
458 clear_thread_flag(TIF_IA32);
459 clear_thread_flag(TIF_ADDR32);
460 clear_thread_flag(TIF_X32);
462 /* Ensure the corresponding mm is not marked. */
464 current->mm->context.ia32_compat = 0;
466 /* TBD: overwrites user setup. Should have two bits.
467 But 64bit processes have always behaved this way,
468 so it's not too bad. The main problem is just that
469 32bit childs are affected again. */
470 current->personality &= ~READ_IMPLIES_EXEC;
473 void set_personality_ia32(bool x32)
475 /* inherit personality from parent */
477 /* Make sure to be in 32bit mode */
478 set_thread_flag(TIF_ADDR32);
480 /* Mark the associated mm as containing 32-bit tasks. */
482 clear_thread_flag(TIF_IA32);
483 set_thread_flag(TIF_X32);
485 current->mm->context.ia32_compat = TIF_X32;
486 current->personality &= ~READ_IMPLIES_EXEC;
487 /* is_compat_task() uses the presence of the x32
488 syscall bit flag to determine compat status */
489 current_thread_info()->status &= ~TS_COMPAT;
491 set_thread_flag(TIF_IA32);
492 clear_thread_flag(TIF_X32);
494 current->mm->context.ia32_compat = TIF_IA32;
495 current->personality |= force_personality32;
496 /* Prepare the first "return" to user space */
497 current_thread_info()->status |= TS_COMPAT;
500 EXPORT_SYMBOL_GPL(set_personality_ia32);
502 unsigned long get_wchan(struct task_struct *p)
508 if (!p || p == current || p->state == TASK_RUNNING)
510 stack = (unsigned long)task_stack_page(p);
511 if (p->thread.sp < stack || p->thread.sp >= stack+THREAD_SIZE)
513 fp = *(u64 *)(p->thread.sp);
515 if (fp < (unsigned long)stack ||
516 fp >= (unsigned long)stack+THREAD_SIZE)
519 if (!in_sched_functions(ip))
522 } while (count++ < 16);
526 long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
529 int doit = task == current;
534 if (addr >= TASK_SIZE_OF(task))
537 /* handle small bases via the GDT because that's faster to
539 if (addr <= 0xffffffff) {
540 set_32bit_tls(task, GS_TLS, addr);
542 load_TLS(&task->thread, cpu);
543 load_gs_index(GS_TLS_SEL);
545 task->thread.gsindex = GS_TLS_SEL;
548 task->thread.gsindex = 0;
549 task->thread.gs = addr;
552 ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr);
558 /* Not strictly needed for fs, but do it for symmetry
560 if (addr >= TASK_SIZE_OF(task))
563 /* handle small bases via the GDT because that's faster to
565 if (addr <= 0xffffffff) {
566 set_32bit_tls(task, FS_TLS, addr);
568 load_TLS(&task->thread, cpu);
569 loadsegment(fs, FS_TLS_SEL);
571 task->thread.fsindex = FS_TLS_SEL;
574 task->thread.fsindex = 0;
575 task->thread.fs = addr;
577 /* set the selector to 0 to not confuse
580 ret = wrmsrl_safe(MSR_FS_BASE, addr);
587 if (task->thread.fsindex == FS_TLS_SEL)
588 base = read_32bit_tls(task, FS_TLS);
590 rdmsrl(MSR_FS_BASE, base);
592 base = task->thread.fs;
593 ret = put_user(base, (unsigned long __user *)addr);
599 if (task->thread.gsindex == GS_TLS_SEL)
600 base = read_32bit_tls(task, GS_TLS);
602 savesegment(gs, gsindex);
604 rdmsrl(MSR_KERNEL_GS_BASE, base);
606 base = task->thread.gs;
608 base = task->thread.gs;
609 ret = put_user(base, (unsigned long __user *)addr);
621 long sys_arch_prctl(int code, unsigned long addr)
623 return do_arch_prctl(current, code, addr);
626 unsigned long KSTK_ESP(struct task_struct *task)
628 return task_pt_regs(task)->sp;