2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53 #include <linux/cpuidle.h>
60 #include <asm/trampoline.h>
63 #include <asm/pgtable.h>
64 #include <asm/tlbflush.h>
66 #include <asm/mwait.h>
68 #include <asm/io_apic.h>
69 #include <asm/setup.h>
70 #include <asm/uv/uv.h>
71 #include <linux/mc146818rtc.h>
73 #include <asm/smpboot_hooks.h>
74 #include <asm/i8259.h>
76 /* State of each CPU */
77 DEFINE_PER_CPU(int, cpu_state) = { 0 };
79 /* Store all idle threads, this can be reused instead of creating
80 * a new thread. Also avoids complicated thread destroy functionality
83 #ifdef CONFIG_HOTPLUG_CPU
85 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
86 * removed after init for !CONFIG_HOTPLUG_CPU.
88 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
89 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
90 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
93 * We need this for trampoline_base protection from concurrent accesses when
94 * off- and onlining cores wildly.
96 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
98 void cpu_hotplug_driver_lock(void)
100 mutex_lock(&x86_cpu_hotplug_driver_mutex);
103 void cpu_hotplug_driver_unlock(void)
105 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
108 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
109 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
111 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
112 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
113 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
116 /* Number of siblings per CPU package */
117 int smp_num_siblings = 1;
118 EXPORT_SYMBOL(smp_num_siblings);
120 /* Last level cache ID of each logical CPU */
121 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
123 /* representing HT siblings of each logical CPU */
124 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
125 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
127 /* representing HT and core siblings of each logical CPU */
128 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
129 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
131 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
133 /* Per CPU bogomips and other parameters */
134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
135 EXPORT_PER_CPU_SYMBOL(cpu_info);
137 atomic_t init_deasserted;
140 * Report back to the Boot Processor.
143 static void __cpuinit smp_callin(void)
146 unsigned long timeout;
149 * If waken up by an INIT in an 82489DX configuration
150 * we may get here before an INIT-deassert IPI reaches
151 * our local APIC. We have to wait for the IPI or we'll
152 * lock up on an APIC access.
154 if (apic->wait_for_init_deassert)
155 apic->wait_for_init_deassert(&init_deasserted);
158 * (This works even if the APIC is not enabled.)
160 phys_id = read_apic_id();
161 cpuid = smp_processor_id();
162 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
163 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
166 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
169 * STARTUP IPIs are fragile beasts as they might sometimes
170 * trigger some glue motherboard logic. Complete APIC bus
171 * silence for 1 second, this overestimates the time the
172 * boot CPU is spending to send the up to 2 STARTUP IPIs
173 * by a factor of two. This should be enough.
177 * Waiting 2s total for startup (udelay is not yet working)
179 timeout = jiffies + 2*HZ;
180 while (time_before(jiffies, timeout)) {
182 * Has the boot CPU finished it's STARTUP sequence?
184 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
189 if (!time_before(jiffies, timeout)) {
190 panic("%s: CPU%d started up but did not get a callout!\n",
195 * the boot CPU has finished the init stage and is spinning
196 * on callin_map until we finish. We are free to set up this
197 * CPU, first the APIC. (this is probably redundant on most
201 pr_debug("CALLIN, before setup_local_APIC().\n");
202 if (apic->smp_callin_clear_local_apic)
203 apic->smp_callin_clear_local_apic();
205 end_local_APIC_setup();
208 * Need to setup vector mappings before we enable interrupts.
210 setup_vector_irq(smp_processor_id());
213 * Save our processor parameters. Note: this information
214 * is needed for clock calibration.
216 smp_store_cpu_info(cpuid);
220 * Update loops_per_jiffy in cpu_data. Previous call to
221 * smp_store_cpu_info() stored a value that is close but not as
222 * accurate as the value just calculated.
225 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
226 pr_debug("Stack at about %p\n", &cpuid);
229 * This must be done before setting cpu_online_mask
230 * or calling notify_cpu_starting.
232 set_cpu_sibling_map(raw_smp_processor_id());
235 notify_cpu_starting(cpuid);
238 * Allow the master to continue.
240 cpumask_set_cpu(cpuid, cpu_callin_mask);
244 * Activate a secondary processor.
246 notrace static void __cpuinit start_secondary(void *unused)
249 * Don't put *anything* before cpu_init(), SMP booting is too
250 * fragile that we want to limit the things done here to the
251 * most necessary things.
254 x86_cpuinit.early_percpu_clock_init();
259 /* switch away from the initial page table */
260 load_cr3(swapper_pg_dir);
264 /* otherwise gcc will move up smp_processor_id before the cpu_init */
267 * Check TSC synchronization with the BP:
269 check_tsc_sync_target();
272 * We need to hold call_lock, so there is no inconsistency
273 * between the time smp_call_function() determines number of
274 * IPI recipients, and the time when the determination is made
275 * for which cpus receive the IPI. Holding this
276 * lock helps us to not include this cpu in a currently in progress
277 * smp_call_function().
279 * We need to hold vector_lock so there the set of online cpus
280 * does not change while we are assigning vectors to cpus. Holding
281 * this lock ensures we don't half assign or remove an irq from a cpu.
285 set_cpu_online(smp_processor_id(), true);
286 unlock_vector_lock();
288 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
289 x86_platform.nmi_init();
291 /* enable local interrupts */
294 /* to prevent fake stack check failure in clock setup */
295 boot_init_stack_canary();
297 x86_cpuinit.setup_percpu_clockev();
304 * The bootstrap kernel entry code has set these up. Save them for
308 void __cpuinit smp_store_cpu_info(int id)
310 struct cpuinfo_x86 *c = &cpu_data(id);
315 identify_secondary_cpu(c);
318 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
320 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
321 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
322 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
323 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
324 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
325 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
329 void __cpuinit set_cpu_sibling_map(int cpu)
332 struct cpuinfo_x86 *c = &cpu_data(cpu);
334 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
336 if (smp_num_siblings > 1) {
337 for_each_cpu(i, cpu_sibling_setup_mask) {
338 struct cpuinfo_x86 *o = &cpu_data(i);
340 if (cpu_to_node(cpu) != cpu_to_node(i)) {
341 WARN_ONCE(1, "sched: CPU #%d's thread-sibling CPU #%d not on the same node! [node %d != %d]. Ignoring sibling dependency.\n", cpu, i, cpu_to_node(cpu), cpu_to_node(i));
345 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
346 if (c->phys_proc_id == o->phys_proc_id &&
347 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
348 c->compute_unit_id == o->compute_unit_id)
349 link_thread_siblings(cpu, i);
350 } else if (c->phys_proc_id == o->phys_proc_id &&
351 c->cpu_core_id == o->cpu_core_id) {
352 link_thread_siblings(cpu, i);
356 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
359 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
361 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
362 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
367 for_each_cpu(i, cpu_sibling_setup_mask) {
368 if (cpu_to_node(cpu) != cpu_to_node(i)) {
369 WARN_ONCE(1, "sched: CPU #%d's core-sibling CPU #%d not on the same node! [node %d != %d]. Ignoring sibling dependency.\n", cpu, i, cpu_to_node(cpu), cpu_to_node(i));
373 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
374 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
375 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
376 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
379 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
380 cpumask_set_cpu(i, cpu_core_mask(cpu));
381 cpumask_set_cpu(cpu, cpu_core_mask(i));
383 * Does this new cpu bringup a new core?
385 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
387 * for each core in package, increment
388 * the booted_cores for this new cpu
390 if (cpumask_first(cpu_sibling_mask(i)) == i)
393 * increment the core count for all
394 * the other cpus in this package
397 cpu_data(i).booted_cores++;
398 } else if (i != cpu && !c->booted_cores)
399 c->booted_cores = cpu_data(i).booted_cores;
404 /* maps the cpu to the sched domain representing multi-core */
405 const struct cpumask *cpu_coregroup_mask(int cpu)
407 struct cpuinfo_x86 *c = &cpu_data(cpu);
409 * For perf, we return last level cache shared map.
410 * And for power savings, we return cpu_core_map
412 if ((sched_mc_power_savings || sched_smt_power_savings) &&
413 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
414 return cpu_core_mask(cpu);
416 return cpu_llc_shared_mask(cpu);
419 static void impress_friends(void)
422 unsigned long bogosum = 0;
424 * Allow the user to impress friends.
426 pr_debug("Before bogomips.\n");
427 for_each_possible_cpu(cpu)
428 if (cpumask_test_cpu(cpu, cpu_callout_mask))
429 bogosum += cpu_data(cpu).loops_per_jiffy;
431 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
434 (bogosum/(5000/HZ))%100);
436 pr_debug("Before bogocount - setting activated=1.\n");
439 void __inquire_remote_apic(int apicid)
441 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
442 const char * const names[] = { "ID", "VERSION", "SPIV" };
446 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
448 for (i = 0; i < ARRAY_SIZE(regs); i++) {
449 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
454 status = safe_apic_wait_icr_idle();
457 "a previous APIC delivery may have failed\n");
459 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
464 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
465 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
468 case APIC_ICR_RR_VALID:
469 status = apic_read(APIC_RRR);
470 printk(KERN_CONT "%08x\n", status);
473 printk(KERN_CONT "failed\n");
479 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
480 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
481 * won't ... remember to clear down the APIC, etc later.
484 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
486 unsigned long send_status, accept_status = 0;
490 /* Boot on the stack */
491 /* Kick the second */
492 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
494 pr_debug("Waiting for send to finish...\n");
495 send_status = safe_apic_wait_icr_idle();
498 * Give the other CPU some time to accept the IPI.
501 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
502 maxlvt = lapic_get_maxlvt();
503 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
504 apic_write(APIC_ESR, 0);
505 accept_status = (apic_read(APIC_ESR) & 0xEF);
507 pr_debug("NMI sent.\n");
510 printk(KERN_ERR "APIC never delivered???\n");
512 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
514 return (send_status | accept_status);
518 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
520 unsigned long send_status, accept_status = 0;
521 int maxlvt, num_starts, j;
523 maxlvt = lapic_get_maxlvt();
526 * Be paranoid about clearing APIC errors.
528 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
529 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
530 apic_write(APIC_ESR, 0);
534 pr_debug("Asserting INIT.\n");
537 * Turn INIT on target chip
542 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
545 pr_debug("Waiting for send to finish...\n");
546 send_status = safe_apic_wait_icr_idle();
550 pr_debug("Deasserting INIT.\n");
554 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
556 pr_debug("Waiting for send to finish...\n");
557 send_status = safe_apic_wait_icr_idle();
560 atomic_set(&init_deasserted, 1);
563 * Should we send STARTUP IPIs ?
565 * Determine this based on the APIC version.
566 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
568 if (APIC_INTEGRATED(apic_version[phys_apicid]))
574 * Paravirt / VMI wants a startup IPI hook here to set up the
575 * target processor state.
577 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
581 * Run STARTUP IPI loop.
583 pr_debug("#startup loops: %d.\n", num_starts);
585 for (j = 1; j <= num_starts; j++) {
586 pr_debug("Sending STARTUP #%d.\n", j);
587 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
588 apic_write(APIC_ESR, 0);
590 pr_debug("After apic_write.\n");
597 /* Boot on the stack */
598 /* Kick the second */
599 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
603 * Give the other CPU some time to accept the IPI.
607 pr_debug("Startup point 1.\n");
609 pr_debug("Waiting for send to finish...\n");
610 send_status = safe_apic_wait_icr_idle();
613 * Give the other CPU some time to accept the IPI.
616 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
617 apic_write(APIC_ESR, 0);
618 accept_status = (apic_read(APIC_ESR) & 0xEF);
619 if (send_status || accept_status)
622 pr_debug("After Startup.\n");
625 printk(KERN_ERR "APIC never delivered???\n");
627 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
629 return (send_status | accept_status);
633 struct work_struct work;
634 struct task_struct *idle;
635 struct completion done;
639 static void __cpuinit do_fork_idle(struct work_struct *work)
641 struct create_idle *c_idle =
642 container_of(work, struct create_idle, work);
644 c_idle->idle = fork_idle(c_idle->cpu);
645 complete(&c_idle->done);
648 /* reduce the number of lines printed when booting a large cpu count system */
649 static void __cpuinit announce_cpu(int cpu, int apicid)
651 static int current_node = -1;
652 int node = early_cpu_to_node(cpu);
654 if (system_state == SYSTEM_BOOTING) {
655 if (node != current_node) {
656 if (current_node > (-1))
659 pr_info("Booting Node %3d, Processors ", node);
661 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
664 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
669 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
670 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
671 * Returns zero if CPU booted OK, else error code from
672 * ->wakeup_secondary_cpu.
674 static int __cpuinit do_boot_cpu(int apicid, int cpu)
676 unsigned long boot_error = 0;
677 unsigned long start_ip;
679 struct create_idle c_idle = {
681 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
684 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
686 alternatives_smp_switch(1);
688 c_idle.idle = get_idle_for_cpu(cpu);
691 * We can't use kernel_thread since we must avoid to
692 * reschedule the child.
695 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
696 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
697 init_idle(c_idle.idle, cpu);
701 schedule_work(&c_idle.work);
702 wait_for_completion(&c_idle.done);
704 if (IS_ERR(c_idle.idle)) {
705 printk("failed fork for CPU %d\n", cpu);
706 destroy_work_on_stack(&c_idle.work);
707 return PTR_ERR(c_idle.idle);
710 set_idle_for_cpu(cpu, c_idle.idle);
712 per_cpu(current_task, cpu) = c_idle.idle;
714 /* Stack for startup_32 can be just as for start_secondary onwards */
717 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
718 initial_gs = per_cpu_offset(cpu);
719 per_cpu(kernel_stack, cpu) =
720 (unsigned long)task_stack_page(c_idle.idle) -
721 KERNEL_STACK_OFFSET + THREAD_SIZE;
723 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
724 initial_code = (unsigned long)start_secondary;
725 stack_start = c_idle.idle->thread.sp;
727 /* start_ip had better be page-aligned! */
728 start_ip = trampoline_address();
730 /* So we see what's up */
731 announce_cpu(cpu, apicid);
734 * This grunge runs the startup process for
735 * the targeted processor.
738 atomic_set(&init_deasserted, 0);
740 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
742 pr_debug("Setting warm reset code and vector.\n");
744 smpboot_setup_warm_reset_vector(start_ip);
746 * Be paranoid about clearing APIC errors.
748 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
749 apic_write(APIC_ESR, 0);
755 * Kick the secondary CPU. Use the method in the APIC driver
756 * if it's defined - or use an INIT boot APIC message otherwise:
758 if (apic->wakeup_secondary_cpu)
759 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
761 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
765 * allow APs to start initializing.
767 pr_debug("Before Callout %d.\n", cpu);
768 cpumask_set_cpu(cpu, cpu_callout_mask);
769 pr_debug("After Callout %d.\n", cpu);
772 * Wait 5s total for a response
774 for (timeout = 0; timeout < 50000; timeout++) {
775 if (cpumask_test_cpu(cpu, cpu_callin_mask))
776 break; /* It has booted */
779 * Allow other tasks to run while we wait for the
780 * AP to come online. This also gives a chance
781 * for the MTRR work(triggered by the AP coming online)
782 * to be completed in the stop machine context.
787 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
788 print_cpu_msr(&cpu_data(cpu));
789 pr_debug("CPU%d: has booted.\n", cpu);
792 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
794 /* trampoline started but...? */
795 pr_err("CPU%d: Stuck ??\n", cpu);
797 /* trampoline code not run */
798 pr_err("CPU%d: Not responding.\n", cpu);
799 if (apic->inquire_remote_apic)
800 apic->inquire_remote_apic(apicid);
805 /* Try to put things back the way they were before ... */
806 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
808 /* was set by do_boot_cpu() */
809 cpumask_clear_cpu(cpu, cpu_callout_mask);
811 /* was set by cpu_init() */
812 cpumask_clear_cpu(cpu, cpu_initialized_mask);
814 set_cpu_present(cpu, false);
815 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
818 /* mark "stuck" area as not stuck */
819 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
821 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
823 * Cleanup possible dangling ends...
825 smpboot_restore_warm_reset_vector();
828 destroy_work_on_stack(&c_idle.work);
832 int __cpuinit native_cpu_up(unsigned int cpu)
834 int apicid = apic->cpu_present_to_apicid(cpu);
838 WARN_ON(irqs_disabled());
840 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
842 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
843 !physid_isset(apicid, phys_cpu_present_map) ||
844 !apic->apic_id_valid(apicid)) {
845 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
850 * Already booted CPU?
852 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
853 pr_debug("do_boot_cpu %d Already started\n", cpu);
858 * Save current MTRR state in case it was changed since early boot
859 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
863 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
865 err = do_boot_cpu(apicid, cpu);
867 pr_debug("do_boot_cpu failed %d\n", err);
872 * Check TSC synchronization with the AP (keep irqs disabled
875 local_irq_save(flags);
876 check_tsc_sync_source(cpu);
877 local_irq_restore(flags);
879 while (!cpu_online(cpu)) {
881 touch_nmi_watchdog();
888 * arch_disable_smp_support() - disables SMP support for x86 at runtime
890 void arch_disable_smp_support(void)
892 disable_ioapic_support();
896 * Fall back to non SMP mode after errors.
898 * RED-PEN audit/test this more. I bet there is more state messed up here.
900 static __init void disable_smp(void)
902 init_cpu_present(cpumask_of(0));
903 init_cpu_possible(cpumask_of(0));
904 smpboot_clear_io_apic_irqs();
906 if (smp_found_config)
907 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
909 physid_set_mask_of_physid(0, &phys_cpu_present_map);
910 cpumask_set_cpu(0, cpu_sibling_mask(0));
911 cpumask_set_cpu(0, cpu_core_mask(0));
915 * Various sanity checks.
917 static int __init smp_sanity_check(unsigned max_cpus)
921 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
922 if (def_to_bigsmp && nr_cpu_ids > 8) {
927 "More than 8 CPUs detected - skipping them.\n"
928 "Use CONFIG_X86_BIGSMP.\n");
931 for_each_present_cpu(cpu) {
933 set_cpu_present(cpu, false);
938 for_each_possible_cpu(cpu) {
940 set_cpu_possible(cpu, false);
948 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
950 "weird, boot CPU (#%d) not listed by the BIOS.\n",
951 hard_smp_processor_id());
953 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
957 * If we couldn't find an SMP configuration at boot time,
958 * get out of here now!
960 if (!smp_found_config && !acpi_lapic) {
962 printk(KERN_NOTICE "SMP motherboard not detected.\n");
964 if (APIC_init_uniprocessor())
965 printk(KERN_NOTICE "Local APIC not detected."
966 " Using dummy APIC emulation.\n");
971 * Should not be necessary because the MP table should list the boot
972 * CPU too, but we do it for the sake of robustness anyway.
974 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
976 "weird, boot CPU (#%d) not listed by the BIOS.\n",
977 boot_cpu_physical_apicid);
978 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
983 * If we couldn't find a local APIC, then get out of here now!
985 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
988 pr_err("BIOS bug, local APIC #%d not detected!...\n",
989 boot_cpu_physical_apicid);
990 pr_err("... forcing use of dummy APIC emulation."
991 "(tell your hw vendor)\n");
993 smpboot_clear_io_apic();
994 disable_ioapic_support();
1001 * If SMP should be disabled, then really disable it!
1004 printk(KERN_INFO "SMP mode deactivated.\n");
1005 smpboot_clear_io_apic();
1009 bsp_end_local_APIC_setup();
1016 static void __init smp_cpu_index_default(void)
1019 struct cpuinfo_x86 *c;
1021 for_each_possible_cpu(i) {
1023 /* mark all to hotplug */
1024 c->cpu_index = nr_cpu_ids;
1029 * Prepare for SMP bootup. The MP table or ACPI has been read
1030 * earlier. Just do some sanity checking here and enable APIC mode.
1032 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1037 smp_cpu_index_default();
1040 * Setup boot CPU information
1042 smp_store_cpu_info(0); /* Final full version of the data */
1043 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1046 current_thread_info()->cpu = 0; /* needed? */
1047 for_each_possible_cpu(i) {
1048 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1049 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1050 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1052 set_cpu_sibling_map(0);
1055 if (smp_sanity_check(max_cpus) < 0) {
1056 printk(KERN_INFO "SMP disabled\n");
1061 default_setup_apic_routing();
1064 if (read_apic_id() != boot_cpu_physical_apicid) {
1065 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1066 read_apic_id(), boot_cpu_physical_apicid);
1067 /* Or can we switch back to PIC here? */
1074 * Switch from PIC to APIC mode.
1079 * Enable IO APIC before setting up error vector
1081 if (!skip_ioapic_setup && nr_ioapics)
1084 bsp_end_local_APIC_setup();
1086 if (apic->setup_portio_remap)
1087 apic->setup_portio_remap();
1089 smpboot_setup_io_apic();
1091 * Set up local APIC timer on boot CPU.
1094 printk(KERN_INFO "CPU%d: ", 0);
1095 print_cpu_info(&cpu_data(0));
1096 x86_init.timers.setup_percpu_clockev();
1101 set_mtrr_aps_delayed_init();
1106 void arch_disable_nonboot_cpus_begin(void)
1109 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1110 * In the suspend path, we will be back in the SMP mode shortly anyways.
1112 skip_smp_alternatives = true;
1115 void arch_disable_nonboot_cpus_end(void)
1117 skip_smp_alternatives = false;
1120 void arch_enable_nonboot_cpus_begin(void)
1122 set_mtrr_aps_delayed_init();
1125 void arch_enable_nonboot_cpus_end(void)
1131 * Early setup to make printk work.
1133 void __init native_smp_prepare_boot_cpu(void)
1135 int me = smp_processor_id();
1136 switch_to_new_gdt(me);
1137 /* already set me in cpu_online_mask in boot_cpu_init() */
1138 cpumask_set_cpu(me, cpu_callout_mask);
1139 per_cpu(cpu_state, me) = CPU_ONLINE;
1142 void __init native_smp_cpus_done(unsigned int max_cpus)
1144 pr_debug("Boot done.\n");
1148 #ifdef CONFIG_X86_IO_APIC
1149 setup_ioapic_dest();
1154 static int __initdata setup_possible_cpus = -1;
1155 static int __init _setup_possible_cpus(char *str)
1157 get_option(&str, &setup_possible_cpus);
1160 early_param("possible_cpus", _setup_possible_cpus);
1164 * cpu_possible_mask should be static, it cannot change as cpu's
1165 * are onlined, or offlined. The reason is per-cpu data-structures
1166 * are allocated by some modules at init time, and dont expect to
1167 * do this dynamically on cpu arrival/departure.
1168 * cpu_present_mask on the other hand can change dynamically.
1169 * In case when cpu_hotplug is not compiled, then we resort to current
1170 * behaviour, which is cpu_possible == cpu_present.
1173 * Three ways to find out the number of additional hotplug CPUs:
1174 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1175 * - The user can overwrite it with possible_cpus=NUM
1176 * - Otherwise don't reserve additional CPUs.
1177 * We do this because additional CPUs waste a lot of memory.
1180 __init void prefill_possible_map(void)
1184 /* no processor from mptable or madt */
1185 if (!num_processors)
1188 i = setup_max_cpus ?: 1;
1189 if (setup_possible_cpus == -1) {
1190 possible = num_processors;
1191 #ifdef CONFIG_HOTPLUG_CPU
1193 possible += disabled_cpus;
1199 possible = setup_possible_cpus;
1201 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1203 /* nr_cpu_ids could be reduced via nr_cpus= */
1204 if (possible > nr_cpu_ids) {
1206 "%d Processors exceeds NR_CPUS limit of %d\n",
1207 possible, nr_cpu_ids);
1208 possible = nr_cpu_ids;
1211 #ifdef CONFIG_HOTPLUG_CPU
1212 if (!setup_max_cpus)
1216 "%d Processors exceeds max_cpus limit of %u\n",
1217 possible, setup_max_cpus);
1221 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1222 possible, max_t(int, possible - num_processors, 0));
1224 for (i = 0; i < possible; i++)
1225 set_cpu_possible(i, true);
1226 for (; i < NR_CPUS; i++)
1227 set_cpu_possible(i, false);
1229 nr_cpu_ids = possible;
1232 #ifdef CONFIG_HOTPLUG_CPU
1234 static void remove_siblinginfo(int cpu)
1237 struct cpuinfo_x86 *c = &cpu_data(cpu);
1239 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1240 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1242 * last thread sibling in this cpu core going down
1244 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1245 cpu_data(sibling).booted_cores--;
1248 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1249 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1250 cpumask_clear(cpu_sibling_mask(cpu));
1251 cpumask_clear(cpu_core_mask(cpu));
1252 c->phys_proc_id = 0;
1254 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1257 static void __ref remove_cpu_from_maps(int cpu)
1259 set_cpu_online(cpu, false);
1260 cpumask_clear_cpu(cpu, cpu_callout_mask);
1261 cpumask_clear_cpu(cpu, cpu_callin_mask);
1262 /* was set by cpu_init() */
1263 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1264 numa_remove_cpu(cpu);
1267 void cpu_disable_common(void)
1269 int cpu = smp_processor_id();
1271 remove_siblinginfo(cpu);
1273 /* It's now safe to remove this processor from the online map */
1275 remove_cpu_from_maps(cpu);
1276 unlock_vector_lock();
1280 int native_cpu_disable(void)
1282 int cpu = smp_processor_id();
1285 * Perhaps use cpufreq to drop frequency, but that could go
1286 * into generic code.
1288 * We won't take down the boot processor on i386 due to some
1289 * interrupts only being able to be serviced by the BSP.
1290 * Especially so if we're not using an IOAPIC -zwane
1297 cpu_disable_common();
1301 void native_cpu_die(unsigned int cpu)
1303 /* We don't do anything here: idle task is faking death itself. */
1306 for (i = 0; i < 10; i++) {
1307 /* They ack this in play_dead by setting CPU_DEAD */
1308 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1309 if (system_state == SYSTEM_RUNNING)
1310 pr_info("CPU %u is now offline\n", cpu);
1312 if (1 == num_online_cpus())
1313 alternatives_smp_switch(0);
1318 pr_err("CPU %u didn't die...\n", cpu);
1321 void play_dead_common(void)
1324 reset_lazy_tlbstate();
1325 amd_e400_remove_cpu(raw_smp_processor_id());
1329 __this_cpu_write(cpu_state, CPU_DEAD);
1332 * With physical CPU hotplug, we should halt the cpu
1334 local_irq_disable();
1338 * We need to flush the caches before going to sleep, lest we have
1339 * dirty data in our caches when we come back up.
1341 static inline void mwait_play_dead(void)
1343 unsigned int eax, ebx, ecx, edx;
1344 unsigned int highest_cstate = 0;
1345 unsigned int highest_subcstate = 0;
1348 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1350 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1352 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1354 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1357 eax = CPUID_MWAIT_LEAF;
1359 native_cpuid(&eax, &ebx, &ecx, &edx);
1362 * eax will be 0 if EDX enumeration is not valid.
1363 * Initialized below to cstate, sub_cstate value when EDX is valid.
1365 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1368 edx >>= MWAIT_SUBSTATE_SIZE;
1369 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1370 if (edx & MWAIT_SUBSTATE_MASK) {
1372 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1375 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1376 (highest_subcstate - 1);
1380 * This should be a memory location in a cache line which is
1381 * unlikely to be touched by other processors. The actual
1382 * content is immaterial as it is not actually modified in any way.
1384 mwait_ptr = ¤t_thread_info()->flags;
1390 * The CLFLUSH is a workaround for erratum AAI65 for
1391 * the Xeon 7400 series. It's not clear it is actually
1392 * needed, but it should be harmless in either case.
1393 * The WBINVD is insufficient due to the spurious-wakeup
1394 * case where we return around the loop.
1397 __monitor(mwait_ptr, 0, 0);
1403 static inline void hlt_play_dead(void)
1405 if (__this_cpu_read(cpu_info.x86) >= 4)
1413 void native_play_dead(void)
1416 tboot_shutdown(TB_SHUTDOWN_WFS);
1418 mwait_play_dead(); /* Only returns on failure */
1419 if (cpuidle_play_dead())
1423 #else /* ... !CONFIG_HOTPLUG_CPU */
1424 int native_cpu_disable(void)
1429 void native_cpu_die(unsigned int cpu)
1431 /* We said "no" in __cpu_disable */
1435 void native_play_dead(void)