2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53 #include <linux/cpuidle.h>
60 #include <asm/trampoline.h>
63 #include <asm/pgtable.h>
64 #include <asm/tlbflush.h>
66 #include <asm/mwait.h>
68 #include <asm/io_apic.h>
69 #include <asm/setup.h>
70 #include <asm/uv/uv.h>
71 #include <linux/mc146818rtc.h>
73 #include <asm/smpboot_hooks.h>
74 #include <asm/i8259.h>
76 /* State of each CPU */
77 DEFINE_PER_CPU(int, cpu_state) = { 0 };
79 /* Store all idle threads, this can be reused instead of creating
80 * a new thread. Also avoids complicated thread destroy functionality
83 #ifdef CONFIG_HOTPLUG_CPU
85 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
86 * removed after init for !CONFIG_HOTPLUG_CPU.
88 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
89 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
90 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
93 * We need this for trampoline_base protection from concurrent accesses when
94 * off- and onlining cores wildly.
96 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
98 void cpu_hotplug_driver_lock(void)
100 mutex_lock(&x86_cpu_hotplug_driver_mutex);
103 void cpu_hotplug_driver_unlock(void)
105 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
108 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
109 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
111 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
112 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
113 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
116 /* Number of siblings per CPU package */
117 int smp_num_siblings = 1;
118 EXPORT_SYMBOL(smp_num_siblings);
120 /* Last level cache ID of each logical CPU */
121 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
123 /* representing HT siblings of each logical CPU */
124 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
125 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
127 /* representing HT and core siblings of each logical CPU */
128 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
129 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
131 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
133 /* Per CPU bogomips and other parameters */
134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
135 EXPORT_PER_CPU_SYMBOL(cpu_info);
137 atomic_t init_deasserted;
140 * Report back to the Boot Processor.
143 static void __cpuinit smp_callin(void)
146 unsigned long timeout;
149 * If waken up by an INIT in an 82489DX configuration
150 * we may get here before an INIT-deassert IPI reaches
151 * our local APIC. We have to wait for the IPI or we'll
152 * lock up on an APIC access.
154 if (apic->wait_for_init_deassert)
155 apic->wait_for_init_deassert(&init_deasserted);
158 * (This works even if the APIC is not enabled.)
160 phys_id = read_apic_id();
161 cpuid = smp_processor_id();
162 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
163 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
166 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
169 * STARTUP IPIs are fragile beasts as they might sometimes
170 * trigger some glue motherboard logic. Complete APIC bus
171 * silence for 1 second, this overestimates the time the
172 * boot CPU is spending to send the up to 2 STARTUP IPIs
173 * by a factor of two. This should be enough.
177 * Waiting 2s total for startup (udelay is not yet working)
179 timeout = jiffies + 2*HZ;
180 while (time_before(jiffies, timeout)) {
182 * Has the boot CPU finished it's STARTUP sequence?
184 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
189 if (!time_before(jiffies, timeout)) {
190 panic("%s: CPU%d started up but did not get a callout!\n",
195 * the boot CPU has finished the init stage and is spinning
196 * on callin_map until we finish. We are free to set up this
197 * CPU, first the APIC. (this is probably redundant on most
201 pr_debug("CALLIN, before setup_local_APIC().\n");
202 if (apic->smp_callin_clear_local_apic)
203 apic->smp_callin_clear_local_apic();
205 end_local_APIC_setup();
208 * Need to setup vector mappings before we enable interrupts.
210 setup_vector_irq(smp_processor_id());
213 * Save our processor parameters. Note: this information
214 * is needed for clock calibration.
216 smp_store_cpu_info(cpuid);
220 * Update loops_per_jiffy in cpu_data. Previous call to
221 * smp_store_cpu_info() stored a value that is close but not as
222 * accurate as the value just calculated.
225 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
226 pr_debug("Stack at about %p\n", &cpuid);
229 * This must be done before setting cpu_online_mask
230 * or calling notify_cpu_starting.
232 set_cpu_sibling_map(raw_smp_processor_id());
235 notify_cpu_starting(cpuid);
238 * Allow the master to continue.
240 cpumask_set_cpu(cpuid, cpu_callin_mask);
244 * Activate a secondary processor.
246 notrace static void __cpuinit start_secondary(void *unused)
249 * Don't put *anything* before cpu_init(), SMP booting is too
250 * fragile that we want to limit the things done here to the
251 * most necessary things.
254 x86_cpuinit.early_percpu_clock_init();
259 /* switch away from the initial page table */
260 load_cr3(swapper_pg_dir);
264 /* otherwise gcc will move up smp_processor_id before the cpu_init */
267 * Check TSC synchronization with the BP:
269 check_tsc_sync_target();
272 * We need to hold call_lock, so there is no inconsistency
273 * between the time smp_call_function() determines number of
274 * IPI recipients, and the time when the determination is made
275 * for which cpus receive the IPI. Holding this
276 * lock helps us to not include this cpu in a currently in progress
277 * smp_call_function().
279 * We need to hold vector_lock so there the set of online cpus
280 * does not change while we are assigning vectors to cpus. Holding
281 * this lock ensures we don't half assign or remove an irq from a cpu.
285 set_cpu_online(smp_processor_id(), true);
286 unlock_vector_lock();
288 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
289 x86_platform.nmi_init();
291 /* enable local interrupts */
294 /* to prevent fake stack check failure in clock setup */
295 boot_init_stack_canary();
297 x86_cpuinit.setup_percpu_clockev();
304 * The bootstrap kernel entry code has set these up. Save them for
308 void __cpuinit smp_store_cpu_info(int id)
310 struct cpuinfo_x86 *c = &cpu_data(id);
315 identify_secondary_cpu(c);
318 static bool __cpuinit
319 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
321 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
323 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
324 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
325 "[node: %d != %d]. Ignoring dependency.\n",
326 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
329 #define link_mask(_m, c1, c2) \
331 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
332 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
335 static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
337 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
338 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
340 if (c->phys_proc_id == o->phys_proc_id &&
341 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
342 c->compute_unit_id == o->compute_unit_id)
343 return topology_sane(c, o, "smt");
345 } else if (c->phys_proc_id == o->phys_proc_id &&
346 c->cpu_core_id == o->cpu_core_id) {
347 return topology_sane(c, o, "smt");
353 static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
355 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
357 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
358 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
359 return topology_sane(c, o, "llc");
364 static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
366 if (c->phys_proc_id == o->phys_proc_id)
367 return topology_sane(c, o, "mc");
372 void __cpuinit set_cpu_sibling_map(int cpu)
374 bool has_mc = boot_cpu_data.x86_max_cores > 1;
375 bool has_smt = smp_num_siblings > 1;
376 struct cpuinfo_x86 *c = &cpu_data(cpu);
377 struct cpuinfo_x86 *o;
380 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
382 if (!has_smt && !has_mc) {
383 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
384 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
385 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
390 for_each_cpu(i, cpu_sibling_setup_mask) {
393 if ((i == cpu) || (has_smt && match_smt(c, o)))
394 link_mask(sibling, cpu, i);
396 if ((i == cpu) || (has_mc && match_llc(c, o)))
397 link_mask(llc_shared, cpu, i);
399 if ((i == cpu) || (has_mc && match_mc(c, o))) {
400 link_mask(core, cpu, i);
403 * Does this new cpu bringup a new core?
405 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
407 * for each core in package, increment
408 * the booted_cores for this new cpu
410 if (cpumask_first(cpu_sibling_mask(i)) == i)
413 * increment the core count for all
414 * the other cpus in this package
417 cpu_data(i).booted_cores++;
418 } else if (i != cpu && !c->booted_cores)
419 c->booted_cores = cpu_data(i).booted_cores;
424 /* maps the cpu to the sched domain representing multi-core */
425 const struct cpumask *cpu_coregroup_mask(int cpu)
427 struct cpuinfo_x86 *c = &cpu_data(cpu);
429 * For perf, we return last level cache shared map.
430 * And for power savings, we return cpu_core_map
432 if ((sched_mc_power_savings || sched_smt_power_savings) &&
433 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
434 return cpu_core_mask(cpu);
436 return cpu_llc_shared_mask(cpu);
439 static void impress_friends(void)
442 unsigned long bogosum = 0;
444 * Allow the user to impress friends.
446 pr_debug("Before bogomips.\n");
447 for_each_possible_cpu(cpu)
448 if (cpumask_test_cpu(cpu, cpu_callout_mask))
449 bogosum += cpu_data(cpu).loops_per_jiffy;
451 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
454 (bogosum/(5000/HZ))%100);
456 pr_debug("Before bogocount - setting activated=1.\n");
459 void __inquire_remote_apic(int apicid)
461 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
462 const char * const names[] = { "ID", "VERSION", "SPIV" };
466 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
468 for (i = 0; i < ARRAY_SIZE(regs); i++) {
469 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
474 status = safe_apic_wait_icr_idle();
477 "a previous APIC delivery may have failed\n");
479 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
484 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
485 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
488 case APIC_ICR_RR_VALID:
489 status = apic_read(APIC_RRR);
490 printk(KERN_CONT "%08x\n", status);
493 printk(KERN_CONT "failed\n");
499 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
500 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
501 * won't ... remember to clear down the APIC, etc later.
504 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
506 unsigned long send_status, accept_status = 0;
510 /* Boot on the stack */
511 /* Kick the second */
512 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
514 pr_debug("Waiting for send to finish...\n");
515 send_status = safe_apic_wait_icr_idle();
518 * Give the other CPU some time to accept the IPI.
521 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
522 maxlvt = lapic_get_maxlvt();
523 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
524 apic_write(APIC_ESR, 0);
525 accept_status = (apic_read(APIC_ESR) & 0xEF);
527 pr_debug("NMI sent.\n");
530 printk(KERN_ERR "APIC never delivered???\n");
532 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
534 return (send_status | accept_status);
538 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
540 unsigned long send_status, accept_status = 0;
541 int maxlvt, num_starts, j;
543 maxlvt = lapic_get_maxlvt();
546 * Be paranoid about clearing APIC errors.
548 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
549 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
550 apic_write(APIC_ESR, 0);
554 pr_debug("Asserting INIT.\n");
557 * Turn INIT on target chip
562 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
565 pr_debug("Waiting for send to finish...\n");
566 send_status = safe_apic_wait_icr_idle();
570 pr_debug("Deasserting INIT.\n");
574 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
576 pr_debug("Waiting for send to finish...\n");
577 send_status = safe_apic_wait_icr_idle();
580 atomic_set(&init_deasserted, 1);
583 * Should we send STARTUP IPIs ?
585 * Determine this based on the APIC version.
586 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
588 if (APIC_INTEGRATED(apic_version[phys_apicid]))
594 * Paravirt / VMI wants a startup IPI hook here to set up the
595 * target processor state.
597 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
601 * Run STARTUP IPI loop.
603 pr_debug("#startup loops: %d.\n", num_starts);
605 for (j = 1; j <= num_starts; j++) {
606 pr_debug("Sending STARTUP #%d.\n", j);
607 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
608 apic_write(APIC_ESR, 0);
610 pr_debug("After apic_write.\n");
617 /* Boot on the stack */
618 /* Kick the second */
619 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
623 * Give the other CPU some time to accept the IPI.
627 pr_debug("Startup point 1.\n");
629 pr_debug("Waiting for send to finish...\n");
630 send_status = safe_apic_wait_icr_idle();
633 * Give the other CPU some time to accept the IPI.
636 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
637 apic_write(APIC_ESR, 0);
638 accept_status = (apic_read(APIC_ESR) & 0xEF);
639 if (send_status || accept_status)
642 pr_debug("After Startup.\n");
645 printk(KERN_ERR "APIC never delivered???\n");
647 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
649 return (send_status | accept_status);
653 struct work_struct work;
654 struct task_struct *idle;
655 struct completion done;
659 static void __cpuinit do_fork_idle(struct work_struct *work)
661 struct create_idle *c_idle =
662 container_of(work, struct create_idle, work);
664 c_idle->idle = fork_idle(c_idle->cpu);
665 complete(&c_idle->done);
668 /* reduce the number of lines printed when booting a large cpu count system */
669 static void __cpuinit announce_cpu(int cpu, int apicid)
671 static int current_node = -1;
672 int node = early_cpu_to_node(cpu);
674 if (system_state == SYSTEM_BOOTING) {
675 if (node != current_node) {
676 if (current_node > (-1))
679 pr_info("Booting Node %3d, Processors ", node);
681 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
684 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
689 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
690 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
691 * Returns zero if CPU booted OK, else error code from
692 * ->wakeup_secondary_cpu.
694 static int __cpuinit do_boot_cpu(int apicid, int cpu)
696 unsigned long boot_error = 0;
697 unsigned long start_ip;
699 struct create_idle c_idle = {
701 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
704 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
706 alternatives_smp_switch(1);
708 c_idle.idle = get_idle_for_cpu(cpu);
711 * We can't use kernel_thread since we must avoid to
712 * reschedule the child.
715 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
716 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
717 init_idle(c_idle.idle, cpu);
721 schedule_work(&c_idle.work);
722 wait_for_completion(&c_idle.done);
724 if (IS_ERR(c_idle.idle)) {
725 printk("failed fork for CPU %d\n", cpu);
726 destroy_work_on_stack(&c_idle.work);
727 return PTR_ERR(c_idle.idle);
730 set_idle_for_cpu(cpu, c_idle.idle);
732 per_cpu(current_task, cpu) = c_idle.idle;
734 /* Stack for startup_32 can be just as for start_secondary onwards */
737 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
738 initial_gs = per_cpu_offset(cpu);
739 per_cpu(kernel_stack, cpu) =
740 (unsigned long)task_stack_page(c_idle.idle) -
741 KERNEL_STACK_OFFSET + THREAD_SIZE;
743 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
744 initial_code = (unsigned long)start_secondary;
745 stack_start = c_idle.idle->thread.sp;
747 /* start_ip had better be page-aligned! */
748 start_ip = trampoline_address();
750 /* So we see what's up */
751 announce_cpu(cpu, apicid);
754 * This grunge runs the startup process for
755 * the targeted processor.
758 atomic_set(&init_deasserted, 0);
760 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
762 pr_debug("Setting warm reset code and vector.\n");
764 smpboot_setup_warm_reset_vector(start_ip);
766 * Be paranoid about clearing APIC errors.
768 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
769 apic_write(APIC_ESR, 0);
775 * Kick the secondary CPU. Use the method in the APIC driver
776 * if it's defined - or use an INIT boot APIC message otherwise:
778 if (apic->wakeup_secondary_cpu)
779 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
781 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
785 * allow APs to start initializing.
787 pr_debug("Before Callout %d.\n", cpu);
788 cpumask_set_cpu(cpu, cpu_callout_mask);
789 pr_debug("After Callout %d.\n", cpu);
792 * Wait 5s total for a response
794 for (timeout = 0; timeout < 50000; timeout++) {
795 if (cpumask_test_cpu(cpu, cpu_callin_mask))
796 break; /* It has booted */
799 * Allow other tasks to run while we wait for the
800 * AP to come online. This also gives a chance
801 * for the MTRR work(triggered by the AP coming online)
802 * to be completed in the stop machine context.
807 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
808 print_cpu_msr(&cpu_data(cpu));
809 pr_debug("CPU%d: has booted.\n", cpu);
812 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
814 /* trampoline started but...? */
815 pr_err("CPU%d: Stuck ??\n", cpu);
817 /* trampoline code not run */
818 pr_err("CPU%d: Not responding.\n", cpu);
819 if (apic->inquire_remote_apic)
820 apic->inquire_remote_apic(apicid);
825 /* Try to put things back the way they were before ... */
826 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
828 /* was set by do_boot_cpu() */
829 cpumask_clear_cpu(cpu, cpu_callout_mask);
831 /* was set by cpu_init() */
832 cpumask_clear_cpu(cpu, cpu_initialized_mask);
834 set_cpu_present(cpu, false);
835 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
838 /* mark "stuck" area as not stuck */
839 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
841 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
843 * Cleanup possible dangling ends...
845 smpboot_restore_warm_reset_vector();
848 destroy_work_on_stack(&c_idle.work);
852 int __cpuinit native_cpu_up(unsigned int cpu)
854 int apicid = apic->cpu_present_to_apicid(cpu);
858 WARN_ON(irqs_disabled());
860 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
862 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
863 !physid_isset(apicid, phys_cpu_present_map) ||
864 !apic->apic_id_valid(apicid)) {
865 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
870 * Already booted CPU?
872 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
873 pr_debug("do_boot_cpu %d Already started\n", cpu);
878 * Save current MTRR state in case it was changed since early boot
879 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
883 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
885 err = do_boot_cpu(apicid, cpu);
887 pr_debug("do_boot_cpu failed %d\n", err);
892 * Check TSC synchronization with the AP (keep irqs disabled
895 local_irq_save(flags);
896 check_tsc_sync_source(cpu);
897 local_irq_restore(flags);
899 while (!cpu_online(cpu)) {
901 touch_nmi_watchdog();
908 * arch_disable_smp_support() - disables SMP support for x86 at runtime
910 void arch_disable_smp_support(void)
912 disable_ioapic_support();
916 * Fall back to non SMP mode after errors.
918 * RED-PEN audit/test this more. I bet there is more state messed up here.
920 static __init void disable_smp(void)
922 init_cpu_present(cpumask_of(0));
923 init_cpu_possible(cpumask_of(0));
924 smpboot_clear_io_apic_irqs();
926 if (smp_found_config)
927 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
929 physid_set_mask_of_physid(0, &phys_cpu_present_map);
930 cpumask_set_cpu(0, cpu_sibling_mask(0));
931 cpumask_set_cpu(0, cpu_core_mask(0));
935 * Various sanity checks.
937 static int __init smp_sanity_check(unsigned max_cpus)
941 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
942 if (def_to_bigsmp && nr_cpu_ids > 8) {
947 "More than 8 CPUs detected - skipping them.\n"
948 "Use CONFIG_X86_BIGSMP.\n");
951 for_each_present_cpu(cpu) {
953 set_cpu_present(cpu, false);
958 for_each_possible_cpu(cpu) {
960 set_cpu_possible(cpu, false);
968 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
970 "weird, boot CPU (#%d) not listed by the BIOS.\n",
971 hard_smp_processor_id());
973 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
977 * If we couldn't find an SMP configuration at boot time,
978 * get out of here now!
980 if (!smp_found_config && !acpi_lapic) {
982 printk(KERN_NOTICE "SMP motherboard not detected.\n");
984 if (APIC_init_uniprocessor())
985 printk(KERN_NOTICE "Local APIC not detected."
986 " Using dummy APIC emulation.\n");
991 * Should not be necessary because the MP table should list the boot
992 * CPU too, but we do it for the sake of robustness anyway.
994 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
996 "weird, boot CPU (#%d) not listed by the BIOS.\n",
997 boot_cpu_physical_apicid);
998 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1003 * If we couldn't find a local APIC, then get out of here now!
1005 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1007 if (!disable_apic) {
1008 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1009 boot_cpu_physical_apicid);
1010 pr_err("... forcing use of dummy APIC emulation."
1011 "(tell your hw vendor)\n");
1013 smpboot_clear_io_apic();
1014 disable_ioapic_support();
1018 verify_local_APIC();
1021 * If SMP should be disabled, then really disable it!
1024 printk(KERN_INFO "SMP mode deactivated.\n");
1025 smpboot_clear_io_apic();
1029 bsp_end_local_APIC_setup();
1036 static void __init smp_cpu_index_default(void)
1039 struct cpuinfo_x86 *c;
1041 for_each_possible_cpu(i) {
1043 /* mark all to hotplug */
1044 c->cpu_index = nr_cpu_ids;
1049 * Prepare for SMP bootup. The MP table or ACPI has been read
1050 * earlier. Just do some sanity checking here and enable APIC mode.
1052 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1057 smp_cpu_index_default();
1060 * Setup boot CPU information
1062 smp_store_cpu_info(0); /* Final full version of the data */
1063 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1066 current_thread_info()->cpu = 0; /* needed? */
1067 for_each_possible_cpu(i) {
1068 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1069 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1070 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1072 set_cpu_sibling_map(0);
1075 if (smp_sanity_check(max_cpus) < 0) {
1076 printk(KERN_INFO "SMP disabled\n");
1081 default_setup_apic_routing();
1084 if (read_apic_id() != boot_cpu_physical_apicid) {
1085 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1086 read_apic_id(), boot_cpu_physical_apicid);
1087 /* Or can we switch back to PIC here? */
1094 * Switch from PIC to APIC mode.
1099 * Enable IO APIC before setting up error vector
1101 if (!skip_ioapic_setup && nr_ioapics)
1104 bsp_end_local_APIC_setup();
1106 if (apic->setup_portio_remap)
1107 apic->setup_portio_remap();
1109 smpboot_setup_io_apic();
1111 * Set up local APIC timer on boot CPU.
1114 printk(KERN_INFO "CPU%d: ", 0);
1115 print_cpu_info(&cpu_data(0));
1116 x86_init.timers.setup_percpu_clockev();
1121 set_mtrr_aps_delayed_init();
1126 void arch_disable_nonboot_cpus_begin(void)
1129 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1130 * In the suspend path, we will be back in the SMP mode shortly anyways.
1132 skip_smp_alternatives = true;
1135 void arch_disable_nonboot_cpus_end(void)
1137 skip_smp_alternatives = false;
1140 void arch_enable_nonboot_cpus_begin(void)
1142 set_mtrr_aps_delayed_init();
1145 void arch_enable_nonboot_cpus_end(void)
1151 * Early setup to make printk work.
1153 void __init native_smp_prepare_boot_cpu(void)
1155 int me = smp_processor_id();
1156 switch_to_new_gdt(me);
1157 /* already set me in cpu_online_mask in boot_cpu_init() */
1158 cpumask_set_cpu(me, cpu_callout_mask);
1159 per_cpu(cpu_state, me) = CPU_ONLINE;
1162 void __init native_smp_cpus_done(unsigned int max_cpus)
1164 pr_debug("Boot done.\n");
1168 #ifdef CONFIG_X86_IO_APIC
1169 setup_ioapic_dest();
1174 static int __initdata setup_possible_cpus = -1;
1175 static int __init _setup_possible_cpus(char *str)
1177 get_option(&str, &setup_possible_cpus);
1180 early_param("possible_cpus", _setup_possible_cpus);
1184 * cpu_possible_mask should be static, it cannot change as cpu's
1185 * are onlined, or offlined. The reason is per-cpu data-structures
1186 * are allocated by some modules at init time, and dont expect to
1187 * do this dynamically on cpu arrival/departure.
1188 * cpu_present_mask on the other hand can change dynamically.
1189 * In case when cpu_hotplug is not compiled, then we resort to current
1190 * behaviour, which is cpu_possible == cpu_present.
1193 * Three ways to find out the number of additional hotplug CPUs:
1194 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1195 * - The user can overwrite it with possible_cpus=NUM
1196 * - Otherwise don't reserve additional CPUs.
1197 * We do this because additional CPUs waste a lot of memory.
1200 __init void prefill_possible_map(void)
1204 /* no processor from mptable or madt */
1205 if (!num_processors)
1208 i = setup_max_cpus ?: 1;
1209 if (setup_possible_cpus == -1) {
1210 possible = num_processors;
1211 #ifdef CONFIG_HOTPLUG_CPU
1213 possible += disabled_cpus;
1219 possible = setup_possible_cpus;
1221 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1223 /* nr_cpu_ids could be reduced via nr_cpus= */
1224 if (possible > nr_cpu_ids) {
1226 "%d Processors exceeds NR_CPUS limit of %d\n",
1227 possible, nr_cpu_ids);
1228 possible = nr_cpu_ids;
1231 #ifdef CONFIG_HOTPLUG_CPU
1232 if (!setup_max_cpus)
1236 "%d Processors exceeds max_cpus limit of %u\n",
1237 possible, setup_max_cpus);
1241 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1242 possible, max_t(int, possible - num_processors, 0));
1244 for (i = 0; i < possible; i++)
1245 set_cpu_possible(i, true);
1246 for (; i < NR_CPUS; i++)
1247 set_cpu_possible(i, false);
1249 nr_cpu_ids = possible;
1252 #ifdef CONFIG_HOTPLUG_CPU
1254 static void remove_siblinginfo(int cpu)
1257 struct cpuinfo_x86 *c = &cpu_data(cpu);
1259 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1260 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1262 * last thread sibling in this cpu core going down
1264 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1265 cpu_data(sibling).booted_cores--;
1268 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1269 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1270 cpumask_clear(cpu_sibling_mask(cpu));
1271 cpumask_clear(cpu_core_mask(cpu));
1272 c->phys_proc_id = 0;
1274 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1277 static void __ref remove_cpu_from_maps(int cpu)
1279 set_cpu_online(cpu, false);
1280 cpumask_clear_cpu(cpu, cpu_callout_mask);
1281 cpumask_clear_cpu(cpu, cpu_callin_mask);
1282 /* was set by cpu_init() */
1283 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1284 numa_remove_cpu(cpu);
1287 void cpu_disable_common(void)
1289 int cpu = smp_processor_id();
1291 remove_siblinginfo(cpu);
1293 /* It's now safe to remove this processor from the online map */
1295 remove_cpu_from_maps(cpu);
1296 unlock_vector_lock();
1300 int native_cpu_disable(void)
1302 int cpu = smp_processor_id();
1305 * Perhaps use cpufreq to drop frequency, but that could go
1306 * into generic code.
1308 * We won't take down the boot processor on i386 due to some
1309 * interrupts only being able to be serviced by the BSP.
1310 * Especially so if we're not using an IOAPIC -zwane
1317 cpu_disable_common();
1321 void native_cpu_die(unsigned int cpu)
1323 /* We don't do anything here: idle task is faking death itself. */
1326 for (i = 0; i < 10; i++) {
1327 /* They ack this in play_dead by setting CPU_DEAD */
1328 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1329 if (system_state == SYSTEM_RUNNING)
1330 pr_info("CPU %u is now offline\n", cpu);
1332 if (1 == num_online_cpus())
1333 alternatives_smp_switch(0);
1338 pr_err("CPU %u didn't die...\n", cpu);
1341 void play_dead_common(void)
1344 reset_lazy_tlbstate();
1345 amd_e400_remove_cpu(raw_smp_processor_id());
1349 __this_cpu_write(cpu_state, CPU_DEAD);
1352 * With physical CPU hotplug, we should halt the cpu
1354 local_irq_disable();
1358 * We need to flush the caches before going to sleep, lest we have
1359 * dirty data in our caches when we come back up.
1361 static inline void mwait_play_dead(void)
1363 unsigned int eax, ebx, ecx, edx;
1364 unsigned int highest_cstate = 0;
1365 unsigned int highest_subcstate = 0;
1368 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1370 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1372 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1374 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1377 eax = CPUID_MWAIT_LEAF;
1379 native_cpuid(&eax, &ebx, &ecx, &edx);
1382 * eax will be 0 if EDX enumeration is not valid.
1383 * Initialized below to cstate, sub_cstate value when EDX is valid.
1385 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1388 edx >>= MWAIT_SUBSTATE_SIZE;
1389 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1390 if (edx & MWAIT_SUBSTATE_MASK) {
1392 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1395 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1396 (highest_subcstate - 1);
1400 * This should be a memory location in a cache line which is
1401 * unlikely to be touched by other processors. The actual
1402 * content is immaterial as it is not actually modified in any way.
1404 mwait_ptr = ¤t_thread_info()->flags;
1410 * The CLFLUSH is a workaround for erratum AAI65 for
1411 * the Xeon 7400 series. It's not clear it is actually
1412 * needed, but it should be harmless in either case.
1413 * The WBINVD is insufficient due to the spurious-wakeup
1414 * case where we return around the loop.
1417 __monitor(mwait_ptr, 0, 0);
1423 static inline void hlt_play_dead(void)
1425 if (__this_cpu_read(cpu_info.x86) >= 4)
1433 void native_play_dead(void)
1436 tboot_shutdown(TB_SHUTDOWN_WFS);
1438 mwait_play_dead(); /* Only returns on failure */
1439 if (cpuidle_play_dead())
1443 #else /* ... !CONFIG_HOTPLUG_CPU */
1444 int native_cpu_disable(void)
1449 void native_cpu_die(unsigned int cpu)
1451 /* We said "no" in __cpu_disable */
1455 void native_play_dead(void)