2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
67 #include <asm/io_apic.h>
68 #include <asm/setup.h>
69 #include <asm/uv/uv.h>
70 #include <linux/mc146818rtc.h>
72 #include <asm/smpboot_hooks.h>
73 #include <asm/i8259.h>
75 /* State of each CPU */
76 DEFINE_PER_CPU(int, cpu_state) = { 0 };
78 /* Store all idle threads, this can be reused instead of creating
79 * a new thread. Also avoids complicated thread destroy functionality
82 #ifdef CONFIG_HOTPLUG_CPU
84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
85 * removed after init for !CONFIG_HOTPLUG_CPU.
87 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
88 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
89 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
92 * We need this for trampoline_base protection from concurrent accesses when
93 * off- and onlining cores wildly.
95 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
97 void cpu_hotplug_driver_lock(void)
99 mutex_lock(&x86_cpu_hotplug_driver_mutex);
102 void cpu_hotplug_driver_unlock(void)
104 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
107 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
108 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
110 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
111 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
112 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
115 /* Number of siblings per CPU package */
116 int smp_num_siblings = 1;
117 EXPORT_SYMBOL(smp_num_siblings);
119 /* Last level cache ID of each logical CPU */
120 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
122 /* representing HT siblings of each logical CPU */
123 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
124 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
126 /* representing HT and core siblings of each logical CPU */
127 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
128 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
130 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
132 /* Per CPU bogomips and other parameters */
133 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
134 EXPORT_PER_CPU_SYMBOL(cpu_info);
136 atomic_t init_deasserted;
139 * Report back to the Boot Processor.
142 static void __cpuinit smp_callin(void)
145 unsigned long timeout;
148 * If waken up by an INIT in an 82489DX configuration
149 * we may get here before an INIT-deassert IPI reaches
150 * our local APIC. We have to wait for the IPI or we'll
151 * lock up on an APIC access.
153 if (apic->wait_for_init_deassert)
154 apic->wait_for_init_deassert(&init_deasserted);
157 * (This works even if the APIC is not enabled.)
159 phys_id = read_apic_id();
160 cpuid = smp_processor_id();
161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
168 * STARTUP IPIs are fragile beasts as they might sometimes
169 * trigger some glue motherboard logic. Complete APIC bus
170 * silence for 1 second, this overestimates the time the
171 * boot CPU is spending to send the up to 2 STARTUP IPIs
172 * by a factor of two. This should be enough.
176 * Waiting 2s total for startup (udelay is not yet working)
178 timeout = jiffies + 2*HZ;
179 while (time_before(jiffies, timeout)) {
181 * Has the boot CPU finished it's STARTUP sequence?
183 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
188 if (!time_before(jiffies, timeout)) {
189 panic("%s: CPU%d started up but did not get a callout!\n",
194 * the boot CPU has finished the init stage and is spinning
195 * on callin_map until we finish. We are free to set up this
196 * CPU, first the APIC. (this is probably redundant on most
200 pr_debug("CALLIN, before setup_local_APIC().\n");
201 if (apic->smp_callin_clear_local_apic)
202 apic->smp_callin_clear_local_apic();
204 end_local_APIC_setup();
207 * Need to setup vector mappings before we enable interrupts.
209 setup_vector_irq(smp_processor_id());
213 * Need to enable IRQs because it can take longer and then
214 * the NMI watchdog might kill us.
219 pr_debug("Stack at about %p\n", &cpuid);
222 * Save our processor parameters
224 smp_store_cpu_info(cpuid);
227 * This must be done before setting cpu_online_mask
228 * or calling notify_cpu_starting.
230 set_cpu_sibling_map(raw_smp_processor_id());
233 notify_cpu_starting(cpuid);
236 * Allow the master to continue.
238 cpumask_set_cpu(cpuid, cpu_callin_mask);
242 * Activate a secondary processor.
244 notrace static void __cpuinit start_secondary(void *unused)
247 * Don't put *anything* before cpu_init(), SMP booting is too
248 * fragile that we want to limit the things done here to the
249 * most necessary things.
256 /* switch away from the initial page table */
257 load_cr3(swapper_pg_dir);
261 /* otherwise gcc will move up smp_processor_id before the cpu_init */
264 * Check TSC synchronization with the BP:
266 check_tsc_sync_target();
269 * We need to hold call_lock, so there is no inconsistency
270 * between the time smp_call_function() determines number of
271 * IPI recipients, and the time when the determination is made
272 * for which cpus receive the IPI. Holding this
273 * lock helps us to not include this cpu in a currently in progress
274 * smp_call_function().
276 * We need to hold vector_lock so there the set of online cpus
277 * does not change while we are assigning vectors to cpus. Holding
278 * this lock ensures we don't half assign or remove an irq from a cpu.
282 set_cpu_online(smp_processor_id(), true);
283 unlock_vector_lock();
285 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
286 x86_platform.nmi_init();
289 * Wait until the cpu which brought this one up marked it
290 * online before enabling interrupts. If we don't do that then
291 * we can end up waking up the softirq thread before this cpu
292 * reached the active state, which makes the scheduler unhappy
293 * and schedule the softirq thread on the wrong cpu. This is
294 * only observable with forced threaded interrupts, but in
295 * theory it could also happen w/o them. It's just way harder
298 while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask))
301 /* enable local interrupts */
304 /* to prevent fake stack check failure in clock setup */
305 boot_init_stack_canary();
307 x86_cpuinit.setup_percpu_clockev();
314 * The bootstrap kernel entry code has set these up. Save them for
318 void __cpuinit smp_store_cpu_info(int id)
320 struct cpuinfo_x86 *c = &cpu_data(id);
325 identify_secondary_cpu(c);
328 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
330 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
331 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
332 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
333 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
334 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
335 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
339 void __cpuinit set_cpu_sibling_map(int cpu)
342 struct cpuinfo_x86 *c = &cpu_data(cpu);
344 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
346 if (smp_num_siblings > 1) {
347 for_each_cpu(i, cpu_sibling_setup_mask) {
348 struct cpuinfo_x86 *o = &cpu_data(i);
350 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
351 if (c->phys_proc_id == o->phys_proc_id &&
352 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
353 c->compute_unit_id == o->compute_unit_id)
354 link_thread_siblings(cpu, i);
355 } else if (c->phys_proc_id == o->phys_proc_id &&
356 c->cpu_core_id == o->cpu_core_id) {
357 link_thread_siblings(cpu, i);
361 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
366 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
367 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
372 for_each_cpu(i, cpu_sibling_setup_mask) {
373 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
374 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
375 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
376 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
378 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
379 cpumask_set_cpu(i, cpu_core_mask(cpu));
380 cpumask_set_cpu(cpu, cpu_core_mask(i));
382 * Does this new cpu bringup a new core?
384 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
386 * for each core in package, increment
387 * the booted_cores for this new cpu
389 if (cpumask_first(cpu_sibling_mask(i)) == i)
392 * increment the core count for all
393 * the other cpus in this package
396 cpu_data(i).booted_cores++;
397 } else if (i != cpu && !c->booted_cores)
398 c->booted_cores = cpu_data(i).booted_cores;
403 /* maps the cpu to the sched domain representing multi-core */
404 const struct cpumask *cpu_coregroup_mask(int cpu)
406 struct cpuinfo_x86 *c = &cpu_data(cpu);
408 * For perf, we return last level cache shared map.
409 * And for power savings, we return cpu_core_map
411 if ((sched_mc_power_savings || sched_smt_power_savings) &&
412 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
413 return cpu_core_mask(cpu);
415 return cpu_llc_shared_mask(cpu);
418 static void impress_friends(void)
421 unsigned long bogosum = 0;
423 * Allow the user to impress friends.
425 pr_debug("Before bogomips.\n");
426 for_each_possible_cpu(cpu)
427 if (cpumask_test_cpu(cpu, cpu_callout_mask))
428 bogosum += cpu_data(cpu).loops_per_jiffy;
430 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
433 (bogosum/(5000/HZ))%100);
435 pr_debug("Before bogocount - setting activated=1.\n");
438 void __inquire_remote_apic(int apicid)
440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
441 char *names[] = { "ID", "VERSION", "SPIV" };
445 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
447 for (i = 0; i < ARRAY_SIZE(regs); i++) {
448 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
453 status = safe_apic_wait_icr_idle();
456 "a previous APIC delivery may have failed\n");
458 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
463 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
464 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
467 case APIC_ICR_RR_VALID:
468 status = apic_read(APIC_RRR);
469 printk(KERN_CONT "%08x\n", status);
472 printk(KERN_CONT "failed\n");
478 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
479 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
480 * won't ... remember to clear down the APIC, etc later.
483 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
485 unsigned long send_status, accept_status = 0;
489 /* Boot on the stack */
490 /* Kick the second */
491 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
493 pr_debug("Waiting for send to finish...\n");
494 send_status = safe_apic_wait_icr_idle();
497 * Give the other CPU some time to accept the IPI.
500 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
501 maxlvt = lapic_get_maxlvt();
502 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
503 apic_write(APIC_ESR, 0);
504 accept_status = (apic_read(APIC_ESR) & 0xEF);
506 pr_debug("NMI sent.\n");
509 printk(KERN_ERR "APIC never delivered???\n");
511 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
513 return (send_status | accept_status);
517 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
519 unsigned long send_status, accept_status = 0;
520 int maxlvt, num_starts, j;
522 maxlvt = lapic_get_maxlvt();
525 * Be paranoid about clearing APIC errors.
527 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
528 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
529 apic_write(APIC_ESR, 0);
533 pr_debug("Asserting INIT.\n");
536 * Turn INIT on target chip
541 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
544 pr_debug("Waiting for send to finish...\n");
545 send_status = safe_apic_wait_icr_idle();
549 pr_debug("Deasserting INIT.\n");
553 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
555 pr_debug("Waiting for send to finish...\n");
556 send_status = safe_apic_wait_icr_idle();
559 atomic_set(&init_deasserted, 1);
562 * Should we send STARTUP IPIs ?
564 * Determine this based on the APIC version.
565 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
567 if (APIC_INTEGRATED(apic_version[phys_apicid]))
573 * Paravirt / VMI wants a startup IPI hook here to set up the
574 * target processor state.
576 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
580 * Run STARTUP IPI loop.
582 pr_debug("#startup loops: %d.\n", num_starts);
584 for (j = 1; j <= num_starts; j++) {
585 pr_debug("Sending STARTUP #%d.\n", j);
586 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
587 apic_write(APIC_ESR, 0);
589 pr_debug("After apic_write.\n");
596 /* Boot on the stack */
597 /* Kick the second */
598 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
602 * Give the other CPU some time to accept the IPI.
606 pr_debug("Startup point 1.\n");
608 pr_debug("Waiting for send to finish...\n");
609 send_status = safe_apic_wait_icr_idle();
612 * Give the other CPU some time to accept the IPI.
615 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
616 apic_write(APIC_ESR, 0);
617 accept_status = (apic_read(APIC_ESR) & 0xEF);
618 if (send_status || accept_status)
621 pr_debug("After Startup.\n");
624 printk(KERN_ERR "APIC never delivered???\n");
626 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
628 return (send_status | accept_status);
632 struct work_struct work;
633 struct task_struct *idle;
634 struct completion done;
638 static void __cpuinit do_fork_idle(struct work_struct *work)
640 struct create_idle *c_idle =
641 container_of(work, struct create_idle, work);
643 c_idle->idle = fork_idle(c_idle->cpu);
644 complete(&c_idle->done);
647 /* reduce the number of lines printed when booting a large cpu count system */
648 static void __cpuinit announce_cpu(int cpu, int apicid)
650 static int current_node = -1;
651 int node = early_cpu_to_node(cpu);
653 if (system_state == SYSTEM_BOOTING) {
654 if (node != current_node) {
655 if (current_node > (-1))
658 pr_info("Booting Node %3d, Processors ", node);
660 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
663 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
668 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
669 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
670 * Returns zero if CPU booted OK, else error code from
671 * ->wakeup_secondary_cpu.
673 static int __cpuinit do_boot_cpu(int apicid, int cpu)
675 unsigned long boot_error = 0;
676 unsigned long start_ip;
678 struct create_idle c_idle = {
680 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
683 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
685 alternatives_smp_switch(1);
687 c_idle.idle = get_idle_for_cpu(cpu);
690 * We can't use kernel_thread since we must avoid to
691 * reschedule the child.
694 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
695 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
696 init_idle(c_idle.idle, cpu);
700 schedule_work(&c_idle.work);
701 wait_for_completion(&c_idle.done);
703 if (IS_ERR(c_idle.idle)) {
704 printk("failed fork for CPU %d\n", cpu);
705 destroy_work_on_stack(&c_idle.work);
706 return PTR_ERR(c_idle.idle);
709 set_idle_for_cpu(cpu, c_idle.idle);
711 per_cpu(current_task, cpu) = c_idle.idle;
713 /* Stack for startup_32 can be just as for start_secondary onwards */
716 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
717 initial_gs = per_cpu_offset(cpu);
718 per_cpu(kernel_stack, cpu) =
719 (unsigned long)task_stack_page(c_idle.idle) -
720 KERNEL_STACK_OFFSET + THREAD_SIZE;
722 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
723 initial_code = (unsigned long)start_secondary;
724 stack_start = c_idle.idle->thread.sp;
726 /* start_ip had better be page-aligned! */
727 start_ip = trampoline_address();
729 /* So we see what's up */
730 announce_cpu(cpu, apicid);
733 * This grunge runs the startup process for
734 * the targeted processor.
737 printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip);
739 atomic_set(&init_deasserted, 0);
741 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
743 pr_debug("Setting warm reset code and vector.\n");
745 smpboot_setup_warm_reset_vector(start_ip);
747 * Be paranoid about clearing APIC errors.
749 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
750 apic_write(APIC_ESR, 0);
756 * Kick the secondary CPU. Use the method in the APIC driver
757 * if it's defined - or use an INIT boot APIC message otherwise:
759 if (apic->wakeup_secondary_cpu)
760 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
762 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
766 * allow APs to start initializing.
768 pr_debug("Before Callout %d.\n", cpu);
769 cpumask_set_cpu(cpu, cpu_callout_mask);
770 pr_debug("After Callout %d.\n", cpu);
773 * Wait 5s total for a response
775 for (timeout = 0; timeout < 50000; timeout++) {
776 if (cpumask_test_cpu(cpu, cpu_callin_mask))
777 break; /* It has booted */
780 * Allow other tasks to run while we wait for the
781 * AP to come online. This also gives a chance
782 * for the MTRR work(triggered by the AP coming online)
783 * to be completed in the stop machine context.
788 if (cpumask_test_cpu(cpu, cpu_callin_mask))
789 pr_debug("CPU%d: has booted.\n", cpu);
792 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
794 /* trampoline started but...? */
795 pr_err("CPU%d: Stuck ??\n", cpu);
797 /* trampoline code not run */
798 pr_err("CPU%d: Not responding.\n", cpu);
799 if (apic->inquire_remote_apic)
800 apic->inquire_remote_apic(apicid);
805 /* Try to put things back the way they were before ... */
806 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
808 /* was set by do_boot_cpu() */
809 cpumask_clear_cpu(cpu, cpu_callout_mask);
811 /* was set by cpu_init() */
812 cpumask_clear_cpu(cpu, cpu_initialized_mask);
814 set_cpu_present(cpu, false);
815 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
818 /* mark "stuck" area as not stuck */
819 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
821 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
823 * Cleanup possible dangling ends...
825 smpboot_restore_warm_reset_vector();
828 destroy_work_on_stack(&c_idle.work);
832 int __cpuinit native_cpu_up(unsigned int cpu)
834 int apicid = apic->cpu_present_to_apicid(cpu);
838 WARN_ON(irqs_disabled());
840 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
842 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
843 !physid_isset(apicid, phys_cpu_present_map)) {
844 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
849 * Already booted CPU?
851 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
852 pr_debug("do_boot_cpu %d Already started\n", cpu);
857 * Save current MTRR state in case it was changed since early boot
858 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
862 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
864 err = do_boot_cpu(apicid, cpu);
866 pr_debug("do_boot_cpu failed %d\n", err);
871 * Check TSC synchronization with the AP (keep irqs disabled
874 local_irq_save(flags);
875 check_tsc_sync_source(cpu);
876 local_irq_restore(flags);
878 while (!cpu_online(cpu)) {
880 touch_nmi_watchdog();
887 * arch_disable_smp_support() - disables SMP support for x86 at runtime
889 void arch_disable_smp_support(void)
891 disable_ioapic_support();
895 * Fall back to non SMP mode after errors.
897 * RED-PEN audit/test this more. I bet there is more state messed up here.
899 static __init void disable_smp(void)
901 init_cpu_present(cpumask_of(0));
902 init_cpu_possible(cpumask_of(0));
903 smpboot_clear_io_apic_irqs();
905 if (smp_found_config)
906 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
908 physid_set_mask_of_physid(0, &phys_cpu_present_map);
909 cpumask_set_cpu(0, cpu_sibling_mask(0));
910 cpumask_set_cpu(0, cpu_core_mask(0));
914 * Various sanity checks.
916 static int __init smp_sanity_check(unsigned max_cpus)
920 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
921 if (def_to_bigsmp && nr_cpu_ids > 8) {
926 "More than 8 CPUs detected - skipping them.\n"
927 "Use CONFIG_X86_BIGSMP.\n");
930 for_each_present_cpu(cpu) {
932 set_cpu_present(cpu, false);
937 for_each_possible_cpu(cpu) {
939 set_cpu_possible(cpu, false);
947 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
949 "weird, boot CPU (#%d) not listed by the BIOS.\n",
950 hard_smp_processor_id());
952 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
956 * If we couldn't find an SMP configuration at boot time,
957 * get out of here now!
959 if (!smp_found_config && !acpi_lapic) {
961 printk(KERN_NOTICE "SMP motherboard not detected.\n");
963 if (APIC_init_uniprocessor())
964 printk(KERN_NOTICE "Local APIC not detected."
965 " Using dummy APIC emulation.\n");
970 * Should not be necessary because the MP table should list the boot
971 * CPU too, but we do it for the sake of robustness anyway.
973 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
975 "weird, boot CPU (#%d) not listed by the BIOS.\n",
976 boot_cpu_physical_apicid);
977 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
982 * If we couldn't find a local APIC, then get out of here now!
984 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
987 pr_err("BIOS bug, local APIC #%d not detected!...\n",
988 boot_cpu_physical_apicid);
989 pr_err("... forcing use of dummy APIC emulation."
990 "(tell your hw vendor)\n");
992 smpboot_clear_io_apic();
993 disable_ioapic_support();
1000 * If SMP should be disabled, then really disable it!
1003 printk(KERN_INFO "SMP mode deactivated.\n");
1004 smpboot_clear_io_apic();
1008 bsp_end_local_APIC_setup();
1015 static void __init smp_cpu_index_default(void)
1018 struct cpuinfo_x86 *c;
1020 for_each_possible_cpu(i) {
1022 /* mark all to hotplug */
1023 c->cpu_index = nr_cpu_ids;
1028 * Prepare for SMP bootup. The MP table or ACPI has been read
1029 * earlier. Just do some sanity checking here and enable APIC mode.
1031 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1036 smp_cpu_index_default();
1039 * Setup boot CPU information
1041 smp_store_cpu_info(0); /* Final full version of the data */
1042 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1045 current_thread_info()->cpu = 0; /* needed? */
1046 for_each_possible_cpu(i) {
1047 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1048 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1049 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1051 set_cpu_sibling_map(0);
1054 if (smp_sanity_check(max_cpus) < 0) {
1055 printk(KERN_INFO "SMP disabled\n");
1060 default_setup_apic_routing();
1063 if (read_apic_id() != boot_cpu_physical_apicid) {
1064 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1065 read_apic_id(), boot_cpu_physical_apicid);
1066 /* Or can we switch back to PIC here? */
1073 * Switch from PIC to APIC mode.
1078 * Enable IO APIC before setting up error vector
1080 if (!skip_ioapic_setup && nr_ioapics)
1083 bsp_end_local_APIC_setup();
1085 if (apic->setup_portio_remap)
1086 apic->setup_portio_remap();
1088 smpboot_setup_io_apic();
1090 * Set up local APIC timer on boot CPU.
1093 printk(KERN_INFO "CPU%d: ", 0);
1094 print_cpu_info(&cpu_data(0));
1095 x86_init.timers.setup_percpu_clockev();
1100 set_mtrr_aps_delayed_init();
1105 void arch_disable_nonboot_cpus_begin(void)
1108 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1109 * In the suspend path, we will be back in the SMP mode shortly anyways.
1111 skip_smp_alternatives = true;
1114 void arch_disable_nonboot_cpus_end(void)
1116 skip_smp_alternatives = false;
1119 void arch_enable_nonboot_cpus_begin(void)
1121 set_mtrr_aps_delayed_init();
1124 void arch_enable_nonboot_cpus_end(void)
1130 * Early setup to make printk work.
1132 void __init native_smp_prepare_boot_cpu(void)
1134 int me = smp_processor_id();
1135 switch_to_new_gdt(me);
1136 /* already set me in cpu_online_mask in boot_cpu_init() */
1137 cpumask_set_cpu(me, cpu_callout_mask);
1138 per_cpu(cpu_state, me) = CPU_ONLINE;
1141 void __init native_smp_cpus_done(unsigned int max_cpus)
1143 pr_debug("Boot done.\n");
1146 #ifdef CONFIG_X86_IO_APIC
1147 setup_ioapic_dest();
1152 static int __initdata setup_possible_cpus = -1;
1153 static int __init _setup_possible_cpus(char *str)
1155 get_option(&str, &setup_possible_cpus);
1158 early_param("possible_cpus", _setup_possible_cpus);
1162 * cpu_possible_mask should be static, it cannot change as cpu's
1163 * are onlined, or offlined. The reason is per-cpu data-structures
1164 * are allocated by some modules at init time, and dont expect to
1165 * do this dynamically on cpu arrival/departure.
1166 * cpu_present_mask on the other hand can change dynamically.
1167 * In case when cpu_hotplug is not compiled, then we resort to current
1168 * behaviour, which is cpu_possible == cpu_present.
1171 * Three ways to find out the number of additional hotplug CPUs:
1172 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1173 * - The user can overwrite it with possible_cpus=NUM
1174 * - Otherwise don't reserve additional CPUs.
1175 * We do this because additional CPUs waste a lot of memory.
1178 __init void prefill_possible_map(void)
1182 /* no processor from mptable or madt */
1183 if (!num_processors)
1186 i = setup_max_cpus ?: 1;
1187 if (setup_possible_cpus == -1) {
1188 possible = num_processors;
1189 #ifdef CONFIG_HOTPLUG_CPU
1191 possible += disabled_cpus;
1197 possible = setup_possible_cpus;
1199 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1201 /* nr_cpu_ids could be reduced via nr_cpus= */
1202 if (possible > nr_cpu_ids) {
1204 "%d Processors exceeds NR_CPUS limit of %d\n",
1205 possible, nr_cpu_ids);
1206 possible = nr_cpu_ids;
1209 #ifdef CONFIG_HOTPLUG_CPU
1210 if (!setup_max_cpus)
1214 "%d Processors exceeds max_cpus limit of %u\n",
1215 possible, setup_max_cpus);
1219 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1220 possible, max_t(int, possible - num_processors, 0));
1222 for (i = 0; i < possible; i++)
1223 set_cpu_possible(i, true);
1224 for (; i < NR_CPUS; i++)
1225 set_cpu_possible(i, false);
1227 nr_cpu_ids = possible;
1230 #ifdef CONFIG_HOTPLUG_CPU
1232 static void remove_siblinginfo(int cpu)
1235 struct cpuinfo_x86 *c = &cpu_data(cpu);
1237 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1238 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1240 * last thread sibling in this cpu core going down
1242 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1243 cpu_data(sibling).booted_cores--;
1246 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1247 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1248 cpumask_clear(cpu_sibling_mask(cpu));
1249 cpumask_clear(cpu_core_mask(cpu));
1250 c->phys_proc_id = 0;
1252 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1255 static void __ref remove_cpu_from_maps(int cpu)
1257 set_cpu_online(cpu, false);
1258 cpumask_clear_cpu(cpu, cpu_callout_mask);
1259 cpumask_clear_cpu(cpu, cpu_callin_mask);
1260 /* was set by cpu_init() */
1261 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1262 numa_remove_cpu(cpu);
1265 void cpu_disable_common(void)
1267 int cpu = smp_processor_id();
1269 remove_siblinginfo(cpu);
1271 /* It's now safe to remove this processor from the online map */
1273 remove_cpu_from_maps(cpu);
1274 unlock_vector_lock();
1278 int native_cpu_disable(void)
1280 int cpu = smp_processor_id();
1283 * Perhaps use cpufreq to drop frequency, but that could go
1284 * into generic code.
1286 * We won't take down the boot processor on i386 due to some
1287 * interrupts only being able to be serviced by the BSP.
1288 * Especially so if we're not using an IOAPIC -zwane
1295 cpu_disable_common();
1299 void native_cpu_die(unsigned int cpu)
1301 /* We don't do anything here: idle task is faking death itself. */
1304 for (i = 0; i < 10; i++) {
1305 /* They ack this in play_dead by setting CPU_DEAD */
1306 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1307 if (system_state == SYSTEM_RUNNING)
1308 pr_info("CPU %u is now offline\n", cpu);
1310 if (1 == num_online_cpus())
1311 alternatives_smp_switch(0);
1316 pr_err("CPU %u didn't die...\n", cpu);
1319 void play_dead_common(void)
1322 reset_lazy_tlbstate();
1323 amd_e400_remove_cpu(raw_smp_processor_id());
1327 __this_cpu_write(cpu_state, CPU_DEAD);
1330 * With physical CPU hotplug, we should halt the cpu
1332 local_irq_disable();
1336 * We need to flush the caches before going to sleep, lest we have
1337 * dirty data in our caches when we come back up.
1339 static inline void mwait_play_dead(void)
1341 unsigned int eax, ebx, ecx, edx;
1342 unsigned int highest_cstate = 0;
1343 unsigned int highest_subcstate = 0;
1346 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1348 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1350 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1352 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1355 eax = CPUID_MWAIT_LEAF;
1357 native_cpuid(&eax, &ebx, &ecx, &edx);
1360 * eax will be 0 if EDX enumeration is not valid.
1361 * Initialized below to cstate, sub_cstate value when EDX is valid.
1363 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1366 edx >>= MWAIT_SUBSTATE_SIZE;
1367 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1368 if (edx & MWAIT_SUBSTATE_MASK) {
1370 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1373 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1374 (highest_subcstate - 1);
1378 * This should be a memory location in a cache line which is
1379 * unlikely to be touched by other processors. The actual
1380 * content is immaterial as it is not actually modified in any way.
1382 mwait_ptr = ¤t_thread_info()->flags;
1388 * The CLFLUSH is a workaround for erratum AAI65 for
1389 * the Xeon 7400 series. It's not clear it is actually
1390 * needed, but it should be harmless in either case.
1391 * The WBINVD is insufficient due to the spurious-wakeup
1392 * case where we return around the loop.
1395 __monitor(mwait_ptr, 0, 0);
1401 static inline void hlt_play_dead(void)
1403 if (__this_cpu_read(cpu_info.x86) >= 4)
1411 void native_play_dead(void)
1414 tboot_shutdown(TB_SHUTDOWN_WFS);
1416 mwait_play_dead(); /* Only returns on failure */
1420 #else /* ... !CONFIG_HOTPLUG_CPU */
1421 int native_cpu_disable(void)
1426 void native_cpu_die(unsigned int cpu)
1428 /* We said "no" in __cpu_disable */
1432 void native_play_dead(void)