2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/smpboot_hooks.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
81 /* State of each CPU */
82 DEFINE_PER_CPU(int, cpu_state) = { 0 };
84 /* Number of siblings per CPU package */
85 int smp_num_siblings = 1;
86 EXPORT_SYMBOL(smp_num_siblings);
88 /* Last level cache ID of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
91 /* representing HT siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
95 /* representing HT and core siblings of each logical CPU */
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
97 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
101 /* Per CPU bogomips and other parameters */
102 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
103 EXPORT_PER_CPU_SYMBOL(cpu_info);
105 atomic_t init_deasserted;
108 * Report back to the Boot Processor during boot time or to the caller processor
111 static void smp_callin(void)
114 unsigned long timeout;
117 * If waken up by an INIT in an 82489DX configuration
118 * we may get here before an INIT-deassert IPI reaches
119 * our local APIC. We have to wait for the IPI or we'll
120 * lock up on an APIC access.
122 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
124 cpuid = smp_processor_id();
125 if (apic->wait_for_init_deassert && cpuid != 0)
126 apic->wait_for_init_deassert(&init_deasserted);
129 * (This works even if the APIC is not enabled.)
131 phys_id = read_apic_id();
132 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
133 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
136 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
139 * STARTUP IPIs are fragile beasts as they might sometimes
140 * trigger some glue motherboard logic. Complete APIC bus
141 * silence for 1 second, this overestimates the time the
142 * boot CPU is spending to send the up to 2 STARTUP IPIs
143 * by a factor of two. This should be enough.
147 * Waiting 2s total for startup (udelay is not yet working)
149 timeout = jiffies + 2*HZ;
150 while (time_before(jiffies, timeout)) {
152 * Has the boot CPU finished it's STARTUP sequence?
154 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
159 if (!time_before(jiffies, timeout)) {
160 panic("%s: CPU%d started up but did not get a callout!\n",
165 * the boot CPU has finished the init stage and is spinning
166 * on callin_map until we finish. We are free to set up this
167 * CPU, first the APIC. (this is probably redundant on most
171 pr_debug("CALLIN, before setup_local_APIC()\n");
172 if (apic->smp_callin_clear_local_apic)
173 apic->smp_callin_clear_local_apic();
175 end_local_APIC_setup();
178 * Need to setup vector mappings before we enable interrupts.
180 setup_vector_irq(smp_processor_id());
183 * Save our processor parameters. Note: this information
184 * is needed for clock calibration.
186 smp_store_cpu_info(cpuid);
190 * Update loops_per_jiffy in cpu_data. Previous call to
191 * smp_store_cpu_info() stored a value that is close but not as
192 * accurate as the value just calculated.
195 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
196 pr_debug("Stack at about %p\n", &cpuid);
199 * This must be done before setting cpu_online_mask
200 * or calling notify_cpu_starting.
202 set_cpu_sibling_map(raw_smp_processor_id());
205 notify_cpu_starting(cpuid);
208 * Allow the master to continue.
210 cpumask_set_cpu(cpuid, cpu_callin_mask);
213 static int cpu0_logical_apicid;
214 static int enable_start_cpu0;
216 * Activate a secondary processor.
218 static void notrace start_secondary(void *unused)
221 * Don't put *anything* before cpu_init(), SMP booting is too
222 * fragile that we want to limit the things done here to the
223 * most necessary things.
226 x86_cpuinit.early_percpu_clock_init();
230 enable_start_cpu0 = 0;
233 /* switch away from the initial page table */
234 load_cr3(swapper_pg_dir);
238 /* otherwise gcc will move up smp_processor_id before the cpu_init */
241 * Check TSC synchronization with the BP:
243 check_tsc_sync_target();
246 * We need to hold vector_lock so there the set of online cpus
247 * does not change while we are assigning vectors to cpus. Holding
248 * this lock ensures we don't half assign or remove an irq from a cpu.
251 set_cpu_online(smp_processor_id(), true);
252 unlock_vector_lock();
253 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
254 x86_platform.nmi_init();
256 /* enable local interrupts */
259 /* to prevent fake stack check failure in clock setup */
260 boot_init_stack_canary();
262 x86_cpuinit.setup_percpu_clockev();
265 cpu_startup_entry(CPUHP_ONLINE);
268 void __init smp_store_boot_cpu_info(void)
270 int id = 0; /* CPU 0 */
271 struct cpuinfo_x86 *c = &cpu_data(id);
278 * The bootstrap kernel entry code has set these up. Save them for
281 void smp_store_cpu_info(int id)
283 struct cpuinfo_x86 *c = &cpu_data(id);
288 * During boot time, CPU0 has this setup already. Save the info when
289 * bringing up AP or offlined CPU0.
291 identify_secondary_cpu(c);
295 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
297 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
299 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
300 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
301 "[node: %d != %d]. Ignoring dependency.\n",
302 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
305 #define link_mask(_m, c1, c2) \
307 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
308 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
311 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
313 if (cpu_has_topoext) {
314 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
316 if (c->phys_proc_id == o->phys_proc_id &&
317 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
318 c->compute_unit_id == o->compute_unit_id)
319 return topology_sane(c, o, "smt");
321 } else if (c->phys_proc_id == o->phys_proc_id &&
322 c->cpu_core_id == o->cpu_core_id) {
323 return topology_sane(c, o, "smt");
329 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
331 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
333 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
334 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
335 return topology_sane(c, o, "llc");
340 static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
342 if (c->phys_proc_id == o->phys_proc_id) {
343 if (cpu_has(c, X86_FEATURE_AMD_DCM))
346 return topology_sane(c, o, "mc");
351 void set_cpu_sibling_map(int cpu)
353 bool has_smt = smp_num_siblings > 1;
354 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
355 struct cpuinfo_x86 *c = &cpu_data(cpu);
356 struct cpuinfo_x86 *o;
359 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
362 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
363 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
364 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
369 for_each_cpu(i, cpu_sibling_setup_mask) {
372 if ((i == cpu) || (has_smt && match_smt(c, o)))
373 link_mask(sibling, cpu, i);
375 if ((i == cpu) || (has_mp && match_llc(c, o)))
376 link_mask(llc_shared, cpu, i);
381 * This needs a separate iteration over the cpus because we rely on all
382 * cpu_sibling_mask links to be set-up.
384 for_each_cpu(i, cpu_sibling_setup_mask) {
387 if ((i == cpu) || (has_mp && match_mc(c, o))) {
388 link_mask(core, cpu, i);
391 * Does this new cpu bringup a new core?
393 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
395 * for each core in package, increment
396 * the booted_cores for this new cpu
398 if (cpumask_first(cpu_sibling_mask(i)) == i)
401 * increment the core count for all
402 * the other cpus in this package
405 cpu_data(i).booted_cores++;
406 } else if (i != cpu && !c->booted_cores)
407 c->booted_cores = cpu_data(i).booted_cores;
412 /* maps the cpu to the sched domain representing multi-core */
413 const struct cpumask *cpu_coregroup_mask(int cpu)
415 return cpu_llc_shared_mask(cpu);
418 static void impress_friends(void)
421 unsigned long bogosum = 0;
423 * Allow the user to impress friends.
425 pr_debug("Before bogomips\n");
426 for_each_possible_cpu(cpu)
427 if (cpumask_test_cpu(cpu, cpu_callout_mask))
428 bogosum += cpu_data(cpu).loops_per_jiffy;
429 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
432 (bogosum/(5000/HZ))%100);
434 pr_debug("Before bogocount - setting activated=1\n");
437 void __inquire_remote_apic(int apicid)
439 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
440 const char * const names[] = { "ID", "VERSION", "SPIV" };
444 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
446 for (i = 0; i < ARRAY_SIZE(regs); i++) {
447 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
452 status = safe_apic_wait_icr_idle();
454 pr_cont("a previous APIC delivery may have failed\n");
456 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
461 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
462 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
465 case APIC_ICR_RR_VALID:
466 status = apic_read(APIC_RRR);
467 pr_cont("%08x\n", status);
476 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
477 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
478 * won't ... remember to clear down the APIC, etc later.
481 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
483 unsigned long send_status, accept_status = 0;
487 /* Boot on the stack */
488 /* Kick the second */
489 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
491 pr_debug("Waiting for send to finish...\n");
492 send_status = safe_apic_wait_icr_idle();
495 * Give the other CPU some time to accept the IPI.
498 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
499 maxlvt = lapic_get_maxlvt();
500 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
501 apic_write(APIC_ESR, 0);
502 accept_status = (apic_read(APIC_ESR) & 0xEF);
504 pr_debug("NMI sent\n");
507 pr_err("APIC never delivered???\n");
509 pr_err("APIC delivery error (%lx)\n", accept_status);
511 return (send_status | accept_status);
515 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
517 unsigned long send_status, accept_status = 0;
518 int maxlvt, num_starts, j;
520 maxlvt = lapic_get_maxlvt();
523 * Be paranoid about clearing APIC errors.
525 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
526 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
527 apic_write(APIC_ESR, 0);
531 pr_debug("Asserting INIT\n");
534 * Turn INIT on target chip
539 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
542 pr_debug("Waiting for send to finish...\n");
543 send_status = safe_apic_wait_icr_idle();
547 pr_debug("Deasserting INIT\n");
551 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
553 pr_debug("Waiting for send to finish...\n");
554 send_status = safe_apic_wait_icr_idle();
557 atomic_set(&init_deasserted, 1);
560 * Should we send STARTUP IPIs ?
562 * Determine this based on the APIC version.
563 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
565 if (APIC_INTEGRATED(apic_version[phys_apicid]))
571 * Paravirt / VMI wants a startup IPI hook here to set up the
572 * target processor state.
574 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
578 * Run STARTUP IPI loop.
580 pr_debug("#startup loops: %d\n", num_starts);
582 for (j = 1; j <= num_starts; j++) {
583 pr_debug("Sending STARTUP #%d\n", j);
584 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
585 apic_write(APIC_ESR, 0);
587 pr_debug("After apic_write\n");
594 /* Boot on the stack */
595 /* Kick the second */
596 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
600 * Give the other CPU some time to accept the IPI.
604 pr_debug("Startup point 1\n");
606 pr_debug("Waiting for send to finish...\n");
607 send_status = safe_apic_wait_icr_idle();
610 * Give the other CPU some time to accept the IPI.
613 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
614 apic_write(APIC_ESR, 0);
615 accept_status = (apic_read(APIC_ESR) & 0xEF);
616 if (send_status || accept_status)
619 pr_debug("After Startup\n");
622 pr_err("APIC never delivered???\n");
624 pr_err("APIC delivery error (%lx)\n", accept_status);
626 return (send_status | accept_status);
629 void smp_announce(void)
631 int num_nodes = num_online_nodes();
633 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
634 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
637 /* reduce the number of lines printed when booting a large cpu count system */
638 static void announce_cpu(int cpu, int apicid)
640 static int current_node = -1;
641 int node = early_cpu_to_node(cpu);
642 static int width, node_width;
645 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
648 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
651 printk(KERN_INFO "x86: Booting SMP configuration:\n");
653 if (system_state == SYSTEM_BOOTING) {
654 if (node != current_node) {
655 if (current_node > (-1))
659 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
660 node_width - num_digits(node), " ", node);
663 /* Add padding for the BSP */
665 pr_cont("%*s", width + 1, " ");
667 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
670 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
674 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
678 cpu = smp_processor_id();
679 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
686 * Wake up AP by INIT, INIT, STARTUP sequence.
688 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
689 * boot-strap code which is not a desired behavior for waking up BSP. To
690 * void the boot-strap code, wake up CPU0 by NMI instead.
692 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
693 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
694 * We'll change this code in the future to wake up hard offlined CPU0 if
695 * real platform and request are available.
698 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
699 int *cpu0_nmi_registered)
705 * Wake up AP by INIT, INIT, STARTUP sequence.
708 return wakeup_secondary_cpu_via_init(apicid, start_ip);
711 * Wake up BSP by nmi.
713 * Register a NMI handler to help wake up CPU0.
715 boot_error = register_nmi_handler(NMI_LOCAL,
716 wakeup_cpu0_nmi, 0, "wake_cpu0");
719 enable_start_cpu0 = 1;
720 *cpu0_nmi_registered = 1;
721 if (apic->dest_logical == APIC_DEST_LOGICAL)
722 id = cpu0_logical_apicid;
725 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
732 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
733 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
734 * Returns zero if CPU booted OK, else error code from
735 * ->wakeup_secondary_cpu.
737 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
739 volatile u32 *trampoline_status =
740 (volatile u32 *) __va(real_mode_header->trampoline_status);
741 /* start_ip had better be page-aligned! */
742 unsigned long start_ip = real_mode_header->trampoline_start;
744 unsigned long boot_error = 0;
746 int cpu0_nmi_registered = 0;
748 /* Just in case we booted with a single CPU. */
749 alternatives_enable_smp();
751 idle->thread.sp = (unsigned long) (((struct pt_regs *)
752 (THREAD_SIZE + task_stack_page(idle))) - 1);
753 per_cpu(current_task, cpu) = idle;
756 /* Stack for startup_32 can be just as for start_secondary onwards */
759 clear_tsk_thread_flag(idle, TIF_FORK);
760 initial_gs = per_cpu_offset(cpu);
761 per_cpu(kernel_stack, cpu) =
762 (unsigned long)task_stack_page(idle) -
763 KERNEL_STACK_OFFSET + THREAD_SIZE;
765 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
766 initial_code = (unsigned long)start_secondary;
767 stack_start = idle->thread.sp;
769 /* So we see what's up */
770 announce_cpu(cpu, apicid);
773 * This grunge runs the startup process for
774 * the targeted processor.
777 atomic_set(&init_deasserted, 0);
779 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
781 pr_debug("Setting warm reset code and vector.\n");
783 smpboot_setup_warm_reset_vector(start_ip);
785 * Be paranoid about clearing APIC errors.
787 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
788 apic_write(APIC_ESR, 0);
794 * Wake up a CPU in difference cases:
795 * - Use the method in the APIC driver if it's defined
797 * - Use an INIT boot APIC message for APs or NMI for BSP.
799 if (apic->wakeup_secondary_cpu)
800 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
802 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
803 &cpu0_nmi_registered);
807 * allow APs to start initializing.
809 pr_debug("Before Callout %d\n", cpu);
810 cpumask_set_cpu(cpu, cpu_callout_mask);
811 pr_debug("After Callout %d\n", cpu);
814 * Wait 5s total for a response
816 for (timeout = 0; timeout < 50000; timeout++) {
817 if (cpumask_test_cpu(cpu, cpu_callin_mask))
818 break; /* It has booted */
821 * Allow other tasks to run while we wait for the
822 * AP to come online. This also gives a chance
823 * for the MTRR work(triggered by the AP coming online)
824 * to be completed in the stop machine context.
829 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
830 print_cpu_msr(&cpu_data(cpu));
831 pr_debug("CPU%d: has booted.\n", cpu);
834 if (*trampoline_status == 0xA5A5A5A5)
835 /* trampoline started but...? */
836 pr_err("CPU%d: Stuck ??\n", cpu);
838 /* trampoline code not run */
839 pr_err("CPU%d: Not responding\n", cpu);
840 if (apic->inquire_remote_apic)
841 apic->inquire_remote_apic(apicid);
846 /* Try to put things back the way they were before ... */
847 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
849 /* was set by do_boot_cpu() */
850 cpumask_clear_cpu(cpu, cpu_callout_mask);
852 /* was set by cpu_init() */
853 cpumask_clear_cpu(cpu, cpu_initialized_mask);
855 set_cpu_present(cpu, false);
856 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
859 /* mark "stuck" area as not stuck */
860 *trampoline_status = 0;
862 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
864 * Cleanup possible dangling ends...
866 smpboot_restore_warm_reset_vector();
869 * Clean up the nmi handler. Do this after the callin and callout sync
870 * to avoid impact of possible long unregister time.
872 if (cpu0_nmi_registered)
873 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
878 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
880 int apicid = apic->cpu_present_to_apicid(cpu);
884 WARN_ON(irqs_disabled());
886 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
888 if (apicid == BAD_APICID ||
889 !physid_isset(apicid, phys_cpu_present_map) ||
890 !apic->apic_id_valid(apicid)) {
891 pr_err("%s: bad cpu %d\n", __func__, cpu);
896 * Already booted CPU?
898 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
899 pr_debug("do_boot_cpu %d Already started\n", cpu);
904 * Save current MTRR state in case it was changed since early boot
905 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
909 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
911 /* the FPU context is blank, nobody can own it */
912 __cpu_disable_lazy_restore(cpu);
914 err = do_boot_cpu(apicid, cpu, tidle);
916 pr_debug("do_boot_cpu failed %d\n", err);
921 * Check TSC synchronization with the AP (keep irqs disabled
924 local_irq_save(flags);
925 check_tsc_sync_source(cpu);
926 local_irq_restore(flags);
928 while (!cpu_online(cpu)) {
930 touch_nmi_watchdog();
937 * arch_disable_smp_support() - disables SMP support for x86 at runtime
939 void arch_disable_smp_support(void)
941 disable_ioapic_support();
945 * Fall back to non SMP mode after errors.
947 * RED-PEN audit/test this more. I bet there is more state messed up here.
949 static __init void disable_smp(void)
951 init_cpu_present(cpumask_of(0));
952 init_cpu_possible(cpumask_of(0));
953 smpboot_clear_io_apic_irqs();
955 if (smp_found_config)
956 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
958 physid_set_mask_of_physid(0, &phys_cpu_present_map);
959 cpumask_set_cpu(0, cpu_sibling_mask(0));
960 cpumask_set_cpu(0, cpu_core_mask(0));
964 * Various sanity checks.
966 static int __init smp_sanity_check(unsigned max_cpus)
970 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
971 if (def_to_bigsmp && nr_cpu_ids > 8) {
975 pr_warn("More than 8 CPUs detected - skipping them\n"
976 "Use CONFIG_X86_BIGSMP\n");
979 for_each_present_cpu(cpu) {
981 set_cpu_present(cpu, false);
986 for_each_possible_cpu(cpu) {
988 set_cpu_possible(cpu, false);
996 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
997 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
998 hard_smp_processor_id());
1000 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1004 * If we couldn't find an SMP configuration at boot time,
1005 * get out of here now!
1007 if (!smp_found_config && !acpi_lapic) {
1009 pr_notice("SMP motherboard not detected\n");
1011 if (APIC_init_uniprocessor())
1012 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1017 * Should not be necessary because the MP table should list the boot
1018 * CPU too, but we do it for the sake of robustness anyway.
1020 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1021 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1022 boot_cpu_physical_apicid);
1023 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1028 * If we couldn't find a local APIC, then get out of here now!
1030 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1032 if (!disable_apic) {
1033 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1034 boot_cpu_physical_apicid);
1035 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1037 smpboot_clear_io_apic();
1038 disable_ioapic_support();
1042 verify_local_APIC();
1045 * If SMP should be disabled, then really disable it!
1048 pr_info("SMP mode deactivated\n");
1049 smpboot_clear_io_apic();
1053 bsp_end_local_APIC_setup();
1060 static void __init smp_cpu_index_default(void)
1063 struct cpuinfo_x86 *c;
1065 for_each_possible_cpu(i) {
1067 /* mark all to hotplug */
1068 c->cpu_index = nr_cpu_ids;
1073 * Prepare for SMP bootup. The MP table or ACPI has been read
1074 * earlier. Just do some sanity checking here and enable APIC mode.
1076 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1081 smp_cpu_index_default();
1084 * Setup boot CPU information
1086 smp_store_boot_cpu_info(); /* Final full version of the data */
1087 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1090 current_thread_info()->cpu = 0; /* needed? */
1091 for_each_possible_cpu(i) {
1092 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1093 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1094 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1096 set_cpu_sibling_map(0);
1099 if (smp_sanity_check(max_cpus) < 0) {
1100 pr_info("SMP disabled\n");
1105 default_setup_apic_routing();
1108 if (read_apic_id() != boot_cpu_physical_apicid) {
1109 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1110 read_apic_id(), boot_cpu_physical_apicid);
1111 /* Or can we switch back to PIC here? */
1118 * Switch from PIC to APIC mode.
1123 cpu0_logical_apicid = apic_read(APIC_LDR);
1125 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1128 * Enable IO APIC before setting up error vector
1130 if (!skip_ioapic_setup && nr_ioapics)
1133 bsp_end_local_APIC_setup();
1135 if (apic->setup_portio_remap)
1136 apic->setup_portio_remap();
1138 smpboot_setup_io_apic();
1140 * Set up local APIC timer on boot CPU.
1143 pr_info("CPU%d: ", 0);
1144 print_cpu_info(&cpu_data(0));
1145 x86_init.timers.setup_percpu_clockev();
1150 set_mtrr_aps_delayed_init();
1155 void arch_enable_nonboot_cpus_begin(void)
1157 set_mtrr_aps_delayed_init();
1160 void arch_enable_nonboot_cpus_end(void)
1166 * Early setup to make printk work.
1168 void __init native_smp_prepare_boot_cpu(void)
1170 int me = smp_processor_id();
1171 switch_to_new_gdt(me);
1172 /* already set me in cpu_online_mask in boot_cpu_init() */
1173 cpumask_set_cpu(me, cpu_callout_mask);
1174 per_cpu(cpu_state, me) = CPU_ONLINE;
1177 void __init native_smp_cpus_done(unsigned int max_cpus)
1179 pr_debug("Boot done\n");
1183 #ifdef CONFIG_X86_IO_APIC
1184 setup_ioapic_dest();
1189 static int __initdata setup_possible_cpus = -1;
1190 static int __init _setup_possible_cpus(char *str)
1192 get_option(&str, &setup_possible_cpus);
1195 early_param("possible_cpus", _setup_possible_cpus);
1199 * cpu_possible_mask should be static, it cannot change as cpu's
1200 * are onlined, or offlined. The reason is per-cpu data-structures
1201 * are allocated by some modules at init time, and dont expect to
1202 * do this dynamically on cpu arrival/departure.
1203 * cpu_present_mask on the other hand can change dynamically.
1204 * In case when cpu_hotplug is not compiled, then we resort to current
1205 * behaviour, which is cpu_possible == cpu_present.
1208 * Three ways to find out the number of additional hotplug CPUs:
1209 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1210 * - The user can overwrite it with possible_cpus=NUM
1211 * - Otherwise don't reserve additional CPUs.
1212 * We do this because additional CPUs waste a lot of memory.
1215 __init void prefill_possible_map(void)
1219 /* no processor from mptable or madt */
1220 if (!num_processors)
1223 i = setup_max_cpus ?: 1;
1224 if (setup_possible_cpus == -1) {
1225 possible = num_processors;
1226 #ifdef CONFIG_HOTPLUG_CPU
1228 possible += disabled_cpus;
1234 possible = setup_possible_cpus;
1236 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1238 /* nr_cpu_ids could be reduced via nr_cpus= */
1239 if (possible > nr_cpu_ids) {
1240 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1241 possible, nr_cpu_ids);
1242 possible = nr_cpu_ids;
1245 #ifdef CONFIG_HOTPLUG_CPU
1246 if (!setup_max_cpus)
1249 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1250 possible, setup_max_cpus);
1254 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1255 possible, max_t(int, possible - num_processors, 0));
1257 for (i = 0; i < possible; i++)
1258 set_cpu_possible(i, true);
1259 for (; i < NR_CPUS; i++)
1260 set_cpu_possible(i, false);
1262 nr_cpu_ids = possible;
1265 #ifdef CONFIG_HOTPLUG_CPU
1267 static void remove_siblinginfo(int cpu)
1270 struct cpuinfo_x86 *c = &cpu_data(cpu);
1272 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1273 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1275 * last thread sibling in this cpu core going down
1277 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1278 cpu_data(sibling).booted_cores--;
1281 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1282 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1283 cpumask_clear(cpu_sibling_mask(cpu));
1284 cpumask_clear(cpu_core_mask(cpu));
1285 c->phys_proc_id = 0;
1287 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1290 static void __ref remove_cpu_from_maps(int cpu)
1292 set_cpu_online(cpu, false);
1293 cpumask_clear_cpu(cpu, cpu_callout_mask);
1294 cpumask_clear_cpu(cpu, cpu_callin_mask);
1295 /* was set by cpu_init() */
1296 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1297 numa_remove_cpu(cpu);
1300 void cpu_disable_common(void)
1302 int cpu = smp_processor_id();
1304 remove_siblinginfo(cpu);
1306 /* It's now safe to remove this processor from the online map */
1308 remove_cpu_from_maps(cpu);
1309 unlock_vector_lock();
1313 int native_cpu_disable(void)
1317 ret = check_irq_vectors_for_cpu_disable();
1323 cpu_disable_common();
1327 void native_cpu_die(unsigned int cpu)
1329 /* We don't do anything here: idle task is faking death itself. */
1332 for (i = 0; i < 10; i++) {
1333 /* They ack this in play_dead by setting CPU_DEAD */
1334 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1335 if (system_state == SYSTEM_RUNNING)
1336 pr_info("CPU %u is now offline\n", cpu);
1341 pr_err("CPU %u didn't die...\n", cpu);
1344 void play_dead_common(void)
1347 reset_lazy_tlbstate();
1348 amd_e400_remove_cpu(raw_smp_processor_id());
1352 __this_cpu_write(cpu_state, CPU_DEAD);
1355 * With physical CPU hotplug, we should halt the cpu
1357 local_irq_disable();
1360 static bool wakeup_cpu0(void)
1362 if (smp_processor_id() == 0 && enable_start_cpu0)
1369 * We need to flush the caches before going to sleep, lest we have
1370 * dirty data in our caches when we come back up.
1372 static inline void mwait_play_dead(void)
1374 unsigned int eax, ebx, ecx, edx;
1375 unsigned int highest_cstate = 0;
1376 unsigned int highest_subcstate = 0;
1380 if (!this_cpu_has(X86_FEATURE_MWAIT))
1382 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1384 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1387 eax = CPUID_MWAIT_LEAF;
1389 native_cpuid(&eax, &ebx, &ecx, &edx);
1392 * eax will be 0 if EDX enumeration is not valid.
1393 * Initialized below to cstate, sub_cstate value when EDX is valid.
1395 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1398 edx >>= MWAIT_SUBSTATE_SIZE;
1399 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1400 if (edx & MWAIT_SUBSTATE_MASK) {
1402 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1405 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1406 (highest_subcstate - 1);
1410 * This should be a memory location in a cache line which is
1411 * unlikely to be touched by other processors. The actual
1412 * content is immaterial as it is not actually modified in any way.
1414 mwait_ptr = ¤t_thread_info()->flags;
1420 * The CLFLUSH is a workaround for erratum AAI65 for
1421 * the Xeon 7400 series. It's not clear it is actually
1422 * needed, but it should be harmless in either case.
1423 * The WBINVD is insufficient due to the spurious-wakeup
1424 * case where we return around the loop.
1429 __monitor(mwait_ptr, 0, 0);
1433 * If NMI wants to wake up CPU0, start CPU0.
1440 static inline void hlt_play_dead(void)
1442 if (__this_cpu_read(cpu_info.x86) >= 4)
1448 * If NMI wants to wake up CPU0, start CPU0.
1455 void native_play_dead(void)
1458 tboot_shutdown(TB_SHUTDOWN_WFS);
1460 mwait_play_dead(); /* Only returns on failure */
1461 if (cpuidle_play_dead())
1465 #else /* ... !CONFIG_HOTPLUG_CPU */
1466 int native_cpu_disable(void)
1471 void native_cpu_die(unsigned int cpu)
1473 /* We said "no" in __cpu_disable */
1477 void native_play_dead(void)