1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/timer.h>
8 #include <linux/acpi_pmtmr.h>
9 #include <linux/cpufreq.h>
10 #include <linux/delay.h>
11 #include <linux/clocksource.h>
12 #include <linux/percpu.h>
13 #include <linux/timex.h>
14 #include <linux/static_key.h>
17 #include <asm/timer.h>
18 #include <asm/vgtod.h>
20 #include <asm/delay.h>
21 #include <asm/hypervisor.h>
23 #include <asm/x86_init.h>
24 #include <asm/geode.h>
26 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
27 EXPORT_SYMBOL(cpu_khz);
29 unsigned int __read_mostly tsc_khz;
30 EXPORT_SYMBOL(tsc_khz);
33 * TSC can be unstable due to cpufreq or due to unsynced TSCs
35 static int __read_mostly tsc_unstable;
37 /* native_sched_clock() is called before tsc_init(), so
38 we must start with the TSC soft disabled to prevent
39 erroneous rdtsc usage on !cpu_has_tsc processors */
40 static int __read_mostly tsc_disabled = -1;
42 static DEFINE_STATIC_KEY_FALSE(__use_tsc);
44 int tsc_clocksource_reliable;
47 * Use a ring-buffer like data structure, where a writer advances the head by
48 * writing a new data entry and a reader advances the tail when it observes a
51 * Writers are made to wait on readers until there's space to write a new
54 * This means that we can always use an {offset, mul} pair to compute a ns
55 * value that is 'roughly' in the right direction, even if we're writing a new
56 * {offset, mul} pair during the clock read.
58 * The down-side is that we can no longer guarantee strict monotonicity anymore
59 * (assuming the TSC was that to begin with), because while we compute the
60 * intersection point of the two clock slopes and make sure the time is
61 * continuous at the point of switching; we can no longer guarantee a reader is
62 * strictly before or after the switch point.
64 * It does mean a reader no longer needs to disable IRQs in order to avoid
65 * CPU-Freq updates messing with his times, and similarly an NMI reader will
66 * no longer run the risk of hitting half-written state.
70 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
71 struct cyc2ns_data *head; /* 48 + 8 = 56 */
72 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
73 }; /* exactly fits one cacheline */
75 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
77 struct cyc2ns_data *cyc2ns_read_begin(void)
79 struct cyc2ns_data *head;
83 head = this_cpu_read(cyc2ns.head);
85 * Ensure we observe the entry when we observe the pointer to it.
86 * matches the wmb from cyc2ns_write_end().
88 smp_read_barrier_depends();
95 void cyc2ns_read_end(struct cyc2ns_data *head)
99 * If we're the outer most nested read; update the tail pointer
100 * when we're done. This notifies possible pending writers
101 * that we've observed the head pointer and that the other
104 if (!--head->__count) {
106 * x86-TSO does not reorder writes with older reads;
107 * therefore once this write becomes visible to another
108 * cpu, we must be finished reading the cyc2ns_data.
110 * matches with cyc2ns_write_begin().
112 this_cpu_write(cyc2ns.tail, head);
118 * Begin writing a new @data entry for @cpu.
120 * Assumes some sort of write side lock; currently 'provided' by the assumption
121 * that cpufreq will call its notifiers sequentially.
123 static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
125 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
126 struct cyc2ns_data *data = c2n->data;
128 if (data == c2n->head)
131 /* XXX send an IPI to @cpu in order to guarantee a read? */
134 * When we observe the tail write from cyc2ns_read_end(),
135 * the cpu must be done with that entry and its safe
136 * to start writing to it.
138 while (c2n->tail == data)
144 static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
146 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
149 * Ensure the @data writes are visible before we publish the
150 * entry. Matches the data-depencency in cyc2ns_read_begin().
154 ACCESS_ONCE(c2n->head) = data;
158 * Accelerators for sched_clock()
159 * convert from cycles(64bits) => nanoseconds (64bits)
161 * ns = cycles / (freq / ns_per_sec)
162 * ns = cycles * (ns_per_sec / freq)
163 * ns = cycles * (10^9 / (cpu_khz * 10^3))
164 * ns = cycles * (10^6 / cpu_khz)
166 * Then we use scaling math (suggested by george@mvista.com) to get:
167 * ns = cycles * (10^6 * SC / cpu_khz) / SC
168 * ns = cycles * cyc2ns_scale / SC
170 * And since SC is a constant power of two, we can convert the div
173 * We can use khz divisor instead of mhz to keep a better precision, since
174 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
175 * (mathieu.desnoyers@polymtl.ca)
177 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
180 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
182 static void cyc2ns_data_init(struct cyc2ns_data *data)
184 data->cyc2ns_mul = 0;
185 data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
186 data->cyc2ns_offset = 0;
190 static void cyc2ns_init(int cpu)
192 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
194 cyc2ns_data_init(&c2n->data[0]);
195 cyc2ns_data_init(&c2n->data[1]);
197 c2n->head = c2n->data;
198 c2n->tail = c2n->data;
201 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
203 struct cyc2ns_data *data, *tail;
204 unsigned long long ns;
207 * See cyc2ns_read_*() for details; replicated in order to avoid
208 * an extra few instructions that came with the abstraction.
209 * Notable, it allows us to only do the __count and tail update
210 * dance when its actually needed.
213 preempt_disable_notrace();
214 data = this_cpu_read(cyc2ns.head);
215 tail = this_cpu_read(cyc2ns.tail);
217 if (likely(data == tail)) {
218 ns = data->cyc2ns_offset;
219 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
225 ns = data->cyc2ns_offset;
226 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
230 if (!--data->__count)
231 this_cpu_write(cyc2ns.tail, data);
233 preempt_enable_notrace();
238 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
240 unsigned long long tsc_now, ns_now;
241 struct cyc2ns_data *data;
244 local_irq_save(flags);
245 sched_clock_idle_sleep_event();
250 data = cyc2ns_write_begin(cpu);
253 ns_now = cycles_2_ns(tsc_now);
256 * Compute a new multiplier as per the above comment and ensure our
257 * time function is continuous; see the comment near struct
261 DIV_ROUND_CLOSEST(NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR,
263 data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
264 data->cyc2ns_offset = ns_now -
265 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
267 cyc2ns_write_end(cpu, data);
270 sched_clock_idle_wakeup_event(0);
271 local_irq_restore(flags);
274 * Scheduler clock - returns current time in nanosec units.
276 u64 native_sched_clock(void)
278 if (static_branch_likely(&__use_tsc)) {
279 u64 tsc_now = rdtsc();
281 /* return the value in ns */
282 return cycles_2_ns(tsc_now);
286 * Fall back to jiffies if there's no TSC available:
287 * ( But note that we still use it if the TSC is marked
288 * unstable. We do this because unlike Time Of Day,
289 * the scheduler clock tolerates small errors and it's
290 * very important for it to be as fast as the platform
294 /* No locking but a rare wrong value is not a big deal: */
295 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
299 * Generate a sched_clock if you already have a TSC value.
301 u64 native_sched_clock_from_tsc(u64 tsc)
303 return cycles_2_ns(tsc);
306 /* We need to define a real function for sched_clock, to override the
307 weak default version */
308 #ifdef CONFIG_PARAVIRT
309 unsigned long long sched_clock(void)
311 return paravirt_sched_clock();
315 sched_clock(void) __attribute__((alias("native_sched_clock")));
318 int check_tsc_unstable(void)
322 EXPORT_SYMBOL_GPL(check_tsc_unstable);
324 int check_tsc_disabled(void)
328 EXPORT_SYMBOL_GPL(check_tsc_disabled);
330 #ifdef CONFIG_X86_TSC
331 int __init notsc_setup(char *str)
333 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
339 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
342 int __init notsc_setup(char *str)
344 setup_clear_cpu_cap(X86_FEATURE_TSC);
349 __setup("notsc", notsc_setup);
351 static int no_sched_irq_time;
353 static int __init tsc_setup(char *str)
355 if (!strcmp(str, "reliable"))
356 tsc_clocksource_reliable = 1;
357 if (!strncmp(str, "noirqtime", 9))
358 no_sched_irq_time = 1;
362 __setup("tsc=", tsc_setup);
364 #define MAX_RETRIES 5
365 #define SMI_TRESHOLD 50000
368 * Read TSC and the reference counters. Take care of SMI disturbance
370 static u64 tsc_read_refs(u64 *p, int hpet)
375 for (i = 0; i < MAX_RETRIES; i++) {
378 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
380 *p = acpi_pm_read_early();
382 if ((t2 - t1) < SMI_TRESHOLD)
389 * Calculate the TSC frequency from HPET reference
391 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
396 hpet2 += 0x100000000ULL;
398 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
399 do_div(tmp, 1000000);
400 do_div(deltatsc, tmp);
402 return (unsigned long) deltatsc;
406 * Calculate the TSC frequency from PMTimer reference
408 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
416 pm2 += (u64)ACPI_PM_OVRRUN;
418 tmp = pm2 * 1000000000LL;
419 do_div(tmp, PMTMR_TICKS_PER_SEC);
420 do_div(deltatsc, tmp);
422 return (unsigned long) deltatsc;
426 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
427 #define CAL_PIT_LOOPS 1000
430 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
431 #define CAL2_PIT_LOOPS 5000
435 * Try to calibrate the TSC against the Programmable
436 * Interrupt Timer and return the frequency of the TSC
439 * Return ULONG_MAX on failure to calibrate.
441 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
443 u64 tsc, t1, t2, delta;
444 unsigned long tscmin, tscmax;
447 /* Set the Gate high, disable speaker */
448 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
451 * Setup CTC channel 2* for mode 0, (interrupt on terminal
452 * count mode), binary count. Set the latch register to 50ms
453 * (LSB then MSB) to begin countdown.
456 outb(latch & 0xff, 0x42);
457 outb(latch >> 8, 0x42);
459 tsc = t1 = t2 = get_cycles();
464 while ((inb(0x61) & 0x20) == 0) {
468 if ((unsigned long) delta < tscmin)
469 tscmin = (unsigned int) delta;
470 if ((unsigned long) delta > tscmax)
471 tscmax = (unsigned int) delta;
478 * If we were not able to read the PIT more than loopmin
479 * times, then we have been hit by a massive SMI
481 * If the maximum is 10 times larger than the minimum,
482 * then we got hit by an SMI as well.
484 if (pitcnt < loopmin || tscmax > 10 * tscmin)
487 /* Calculate the PIT value */
494 * This reads the current MSB of the PIT counter, and
495 * checks if we are running on sufficiently fast and
496 * non-virtualized hardware.
498 * Our expectations are:
500 * - the PIT is running at roughly 1.19MHz
502 * - each IO is going to take about 1us on real hardware,
503 * but we allow it to be much faster (by a factor of 10) or
504 * _slightly_ slower (ie we allow up to a 2us read+counter
505 * update - anything else implies a unacceptably slow CPU
506 * or PIT for the fast calibration to work.
508 * - with 256 PIT ticks to read the value, we have 214us to
509 * see the same MSB (and overhead like doing a single TSC
510 * read per MSB value etc).
512 * - We're doing 2 reads per loop (LSB, MSB), and we expect
513 * them each to take about a microsecond on real hardware.
514 * So we expect a count value of around 100. But we'll be
515 * generous, and accept anything over 50.
517 * - if the PIT is stuck, and we see *many* more reads, we
518 * return early (and the next caller of pit_expect_msb()
519 * then consider it a failure when they don't see the
520 * next expected value).
522 * These expectations mean that we know that we have seen the
523 * transition from one expected value to another with a fairly
524 * high accuracy, and we didn't miss any events. We can thus
525 * use the TSC value at the transitions to calculate a pretty
526 * good value for the TSC frequencty.
528 static inline int pit_verify_msb(unsigned char val)
532 return inb(0x42) == val;
535 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
538 u64 tsc = 0, prev_tsc = 0;
540 for (count = 0; count < 50000; count++) {
541 if (!pit_verify_msb(val))
546 *deltap = get_cycles() - prev_tsc;
550 * We require _some_ success, but the quality control
551 * will be based on the error terms on the TSC values.
557 * How many MSB values do we want to see? We aim for
558 * a maximum error rate of 500ppm (in practice the
559 * real error is much smaller), but refuse to spend
560 * more than 50ms on it.
562 #define MAX_QUICK_PIT_MS 50
563 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
565 static unsigned long quick_pit_calibrate(void)
569 unsigned long d1, d2;
571 /* Set the Gate high, disable speaker */
572 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
575 * Counter 2, mode 0 (one-shot), binary count
577 * NOTE! Mode 2 decrements by two (and then the
578 * output is flipped each time, giving the same
579 * final output frequency as a decrement-by-one),
580 * so mode 0 is much better when looking at the
585 /* Start at 0xffff */
590 * The PIT starts counting at the next edge, so we
591 * need to delay for a microsecond. The easiest way
592 * to do that is to just read back the 16-bit counter
597 if (pit_expect_msb(0xff, &tsc, &d1)) {
598 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
599 if (!pit_expect_msb(0xff-i, &delta, &d2))
605 * Extrapolate the error and fail fast if the error will
606 * never be below 500 ppm.
609 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
613 * Iterate until the error is less than 500 ppm
615 if (d1+d2 >= delta >> 11)
619 * Check the PIT one more time to verify that
620 * all TSC reads were stable wrt the PIT.
622 * This also guarantees serialization of the
623 * last cycle read ('d2') in pit_expect_msb.
625 if (!pit_verify_msb(0xfe - i))
630 pr_info("Fast TSC calibration failed\n");
635 * Ok, if we get here, then we've seen the
636 * MSB of the PIT decrement 'i' times, and the
637 * error has shrunk to less than 500 ppm.
639 * As a result, we can depend on there not being
640 * any odd delays anywhere, and the TSC reads are
641 * reliable (within the error).
643 * kHz = ticks / time-in-seconds / 1000;
644 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
645 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
647 delta *= PIT_TICK_RATE;
648 do_div(delta, i*256*1000);
649 pr_info("Fast TSC calibration using PIT\n");
654 * native_calibrate_tsc - calibrate the tsc on boot
656 unsigned long native_calibrate_tsc(void)
658 u64 tsc1, tsc2, delta, ref1, ref2;
659 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
660 unsigned long flags, latch, ms, fast_calibrate;
661 int hpet = is_hpet_enabled(), i, loopmin;
663 /* Calibrate TSC using MSR for Intel Atom SoCs */
664 local_irq_save(flags);
665 fast_calibrate = try_msr_calibrate_tsc();
666 local_irq_restore(flags);
668 return fast_calibrate;
670 local_irq_save(flags);
671 fast_calibrate = quick_pit_calibrate();
672 local_irq_restore(flags);
674 return fast_calibrate;
677 * Run 5 calibration loops to get the lowest frequency value
678 * (the best estimate). We use two different calibration modes
681 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
682 * load a timeout of 50ms. We read the time right after we
683 * started the timer and wait until the PIT count down reaches
684 * zero. In each wait loop iteration we read the TSC and check
685 * the delta to the previous read. We keep track of the min
686 * and max values of that delta. The delta is mostly defined
687 * by the IO time of the PIT access, so we can detect when a
688 * SMI/SMM disturbance happened between the two reads. If the
689 * maximum time is significantly larger than the minimum time,
690 * then we discard the result and have another try.
692 * 2) Reference counter. If available we use the HPET or the
693 * PMTIMER as a reference to check the sanity of that value.
694 * We use separate TSC readouts and check inside of the
695 * reference read for a SMI/SMM disturbance. We dicard
696 * disturbed values here as well. We do that around the PIT
697 * calibration delay loop as we have to wait for a certain
698 * amount of time anyway.
701 /* Preset PIT loop values */
704 loopmin = CAL_PIT_LOOPS;
706 for (i = 0; i < 3; i++) {
707 unsigned long tsc_pit_khz;
710 * Read the start value and the reference count of
711 * hpet/pmtimer when available. Then do the PIT
712 * calibration, which will take at least 50ms, and
713 * read the end value.
715 local_irq_save(flags);
716 tsc1 = tsc_read_refs(&ref1, hpet);
717 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
718 tsc2 = tsc_read_refs(&ref2, hpet);
719 local_irq_restore(flags);
721 /* Pick the lowest PIT TSC calibration so far */
722 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
724 /* hpet or pmtimer available ? */
728 /* Check, whether the sampling was disturbed by an SMI */
729 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
732 tsc2 = (tsc2 - tsc1) * 1000000LL;
734 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
736 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
738 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
740 /* Check the reference deviation */
741 delta = ((u64) tsc_pit_min) * 100;
742 do_div(delta, tsc_ref_min);
745 * If both calibration results are inside a 10% window
746 * then we can be sure, that the calibration
747 * succeeded. We break out of the loop right away. We
748 * use the reference value, as it is more precise.
750 if (delta >= 90 && delta <= 110) {
751 pr_info("PIT calibration matches %s. %d loops\n",
752 hpet ? "HPET" : "PMTIMER", i + 1);
757 * Check whether PIT failed more than once. This
758 * happens in virtualized environments. We need to
759 * give the virtual PC a slightly longer timeframe for
760 * the HPET/PMTIMER to make the result precise.
762 if (i == 1 && tsc_pit_min == ULONG_MAX) {
765 loopmin = CAL2_PIT_LOOPS;
770 * Now check the results.
772 if (tsc_pit_min == ULONG_MAX) {
773 /* PIT gave no useful value */
774 pr_warn("Unable to calibrate against PIT\n");
776 /* We don't have an alternative source, disable TSC */
777 if (!hpet && !ref1 && !ref2) {
778 pr_notice("No reference (HPET/PMTIMER) available\n");
782 /* The alternative source failed as well, disable TSC */
783 if (tsc_ref_min == ULONG_MAX) {
784 pr_warn("HPET/PMTIMER calibration failed\n");
788 /* Use the alternative source */
789 pr_info("using %s reference calibration\n",
790 hpet ? "HPET" : "PMTIMER");
795 /* We don't have an alternative source, use the PIT calibration value */
796 if (!hpet && !ref1 && !ref2) {
797 pr_info("Using PIT calibration value\n");
801 /* The alternative source failed, use the PIT calibration value */
802 if (tsc_ref_min == ULONG_MAX) {
803 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
808 * The calibration values differ too much. In doubt, we use
809 * the PIT value as we know that there are PMTIMERs around
810 * running at double speed. At least we let the user know:
812 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
813 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
814 pr_info("Using PIT calibration value\n");
818 int recalibrate_cpu_khz(void)
821 unsigned long cpu_khz_old = cpu_khz;
824 tsc_khz = x86_platform.calibrate_tsc();
826 cpu_data(0).loops_per_jiffy =
827 cpufreq_scale(cpu_data(0).loops_per_jiffy,
828 cpu_khz_old, cpu_khz);
837 EXPORT_SYMBOL(recalibrate_cpu_khz);
840 static unsigned long long cyc2ns_suspend;
842 void tsc_save_sched_clock_state(void)
844 if (!sched_clock_stable())
847 cyc2ns_suspend = sched_clock();
851 * Even on processors with invariant TSC, TSC gets reset in some the
852 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
853 * arbitrary value (still sync'd across cpu's) during resume from such sleep
854 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
855 * that sched_clock() continues from the point where it was left off during
858 void tsc_restore_sched_clock_state(void)
860 unsigned long long offset;
864 if (!sched_clock_stable())
867 local_irq_save(flags);
870 * We're comming out of suspend, there's no concurrency yet; don't
871 * bother being nice about the RCU stuff, just write to both
875 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
876 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
878 offset = cyc2ns_suspend - sched_clock();
880 for_each_possible_cpu(cpu) {
881 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
882 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
885 local_irq_restore(flags);
888 #ifdef CONFIG_CPU_FREQ
890 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
893 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
894 * not that important because current Opteron setups do not support
895 * scaling on SMP anyroads.
897 * Should fix up last_tsc too. Currently gettimeofday in the
898 * first tick after the change will be slightly wrong.
901 static unsigned int ref_freq;
902 static unsigned long loops_per_jiffy_ref;
903 static unsigned long tsc_khz_ref;
905 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
908 struct cpufreq_freqs *freq = data;
911 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
914 lpj = &boot_cpu_data.loops_per_jiffy;
916 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
917 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
921 ref_freq = freq->old;
922 loops_per_jiffy_ref = *lpj;
923 tsc_khz_ref = tsc_khz;
925 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
926 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
927 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
929 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
930 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
931 mark_tsc_unstable("cpufreq changes");
933 set_cyc2ns_scale(tsc_khz, freq->cpu);
939 static struct notifier_block time_cpufreq_notifier_block = {
940 .notifier_call = time_cpufreq_notifier
943 static int __init cpufreq_tsc(void)
947 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
949 cpufreq_register_notifier(&time_cpufreq_notifier_block,
950 CPUFREQ_TRANSITION_NOTIFIER);
954 core_initcall(cpufreq_tsc);
956 #endif /* CONFIG_CPU_FREQ */
958 /* clocksource code */
960 static struct clocksource clocksource_tsc;
963 * We used to compare the TSC to the cycle_last value in the clocksource
964 * structure to avoid a nasty time-warp. This can be observed in a
965 * very small window right after one CPU updated cycle_last under
966 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
967 * is smaller than the cycle_last reference value due to a TSC which
968 * is slighty behind. This delta is nowhere else observable, but in
969 * that case it results in a forward time jump in the range of hours
970 * due to the unsigned delta calculation of the time keeping core
971 * code, which is necessary to support wrapping clocksources like pm
974 * This sanity check is now done in the core timekeeping code.
975 * checking the result of read_tsc() - cycle_last for being negative.
976 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
978 static cycle_t read_tsc(struct clocksource *cs)
980 return (cycle_t)rdtsc_ordered();
984 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
986 static struct clocksource clocksource_tsc = {
990 .mask = CLOCKSOURCE_MASK(64),
991 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
992 CLOCK_SOURCE_MUST_VERIFY,
993 .archdata = { .vclock_mode = VCLOCK_TSC },
996 void mark_tsc_unstable(char *reason)
1000 clear_sched_clock_stable();
1001 disable_sched_clock_irqtime();
1002 pr_info("Marking TSC unstable due to %s\n", reason);
1003 /* Change only the rating, when not registered */
1004 if (clocksource_tsc.mult)
1005 clocksource_mark_unstable(&clocksource_tsc);
1007 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1008 clocksource_tsc.rating = 0;
1013 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1015 static void __init check_system_tsc_reliable(void)
1017 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1018 if (is_geode_lx()) {
1019 /* RTSC counts during suspend */
1020 #define RTSC_SUSP 0x100
1021 unsigned long res_low, res_high;
1023 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1024 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1025 if (res_low & RTSC_SUSP)
1026 tsc_clocksource_reliable = 1;
1029 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1030 tsc_clocksource_reliable = 1;
1034 * Make an educated guess if the TSC is trustworthy and synchronized
1037 int unsynchronized_tsc(void)
1039 if (!cpu_has_tsc || tsc_unstable)
1043 if (apic_is_clustered_box())
1047 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1050 if (tsc_clocksource_reliable)
1053 * Intel systems are normally all synchronized.
1054 * Exceptions must mark TSC as unstable:
1056 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1057 /* assume multi socket systems are not synchronized: */
1058 if (num_possible_cpus() > 1)
1066 static void tsc_refine_calibration_work(struct work_struct *work);
1067 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1069 * tsc_refine_calibration_work - Further refine tsc freq calibration
1072 * This functions uses delayed work over a period of a
1073 * second to further refine the TSC freq value. Since this is
1074 * timer based, instead of loop based, we don't block the boot
1075 * process while this longer calibration is done.
1077 * If there are any calibration anomalies (too many SMIs, etc),
1078 * or the refined calibration is off by 1% of the fast early
1079 * calibration, we throw out the new calibration and use the
1080 * early calibration.
1082 static void tsc_refine_calibration_work(struct work_struct *work)
1084 static u64 tsc_start = -1, ref_start;
1086 u64 tsc_stop, ref_stop, delta;
1089 /* Don't bother refining TSC on unstable systems */
1090 if (check_tsc_unstable())
1094 * Since the work is started early in boot, we may be
1095 * delayed the first time we expire. So set the workqueue
1096 * again once we know timers are working.
1098 if (tsc_start == -1) {
1100 * Only set hpet once, to avoid mixing hardware
1101 * if the hpet becomes enabled later.
1103 hpet = is_hpet_enabled();
1104 schedule_delayed_work(&tsc_irqwork, HZ);
1105 tsc_start = tsc_read_refs(&ref_start, hpet);
1109 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1111 /* hpet or pmtimer available ? */
1112 if (ref_start == ref_stop)
1115 /* Check, whether the sampling was disturbed by an SMI */
1116 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1119 delta = tsc_stop - tsc_start;
1122 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1124 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1126 /* Make sure we're within 1% */
1127 if (abs(tsc_khz - freq) > tsc_khz/100)
1131 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1132 (unsigned long)tsc_khz / 1000,
1133 (unsigned long)tsc_khz % 1000);
1136 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1140 static int __init init_tsc_clocksource(void)
1142 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
1145 if (tsc_clocksource_reliable)
1146 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1147 /* lower the rating if we already know its unstable: */
1148 if (check_tsc_unstable()) {
1149 clocksource_tsc.rating = 0;
1150 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1153 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1154 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1157 * Trust the results of the earlier calibration on systems
1158 * exporting a reliable TSC.
1160 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
1161 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1165 schedule_delayed_work(&tsc_irqwork, 0);
1169 * We use device_initcall here, to ensure we run after the hpet
1170 * is fully initialized, which may occur at fs_initcall time.
1172 device_initcall(init_tsc_clocksource);
1174 void __init tsc_init(void)
1179 x86_init.timers.tsc_pre_init();
1182 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1186 tsc_khz = x86_platform.calibrate_tsc();
1190 mark_tsc_unstable("could not calculate TSC khz");
1191 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1195 pr_info("Detected %lu.%03lu MHz processor\n",
1196 (unsigned long)cpu_khz / 1000,
1197 (unsigned long)cpu_khz % 1000);
1200 * Secondary CPUs do not run through tsc_init(), so set up
1201 * all the scale factors for all CPUs, assuming the same
1202 * speed as the bootup CPU. (cpufreq notifiers will fix this
1203 * up if their speed diverges)
1205 for_each_possible_cpu(cpu) {
1207 set_cyc2ns_scale(cpu_khz, cpu);
1210 if (tsc_disabled > 0)
1213 /* now allow native_sched_clock() to use rdtsc */
1216 static_branch_enable(&__use_tsc);
1218 if (!no_sched_irq_time)
1219 enable_sched_clock_irqtime();
1221 lpj = ((u64)tsc_khz * 1000);
1227 if (unsynchronized_tsc())
1228 mark_tsc_unstable("TSCs unsynchronized");
1230 check_system_tsc_reliable();
1235 * If we have a constant TSC and are using the TSC for the delay loop,
1236 * we can skip clock calibration if another cpu in the same socket has already
1237 * been calibrated. This assumes that CONSTANT_TSC applies to all
1238 * cpus in the socket - this should be a safe assumption.
1240 unsigned long calibrate_delay_is_known(void)
1242 int i, cpu = smp_processor_id();
1244 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1247 for_each_online_cpu(i)
1248 if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1249 return cpu_data(i).loops_per_jiffy;