2 * SGI Visual Workstation support and quirks, unmaintained.
4 * Split out from setup.c by davej@suse.de
6 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
8 * SGI Visual Workstation interrupt controller
10 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
11 * which serves as the main interrupt controller in the system. Non-legacy
12 * hardware in the system uses this controller directly. Legacy devices
13 * are connected to the PIIX4 which in turn has its 8259(s) connected to
14 * a of the Cobalt APIC entry.
16 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
18 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/smp.h>
25 #include <asm/visws/cobalt.h>
26 #include <asm/visws/piix4.h>
27 #include <asm/io_apic.h>
28 #include <asm/fixmap.h>
29 #include <asm/reboot.h>
30 #include <asm/setup.h>
35 #include <linux/kernel_stat.h>
37 #include <asm/i8259.h>
38 #include <asm/irq_vectors.h>
39 #include <asm/visws/lithium.h>
41 #include <linux/sched.h>
42 #include <linux/kernel.h>
43 #include <linux/pci.h>
44 #include <linux/pci_ids.h>
46 extern int no_broadcast;
48 char visws_board_type = -1;
49 char visws_board_rev = -1;
51 int is_visws_box(void)
53 return visws_board_type >= 0;
56 static int __init visws_time_init(void)
58 printk(KERN_INFO "Starting Cobalt Timer system clock\n");
60 /* Set the countdown value */
61 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
64 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
66 /* Enable (unmask) the timer interrupt */
67 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
70 * Zero return means the generic timer setup code will set up
71 * the standard vector:
76 /* Replaces the default init_ISA_irqs in the generic setup */
77 static void __init visws_pre_intr_init(void)
79 init_VISWS_APIC_irqs();
82 /* Quirk for machine specific memory setup. */
84 #define MB (1024 * 1024)
86 unsigned long sgivwfb_mem_phys;
87 unsigned long sgivwfb_mem_size;
88 EXPORT_SYMBOL(sgivwfb_mem_phys);
89 EXPORT_SYMBOL(sgivwfb_mem_size);
91 long long mem_size __initdata = 0;
93 static char * __init visws_memory_setup(void)
95 long long gfx_mem_size = 8 * MB;
97 mem_size = boot_params.alt_mem_k;
100 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
105 * this hardcodes the graphics memory to 8 MB
106 * it really should be sized dynamically (or at least
107 * set as a boot param)
109 if (!sgivwfb_mem_size) {
110 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
111 sgivwfb_mem_size = 8 * MB;
117 sgivwfb_mem_size &= ~((1 << 20) - 1);
118 sgivwfb_mem_phys = mem_size - gfx_mem_size;
120 e820_add_region(0, LOWMEMSIZE(), E820_RAM);
121 e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
122 e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
127 static void visws_machine_emergency_restart(void)
130 * Visual Workstations restart after this
131 * register is poked on the PIIX4
133 outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
136 static void visws_machine_power_off(void)
138 unsigned short pm_status;
139 /* extern unsigned int pci_bus0; */
141 while ((pm_status = inw(PMSTS_PORT)) & 0x100)
142 outw(pm_status, PMSTS_PORT);
144 outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
148 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
149 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
151 /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
152 outl(PIIX_SPECIAL_STOP, 0xCFC);
155 static void __init visws_get_smp_config(unsigned int early)
160 * The Visual Workstation is Intel MP compliant in the hardware
161 * sense, but it doesn't have a BIOS(-configuration table).
162 * No problem for Linux.
165 static void __init MP_processor_info(struct mpc_cpu *m)
167 int ver, logical_apicid;
168 physid_mask_t apic_cpus;
170 if (!(m->cpuflag & CPU_ENABLED))
173 logical_apicid = m->apicid;
174 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
175 m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
176 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
177 (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
179 if (m->cpuflag & CPU_BOOTPROCESSOR)
180 boot_cpu_physical_apicid = m->apicid;
183 if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
184 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
185 m->apicid, MAX_APICS);
189 apic_cpus = apic->apicid_to_cpu_present(m->apicid);
190 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
195 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
196 "fixing up to 0x10. (tell your hw vendor)\n",
200 apic_version[m->apicid] = ver;
203 static void __init visws_find_smp_config(unsigned int reserve)
205 struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
206 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
208 if (ncpus > CO_CPU_MAX) {
209 printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
215 if (ncpus > setup_max_cpus)
216 ncpus = setup_max_cpus;
218 #ifdef CONFIG_X86_LOCAL_APIC
219 smp_found_config = 1;
222 MP_processor_info(mp++);
224 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
227 static void visws_trap_init(void);
229 static struct x86_quirks visws_x86_quirks __initdata = {
230 .arch_time_init = visws_time_init,
233 void __init visws_early_detect(void)
237 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
238 >> PIIX_GPI_BD_SHIFT;
240 if (visws_board_type < 0)
244 * Install special quirks for timer, interrupt and memory setup:
245 * Fall back to generic behavior for traps:
246 * Override generic MP-table parsing:
248 x86_quirks = &visws_x86_quirks;
250 x86_init.resources.memory_setup = visws_memory_setup;
251 x86_init.mpparse.get_smp_config = visws_get_smp_config;
252 x86_init.mpparse.find_smp_config = visws_find_smp_config;
253 x86_init.irqs.pre_vector_init = visws_pre_intr_init;
254 x86_init.irqs.trap_init = visws_trap_init;
257 * Install reboot quirks:
259 pm_power_off = visws_machine_power_off;
260 machine_ops.emergency_restart = visws_machine_emergency_restart;
263 * Do not use broadcast IPIs:
267 #ifdef CONFIG_X86_IO_APIC
269 * Turn off IO-APIC detection and initialization:
271 skip_ioapic_setup = 1;
276 * First, we have to initialize the 307 part to allow us access
277 * to the GPIO registers. Let's map them at 0x0fc0 which is right
278 * after the PIIX4 PM section.
280 outb_p(SIO_DEV_SEL, SIO_INDEX);
281 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
283 outb_p(SIO_DEV_MSB, SIO_INDEX);
284 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
286 outb_p(SIO_DEV_LSB, SIO_INDEX);
287 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
289 outb_p(SIO_DEV_ENB, SIO_INDEX);
290 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
293 * Now, we have to map the power management section to write
294 * a bit which enables access to the GPIO registers.
295 * What lunatic came up with this shit?
297 outb_p(SIO_DEV_SEL, SIO_INDEX);
298 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
300 outb_p(SIO_DEV_MSB, SIO_INDEX);
301 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
303 outb_p(SIO_DEV_LSB, SIO_INDEX);
304 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
306 outb_p(SIO_DEV_ENB, SIO_INDEX);
307 outb_p(1, SIO_DATA); /* Enable PM registers. */
310 * Now, write the PM register which enables the GPIO registers.
312 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
313 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
316 * Now, initialize the GPIO registers.
317 * We want them all to be inputs which is the
318 * power on default, so let's leave them alone.
319 * So, let's just read the board rev!
321 raw = inb_p(SIO_GP_DATA1);
322 raw &= 0x7f; /* 7 bits of valid board revision ID. */
324 if (visws_board_type == VISWS_320) {
327 } else if (raw < 0xc) {
332 } else if (visws_board_type == VISWS_540) {
335 visws_board_rev = raw;
338 printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
339 (visws_board_type == VISWS_320 ? "320" :
340 (visws_board_type == VISWS_540 ? "540" :
341 "unknown")), visws_board_rev);
344 #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
345 #define BCD (LI_INTB | LI_INTC | LI_INTD)
346 #define ALLDEVS (A01234 | BCD)
348 static __init void lithium_init(void)
350 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
351 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
353 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
354 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
355 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
356 /* panic("This machine is not SGI Visual Workstation 320/540"); */
359 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
360 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
361 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
362 /* panic("This machine is not SGI Visual Workstation 320/540"); */
365 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
366 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
369 static __init void cobalt_init(void)
372 * On normal SMP PC this is used only with SMP, but we have to
373 * use it and set it up here to start the Cobalt clock
375 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
377 printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
378 (unsigned int)apic_read(APIC_LVR),
379 (unsigned int)apic_read(APIC_ID));
381 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
382 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
383 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
384 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
386 /* Enable Cobalt APIC being careful to NOT change the ID! */
387 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
389 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
390 co_apic_read(CO_APIC_ID));
393 static void __init visws_trap_init(void)
400 * IRQ controller / APIC support:
403 static DEFINE_SPINLOCK(cobalt_lock);
406 * Set the given Cobalt APIC Redirection Table entry to point
407 * to the given IDT vector/index.
409 static inline void co_apic_set(int entry, int irq)
411 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
412 co_apic_write(CO_APIC_HI(entry), 0);
416 * Cobalt (IO)-APIC functions to handle PCI devices.
418 static inline int co_apic_ide0_hack(void)
420 extern char visws_board_type;
421 extern char visws_board_rev;
423 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
428 static int is_co_apic(unsigned int irq)
434 case 0: return CO_APIC_CPU;
435 case CO_IRQ_IDE0: return co_apic_ide0_hack();
436 case CO_IRQ_IDE1: return CO_APIC_IDE1;
443 * This is the SGI Cobalt (IO-)APIC:
446 static void enable_cobalt_irq(unsigned int irq)
448 co_apic_set(is_co_apic(irq), irq);
451 static void disable_cobalt_irq(unsigned int irq)
453 int entry = is_co_apic(irq);
455 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
456 co_apic_read(CO_APIC_LO(entry));
460 * "irq" really just serves to identify the device. Here is where we
461 * map this to the Cobalt APIC entry where it's physically wired.
462 * This is called via request_irq -> setup_irq -> irq_desc->startup()
464 static unsigned int startup_cobalt_irq(unsigned int irq)
467 struct irq_desc *desc = irq_to_desc(irq);
469 spin_lock_irqsave(&cobalt_lock, flags);
470 if ((desc->status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
471 desc->status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
472 enable_cobalt_irq(irq);
473 spin_unlock_irqrestore(&cobalt_lock, flags);
477 static void ack_cobalt_irq(unsigned int irq)
481 spin_lock_irqsave(&cobalt_lock, flags);
482 disable_cobalt_irq(irq);
483 apic_write(APIC_EOI, APIC_EIO_ACK);
484 spin_unlock_irqrestore(&cobalt_lock, flags);
487 static void end_cobalt_irq(unsigned int irq)
490 struct irq_desc *desc = irq_to_desc(irq);
492 spin_lock_irqsave(&cobalt_lock, flags);
493 if (!(desc->status & (IRQ_DISABLED | IRQ_INPROGRESS)))
494 enable_cobalt_irq(irq);
495 spin_unlock_irqrestore(&cobalt_lock, flags);
498 static struct irq_chip cobalt_irq_type = {
499 .typename = "Cobalt-APIC",
500 .startup = startup_cobalt_irq,
501 .shutdown = disable_cobalt_irq,
502 .enable = enable_cobalt_irq,
503 .disable = disable_cobalt_irq,
504 .ack = ack_cobalt_irq,
505 .end = end_cobalt_irq,
510 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
511 * -- not the manner expected by the code in i8259.c.
513 * there is a 'master' physical interrupt source that gets sent to
514 * the CPU. But in the chipset there are various 'virtual' interrupts
515 * waiting to be handled. We represent this to Linux through a 'master'
516 * interrupt controller type, and through a special virtual interrupt-
517 * controller. Device drivers only see the virtual interrupt sources.
519 static unsigned int startup_piix4_master_irq(unsigned int irq)
523 return startup_cobalt_irq(irq);
526 static void end_piix4_master_irq(unsigned int irq)
530 spin_lock_irqsave(&cobalt_lock, flags);
531 enable_cobalt_irq(irq);
532 spin_unlock_irqrestore(&cobalt_lock, flags);
535 static struct irq_chip piix4_master_irq_type = {
536 .typename = "PIIX4-master",
537 .startup = startup_piix4_master_irq,
538 .ack = ack_cobalt_irq,
539 .end = end_piix4_master_irq,
543 static struct irq_chip piix4_virtual_irq_type = {
544 .typename = "PIIX4-virtual",
545 .shutdown = disable_8259A_irq,
546 .enable = enable_8259A_irq,
547 .disable = disable_8259A_irq,
552 * PIIX4-8259 master/virtual functions to handle interrupt requests
553 * from legacy devices: floppy, parallel, serial, rtc.
555 * None of these get Cobalt APIC entries, neither do they have IDT
556 * entries. These interrupts are purely virtual and distributed from
557 * the 'master' interrupt source: CO_IRQ_8259.
559 * When the 8259 interrupts its handler figures out which of these
560 * devices is interrupting and dispatches to its handler.
562 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
563 * enable_irq gets the right irq. This 'master' irq is never directly
564 * manipulated by any driver.
566 static irqreturn_t piix4_master_intr(int irq, void *dev_id)
569 struct irq_desc *desc;
572 spin_lock_irqsave(&i8259A_lock, flags);
574 /* Find out what's interrupting in the PIIX4 master 8259 */
575 outb(0x0c, 0x20); /* OCW3 Poll command */
579 * Bit 7 == 0 means invalid/spurious
581 if (unlikely(!(realirq & 0x80)))
586 if (unlikely(realirq == 2)) {
590 if (unlikely(!(realirq & 0x80)))
593 realirq = (realirq & 7) + 8;
596 /* mask and ack interrupt */
597 cached_irq_mask |= 1 << realirq;
598 if (unlikely(realirq > 7)) {
600 outb(cached_slave_mask, 0xa1);
601 outb(0x60 + (realirq & 7), 0xa0);
602 outb(0x60 + 2, 0x20);
605 outb(cached_master_mask, 0x21);
606 outb(0x60 + realirq, 0x20);
609 spin_unlock_irqrestore(&i8259A_lock, flags);
611 desc = irq_to_desc(realirq);
614 * handle this 'virtual interrupt' as a Cobalt one now.
616 kstat_incr_irqs_this_cpu(realirq, desc);
618 if (likely(desc->action != NULL))
619 handle_IRQ_event(realirq, desc->action);
621 if (!(desc->status & IRQ_DISABLED))
622 enable_8259A_irq(realirq);
627 spin_unlock_irqrestore(&i8259A_lock, flags);
631 static struct irqaction master_action = {
632 .handler = piix4_master_intr,
633 .name = "PIIX4-8259",
636 static struct irqaction cascade_action = {
637 .handler = no_action,
642 void init_VISWS_APIC_irqs(void)
646 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
647 struct irq_desc *desc = irq_to_desc(i);
649 desc->status = IRQ_DISABLED;
654 desc->chip = &cobalt_irq_type;
656 else if (i == CO_IRQ_IDE0) {
657 desc->chip = &cobalt_irq_type;
659 else if (i == CO_IRQ_IDE1) {
660 desc->chip = &cobalt_irq_type;
662 else if (i == CO_IRQ_8259) {
663 desc->chip = &piix4_master_irq_type;
665 else if (i < CO_IRQ_APIC0) {
666 desc->chip = &piix4_virtual_irq_type;
668 else if (IS_CO_APIC(i)) {
669 desc->chip = &cobalt_irq_type;
673 setup_irq(CO_IRQ_8259, &master_action);
674 setup_irq(2, &cascade_action);