arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  * Authors:
  26  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  27  *   Port from Qemu.
  28  */
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/bitops.h>
  32 #include "irq.h"
  33
  34 #include <linux/kvm_host.h>
  35 #include "trace.h"
  36
  37 #define pr_pic_unimpl(fmt, ...) \
  38         pr_err_ratelimited("kvm: pic: " fmt, ## __VA_ARGS__)
  39
  40 static void pic_irq_request(struct kvm *kvm, int level);
  41
  42 static void pic_lock(struct kvm_pic *s)
  43         __acquires(&s->lock)
  44 {
  45         spin_lock(&s->lock);
  46 }
  47
  48 static void pic_unlock(struct kvm_pic *s)
  49         __releases(&s->lock)
  50 {
  51         bool wakeup = s->wakeup_needed;
  52         struct kvm_vcpu *vcpu, *found = NULL;
  53         int i;
  54
  55         s->wakeup_needed = false;
  56
  57         spin_unlock(&s->lock);
  58
  59         if (wakeup) {
  60                 kvm_for_each_vcpu(i, vcpu, s->kvm) {
  61                         if (kvm_apic_accept_pic_intr(vcpu)) {
  62                                 found = vcpu;
  63                                 break;
  64                         }
  65                 }
  66
  67                 if (!found)
  68                         return;
  69
  70                 kvm_make_request(KVM_REQ_EVENT, found);
  71                 kvm_vcpu_kick(found);
  72         }
  73 }
  74
  75 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  76 {
  77         s->isr &= ~(1 << irq);
  78         if (s != &s->pics_state->pics[0])
  79                 irq += 8;
  80         /*
  81          * We are dropping lock while calling ack notifiers since ack
  82          * notifier callbacks for assigned devices call into PIC recursively.
  83          * Other interrupt may be delivered to PIC while lock is dropped but
  84          * it should be safe since PIC state is already updated at this stage.
  85          */
  86         pic_unlock(s->pics_state);
  87         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  88         pic_lock(s->pics_state);
  89 }
  90
  91 /*
  92  * set irq level. If an edge is detected, then the IRR is set to 1
  93  */
  94 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  95 {
  96         int mask, ret = 1;
  97         mask = 1 << irq;
  98         if (s->elcr & mask)     /* level triggered */
  99                 if (level) {
 100                         ret = !(s->irr & mask);
 101                         s->irr |= mask;
 102                         s->last_irr |= mask;
 103                 } else {
 104                         s->irr &= ~mask;
 105                         s->last_irr &= ~mask;
 106                 }
 107         else    /* edge triggered */
 108                 if (level) {
 109                         if ((s->last_irr & mask) == 0) {
 110                                 ret = !(s->irr & mask);
 111                                 s->irr |= mask;
 112                         }
 113                         s->last_irr |= mask;
 114                 } else
 115                         s->last_irr &= ~mask;
 116
 117         return (s->imr & mask) ? -1 : ret;
 118 }
 119
 120 /*
 121  * return the highest priority found in mask (highest = smallest
 122  * number). Return 8 if no irq
 123  */
 124 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 125 {
 126         int priority;
 127         if (mask == 0)
 128                 return 8;
 129         priority = 0;
 130         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 131                 priority++;
 132         return priority;
 133 }
 134
 135 /*
 136  * return the pic wanted interrupt. return -1 if none
 137  */
 138 static int pic_get_irq(struct kvm_kpic_state *s)
 139 {
 140         int mask, cur_priority, priority;
 141
 142         mask = s->irr & ~s->imr;
 143         priority = get_priority(s, mask);
 144         if (priority == 8)
 145                 return -1;
 146         /*
 147          * compute current priority. If special fully nested mode on the
 148          * master, the IRQ coming from the slave is not taken into account
 149          * for the priority computation.
 150          */
 151         mask = s->isr;
 152         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 153                 mask &= ~(1 << 2);
 154         cur_priority = get_priority(s, mask);
 155         if (priority < cur_priority)
 156                 /*
 157                  * higher priority found: an irq should be generated
 158                  */
 159                 return (priority + s->priority_add) & 7;
 160         else
 161                 return -1;
 162 }
 163
 164 /*
 165  * raise irq to CPU if necessary. must be called every time the active
 166  * irq may change
 167  */
 168 static void pic_update_irq(struct kvm_pic *s)
 169 {
 170         int irq2, irq;
 171
 172         irq2 = pic_get_irq(&s->pics[1]);
 173         if (irq2 >= 0) {
 174                 /*
 175                  * if irq request by slave pic, signal master PIC
 176                  */
 177                 pic_set_irq1(&s->pics[0], 2, 1);
 178                 pic_set_irq1(&s->pics[0], 2, 0);
 179         }
 180         irq = pic_get_irq(&s->pics[0]);
 181         pic_irq_request(s->kvm, irq >= 0);
 182 }
 183
 184 void kvm_pic_update_irq(struct kvm_pic *s)
 185 {
 186         pic_lock(s);
 187         pic_update_irq(s);
 188         pic_unlock(s);
 189 }
 190
 191 int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
 192 {
 193         int ret, irq_level;
 194
 195         BUG_ON(irq < 0 || irq >= PIC_NUM_PINS);
 196
 197         pic_lock(s);
 198         irq_level = __kvm_irq_line_state(&s->irq_states[irq],
 199                                          irq_source_id, level);
 200         ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
 201         pic_update_irq(s);
 202         trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 203                               s->pics[irq >> 3].imr, ret == 0);
 204         pic_unlock(s);
 205
 206         return ret;
 207 }
 208
 209 void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
 210 {
 211         int i;
 212
 213         pic_lock(s);
 214         for (i = 0; i < PIC_NUM_PINS; i++)
 215                 __clear_bit(irq_source_id, &s->irq_states[i]);
 216         pic_unlock(s);
 217 }
 218
 219 /*
 220  * acknowledge interrupt 'irq'
 221  */
 222 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 223 {
 224         s->isr |= 1 << irq;
 225         /*
 226          * We don't clear a level sensitive interrupt here
 227          */
 228         if (!(s->elcr & (1 << irq)))
 229                 s->irr &= ~(1 << irq);
 230
 231         if (s->auto_eoi) {
 232                 if (s->rotate_on_auto_eoi)
 233                         s->priority_add = (irq + 1) & 7;
 234                 pic_clear_isr(s, irq);
 235         }
 236
 237 }
 238
 239 int kvm_pic_read_irq(struct kvm *kvm)
 240 {
 241         int irq, irq2, intno;
 242         struct kvm_pic *s = pic_irqchip(kvm);
 243
 244         s->output = 0;
 245
 246         pic_lock(s);
 247         irq = pic_get_irq(&s->pics[0]);
 248         if (irq >= 0) {
 249                 pic_intack(&s->pics[0], irq);
 250                 if (irq == 2) {
 251                         irq2 = pic_get_irq(&s->pics[1]);
 252                         if (irq2 >= 0)
 253                                 pic_intack(&s->pics[1], irq2);
 254                         else
 255                                 /*
 256                                  * spurious IRQ on slave controller
 257                                  */
 258                                 irq2 = 7;
 259                         intno = s->pics[1].irq_base + irq2;
 260                         irq = irq2 + 8;
 261                 } else
 262                         intno = s->pics[0].irq_base + irq;
 263         } else {
 264                 /*
 265                  * spurious IRQ on host controller
 266                  */
 267                 irq = 7;
 268                 intno = s->pics[0].irq_base + irq;
 269         }
 270         pic_update_irq(s);
 271         pic_unlock(s);
 272
 273         return intno;
 274 }
 275
 276 void kvm_pic_reset(struct kvm_kpic_state *s)
 277 {
 278         int irq, i;
 279         struct kvm_vcpu *vcpu;
 280         u8 edge_irr = s->irr & ~s->elcr;
 281         bool found = false;
 282
 283         s->last_irr = 0;
 284         s->irr &= s->elcr;
 285         s->imr = 0;
 286         s->priority_add = 0;
 287         s->special_mask = 0;
 288         s->read_reg_select = 0;
 289         if (!s->init4) {
 290                 s->special_fully_nested_mode = 0;
 291                 s->auto_eoi = 0;
 292         }
 293         s->init_state = 1;
 294
 295         kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
 296                 if (kvm_apic_accept_pic_intr(vcpu)) {
 297                         found = true;
 298                         break;
 299                 }
 300
 301
 302         if (!found)
 303                 return;
 304
 305         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 306                 if (edge_irr & (1 << irq))
 307                         pic_clear_isr(s, irq);
 308 }
 309
 310 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 311 {
 312         struct kvm_kpic_state *s = opaque;
 313         int priority, cmd, irq;
 314
 315         addr &= 1;
 316         if (addr == 0) {
 317                 if (val & 0x10) {
 318                         s->init4 = val & 1;
 319                         if (val & 0x02)
 320                                 pr_pic_unimpl("single mode not supported");
 321                         if (val & 0x08)
 322                                 pr_pic_unimpl(
 323                                                 "level sensitive irq not supported");
 324                         kvm_pic_reset(s);
 325                 } else if (val & 0x08) {
 326                         if (val & 0x04)
 327                                 s->poll = 1;
 328                         if (val & 0x02)
 329                                 s->read_reg_select = val & 1;
 330                         if (val & 0x40)
 331                                 s->special_mask = (val >> 5) & 1;
 332                 } else {
 333                         cmd = val >> 5;
 334                         switch (cmd) {
 335                         case 0:
 336                         case 4:
 337                                 s->rotate_on_auto_eoi = cmd >> 2;
 338                                 break;
 339                         case 1: /* end of interrupt */
 340                         case 5:
 341                                 priority = get_priority(s, s->isr);
 342                                 if (priority != 8) {
 343                                         irq = (priority + s->priority_add) & 7;
 344                                         if (cmd == 5)
 345                                                 s->priority_add = (irq + 1) & 7;
 346                                         pic_clear_isr(s, irq);
 347                                         pic_update_irq(s->pics_state);
 348                                 }
 349                                 break;
 350                         case 3:
 351                                 irq = val & 7;
 352                                 pic_clear_isr(s, irq);
 353                                 pic_update_irq(s->pics_state);
 354                                 break;
 355                         case 6:
 356                                 s->priority_add = (val + 1) & 7;
 357                                 pic_update_irq(s->pics_state);
 358                                 break;
 359                         case 7:
 360                                 irq = val & 7;
 361                                 s->priority_add = (irq + 1) & 7;
 362                                 pic_clear_isr(s, irq);
 363                                 pic_update_irq(s->pics_state);
 364                                 break;
 365                         default:
 366                                 break;  /* no operation */
 367                         }
 368                 }
 369         } else
 370                 switch (s->init_state) {
 371                 case 0: { /* normal mode */
 372                         u8 imr_diff = s->imr ^ val,
 373                                 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
 374                         s->imr = val;
 375                         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 376                                 if (imr_diff & (1 << irq))
 377                                         kvm_fire_mask_notifiers(
 378                                                 s->pics_state->kvm,
 379                                                 SELECT_PIC(irq + off),
 380                                                 irq + off,
 381                                                 !!(s->imr & (1 << irq)));
 382                         pic_update_irq(s->pics_state);
 383                         break;
 384                 }
 385                 case 1:
 386                         s->irq_base = val & 0xf8;
 387                         s->init_state = 2;
 388                         break;
 389                 case 2:
 390                         if (s->init4)
 391                                 s->init_state = 3;
 392                         else
 393                                 s->init_state = 0;
 394                         break;
 395                 case 3:
 396                         s->special_fully_nested_mode = (val >> 4) & 1;
 397                         s->auto_eoi = (val >> 1) & 1;
 398                         s->init_state = 0;
 399                         break;
 400                 }
 401 }
 402
 403 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 404 {
 405         int ret;
 406
 407         ret = pic_get_irq(s);
 408         if (ret >= 0) {
 409                 if (addr1 >> 7) {
 410                         s->pics_state->pics[0].isr &= ~(1 << 2);
 411                         s->pics_state->pics[0].irr &= ~(1 << 2);
 412                 }
 413                 s->irr &= ~(1 << ret);
 414                 pic_clear_isr(s, ret);
 415                 if (addr1 >> 7 || ret != 2)
 416                         pic_update_irq(s->pics_state);
 417         } else {
 418                 ret = 0x07;
 419                 pic_update_irq(s->pics_state);
 420         }
 421
 422         return ret;
 423 }
 424
 425 static u32 pic_ioport_read(void *opaque, u32 addr1)
 426 {
 427         struct kvm_kpic_state *s = opaque;
 428         unsigned int addr;
 429         int ret;
 430
 431         addr = addr1;
 432         addr &= 1;
 433         if (s->poll) {
 434                 ret = pic_poll_read(s, addr1);
 435                 s->poll = 0;
 436         } else
 437                 if (addr == 0)
 438                         if (s->read_reg_select)
 439                                 ret = s->isr;
 440                         else
 441                                 ret = s->irr;
 442                 else
 443                         ret = s->imr;
 444         return ret;
 445 }
 446
 447 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 448 {
 449         struct kvm_kpic_state *s = opaque;
 450         s->elcr = val & s->elcr_mask;
 451 }
 452
 453 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 454 {
 455         struct kvm_kpic_state *s = opaque;
 456         return s->elcr;
 457 }
 458
 459 static int picdev_in_range(gpa_t addr)
 460 {
 461         switch (addr) {
 462         case 0x20:
 463         case 0x21:
 464         case 0xa0:
 465         case 0xa1:
 466         case 0x4d0:
 467         case 0x4d1:
 468                 return 1;
 469         default:
 470                 return 0;
 471         }
 472 }
 473
 474 static int picdev_write(struct kvm_pic *s,
 475                          gpa_t addr, int len, const void *val)
 476 {
 477         unsigned char data = *(unsigned char *)val;
 478         if (!picdev_in_range(addr))
 479                 return -EOPNOTSUPP;
 480
 481         if (len != 1) {
 482                 pr_pic_unimpl("non byte write\n");
 483                 return 0;
 484         }
 485         pic_lock(s);
 486         switch (addr) {
 487         case 0x20:
 488         case 0x21:
 489         case 0xa0:
 490         case 0xa1:
 491                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 492                 break;
 493         case 0x4d0:
 494         case 0x4d1:
 495                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 496                 break;
 497         }
 498         pic_unlock(s);
 499         return 0;
 500 }
 501
 502 static int picdev_read(struct kvm_pic *s,
 503                        gpa_t addr, int len, void *val)
 504 {
 505         unsigned char data = 0;
 506         if (!picdev_in_range(addr))
 507                 return -EOPNOTSUPP;
 508
 509         if (len != 1) {
 510                 memset(val, 0, len);
 511                 pr_pic_unimpl("non byte read\n");
 512                 return 0;
 513         }
 514         pic_lock(s);
 515         switch (addr) {
 516         case 0x20:
 517         case 0x21:
 518         case 0xa0:
 519         case 0xa1:
 520                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 521                 break;
 522         case 0x4d0:
 523         case 0x4d1:
 524                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 525                 break;
 526         }
 527         *(unsigned char *)val = data;
 528         pic_unlock(s);
 529         return 0;
 530 }
 531
 532 static int picdev_master_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 533                                gpa_t addr, int len, const void *val)
 534 {
 535         return picdev_write(container_of(dev, struct kvm_pic, dev_master),
 536                             addr, len, val);
 537 }
 538
 539 static int picdev_master_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 540                               gpa_t addr, int len, void *val)
 541 {
 542         return picdev_read(container_of(dev, struct kvm_pic, dev_master),
 543                             addr, len, val);
 544 }
 545
 546 static int picdev_slave_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 547                               gpa_t addr, int len, const void *val)
 548 {
 549         return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
 550                             addr, len, val);
 551 }
 552
 553 static int picdev_slave_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 554                              gpa_t addr, int len, void *val)
 555 {
 556         return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
 557                             addr, len, val);
 558 }
 559
 560 static int picdev_eclr_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 561                              gpa_t addr, int len, const void *val)
 562 {
 563         return picdev_write(container_of(dev, struct kvm_pic, dev_eclr),
 564                             addr, len, val);
 565 }
 566
 567 static int picdev_eclr_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 568                             gpa_t addr, int len, void *val)
 569 {
 570         return picdev_read(container_of(dev, struct kvm_pic, dev_eclr),
 571                             addr, len, val);
 572 }
 573
 574 /*
 575  * callback when PIC0 irq status changed
 576  */
 577 static void pic_irq_request(struct kvm *kvm, int level)
 578 {
 579         struct kvm_pic *s = pic_irqchip(kvm);
 580
 581         if (!s->output)
 582                 s->wakeup_needed = true;
 583         s->output = level;
 584 }
 585
 586 static const struct kvm_io_device_ops picdev_master_ops = {
 587         .read     = picdev_master_read,
 588         .write    = picdev_master_write,
 589 };
 590
 591 static const struct kvm_io_device_ops picdev_slave_ops = {
 592         .read     = picdev_slave_read,
 593         .write    = picdev_slave_write,
 594 };
 595
 596 static const struct kvm_io_device_ops picdev_eclr_ops = {
 597         .read     = picdev_eclr_read,
 598         .write    = picdev_eclr_write,
 599 };
 600
 601 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 602 {
 603         struct kvm_pic *s;
 604         int ret;
 605
 606         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 607         if (!s)
 608                 return NULL;
 609         spin_lock_init(&s->lock);
 610         s->kvm = kvm;
 611         s->pics[0].elcr_mask = 0xf8;
 612         s->pics[1].elcr_mask = 0xde;
 613         s->pics[0].pics_state = s;
 614         s->pics[1].pics_state = s;
 615
 616         /*
 617          * Initialize PIO device
 618          */
 619         kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
 620         kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
 621         kvm_iodevice_init(&s->dev_eclr, &picdev_eclr_ops);
 622         mutex_lock(&kvm->slots_lock);
 623         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
 624                                       &s->dev_master);
 625         if (ret < 0)
 626                 goto fail_unlock;
 627
 628         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
 629         if (ret < 0)
 630                 goto fail_unreg_2;
 631
 632         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_eclr);
 633         if (ret < 0)
 634                 goto fail_unreg_1;
 635
 636         mutex_unlock(&kvm->slots_lock);
 637
 638         return s;
 639
 640 fail_unreg_1:
 641         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
 642
 643 fail_unreg_2:
 644         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
 645
 646 fail_unlock:
 647         mutex_unlock(&kvm->slots_lock);
 648
 649         kfree(s);
 650
 651         return NULL;
 652 }
 653
 654 void kvm_destroy_pic(struct kvm_pic *vpic)
 655 {
 656         kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_master);
 657         kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_slave);
 658         kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_eclr);
 659         kfree(vpic);
 660 }