arm/arm64: KVM: Enforce unconditional flush to PoC when mapping to stage-2
[firefly-linux-kernel-4.4.55.git] / arch / x86 / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
4  *
5  *    MandrakeSoft S.A.
6  *    43, rue d'Aboukir
7  *    75002 Paris - France
8  *    http://www.linux-mandrake.com/
9  *    http://www.mandrakesoft.com/
10  *
11  *  This library is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU Lesser General Public
13  *  License as published by the Free Software Foundation; either
14  *  version 2 of the License, or (at your option) any later version.
15  *
16  *  This library is distributed in the hope that it will be useful,
17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19  *  Lesser General Public License for more details.
20  *
21  *  You should have received a copy of the GNU Lesser General Public
22  *  License along with this library; if not, write to the Free Software
23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
24  *
25  *  Yunhong Jiang <yunhong.jiang@intel.com>
26  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
27  *  Based on Xen 3.1 code.
28  */
29
30 #include <linux/kvm_host.h>
31 #include <linux/kvm.h>
32 #include <linux/mm.h>
33 #include <linux/highmem.h>
34 #include <linux/smp.h>
35 #include <linux/hrtimer.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/export.h>
39 #include <asm/processor.h>
40 #include <asm/page.h>
41 #include <asm/current.h>
42 #include <trace/events/kvm.h>
43
44 #include "ioapic.h"
45 #include "lapic.h"
46 #include "irq.h"
47
48 #if 0
49 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
50 #else
51 #define ioapic_debug(fmt, arg...)
52 #endif
53 static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
54                 bool line_status);
55
56 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
57                                           unsigned long addr,
58                                           unsigned long length)
59 {
60         unsigned long result = 0;
61
62         switch (ioapic->ioregsel) {
63         case IOAPIC_REG_VERSION:
64                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
65                           | (IOAPIC_VERSION_ID & 0xff));
66                 break;
67
68         case IOAPIC_REG_APIC_ID:
69         case IOAPIC_REG_ARB_ID:
70                 result = ((ioapic->id & 0xf) << 24);
71                 break;
72
73         default:
74                 {
75                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
76                         u64 redir_content;
77
78                         if (redir_index < IOAPIC_NUM_PINS)
79                                 redir_content =
80                                         ioapic->redirtbl[redir_index].bits;
81                         else
82                                 redir_content = ~0ULL;
83
84                         result = (ioapic->ioregsel & 0x1) ?
85                             (redir_content >> 32) & 0xffffffff :
86                             redir_content & 0xffffffff;
87                         break;
88                 }
89         }
90
91         return result;
92 }
93
94 static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
95 {
96         ioapic->rtc_status.pending_eoi = 0;
97         bitmap_zero(ioapic->rtc_status.dest_map, KVM_MAX_VCPUS);
98 }
99
100 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);
101
102 static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
103 {
104         if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
105                 kvm_rtc_eoi_tracking_restore_all(ioapic);
106 }
107
108 static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
109 {
110         bool new_val, old_val;
111         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
112         union kvm_ioapic_redirect_entry *e;
113
114         e = &ioapic->redirtbl[RTC_GSI];
115         if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id,
116                                 e->fields.dest_mode))
117                 return;
118
119         new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
120         old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
121
122         if (new_val == old_val)
123                 return;
124
125         if (new_val) {
126                 __set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
127                 ioapic->rtc_status.pending_eoi++;
128         } else {
129                 __clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
130                 ioapic->rtc_status.pending_eoi--;
131                 rtc_status_pending_eoi_check_valid(ioapic);
132         }
133 }
134
135 void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
136 {
137         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
138
139         spin_lock(&ioapic->lock);
140         __rtc_irq_eoi_tracking_restore_one(vcpu);
141         spin_unlock(&ioapic->lock);
142 }
143
144 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
145 {
146         struct kvm_vcpu *vcpu;
147         int i;
148
149         if (RTC_GSI >= IOAPIC_NUM_PINS)
150                 return;
151
152         rtc_irq_eoi_tracking_reset(ioapic);
153         kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
154             __rtc_irq_eoi_tracking_restore_one(vcpu);
155 }
156
157 static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu)
158 {
159         if (test_and_clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map)) {
160                 --ioapic->rtc_status.pending_eoi;
161                 rtc_status_pending_eoi_check_valid(ioapic);
162         }
163 }
164
165 static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
166 {
167         if (ioapic->rtc_status.pending_eoi > 0)
168                 return true; /* coalesced */
169
170         return false;
171 }
172
173 static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
174                 int irq_level, bool line_status)
175 {
176         union kvm_ioapic_redirect_entry entry;
177         u32 mask = 1 << irq;
178         u32 old_irr;
179         int edge, ret;
180
181         entry = ioapic->redirtbl[irq];
182         edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
183
184         if (!irq_level) {
185                 ioapic->irr &= ~mask;
186                 ret = 1;
187                 goto out;
188         }
189
190         /*
191          * Return 0 for coalesced interrupts; for edge-triggered interrupts,
192          * this only happens if a previous edge has not been delivered due
193          * do masking.  For level interrupts, the remote_irr field tells
194          * us if the interrupt is waiting for an EOI.
195          *
196          * RTC is special: it is edge-triggered, but userspace likes to know
197          * if it has been already ack-ed via EOI because coalesced RTC
198          * interrupts lead to time drift in Windows guests.  So we track
199          * EOI manually for the RTC interrupt.
200          */
201         if (irq == RTC_GSI && line_status &&
202                 rtc_irq_check_coalesced(ioapic)) {
203                 ret = 0;
204                 goto out;
205         }
206
207         old_irr = ioapic->irr;
208         ioapic->irr |= mask;
209         if (edge)
210                 ioapic->irr_delivered &= ~mask;
211         if ((edge && old_irr == ioapic->irr) ||
212             (!edge && entry.fields.remote_irr)) {
213                 ret = 0;
214                 goto out;
215         }
216
217         ret = ioapic_service(ioapic, irq, line_status);
218
219 out:
220         trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
221         return ret;
222 }
223
224 static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
225 {
226         u32 idx;
227
228         rtc_irq_eoi_tracking_reset(ioapic);
229         for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
230                 ioapic_set_irq(ioapic, idx, 1, true);
231
232         kvm_rtc_eoi_tracking_restore_all(ioapic);
233 }
234
235
236 void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
237 {
238         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
239         union kvm_ioapic_redirect_entry *e;
240         int index;
241
242         spin_lock(&ioapic->lock);
243         for (index = 0; index < IOAPIC_NUM_PINS; index++) {
244                 e = &ioapic->redirtbl[index];
245                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
246                     kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) ||
247                     index == RTC_GSI) {
248                         if (kvm_apic_match_dest(vcpu, NULL, 0,
249                                      e->fields.dest_id, e->fields.dest_mode) ||
250                             (e->fields.trig_mode == IOAPIC_EDGE_TRIG &&
251                              kvm_apic_pending_eoi(vcpu, e->fields.vector)))
252                                 __set_bit(e->fields.vector,
253                                         (unsigned long *)eoi_exit_bitmap);
254                 }
255         }
256         spin_unlock(&ioapic->lock);
257 }
258
259 void kvm_vcpu_request_scan_ioapic(struct kvm *kvm)
260 {
261         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
262
263         if (!ioapic)
264                 return;
265         kvm_make_scan_ioapic_request(kvm);
266 }
267
268 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
269 {
270         unsigned index;
271         bool mask_before, mask_after;
272         union kvm_ioapic_redirect_entry *e;
273
274         switch (ioapic->ioregsel) {
275         case IOAPIC_REG_VERSION:
276                 /* Writes are ignored. */
277                 break;
278
279         case IOAPIC_REG_APIC_ID:
280                 ioapic->id = (val >> 24) & 0xf;
281                 break;
282
283         case IOAPIC_REG_ARB_ID:
284                 break;
285
286         default:
287                 index = (ioapic->ioregsel - 0x10) >> 1;
288
289                 ioapic_debug("change redir index %x val %x\n", index, val);
290                 if (index >= IOAPIC_NUM_PINS)
291                         return;
292                 e = &ioapic->redirtbl[index];
293                 mask_before = e->fields.mask;
294                 if (ioapic->ioregsel & 1) {
295                         e->bits &= 0xffffffff;
296                         e->bits |= (u64) val << 32;
297                 } else {
298                         e->bits &= ~0xffffffffULL;
299                         e->bits |= (u32) val;
300                         e->fields.remote_irr = 0;
301                 }
302                 mask_after = e->fields.mask;
303                 if (mask_before != mask_after)
304                         kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
305                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
306                     && ioapic->irr & (1 << index))
307                         ioapic_service(ioapic, index, false);
308                 kvm_vcpu_request_scan_ioapic(ioapic->kvm);
309                 break;
310         }
311 }
312
313 static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
314 {
315         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
316         struct kvm_lapic_irq irqe;
317         int ret;
318
319         if (entry->fields.mask)
320                 return -1;
321
322         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
323                      "vector=%x trig_mode=%x\n",
324                      entry->fields.dest_id, entry->fields.dest_mode,
325                      entry->fields.delivery_mode, entry->fields.vector,
326                      entry->fields.trig_mode);
327
328         irqe.dest_id = entry->fields.dest_id;
329         irqe.vector = entry->fields.vector;
330         irqe.dest_mode = entry->fields.dest_mode;
331         irqe.trig_mode = entry->fields.trig_mode;
332         irqe.delivery_mode = entry->fields.delivery_mode << 8;
333         irqe.level = 1;
334         irqe.shorthand = 0;
335         irqe.msi_redir_hint = false;
336
337         if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
338                 ioapic->irr_delivered |= 1 << irq;
339
340         if (irq == RTC_GSI && line_status) {
341                 /*
342                  * pending_eoi cannot ever become negative (see
343                  * rtc_status_pending_eoi_check_valid) and the caller
344                  * ensures that it is only called if it is >= zero, namely
345                  * if rtc_irq_check_coalesced returns false).
346                  */
347                 BUG_ON(ioapic->rtc_status.pending_eoi != 0);
348                 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
349                                 ioapic->rtc_status.dest_map);
350                 ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
351         } else
352                 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
353
354         if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
355                 entry->fields.remote_irr = 1;
356
357         return ret;
358 }
359
360 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
361                        int level, bool line_status)
362 {
363         int ret, irq_level;
364
365         BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
366
367         spin_lock(&ioapic->lock);
368         irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
369                                          irq_source_id, level);
370         ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);
371
372         spin_unlock(&ioapic->lock);
373
374         return ret;
375 }
376
377 void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
378 {
379         int i;
380
381         spin_lock(&ioapic->lock);
382         for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
383                 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
384         spin_unlock(&ioapic->lock);
385 }
386
387 static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
388 {
389         int i;
390         struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
391                                                  eoi_inject.work);
392         spin_lock(&ioapic->lock);
393         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
394                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
395
396                 if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
397                         continue;
398
399                 if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
400                         ioapic_service(ioapic, i, false);
401         }
402         spin_unlock(&ioapic->lock);
403 }
404
405 #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
406
407 static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu,
408                         struct kvm_ioapic *ioapic, int vector, int trigger_mode)
409 {
410         int i;
411         struct kvm_lapic *apic = vcpu->arch.apic;
412
413         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
414                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
415
416                 if (ent->fields.vector != vector)
417                         continue;
418
419                 if (i == RTC_GSI)
420                         rtc_irq_eoi(ioapic, vcpu);
421                 /*
422                  * We are dropping lock while calling ack notifiers because ack
423                  * notifier callbacks for assigned devices call into IOAPIC
424                  * recursively. Since remote_irr is cleared only after call
425                  * to notifiers if the same vector will be delivered while lock
426                  * is dropped it will be put into irr and will be delivered
427                  * after ack notifier returns.
428                  */
429                 spin_unlock(&ioapic->lock);
430                 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
431                 spin_lock(&ioapic->lock);
432
433                 if (trigger_mode != IOAPIC_LEVEL_TRIG ||
434                     kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
435                         continue;
436
437                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
438                 ent->fields.remote_irr = 0;
439                 if (!ent->fields.mask && (ioapic->irr & (1 << i))) {
440                         ++ioapic->irq_eoi[i];
441                         if (ioapic->irq_eoi[i] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
442                                 /*
443                                  * Real hardware does not deliver the interrupt
444                                  * immediately during eoi broadcast, and this
445                                  * lets a buggy guest make slow progress
446                                  * even if it does not correctly handle a
447                                  * level-triggered interrupt.  Emulate this
448                                  * behavior if we detect an interrupt storm.
449                                  */
450                                 schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
451                                 ioapic->irq_eoi[i] = 0;
452                                 trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
453                         } else {
454                                 ioapic_service(ioapic, i, false);
455                         }
456                 } else {
457                         ioapic->irq_eoi[i] = 0;
458                 }
459         }
460 }
461
462 void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
463 {
464         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
465
466         spin_lock(&ioapic->lock);
467         __kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode);
468         spin_unlock(&ioapic->lock);
469 }
470
471 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
472 {
473         return container_of(dev, struct kvm_ioapic, dev);
474 }
475
476 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
477 {
478         return ((addr >= ioapic->base_address &&
479                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
480 }
481
482 static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
483                                 gpa_t addr, int len, void *val)
484 {
485         struct kvm_ioapic *ioapic = to_ioapic(this);
486         u32 result;
487         if (!ioapic_in_range(ioapic, addr))
488                 return -EOPNOTSUPP;
489
490         ioapic_debug("addr %lx\n", (unsigned long)addr);
491         ASSERT(!(addr & 0xf));  /* check alignment */
492
493         addr &= 0xff;
494         spin_lock(&ioapic->lock);
495         switch (addr) {
496         case IOAPIC_REG_SELECT:
497                 result = ioapic->ioregsel;
498                 break;
499
500         case IOAPIC_REG_WINDOW:
501                 result = ioapic_read_indirect(ioapic, addr, len);
502                 break;
503
504         default:
505                 result = 0;
506                 break;
507         }
508         spin_unlock(&ioapic->lock);
509
510         switch (len) {
511         case 8:
512                 *(u64 *) val = result;
513                 break;
514         case 1:
515         case 2:
516         case 4:
517                 memcpy(val, (char *)&result, len);
518                 break;
519         default:
520                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
521         }
522         return 0;
523 }
524
525 static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
526                                  gpa_t addr, int len, const void *val)
527 {
528         struct kvm_ioapic *ioapic = to_ioapic(this);
529         u32 data;
530         if (!ioapic_in_range(ioapic, addr))
531                 return -EOPNOTSUPP;
532
533         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
534                      (void*)addr, len, val);
535         ASSERT(!(addr & 0xf));  /* check alignment */
536
537         switch (len) {
538         case 8:
539         case 4:
540                 data = *(u32 *) val;
541                 break;
542         case 2:
543                 data = *(u16 *) val;
544                 break;
545         case 1:
546                 data = *(u8  *) val;
547                 break;
548         default:
549                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
550                 return 0;
551         }
552
553         addr &= 0xff;
554         spin_lock(&ioapic->lock);
555         switch (addr) {
556         case IOAPIC_REG_SELECT:
557                 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
558                 break;
559
560         case IOAPIC_REG_WINDOW:
561                 ioapic_write_indirect(ioapic, data);
562                 break;
563
564         default:
565                 break;
566         }
567         spin_unlock(&ioapic->lock);
568         return 0;
569 }
570
571 static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
572 {
573         int i;
574
575         cancel_delayed_work_sync(&ioapic->eoi_inject);
576         for (i = 0; i < IOAPIC_NUM_PINS; i++)
577                 ioapic->redirtbl[i].fields.mask = 1;
578         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
579         ioapic->ioregsel = 0;
580         ioapic->irr = 0;
581         ioapic->irr_delivered = 0;
582         ioapic->id = 0;
583         memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi));
584         rtc_irq_eoi_tracking_reset(ioapic);
585 }
586
587 static const struct kvm_io_device_ops ioapic_mmio_ops = {
588         .read     = ioapic_mmio_read,
589         .write    = ioapic_mmio_write,
590 };
591
592 int kvm_ioapic_init(struct kvm *kvm)
593 {
594         struct kvm_ioapic *ioapic;
595         int ret;
596
597         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
598         if (!ioapic)
599                 return -ENOMEM;
600         spin_lock_init(&ioapic->lock);
601         INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
602         kvm->arch.vioapic = ioapic;
603         kvm_ioapic_reset(ioapic);
604         kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
605         ioapic->kvm = kvm;
606         mutex_lock(&kvm->slots_lock);
607         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
608                                       IOAPIC_MEM_LENGTH, &ioapic->dev);
609         mutex_unlock(&kvm->slots_lock);
610         if (ret < 0) {
611                 kvm->arch.vioapic = NULL;
612                 kfree(ioapic);
613                 return ret;
614         }
615
616         kvm_vcpu_request_scan_ioapic(kvm);
617         return ret;
618 }
619
620 void kvm_ioapic_destroy(struct kvm *kvm)
621 {
622         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
623
624         cancel_delayed_work_sync(&ioapic->eoi_inject);
625         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
626         kvm->arch.vioapic = NULL;
627         kfree(ioapic);
628 }
629
630 int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
631 {
632         struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
633         if (!ioapic)
634                 return -EINVAL;
635
636         spin_lock(&ioapic->lock);
637         memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
638         state->irr &= ~ioapic->irr_delivered;
639         spin_unlock(&ioapic->lock);
640         return 0;
641 }
642
643 int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
644 {
645         struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
646         if (!ioapic)
647                 return -EINVAL;
648
649         spin_lock(&ioapic->lock);
650         memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
651         ioapic->irr = 0;
652         ioapic->irr_delivered = 0;
653         kvm_vcpu_request_scan_ioapic(kvm);
654         kvm_ioapic_inject_all(ioapic, state->irr);
655         spin_unlock(&ioapic->lock);
656         return 0;
657 }