3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/atomic.h>
37 #include "kvm_cache_regs.h"
43 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
45 #define mod_64(x, y) ((x) % (y))
53 #define APIC_BUS_CYCLE_NS 1
55 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
56 #define apic_debug(fmt, arg...)
58 #define APIC_LVT_NUM 6
59 /* 14 is the version for Xeon and Pentium 8.4.8*/
60 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
61 #define LAPIC_MMIO_LENGTH (1 << 12)
62 /* followed define is not in apicdef.h */
63 #define APIC_SHORT_MASK 0xc0000
64 #define APIC_DEST_NOSHORT 0x0
65 #define APIC_DEST_MASK 0x800
66 #define MAX_APIC_VECTOR 256
68 #define VEC_POS(v) ((v) & (32 - 1))
69 #define REG_POS(v) (((v) >> 5) << 4)
71 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
73 return *((u32 *) (apic->regs + reg_off));
76 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
78 *((u32 *) (apic->regs + reg_off)) = val;
81 static inline int apic_test_and_set_vector(int vec, void *bitmap)
83 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
88 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 static inline void apic_set_vector(int vec, void *bitmap)
93 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96 static inline void apic_clear_vector(int vec, void *bitmap)
98 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101 static inline int apic_hw_enabled(struct kvm_lapic *apic)
103 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
106 static inline int apic_sw_enabled(struct kvm_lapic *apic)
108 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
111 static inline int apic_enabled(struct kvm_lapic *apic)
113 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
117 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
120 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
121 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
123 static inline int kvm_apic_id(struct kvm_lapic *apic)
125 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
128 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
130 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
133 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
135 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
138 static inline int apic_lvtt_period(struct kvm_lapic *apic)
140 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
143 static inline int apic_lvt_nmi_mode(u32 lvt_val)
145 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
148 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
150 struct kvm_lapic *apic = vcpu->arch.apic;
151 struct kvm_cpuid_entry2 *feat;
152 u32 v = APIC_VERSION;
154 if (!irqchip_in_kernel(vcpu->kvm))
157 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
158 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
159 v |= APIC_LVR_DIRECTED_EOI;
160 apic_set_reg(apic, APIC_LVR, v);
163 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
165 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
168 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
169 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
170 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
171 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
172 LINT_MASK, LINT_MASK, /* LVT0-1 */
173 LVT_MASK /* LVTERR */
176 static int find_highest_vector(void *bitmap)
179 int word_offset = MAX_APIC_VECTOR >> 5;
181 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
184 if (likely(!word_offset && !word[0]))
187 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
190 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
192 apic->irr_pending = true;
193 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
196 static inline int apic_search_irr(struct kvm_lapic *apic)
198 return find_highest_vector(apic->regs + APIC_IRR);
201 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
205 if (!apic->irr_pending)
208 result = apic_search_irr(apic);
209 ASSERT(result == -1 || result >= 16);
214 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
216 apic->irr_pending = false;
217 apic_clear_vector(vec, apic->regs + APIC_IRR);
218 if (apic_search_irr(apic) != -1)
219 apic->irr_pending = true;
222 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
224 struct kvm_lapic *apic = vcpu->arch.apic;
227 /* This may race with setting of irr in __apic_accept_irq() and
228 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
229 * will cause vmexit immediately and the value will be recalculated
230 * on the next vmentry.
234 highest_irr = apic_find_highest_irr(apic);
239 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
240 int vector, int level, int trig_mode);
242 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
244 struct kvm_lapic *apic = vcpu->arch.apic;
246 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
247 irq->level, irq->trig_mode);
250 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
254 result = find_highest_vector(apic->regs + APIC_ISR);
255 ASSERT(result == -1 || result >= 16);
260 static void apic_update_ppr(struct kvm_lapic *apic)
262 u32 tpr, isrv, ppr, old_ppr;
265 old_ppr = apic_get_reg(apic, APIC_PROCPRI);
266 tpr = apic_get_reg(apic, APIC_TASKPRI);
267 isr = apic_find_highest_isr(apic);
268 isrv = (isr != -1) ? isr : 0;
270 if ((tpr & 0xf0) >= (isrv & 0xf0))
275 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
276 apic, ppr, isr, isrv);
278 if (old_ppr != ppr) {
279 apic_set_reg(apic, APIC_PROCPRI, ppr);
281 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
285 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
287 apic_set_reg(apic, APIC_TASKPRI, tpr);
288 apic_update_ppr(apic);
291 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
293 return dest == 0xff || kvm_apic_id(apic) == dest;
296 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
301 if (apic_x2apic_mode(apic)) {
302 logical_id = apic_get_reg(apic, APIC_LDR);
303 return logical_id & mda;
306 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
308 switch (apic_get_reg(apic, APIC_DFR)) {
310 if (logical_id & mda)
313 case APIC_DFR_CLUSTER:
314 if (((logical_id >> 4) == (mda >> 0x4))
315 && (logical_id & mda & 0xf))
319 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
320 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
327 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
328 int short_hand, int dest, int dest_mode)
331 struct kvm_lapic *target = vcpu->arch.apic;
333 apic_debug("target %p, source %p, dest 0x%x, "
334 "dest_mode 0x%x, short_hand 0x%x\n",
335 target, source, dest, dest_mode, short_hand);
338 switch (short_hand) {
339 case APIC_DEST_NOSHORT:
342 result = kvm_apic_match_physical_addr(target, dest);
345 result = kvm_apic_match_logical_addr(target, dest);
348 result = (target == source);
350 case APIC_DEST_ALLINC:
353 case APIC_DEST_ALLBUT:
354 result = (target != source);
357 printk(KERN_WARNING "Bad dest shorthand value %x\n",
366 * Add a pending IRQ into lapic.
367 * Return 1 if successfully added and 0 if discarded.
369 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
370 int vector, int level, int trig_mode)
373 struct kvm_vcpu *vcpu = apic->vcpu;
375 switch (delivery_mode) {
377 vcpu->arch.apic_arb_prio++;
379 /* FIXME add logic for vcpu on reset */
380 if (unlikely(!apic_enabled(apic)))
384 apic_debug("level trig mode for vector %d", vector);
385 apic_set_vector(vector, apic->regs + APIC_TMR);
387 apic_clear_vector(vector, apic->regs + APIC_TMR);
389 result = !apic_test_and_set_irr(vector, apic);
390 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
391 trig_mode, vector, !result);
394 apic_debug("level trig mode repeatedly for "
395 "vector %d", vector);
399 kvm_make_request(KVM_REQ_EVENT, vcpu);
404 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
408 printk(KERN_DEBUG "Ignoring guest SMI\n");
413 kvm_inject_nmi(vcpu);
420 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
421 kvm_make_request(KVM_REQ_EVENT, vcpu);
424 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
429 case APIC_DM_STARTUP:
430 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
431 vcpu->vcpu_id, vector);
432 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
434 vcpu->arch.sipi_vector = vector;
435 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
436 kvm_make_request(KVM_REQ_EVENT, vcpu);
443 * Should only be called by kvm_apic_local_deliver() with LVT0,
444 * before NMI watchdog was enabled. Already handled by
445 * kvm_apic_accept_pic_intr().
450 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
457 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
459 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
462 static void apic_set_eoi(struct kvm_lapic *apic)
464 int vector = apic_find_highest_isr(apic);
467 * Not every write EOI will has corresponding ISR,
468 * one example is when Kernel check timer on setup_IO_APIC
473 apic_clear_vector(vector, apic->regs + APIC_ISR);
474 apic_update_ppr(apic);
476 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
477 trigger_mode = IOAPIC_LEVEL_TRIG;
479 trigger_mode = IOAPIC_EDGE_TRIG;
480 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
481 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
482 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
485 static void apic_send_ipi(struct kvm_lapic *apic)
487 u32 icr_low = apic_get_reg(apic, APIC_ICR);
488 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
489 struct kvm_lapic_irq irq;
491 irq.vector = icr_low & APIC_VECTOR_MASK;
492 irq.delivery_mode = icr_low & APIC_MODE_MASK;
493 irq.dest_mode = icr_low & APIC_DEST_MASK;
494 irq.level = icr_low & APIC_INT_ASSERT;
495 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
496 irq.shorthand = icr_low & APIC_SHORT_MASK;
497 if (apic_x2apic_mode(apic))
498 irq.dest_id = icr_high;
500 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
502 trace_kvm_apic_ipi(icr_low, irq.dest_id);
504 apic_debug("icr_high 0x%x, icr_low 0x%x, "
505 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
506 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
507 icr_high, icr_low, irq.shorthand, irq.dest_id,
508 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
511 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
514 static u32 apic_get_tmcct(struct kvm_lapic *apic)
520 ASSERT(apic != NULL);
522 /* if initial count is 0, current count should also be 0 */
523 if (apic_get_reg(apic, APIC_TMICT) == 0)
526 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
527 if (ktime_to_ns(remaining) < 0)
528 remaining = ktime_set(0, 0);
530 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
531 tmcct = div64_u64(ns,
532 (APIC_BUS_CYCLE_NS * apic->divide_count));
537 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
539 struct kvm_vcpu *vcpu = apic->vcpu;
540 struct kvm_run *run = vcpu->run;
542 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
543 run->tpr_access.rip = kvm_rip_read(vcpu);
544 run->tpr_access.is_write = write;
547 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
549 if (apic->vcpu->arch.tpr_access_reporting)
550 __report_tpr_access(apic, write);
553 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
557 if (offset >= LAPIC_MMIO_LENGTH)
562 if (apic_x2apic_mode(apic))
563 val = kvm_apic_id(apic);
565 val = kvm_apic_id(apic) << 24;
568 printk(KERN_WARNING "Access APIC ARBPRI register "
569 "which is for P6\n");
572 case APIC_TMCCT: /* Timer CCR */
573 val = apic_get_tmcct(apic);
577 report_tpr_access(apic, false);
580 apic_update_ppr(apic);
581 val = apic_get_reg(apic, offset);
588 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
590 return container_of(dev, struct kvm_lapic, dev);
593 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
596 unsigned char alignment = offset & 0xf;
598 /* this bitmask has a bit cleared for each reserver register */
599 static const u64 rmask = 0x43ff01ffffffe70cULL;
601 if ((alignment + len) > 4) {
602 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
607 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
608 apic_debug("KVM_APIC_READ: read reserved register %x\n",
613 result = __apic_read(apic, offset & ~0xf);
615 trace_kvm_apic_read(offset, result);
621 memcpy(data, (char *)&result + alignment, len);
624 printk(KERN_ERR "Local APIC read with len = %x, "
625 "should be 1,2, or 4 instead\n", len);
631 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
633 return apic_hw_enabled(apic) &&
634 addr >= apic->base_address &&
635 addr < apic->base_address + LAPIC_MMIO_LENGTH;
638 static int apic_mmio_read(struct kvm_io_device *this,
639 gpa_t address, int len, void *data)
641 struct kvm_lapic *apic = to_lapic(this);
642 u32 offset = address - apic->base_address;
644 if (!apic_mmio_in_range(apic, address))
647 apic_reg_read(apic, offset, len, data);
652 static void update_divide_count(struct kvm_lapic *apic)
654 u32 tmp1, tmp2, tdcr;
656 tdcr = apic_get_reg(apic, APIC_TDCR);
658 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
659 apic->divide_count = 0x1 << (tmp2 & 0x7);
661 apic_debug("timer divide count is 0x%x\n",
665 static void start_apic_timer(struct kvm_lapic *apic)
667 ktime_t now = apic->lapic_timer.timer.base->get_time();
669 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
670 APIC_BUS_CYCLE_NS * apic->divide_count;
671 atomic_set(&apic->lapic_timer.pending, 0);
673 if (!apic->lapic_timer.period)
676 * Do not allow the guest to program periodic timers with small
677 * interval, since the hrtimers are not throttled by the host
680 if (apic_lvtt_period(apic)) {
681 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
682 apic->lapic_timer.period = NSEC_PER_MSEC/2;
685 hrtimer_start(&apic->lapic_timer.timer,
686 ktime_add_ns(now, apic->lapic_timer.period),
689 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
691 "timer initial count 0x%x, period %lldns, "
692 "expire @ 0x%016" PRIx64 ".\n", __func__,
693 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
694 apic_get_reg(apic, APIC_TMICT),
695 apic->lapic_timer.period,
696 ktime_to_ns(ktime_add_ns(now,
697 apic->lapic_timer.period)));
700 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
702 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
704 if (apic_lvt_nmi_mode(lvt0_val)) {
705 if (!nmi_wd_enabled) {
706 apic_debug("Receive NMI setting on APIC_LVT0 "
707 "for cpu %d\n", apic->vcpu->vcpu_id);
708 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
710 } else if (nmi_wd_enabled)
711 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
714 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
718 trace_kvm_apic_write(reg, val);
721 case APIC_ID: /* Local APIC ID */
722 if (!apic_x2apic_mode(apic))
723 apic_set_reg(apic, APIC_ID, val);
729 report_tpr_access(apic, true);
730 apic_set_tpr(apic, val & 0xff);
738 if (!apic_x2apic_mode(apic))
739 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
745 if (!apic_x2apic_mode(apic))
746 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
753 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
754 mask |= APIC_SPIV_DIRECTED_EOI;
755 apic_set_reg(apic, APIC_SPIV, val & mask);
756 if (!(val & APIC_SPIV_APIC_ENABLED)) {
760 for (i = 0; i < APIC_LVT_NUM; i++) {
761 lvt_val = apic_get_reg(apic,
762 APIC_LVTT + 0x10 * i);
763 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
764 lvt_val | APIC_LVT_MASKED);
766 atomic_set(&apic->lapic_timer.pending, 0);
772 /* No delay here, so we always clear the pending bit */
773 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
778 if (!apic_x2apic_mode(apic))
780 apic_set_reg(apic, APIC_ICR2, val);
784 apic_manage_nmi_watchdog(apic, val);
790 /* TODO: Check vector */
791 if (!apic_sw_enabled(apic))
792 val |= APIC_LVT_MASKED;
794 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
795 apic_set_reg(apic, reg, val);
800 hrtimer_cancel(&apic->lapic_timer.timer);
801 apic_set_reg(apic, APIC_TMICT, val);
802 start_apic_timer(apic);
807 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
808 apic_set_reg(apic, APIC_TDCR, val);
809 update_divide_count(apic);
813 if (apic_x2apic_mode(apic) && val != 0) {
814 printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
820 if (apic_x2apic_mode(apic)) {
821 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
830 apic_debug("Local APIC Write to read-only register %x\n", reg);
834 static int apic_mmio_write(struct kvm_io_device *this,
835 gpa_t address, int len, const void *data)
837 struct kvm_lapic *apic = to_lapic(this);
838 unsigned int offset = address - apic->base_address;
841 if (!apic_mmio_in_range(apic, address))
845 * APIC register must be aligned on 128-bits boundary.
846 * 32/64/128 bits registers must be accessed thru 32 bits.
849 if (len != 4 || (offset & 0xf)) {
850 /* Don't shout loud, $infamous_os would cause only noise. */
851 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
857 /* too common printing */
858 if (offset != APIC_EOI)
859 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
860 "0x%x\n", __func__, offset, len, val);
862 apic_reg_write(apic, offset & 0xff0, val);
867 void kvm_free_lapic(struct kvm_vcpu *vcpu)
869 if (!vcpu->arch.apic)
872 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
874 if (vcpu->arch.apic->regs)
875 free_page((unsigned long)vcpu->arch.apic->regs);
877 kfree(vcpu->arch.apic);
881 *----------------------------------------------------------------------
883 *----------------------------------------------------------------------
886 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
888 struct kvm_lapic *apic = vcpu->arch.apic;
892 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
893 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
896 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
898 struct kvm_lapic *apic = vcpu->arch.apic;
903 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
905 return (tpr & 0xf0) >> 4;
908 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
910 struct kvm_lapic *apic = vcpu->arch.apic;
913 value |= MSR_IA32_APICBASE_BSP;
914 vcpu->arch.apic_base = value;
918 if (!kvm_vcpu_is_bsp(apic->vcpu))
919 value &= ~MSR_IA32_APICBASE_BSP;
921 vcpu->arch.apic_base = value;
922 if (apic_x2apic_mode(apic)) {
923 u32 id = kvm_apic_id(apic);
924 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
925 apic_set_reg(apic, APIC_LDR, ldr);
927 apic->base_address = apic->vcpu->arch.apic_base &
928 MSR_IA32_APICBASE_BASE;
930 /* with FSB delivery interrupt, we can restart APIC functionality */
931 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
932 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
936 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
938 struct kvm_lapic *apic;
941 apic_debug("%s\n", __func__);
944 apic = vcpu->arch.apic;
945 ASSERT(apic != NULL);
947 /* Stop the timer in case it's a reset to an active apic */
948 hrtimer_cancel(&apic->lapic_timer.timer);
950 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
951 kvm_apic_set_version(apic->vcpu);
953 for (i = 0; i < APIC_LVT_NUM; i++)
954 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
955 apic_set_reg(apic, APIC_LVT0,
956 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
958 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
959 apic_set_reg(apic, APIC_SPIV, 0xff);
960 apic_set_reg(apic, APIC_TASKPRI, 0);
961 apic_set_reg(apic, APIC_LDR, 0);
962 apic_set_reg(apic, APIC_ESR, 0);
963 apic_set_reg(apic, APIC_ICR, 0);
964 apic_set_reg(apic, APIC_ICR2, 0);
965 apic_set_reg(apic, APIC_TDCR, 0);
966 apic_set_reg(apic, APIC_TMICT, 0);
967 for (i = 0; i < 8; i++) {
968 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
969 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
970 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
972 apic->irr_pending = false;
973 update_divide_count(apic);
974 atomic_set(&apic->lapic_timer.pending, 0);
975 if (kvm_vcpu_is_bsp(vcpu))
976 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
977 apic_update_ppr(apic);
979 vcpu->arch.apic_arb_prio = 0;
981 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
982 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
983 vcpu, kvm_apic_id(apic),
984 vcpu->arch.apic_base, apic->base_address);
987 bool kvm_apic_present(struct kvm_vcpu *vcpu)
989 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
992 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
994 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
998 *----------------------------------------------------------------------
1000 *----------------------------------------------------------------------
1003 static bool lapic_is_periodic(struct kvm_timer *ktimer)
1005 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1007 return apic_lvtt_period(apic);
1010 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1012 struct kvm_lapic *lapic = vcpu->arch.apic;
1014 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1015 return atomic_read(&lapic->lapic_timer.pending);
1020 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1022 u32 reg = apic_get_reg(apic, lvt_type);
1023 int vector, mode, trig_mode;
1025 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1026 vector = reg & APIC_VECTOR_MASK;
1027 mode = reg & APIC_MODE_MASK;
1028 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1029 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1034 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1036 struct kvm_lapic *apic = vcpu->arch.apic;
1039 kvm_apic_local_deliver(apic, APIC_LVT0);
1042 static struct kvm_timer_ops lapic_timer_ops = {
1043 .is_periodic = lapic_is_periodic,
1046 static const struct kvm_io_device_ops apic_mmio_ops = {
1047 .read = apic_mmio_read,
1048 .write = apic_mmio_write,
1051 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1053 struct kvm_lapic *apic;
1055 ASSERT(vcpu != NULL);
1056 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1058 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1062 vcpu->arch.apic = apic;
1064 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1066 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1068 goto nomem_free_apic;
1072 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1074 apic->lapic_timer.timer.function = kvm_timer_fn;
1075 apic->lapic_timer.t_ops = &lapic_timer_ops;
1076 apic->lapic_timer.kvm = vcpu->kvm;
1077 apic->lapic_timer.vcpu = vcpu;
1079 apic->base_address = APIC_DEFAULT_PHYS_BASE;
1080 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1082 kvm_lapic_reset(vcpu);
1083 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1092 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1094 struct kvm_lapic *apic = vcpu->arch.apic;
1097 if (!apic || !apic_enabled(apic))
1100 apic_update_ppr(apic);
1101 highest_irr = apic_find_highest_irr(apic);
1102 if ((highest_irr == -1) ||
1103 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1108 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1110 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1113 if (!apic_hw_enabled(vcpu->arch.apic))
1115 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1116 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1121 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1123 struct kvm_lapic *apic = vcpu->arch.apic;
1125 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1126 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1127 atomic_dec(&apic->lapic_timer.pending);
1131 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1133 int vector = kvm_apic_has_interrupt(vcpu);
1134 struct kvm_lapic *apic = vcpu->arch.apic;
1139 apic_set_vector(vector, apic->regs + APIC_ISR);
1140 apic_update_ppr(apic);
1141 apic_clear_irr(vector, apic);
1145 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1147 struct kvm_lapic *apic = vcpu->arch.apic;
1149 apic->base_address = vcpu->arch.apic_base &
1150 MSR_IA32_APICBASE_BASE;
1151 kvm_apic_set_version(vcpu);
1153 apic_update_ppr(apic);
1154 hrtimer_cancel(&apic->lapic_timer.timer);
1155 update_divide_count(apic);
1156 start_apic_timer(apic);
1157 apic->irr_pending = true;
1158 kvm_make_request(KVM_REQ_EVENT, vcpu);
1161 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1163 struct kvm_lapic *apic = vcpu->arch.apic;
1164 struct hrtimer *timer;
1169 timer = &apic->lapic_timer.timer;
1170 if (hrtimer_cancel(timer))
1171 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1174 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1179 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1182 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1183 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1184 kunmap_atomic(vapic, KM_USER0);
1186 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1189 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1192 int max_irr, max_isr;
1193 struct kvm_lapic *apic;
1196 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1199 apic = vcpu->arch.apic;
1200 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1201 max_irr = apic_find_highest_irr(apic);
1204 max_isr = apic_find_highest_isr(apic);
1207 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1209 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1210 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1211 kunmap_atomic(vapic, KM_USER0);
1214 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1216 if (!irqchip_in_kernel(vcpu->kvm))
1219 vcpu->arch.apic->vapic_addr = vapic_addr;
1222 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1224 struct kvm_lapic *apic = vcpu->arch.apic;
1225 u32 reg = (msr - APIC_BASE_MSR) << 4;
1227 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1230 /* if this is ICR write vector before command */
1232 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1233 return apic_reg_write(apic, reg, (u32)data);
1236 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1238 struct kvm_lapic *apic = vcpu->arch.apic;
1239 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1241 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1244 if (apic_reg_read(apic, reg, 4, &low))
1247 apic_reg_read(apic, APIC_ICR2, 4, &high);
1249 *data = (((u64)high) << 32) | low;
1254 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1256 struct kvm_lapic *apic = vcpu->arch.apic;
1258 if (!irqchip_in_kernel(vcpu->kvm))
1261 /* if this is ICR write vector before command */
1262 if (reg == APIC_ICR)
1263 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1264 return apic_reg_write(apic, reg, (u32)data);
1267 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1269 struct kvm_lapic *apic = vcpu->arch.apic;
1272 if (!irqchip_in_kernel(vcpu->kvm))
1275 if (apic_reg_read(apic, reg, 4, &low))
1277 if (reg == APIC_ICR)
1278 apic_reg_read(apic, APIC_ICR2, 4, &high);
1280 *data = (((u64)high) << 32) | low;