arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define APIC_BROADCAST                  0xFF
  72 #define X2APIC_BROADCAST                0xFFFFFFFFul
  73
  74 #define VEC_POS(v) ((v) & (32 - 1))
  75 #define REG_POS(v) (((v) >> 5) << 4)
  76
  77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  78 {
  79         *((u32 *) (apic->regs + reg_off)) = val;
  80 }
  81
  82 static inline int apic_test_vector(int vec, void *bitmap)
  83 {
  84         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  88 {
  89         struct kvm_lapic *apic = vcpu->arch.apic;
  90
  91         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  92                 apic_test_vector(vector, apic->regs + APIC_IRR);
  93 }
  94
  95 static inline void apic_set_vector(int vec, void *bitmap)
  96 {
  97         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline void apic_clear_vector(int vec, void *bitmap)
 101 {
 102         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 106 {
 107         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 111 {
 112         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 struct static_key_deferred apic_hw_disabled __read_mostly;
 116 struct static_key_deferred apic_sw_disabled __read_mostly;
 117
 118 static inline int apic_enabled(struct kvm_lapic *apic)
 119 {
 120         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 121 }
 122
 123 #define LVT_MASK        \
 124         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 125
 126 #define LINT_MASK       \
 127         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 128          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 129
 130 static inline int kvm_apic_id(struct kvm_lapic *apic)
 131 {
 132         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 133 }
 134
 135 #define KVM_X2APIC_CID_BITS 0
 136
 137 static void recalculate_apic_map(struct kvm *kvm)
 138 {
 139         struct kvm_apic_map *new, *old = NULL;
 140         struct kvm_vcpu *vcpu;
 141         int i;
 142
 143         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 144
 145         mutex_lock(&kvm->arch.apic_map_lock);
 146
 147         if (!new)
 148                 goto out;
 149
 150         new->ldr_bits = 8;
 151         /* flat mode is default */
 152         new->cid_shift = 8;
 153         new->cid_mask = 0;
 154         new->lid_mask = 0xff;
 155         new->broadcast = APIC_BROADCAST;
 156
 157         kvm_for_each_vcpu(i, vcpu, kvm) {
 158                 struct kvm_lapic *apic = vcpu->arch.apic;
 159
 160                 if (!kvm_apic_present(vcpu))
 161                         continue;
 162
 163                 if (apic_x2apic_mode(apic)) {
 164                         new->ldr_bits = 32;
 165                         new->cid_shift = 16;
 166                         new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
 167                         new->lid_mask = 0xffff;
 168                         new->broadcast = X2APIC_BROADCAST;
 169                 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
 170                         if (kvm_apic_get_reg(apic, APIC_DFR) ==
 171                                                         APIC_DFR_CLUSTER) {
 172                                 new->cid_shift = 4;
 173                                 new->cid_mask = 0xf;
 174                                 new->lid_mask = 0xf;
 175                         } else {
 176                                 new->cid_shift = 8;
 177                                 new->cid_mask = 0;
 178                                 new->lid_mask = 0xff;
 179                         }
 180                 }
 181
 182                 /*
 183                  * All APICs have to be configured in the same mode by an OS.
 184                  * We take advatage of this while building logical id loockup
 185                  * table. After reset APICs are in software disabled mode, so if
 186                  * we find apic with different setting we assume this is the mode
 187                  * OS wants all apics to be in; build lookup table accordingly.
 188                  */
 189                 if (kvm_apic_sw_enabled(apic))
 190                         break;
 191         }
 192
 193         kvm_for_each_vcpu(i, vcpu, kvm) {
 194                 struct kvm_lapic *apic = vcpu->arch.apic;
 195                 u16 cid, lid;
 196                 u32 ldr;
 197
 198                 new->phys_map[kvm_apic_id(apic)] = apic;
 199
 200                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 201                 cid = apic_cluster_id(new, ldr);
 202                 lid = apic_logical_id(new, ldr);
 203
 204                 if (lid)
 205                         new->logical_map[cid][ffs(lid) - 1] = apic;
 206         }
 207 out:
 208         old = rcu_dereference_protected(kvm->arch.apic_map,
 209                         lockdep_is_held(&kvm->arch.apic_map_lock));
 210         rcu_assign_pointer(kvm->arch.apic_map, new);
 211         mutex_unlock(&kvm->arch.apic_map_lock);
 212
 213         if (old)
 214                 kfree_rcu(old, rcu);
 215
 216         kvm_vcpu_request_scan_ioapic(kvm);
 217 }
 218
 219 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 220 {
 221         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 222
 223         apic_set_reg(apic, APIC_SPIV, val);
 224
 225         if (enabled != apic->sw_enabled) {
 226                 apic->sw_enabled = enabled;
 227                 if (enabled) {
 228                         static_key_slow_dec_deferred(&apic_sw_disabled);
 229                         recalculate_apic_map(apic->vcpu->kvm);
 230                 } else
 231                         static_key_slow_inc(&apic_sw_disabled.key);
 232         }
 233 }
 234
 235 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 236 {
 237         apic_set_reg(apic, APIC_ID, id << 24);
 238         recalculate_apic_map(apic->vcpu->kvm);
 239 }
 240
 241 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 242 {
 243         apic_set_reg(apic, APIC_LDR, id);
 244         recalculate_apic_map(apic->vcpu->kvm);
 245 }
 246
 247 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 248 {
 249         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 250 }
 251
 252 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 253 {
 254         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 255 }
 256
 257 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 258 {
 259         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 260 }
 261
 262 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 263 {
 264         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 265 }
 266
 267 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 268 {
 269         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 270 }
 271
 272 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 273 {
 274         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 275 }
 276
 277 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 278 {
 279         struct kvm_lapic *apic = vcpu->arch.apic;
 280         struct kvm_cpuid_entry2 *feat;
 281         u32 v = APIC_VERSION;
 282
 283         if (!kvm_vcpu_has_lapic(vcpu))
 284                 return;
 285
 286         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 287         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 288                 v |= APIC_LVR_DIRECTED_EOI;
 289         apic_set_reg(apic, APIC_LVR, v);
 290 }
 291
 292 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 293         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 294         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 295         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 296         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 297         LVT_MASK                /* LVTERR */
 298 };
 299
 300 static int find_highest_vector(void *bitmap)
 301 {
 302         int vec;
 303         u32 *reg;
 304
 305         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 306              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 307                 reg = bitmap + REG_POS(vec);
 308                 if (*reg)
 309                         return fls(*reg) - 1 + vec;
 310         }
 311
 312         return -1;
 313 }
 314
 315 static u8 count_vectors(void *bitmap)
 316 {
 317         int vec;
 318         u32 *reg;
 319         u8 count = 0;
 320
 321         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 322                 reg = bitmap + REG_POS(vec);
 323                 count += hweight32(*reg);
 324         }
 325
 326         return count;
 327 }
 328
 329 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 330 {
 331         u32 i, pir_val;
 332         struct kvm_lapic *apic = vcpu->arch.apic;
 333
 334         for (i = 0; i <= 7; i++) {
 335                 pir_val = xchg(&pir[i], 0);
 336                 if (pir_val)
 337                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 338         }
 339 }
 340 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 341
 342 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 343 {
 344         apic->irr_pending = true;
 345         apic_set_vector(vec, apic->regs + APIC_IRR);
 346 }
 347
 348 static inline int apic_search_irr(struct kvm_lapic *apic)
 349 {
 350         return find_highest_vector(apic->regs + APIC_IRR);
 351 }
 352
 353 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 354 {
 355         int result;
 356
 357         /*
 358          * Note that irr_pending is just a hint. It will be always
 359          * true with virtual interrupt delivery enabled.
 360          */
 361         if (!apic->irr_pending)
 362                 return -1;
 363
 364         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 365         result = apic_search_irr(apic);
 366         ASSERT(result == -1 || result >= 16);
 367
 368         return result;
 369 }
 370
 371 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 372 {
 373         struct kvm_vcpu *vcpu;
 374
 375         vcpu = apic->vcpu;
 376
 377         apic_clear_vector(vec, apic->regs + APIC_IRR);
 378         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 379                 /* try to update RVI */
 380                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 381         else {
 382                 vec = apic_search_irr(apic);
 383                 apic->irr_pending = (vec != -1);
 384         }
 385 }
 386
 387 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 388 {
 389         struct kvm_vcpu *vcpu;
 390
 391         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 392                 return;
 393
 394         vcpu = apic->vcpu;
 395
 396         /*
 397          * With APIC virtualization enabled, all caching is disabled
 398          * because the processor can modify ISR under the hood.  Instead
 399          * just set SVI.
 400          */
 401         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 402                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 403         else {
 404                 ++apic->isr_count;
 405                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 406                 /*
 407                  * ISR (in service register) bit is set when injecting an interrupt.
 408                  * The highest vector is injected. Thus the latest bit set matches
 409                  * the highest bit in ISR.
 410                  */
 411                 apic->highest_isr_cache = vec;
 412         }
 413 }
 414
 415 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 416 {
 417         int result;
 418
 419         /*
 420          * Note that isr_count is always 1, and highest_isr_cache
 421          * is always -1, with APIC virtualization enabled.
 422          */
 423         if (!apic->isr_count)
 424                 return -1;
 425         if (likely(apic->highest_isr_cache != -1))
 426                 return apic->highest_isr_cache;
 427
 428         result = find_highest_vector(apic->regs + APIC_ISR);
 429         ASSERT(result == -1 || result >= 16);
 430
 431         return result;
 432 }
 433
 434 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 435 {
 436         struct kvm_vcpu *vcpu;
 437         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 438                 return;
 439
 440         vcpu = apic->vcpu;
 441
 442         /*
 443          * We do get here for APIC virtualization enabled if the guest
 444          * uses the Hyper-V APIC enlightenment.  In this case we may need
 445          * to trigger a new interrupt delivery by writing the SVI field;
 446          * on the other hand isr_count and highest_isr_cache are unused
 447          * and must be left alone.
 448          */
 449         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 450                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 451                                                apic_find_highest_isr(apic));
 452         else {
 453                 --apic->isr_count;
 454                 BUG_ON(apic->isr_count < 0);
 455                 apic->highest_isr_cache = -1;
 456         }
 457 }
 458
 459 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 460 {
 461         int highest_irr;
 462
 463         /* This may race with setting of irr in __apic_accept_irq() and
 464          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 465          * will cause vmexit immediately and the value will be recalculated
 466          * on the next vmentry.
 467          */
 468         if (!kvm_vcpu_has_lapic(vcpu))
 469                 return 0;
 470         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 471
 472         return highest_irr;
 473 }
 474
 475 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 476                              int vector, int level, int trig_mode,
 477                              unsigned long *dest_map);
 478
 479 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 480                 unsigned long *dest_map)
 481 {
 482         struct kvm_lapic *apic = vcpu->arch.apic;
 483
 484         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 485                         irq->level, irq->trig_mode, dest_map);
 486 }
 487
 488 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 489 {
 490
 491         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 492                                       sizeof(val));
 493 }
 494
 495 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 496 {
 497
 498         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 499                                       sizeof(*val));
 500 }
 501
 502 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 503 {
 504         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 505 }
 506
 507 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 508 {
 509         u8 val;
 510         if (pv_eoi_get_user(vcpu, &val) < 0)
 511                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 512                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 513         return val & 0x1;
 514 }
 515
 516 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 517 {
 518         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 519                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 520                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 521                 return;
 522         }
 523         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 524 }
 525
 526 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 527 {
 528         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 529                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 530                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 531                 return;
 532         }
 533         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 534 }
 535
 536 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 537 {
 538         struct kvm_lapic *apic = vcpu->arch.apic;
 539         int i;
 540
 541         for (i = 0; i < 8; i++)
 542                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 543 }
 544
 545 static void apic_update_ppr(struct kvm_lapic *apic)
 546 {
 547         u32 tpr, isrv, ppr, old_ppr;
 548         int isr;
 549
 550         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 551         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 552         isr = apic_find_highest_isr(apic);
 553         isrv = (isr != -1) ? isr : 0;
 554
 555         if ((tpr & 0xf0) >= (isrv & 0xf0))
 556                 ppr = tpr & 0xff;
 557         else
 558                 ppr = isrv & 0xf0;
 559
 560         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 561                    apic, ppr, isr, isrv);
 562
 563         if (old_ppr != ppr) {
 564                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 565                 if (ppr < old_ppr)
 566                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 567         }
 568 }
 569
 570 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 571 {
 572         apic_set_reg(apic, APIC_TASKPRI, tpr);
 573         apic_update_ppr(apic);
 574 }
 575
 576 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 577 {
 578         return dest == (apic_x2apic_mode(apic) ?
 579                         X2APIC_BROADCAST : APIC_BROADCAST);
 580 }
 581
 582 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 583 {
 584         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 585 }
 586
 587 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 588 {
 589         int result = 0;
 590         u32 logical_id;
 591
 592         if (kvm_apic_broadcast(apic, mda))
 593                 return 1;
 594
 595         if (apic_x2apic_mode(apic)) {
 596                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 597                 return logical_id & mda;
 598         }
 599
 600         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 601
 602         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 603         case APIC_DFR_FLAT:
 604                 if (logical_id & mda)
 605                         result = 1;
 606                 break;
 607         case APIC_DFR_CLUSTER:
 608                 if (((logical_id >> 4) == (mda >> 0x4))
 609                     && (logical_id & mda & 0xf))
 610                         result = 1;
 611                 break;
 612         default:
 613                 apic_debug("Bad DFR vcpu %d: %08x\n",
 614                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 615                 break;
 616         }
 617
 618         return result;
 619 }
 620
 621 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 622                            int short_hand, unsigned int dest, int dest_mode)
 623 {
 624         int result = 0;
 625         struct kvm_lapic *target = vcpu->arch.apic;
 626
 627         apic_debug("target %p, source %p, dest 0x%x, "
 628                    "dest_mode 0x%x, short_hand 0x%x\n",
 629                    target, source, dest, dest_mode, short_hand);
 630
 631         ASSERT(target);
 632         switch (short_hand) {
 633         case APIC_DEST_NOSHORT:
 634                 if (dest_mode == 0)
 635                         /* Physical mode. */
 636                         result = kvm_apic_match_physical_addr(target, dest);
 637                 else
 638                         /* Logical mode. */
 639                         result = kvm_apic_match_logical_addr(target, dest);
 640                 break;
 641         case APIC_DEST_SELF:
 642                 result = (target == source);
 643                 break;
 644         case APIC_DEST_ALLINC:
 645                 result = 1;
 646                 break;
 647         case APIC_DEST_ALLBUT:
 648                 result = (target != source);
 649                 break;
 650         default:
 651                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 652                            short_hand);
 653                 break;
 654         }
 655
 656         return result;
 657 }
 658
 659 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 660                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 661 {
 662         struct kvm_apic_map *map;
 663         unsigned long bitmap = 1;
 664         struct kvm_lapic **dst;
 665         int i;
 666         bool ret = false;
 667
 668         *r = -1;
 669
 670         if (irq->shorthand == APIC_DEST_SELF) {
 671                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 672                 return true;
 673         }
 674
 675         if (irq->shorthand)
 676                 return false;
 677
 678         rcu_read_lock();
 679         map = rcu_dereference(kvm->arch.apic_map);
 680
 681         if (!map)
 682                 goto out;
 683
 684         if (irq->dest_id == map->broadcast)
 685                 goto out;
 686
 687         if (irq->dest_mode == 0) { /* physical mode */
 688                 if (irq->delivery_mode == APIC_DM_LOWEST)
 689                         goto out;
 690                 dst = &map->phys_map[irq->dest_id & 0xff];
 691         } else {
 692                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 693
 694                 dst = map->logical_map[apic_cluster_id(map, mda)];
 695
 696                 bitmap = apic_logical_id(map, mda);
 697
 698                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 699                         int l = -1;
 700                         for_each_set_bit(i, &bitmap, 16) {
 701                                 if (!dst[i])
 702                                         continue;
 703                                 if (l < 0)
 704                                         l = i;
 705                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 706                                         l = i;
 707                         }
 708
 709                         bitmap = (l >= 0) ? 1 << l : 0;
 710                 }
 711         }
 712
 713         for_each_set_bit(i, &bitmap, 16) {
 714                 if (!dst[i])
 715                         continue;
 716                 if (*r < 0)
 717                         *r = 0;
 718                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 719         }
 720
 721         ret = true;
 722 out:
 723         rcu_read_unlock();
 724         return ret;
 725 }
 726
 727 /*
 728  * Add a pending IRQ into lapic.
 729  * Return 1 if successfully added and 0 if discarded.
 730  */
 731 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 732                              int vector, int level, int trig_mode,
 733                              unsigned long *dest_map)
 734 {
 735         int result = 0;
 736         struct kvm_vcpu *vcpu = apic->vcpu;
 737
 738         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 739                                   trig_mode, vector);
 740         switch (delivery_mode) {
 741         case APIC_DM_LOWEST:
 742                 vcpu->arch.apic_arb_prio++;
 743         case APIC_DM_FIXED:
 744                 /* FIXME add logic for vcpu on reset */
 745                 if (unlikely(!apic_enabled(apic)))
 746                         break;
 747
 748                 result = 1;
 749
 750                 if (dest_map)
 751                         __set_bit(vcpu->vcpu_id, dest_map);
 752
 753                 if (kvm_x86_ops->deliver_posted_interrupt)
 754                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 755                 else {
 756                         apic_set_irr(vector, apic);
 757
 758                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 759                         kvm_vcpu_kick(vcpu);
 760                 }
 761                 break;
 762
 763         case APIC_DM_REMRD:
 764                 result = 1;
 765                 vcpu->arch.pv.pv_unhalted = 1;
 766                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 767                 kvm_vcpu_kick(vcpu);
 768                 break;
 769
 770         case APIC_DM_SMI:
 771                 apic_debug("Ignoring guest SMI\n");
 772                 break;
 773
 774         case APIC_DM_NMI:
 775                 result = 1;
 776                 kvm_inject_nmi(vcpu);
 777                 kvm_vcpu_kick(vcpu);
 778                 break;
 779
 780         case APIC_DM_INIT:
 781                 if (!trig_mode || level) {
 782                         result = 1;
 783                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 784                         apic->pending_events = (1UL << KVM_APIC_INIT);
 785                         /* make sure pending_events is visible before sending
 786                          * the request */
 787                         smp_wmb();
 788                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 789                         kvm_vcpu_kick(vcpu);
 790                 } else {
 791                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 792                                    vcpu->vcpu_id);
 793                 }
 794                 break;
 795
 796         case APIC_DM_STARTUP:
 797                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 798                            vcpu->vcpu_id, vector);
 799                 result = 1;
 800                 apic->sipi_vector = vector;
 801                 /* make sure sipi_vector is visible for the receiver */
 802                 smp_wmb();
 803                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 804                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 805                 kvm_vcpu_kick(vcpu);
 806                 break;
 807
 808         case APIC_DM_EXTINT:
 809                 /*
 810                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 811                  * before NMI watchdog was enabled. Already handled by
 812                  * kvm_apic_accept_pic_intr().
 813                  */
 814                 break;
 815
 816         default:
 817                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 818                        delivery_mode);
 819                 break;
 820         }
 821         return result;
 822 }
 823
 824 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 825 {
 826         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 827 }
 828
 829 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 830 {
 831         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 832             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 833                 int trigger_mode;
 834                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 835                         trigger_mode = IOAPIC_LEVEL_TRIG;
 836                 else
 837                         trigger_mode = IOAPIC_EDGE_TRIG;
 838                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 839         }
 840 }
 841
 842 static int apic_set_eoi(struct kvm_lapic *apic)
 843 {
 844         int vector = apic_find_highest_isr(apic);
 845
 846         trace_kvm_eoi(apic, vector);
 847
 848         /*
 849          * Not every write EOI will has corresponding ISR,
 850          * one example is when Kernel check timer on setup_IO_APIC
 851          */
 852         if (vector == -1)
 853                 return vector;
 854
 855         apic_clear_isr(vector, apic);
 856         apic_update_ppr(apic);
 857
 858         kvm_ioapic_send_eoi(apic, vector);
 859         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 860         return vector;
 861 }
 862
 863 /*
 864  * this interface assumes a trap-like exit, which has already finished
 865  * desired side effect including vISR and vPPR update.
 866  */
 867 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 868 {
 869         struct kvm_lapic *apic = vcpu->arch.apic;
 870
 871         trace_kvm_eoi(apic, vector);
 872
 873         kvm_ioapic_send_eoi(apic, vector);
 874         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 875 }
 876 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 877
 878 static void apic_send_ipi(struct kvm_lapic *apic)
 879 {
 880         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 881         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 882         struct kvm_lapic_irq irq;
 883
 884         irq.vector = icr_low & APIC_VECTOR_MASK;
 885         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 886         irq.dest_mode = icr_low & APIC_DEST_MASK;
 887         irq.level = icr_low & APIC_INT_ASSERT;
 888         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 889         irq.shorthand = icr_low & APIC_SHORT_MASK;
 890         if (apic_x2apic_mode(apic))
 891                 irq.dest_id = icr_high;
 892         else
 893                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 894
 895         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 896
 897         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 898                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 899                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 900                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 901                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 902                    irq.vector);
 903
 904         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 905 }
 906
 907 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 908 {
 909         ktime_t remaining;
 910         s64 ns;
 911         u32 tmcct;
 912
 913         ASSERT(apic != NULL);
 914
 915         /* if initial count is 0, current count should also be 0 */
 916         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 917                 apic->lapic_timer.period == 0)
 918                 return 0;
 919
 920         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 921         if (ktime_to_ns(remaining) < 0)
 922                 remaining = ktime_set(0, 0);
 923
 924         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 925         tmcct = div64_u64(ns,
 926                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 927
 928         return tmcct;
 929 }
 930
 931 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 932 {
 933         struct kvm_vcpu *vcpu = apic->vcpu;
 934         struct kvm_run *run = vcpu->run;
 935
 936         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 937         run->tpr_access.rip = kvm_rip_read(vcpu);
 938         run->tpr_access.is_write = write;
 939 }
 940
 941 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 942 {
 943         if (apic->vcpu->arch.tpr_access_reporting)
 944                 __report_tpr_access(apic, write);
 945 }
 946
 947 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 948 {
 949         u32 val = 0;
 950
 951         if (offset >= LAPIC_MMIO_LENGTH)
 952                 return 0;
 953
 954         switch (offset) {
 955         case APIC_ID:
 956                 if (apic_x2apic_mode(apic))
 957                         val = kvm_apic_id(apic);
 958                 else
 959                         val = kvm_apic_id(apic) << 24;
 960                 break;
 961         case APIC_ARBPRI:
 962                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 963                 break;
 964
 965         case APIC_TMCCT:        /* Timer CCR */
 966                 if (apic_lvtt_tscdeadline(apic))
 967                         return 0;
 968
 969                 val = apic_get_tmcct(apic);
 970                 break;
 971         case APIC_PROCPRI:
 972                 apic_update_ppr(apic);
 973                 val = kvm_apic_get_reg(apic, offset);
 974                 break;
 975         case APIC_TASKPRI:
 976                 report_tpr_access(apic, false);
 977                 /* fall thru */
 978         default:
 979                 val = kvm_apic_get_reg(apic, offset);
 980                 break;
 981         }
 982
 983         return val;
 984 }
 985
 986 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 987 {
 988         return container_of(dev, struct kvm_lapic, dev);
 989 }
 990
 991 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 992                 void *data)
 993 {
 994         unsigned char alignment = offset & 0xf;
 995         u32 result;
 996         /* this bitmask has a bit cleared for each reserved register */
 997         static const u64 rmask = 0x43ff01ffffffe70cULL;
 998
 999         if ((alignment + len) > 4) {
1000                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1001                            offset, len);
1002                 return 1;
1003         }
1004
1005         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1006                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1007                            offset);
1008                 return 1;
1009         }
1010
1011         result = __apic_read(apic, offset & ~0xf);
1012
1013         trace_kvm_apic_read(offset, result);
1014
1015         switch (len) {
1016         case 1:
1017         case 2:
1018         case 4:
1019                 memcpy(data, (char *)&result + alignment, len);
1020                 break;
1021         default:
1022                 printk(KERN_ERR "Local APIC read with len = %x, "
1023                        "should be 1,2, or 4 instead\n", len);
1024                 break;
1025         }
1026         return 0;
1027 }
1028
1029 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1030 {
1031         return kvm_apic_hw_enabled(apic) &&
1032             addr >= apic->base_address &&
1033             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1034 }
1035
1036 static int apic_mmio_read(struct kvm_io_device *this,
1037                            gpa_t address, int len, void *data)
1038 {
1039         struct kvm_lapic *apic = to_lapic(this);
1040         u32 offset = address - apic->base_address;
1041
1042         if (!apic_mmio_in_range(apic, address))
1043                 return -EOPNOTSUPP;
1044
1045         apic_reg_read(apic, offset, len, data);
1046
1047         return 0;
1048 }
1049
1050 static void update_divide_count(struct kvm_lapic *apic)
1051 {
1052         u32 tmp1, tmp2, tdcr;
1053
1054         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1055         tmp1 = tdcr & 0xf;
1056         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1057         apic->divide_count = 0x1 << (tmp2 & 0x7);
1058
1059         apic_debug("timer divide count is 0x%x\n",
1060                                    apic->divide_count);
1061 }
1062
1063 static void apic_timer_expired(struct kvm_lapic *apic)
1064 {
1065         struct kvm_vcpu *vcpu = apic->vcpu;
1066         wait_queue_head_t *q = &vcpu->wq;
1067
1068         /*
1069          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1070          * vcpu_enter_guest.
1071          */
1072         if (atomic_read(&apic->lapic_timer.pending))
1073                 return;
1074
1075         atomic_inc(&apic->lapic_timer.pending);
1076         /* FIXME: this code should not know anything about vcpus */
1077         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1078
1079         if (waitqueue_active(q))
1080                 wake_up_interruptible(q);
1081 }
1082
1083 static void start_apic_timer(struct kvm_lapic *apic)
1084 {
1085         ktime_t now;
1086         atomic_set(&apic->lapic_timer.pending, 0);
1087
1088         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1089                 /* lapic timer in oneshot or periodic mode */
1090                 now = apic->lapic_timer.timer.base->get_time();
1091                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1092                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1093
1094                 if (!apic->lapic_timer.period)
1095                         return;
1096                 /*
1097                  * Do not allow the guest to program periodic timers with small
1098                  * interval, since the hrtimers are not throttled by the host
1099                  * scheduler.
1100                  */
1101                 if (apic_lvtt_period(apic)) {
1102                         s64 min_period = min_timer_period_us * 1000LL;
1103
1104                         if (apic->lapic_timer.period < min_period) {
1105                                 pr_info_ratelimited(
1106                                     "kvm: vcpu %i: requested %lld ns "
1107                                     "lapic timer period limited to %lld ns\n",
1108                                     apic->vcpu->vcpu_id,
1109                                     apic->lapic_timer.period, min_period);
1110                                 apic->lapic_timer.period = min_period;
1111                         }
1112                 }
1113
1114                 hrtimer_start(&apic->lapic_timer.timer,
1115                               ktime_add_ns(now, apic->lapic_timer.period),
1116                               HRTIMER_MODE_ABS);
1117
1118                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1119                            PRIx64 ", "
1120                            "timer initial count 0x%x, period %lldns, "
1121                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1122                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1123                            kvm_apic_get_reg(apic, APIC_TMICT),
1124                            apic->lapic_timer.period,
1125                            ktime_to_ns(ktime_add_ns(now,
1126                                         apic->lapic_timer.period)));
1127         } else if (apic_lvtt_tscdeadline(apic)) {
1128                 /* lapic timer in tsc deadline mode */
1129                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1130                 u64 ns = 0;
1131                 struct kvm_vcpu *vcpu = apic->vcpu;
1132                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1133                 unsigned long flags;
1134
1135                 if (unlikely(!tscdeadline || !this_tsc_khz))
1136                         return;
1137
1138                 local_irq_save(flags);
1139
1140                 now = apic->lapic_timer.timer.base->get_time();
1141                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1142                 if (likely(tscdeadline > guest_tsc)) {
1143                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1144                         do_div(ns, this_tsc_khz);
1145                         hrtimer_start(&apic->lapic_timer.timer,
1146                                 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1147                 } else
1148                         apic_timer_expired(apic);
1149
1150                 local_irq_restore(flags);
1151         }
1152 }
1153
1154 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1155 {
1156         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1157
1158         if (apic_lvt_nmi_mode(lvt0_val)) {
1159                 if (!nmi_wd_enabled) {
1160                         apic_debug("Receive NMI setting on APIC_LVT0 "
1161                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1162                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1163                 }
1164         } else if (nmi_wd_enabled)
1165                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1166 }
1167
1168 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1169 {
1170         int ret = 0;
1171
1172         trace_kvm_apic_write(reg, val);
1173
1174         switch (reg) {
1175         case APIC_ID:           /* Local APIC ID */
1176                 if (!apic_x2apic_mode(apic))
1177                         kvm_apic_set_id(apic, val >> 24);
1178                 else
1179                         ret = 1;
1180                 break;
1181
1182         case APIC_TASKPRI:
1183                 report_tpr_access(apic, true);
1184                 apic_set_tpr(apic, val & 0xff);
1185                 break;
1186
1187         case APIC_EOI:
1188                 apic_set_eoi(apic);
1189                 break;
1190
1191         case APIC_LDR:
1192                 if (!apic_x2apic_mode(apic))
1193                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1194                 else
1195                         ret = 1;
1196                 break;
1197
1198         case APIC_DFR:
1199                 if (!apic_x2apic_mode(apic)) {
1200                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1201                         recalculate_apic_map(apic->vcpu->kvm);
1202                 } else
1203                         ret = 1;
1204                 break;
1205
1206         case APIC_SPIV: {
1207                 u32 mask = 0x3ff;
1208                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1209                         mask |= APIC_SPIV_DIRECTED_EOI;
1210                 apic_set_spiv(apic, val & mask);
1211                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1212                         int i;
1213                         u32 lvt_val;
1214
1215                         for (i = 0; i < APIC_LVT_NUM; i++) {
1216                                 lvt_val = kvm_apic_get_reg(apic,
1217                                                        APIC_LVTT + 0x10 * i);
1218                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1219                                              lvt_val | APIC_LVT_MASKED);
1220                         }
1221                         atomic_set(&apic->lapic_timer.pending, 0);
1222
1223                 }
1224                 break;
1225         }
1226         case APIC_ICR:
1227                 /* No delay here, so we always clear the pending bit */
1228                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1229                 apic_send_ipi(apic);
1230                 break;
1231
1232         case APIC_ICR2:
1233                 if (!apic_x2apic_mode(apic))
1234                         val &= 0xff000000;
1235                 apic_set_reg(apic, APIC_ICR2, val);
1236                 break;
1237
1238         case APIC_LVT0:
1239                 apic_manage_nmi_watchdog(apic, val);
1240         case APIC_LVTTHMR:
1241         case APIC_LVTPC:
1242         case APIC_LVT1:
1243         case APIC_LVTERR:
1244                 /* TODO: Check vector */
1245                 if (!kvm_apic_sw_enabled(apic))
1246                         val |= APIC_LVT_MASKED;
1247
1248                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1249                 apic_set_reg(apic, reg, val);
1250
1251                 break;
1252
1253         case APIC_LVTT: {
1254                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1255
1256                 if (apic->lapic_timer.timer_mode != timer_mode) {
1257                         apic->lapic_timer.timer_mode = timer_mode;
1258                         hrtimer_cancel(&apic->lapic_timer.timer);
1259                 }
1260
1261                 if (!kvm_apic_sw_enabled(apic))
1262                         val |= APIC_LVT_MASKED;
1263                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1264                 apic_set_reg(apic, APIC_LVTT, val);
1265                 break;
1266         }
1267
1268         case APIC_TMICT:
1269                 if (apic_lvtt_tscdeadline(apic))
1270                         break;
1271
1272                 hrtimer_cancel(&apic->lapic_timer.timer);
1273                 apic_set_reg(apic, APIC_TMICT, val);
1274                 start_apic_timer(apic);
1275                 break;
1276
1277         case APIC_TDCR:
1278                 if (val & 4)
1279                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1280                 apic_set_reg(apic, APIC_TDCR, val);
1281                 update_divide_count(apic);
1282                 break;
1283
1284         case APIC_ESR:
1285                 if (apic_x2apic_mode(apic) && val != 0) {
1286                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1287                         ret = 1;
1288                 }
1289                 break;
1290
1291         case APIC_SELF_IPI:
1292                 if (apic_x2apic_mode(apic)) {
1293                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1294                 } else
1295                         ret = 1;
1296                 break;
1297         default:
1298                 ret = 1;
1299                 break;
1300         }
1301         if (ret)
1302                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1303         return ret;
1304 }
1305
1306 static int apic_mmio_write(struct kvm_io_device *this,
1307                             gpa_t address, int len, const void *data)
1308 {
1309         struct kvm_lapic *apic = to_lapic(this);
1310         unsigned int offset = address - apic->base_address;
1311         u32 val;
1312
1313         if (!apic_mmio_in_range(apic, address))
1314                 return -EOPNOTSUPP;
1315
1316         /*
1317          * APIC register must be aligned on 128-bits boundary.
1318          * 32/64/128 bits registers must be accessed thru 32 bits.
1319          * Refer SDM 8.4.1
1320          */
1321         if (len != 4 || (offset & 0xf)) {
1322                 /* Don't shout loud, $infamous_os would cause only noise. */
1323                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1324                 return 0;
1325         }
1326
1327         val = *(u32*)data;
1328
1329         /* too common printing */
1330         if (offset != APIC_EOI)
1331                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1332                            "0x%x\n", __func__, offset, len, val);
1333
1334         apic_reg_write(apic, offset & 0xff0, val);
1335
1336         return 0;
1337 }
1338
1339 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1340 {
1341         if (kvm_vcpu_has_lapic(vcpu))
1342                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1343 }
1344 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1345
1346 /* emulate APIC access in a trap manner */
1347 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1348 {
1349         u32 val = 0;
1350
1351         /* hw has done the conditional check and inst decode */
1352         offset &= 0xff0;
1353
1354         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1355
1356         /* TODO: optimize to just emulate side effect w/o one more write */
1357         apic_reg_write(vcpu->arch.apic, offset, val);
1358 }
1359 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1360
1361 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1362 {
1363         struct kvm_lapic *apic = vcpu->arch.apic;
1364
1365         if (!vcpu->arch.apic)
1366                 return;
1367
1368         hrtimer_cancel(&apic->lapic_timer.timer);
1369
1370         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1371                 static_key_slow_dec_deferred(&apic_hw_disabled);
1372
1373         if (!apic->sw_enabled)
1374                 static_key_slow_dec_deferred(&apic_sw_disabled);
1375
1376         if (apic->regs)
1377                 free_page((unsigned long)apic->regs);
1378
1379         kfree(apic);
1380 }
1381
1382 /*
1383  *----------------------------------------------------------------------
1384  * LAPIC interface
1385  *----------------------------------------------------------------------
1386  */
1387
1388 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1389 {
1390         struct kvm_lapic *apic = vcpu->arch.apic;
1391
1392         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1393                         apic_lvtt_period(apic))
1394                 return 0;
1395
1396         return apic->lapic_timer.tscdeadline;
1397 }
1398
1399 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1400 {
1401         struct kvm_lapic *apic = vcpu->arch.apic;
1402
1403         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1404                         apic_lvtt_period(apic))
1405                 return;
1406
1407         hrtimer_cancel(&apic->lapic_timer.timer);
1408         apic->lapic_timer.tscdeadline = data;
1409         start_apic_timer(apic);
1410 }
1411
1412 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1413 {
1414         struct kvm_lapic *apic = vcpu->arch.apic;
1415
1416         if (!kvm_vcpu_has_lapic(vcpu))
1417                 return;
1418
1419         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1420                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1421 }
1422
1423 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1424 {
1425         u64 tpr;
1426
1427         if (!kvm_vcpu_has_lapic(vcpu))
1428                 return 0;
1429
1430         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1431
1432         return (tpr & 0xf0) >> 4;
1433 }
1434
1435 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1436 {
1437         u64 old_value = vcpu->arch.apic_base;
1438         struct kvm_lapic *apic = vcpu->arch.apic;
1439
1440         if (!apic) {
1441                 value |= MSR_IA32_APICBASE_BSP;
1442                 vcpu->arch.apic_base = value;
1443                 return;
1444         }
1445
1446         if (!kvm_vcpu_is_bsp(apic->vcpu))
1447                 value &= ~MSR_IA32_APICBASE_BSP;
1448         vcpu->arch.apic_base = value;
1449
1450         /* update jump label if enable bit changes */
1451         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1452                 if (value & MSR_IA32_APICBASE_ENABLE)
1453                         static_key_slow_dec_deferred(&apic_hw_disabled);
1454                 else
1455                         static_key_slow_inc(&apic_hw_disabled.key);
1456                 recalculate_apic_map(vcpu->kvm);
1457         }
1458
1459         if ((old_value ^ value) & X2APIC_ENABLE) {
1460                 if (value & X2APIC_ENABLE) {
1461                         u32 id = kvm_apic_id(apic);
1462                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1463                         kvm_apic_set_ldr(apic, ldr);
1464                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1465                 } else
1466                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1467         }
1468
1469         apic->base_address = apic->vcpu->arch.apic_base &
1470                              MSR_IA32_APICBASE_BASE;
1471
1472         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1473              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1474                 pr_warn_once("APIC base relocation is unsupported by KVM");
1475
1476         /* with FSB delivery interrupt, we can restart APIC functionality */
1477         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1478                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1479
1480 }
1481
1482 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1483 {
1484         struct kvm_lapic *apic;
1485         int i;
1486
1487         apic_debug("%s\n", __func__);
1488
1489         ASSERT(vcpu);
1490         apic = vcpu->arch.apic;
1491         ASSERT(apic != NULL);
1492
1493         /* Stop the timer in case it's a reset to an active apic */
1494         hrtimer_cancel(&apic->lapic_timer.timer);
1495
1496         kvm_apic_set_id(apic, vcpu->vcpu_id);
1497         kvm_apic_set_version(apic->vcpu);
1498
1499         for (i = 0; i < APIC_LVT_NUM; i++)
1500                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1501         apic->lapic_timer.timer_mode = 0;
1502         apic_set_reg(apic, APIC_LVT0,
1503                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1504
1505         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1506         apic_set_spiv(apic, 0xff);
1507         apic_set_reg(apic, APIC_TASKPRI, 0);
1508         kvm_apic_set_ldr(apic, 0);
1509         apic_set_reg(apic, APIC_ESR, 0);
1510         apic_set_reg(apic, APIC_ICR, 0);
1511         apic_set_reg(apic, APIC_ICR2, 0);
1512         apic_set_reg(apic, APIC_TDCR, 0);
1513         apic_set_reg(apic, APIC_TMICT, 0);
1514         for (i = 0; i < 8; i++) {
1515                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1516                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1517                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1518         }
1519         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1520         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1521         apic->highest_isr_cache = -1;
1522         update_divide_count(apic);
1523         atomic_set(&apic->lapic_timer.pending, 0);
1524         if (kvm_vcpu_is_bsp(vcpu))
1525                 kvm_lapic_set_base(vcpu,
1526                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1527         vcpu->arch.pv_eoi.msr_val = 0;
1528         apic_update_ppr(apic);
1529
1530         vcpu->arch.apic_arb_prio = 0;
1531         vcpu->arch.apic_attention = 0;
1532
1533         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1534                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1535                    vcpu, kvm_apic_id(apic),
1536                    vcpu->arch.apic_base, apic->base_address);
1537 }
1538
1539 /*
1540  *----------------------------------------------------------------------
1541  * timer interface
1542  *----------------------------------------------------------------------
1543  */
1544
1545 static bool lapic_is_periodic(struct kvm_lapic *apic)
1546 {
1547         return apic_lvtt_period(apic);
1548 }
1549
1550 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1551 {
1552         struct kvm_lapic *apic = vcpu->arch.apic;
1553
1554         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1555                         apic_lvt_enabled(apic, APIC_LVTT))
1556                 return atomic_read(&apic->lapic_timer.pending);
1557
1558         return 0;
1559 }
1560
1561 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1562 {
1563         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1564         int vector, mode, trig_mode;
1565
1566         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1567                 vector = reg & APIC_VECTOR_MASK;
1568                 mode = reg & APIC_MODE_MASK;
1569                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1570                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1571                                         NULL);
1572         }
1573         return 0;
1574 }
1575
1576 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1577 {
1578         struct kvm_lapic *apic = vcpu->arch.apic;
1579
1580         if (apic)
1581                 kvm_apic_local_deliver(apic, APIC_LVT0);
1582 }
1583
1584 static const struct kvm_io_device_ops apic_mmio_ops = {
1585         .read     = apic_mmio_read,
1586         .write    = apic_mmio_write,
1587 };
1588
1589 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1590 {
1591         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1592         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1593
1594         apic_timer_expired(apic);
1595
1596         if (lapic_is_periodic(apic)) {
1597                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1598                 return HRTIMER_RESTART;
1599         } else
1600                 return HRTIMER_NORESTART;
1601 }
1602
1603 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1604 {
1605         struct kvm_lapic *apic;
1606
1607         ASSERT(vcpu != NULL);
1608         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1609
1610         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1611         if (!apic)
1612                 goto nomem;
1613
1614         vcpu->arch.apic = apic;
1615
1616         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1617         if (!apic->regs) {
1618                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1619                        vcpu->vcpu_id);
1620                 goto nomem_free_apic;
1621         }
1622         apic->vcpu = vcpu;
1623
1624         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1625                      HRTIMER_MODE_ABS);
1626         apic->lapic_timer.timer.function = apic_timer_fn;
1627
1628         /*
1629          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1630          * thinking that APIC satet has changed.
1631          */
1632         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1633         kvm_lapic_set_base(vcpu,
1634                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1635
1636         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1637         kvm_lapic_reset(vcpu);
1638         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1639
1640         return 0;
1641 nomem_free_apic:
1642         kfree(apic);
1643 nomem:
1644         return -ENOMEM;
1645 }
1646
1647 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1648 {
1649         struct kvm_lapic *apic = vcpu->arch.apic;
1650         int highest_irr;
1651
1652         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1653                 return -1;
1654
1655         apic_update_ppr(apic);
1656         highest_irr = apic_find_highest_irr(apic);
1657         if ((highest_irr == -1) ||
1658             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1659                 return -1;
1660         return highest_irr;
1661 }
1662
1663 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1664 {
1665         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1666         int r = 0;
1667
1668         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1669                 r = 1;
1670         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1671             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1672                 r = 1;
1673         return r;
1674 }
1675
1676 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1677 {
1678         struct kvm_lapic *apic = vcpu->arch.apic;
1679
1680         if (!kvm_vcpu_has_lapic(vcpu))
1681                 return;
1682
1683         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1684                 kvm_apic_local_deliver(apic, APIC_LVTT);
1685                 if (apic_lvtt_tscdeadline(apic))
1686                         apic->lapic_timer.tscdeadline = 0;
1687                 atomic_set(&apic->lapic_timer.pending, 0);
1688         }
1689 }
1690
1691 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1692 {
1693         int vector = kvm_apic_has_interrupt(vcpu);
1694         struct kvm_lapic *apic = vcpu->arch.apic;
1695
1696         if (vector == -1)
1697                 return -1;
1698
1699         /*
1700          * We get here even with APIC virtualization enabled, if doing
1701          * nested virtualization and L1 runs with the "acknowledge interrupt
1702          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1703          * because the process would deliver it through the IDT.
1704          */
1705
1706         apic_set_isr(vector, apic);
1707         apic_update_ppr(apic);
1708         apic_clear_irr(vector, apic);
1709         return vector;
1710 }
1711
1712 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1713                 struct kvm_lapic_state *s)
1714 {
1715         struct kvm_lapic *apic = vcpu->arch.apic;
1716
1717         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1718         /* set SPIV separately to get count of SW disabled APICs right */
1719         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1720         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1721         /* call kvm_apic_set_id() to put apic into apic_map */
1722         kvm_apic_set_id(apic, kvm_apic_id(apic));
1723         kvm_apic_set_version(vcpu);
1724
1725         apic_update_ppr(apic);
1726         hrtimer_cancel(&apic->lapic_timer.timer);
1727         update_divide_count(apic);
1728         start_apic_timer(apic);
1729         apic->irr_pending = true;
1730         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1731                                 1 : count_vectors(apic->regs + APIC_ISR);
1732         apic->highest_isr_cache = -1;
1733         if (kvm_x86_ops->hwapic_irr_update)
1734                 kvm_x86_ops->hwapic_irr_update(vcpu,
1735                                 apic_find_highest_irr(apic));
1736         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1737         kvm_make_request(KVM_REQ_EVENT, vcpu);
1738         kvm_rtc_eoi_tracking_restore_one(vcpu);
1739 }
1740
1741 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1742 {
1743         struct hrtimer *timer;
1744
1745         if (!kvm_vcpu_has_lapic(vcpu))
1746                 return;
1747
1748         timer = &vcpu->arch.apic->lapic_timer.timer;
1749         if (hrtimer_cancel(timer))
1750                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1751 }
1752
1753 /*
1754  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1755  *
1756  * Detect whether guest triggered PV EOI since the
1757  * last entry. If yes, set EOI on guests's behalf.
1758  * Clear PV EOI in guest memory in any case.
1759  */
1760 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1761                                         struct kvm_lapic *apic)
1762 {
1763         bool pending;
1764         int vector;
1765         /*
1766          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1767          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1768          *
1769          * KVM_APIC_PV_EOI_PENDING is unset:
1770          *      -> host disabled PV EOI.
1771          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1772          *      -> host enabled PV EOI, guest did not execute EOI yet.
1773          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1774          *      -> host enabled PV EOI, guest executed EOI.
1775          */
1776         BUG_ON(!pv_eoi_enabled(vcpu));
1777         pending = pv_eoi_get_pending(vcpu);
1778         /*
1779          * Clear pending bit in any case: it will be set again on vmentry.
1780          * While this might not be ideal from performance point of view,
1781          * this makes sure pv eoi is only enabled when we know it's safe.
1782          */
1783         pv_eoi_clr_pending(vcpu);
1784         if (pending)
1785                 return;
1786         vector = apic_set_eoi(apic);
1787         trace_kvm_pv_eoi(apic, vector);
1788 }
1789
1790 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1791 {
1792         u32 data;
1793
1794         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1795                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1796
1797         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1798                 return;
1799
1800         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1801                                 sizeof(u32));
1802
1803         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1804 }
1805
1806 /*
1807  * apic_sync_pv_eoi_to_guest - called before vmentry
1808  *
1809  * Detect whether it's safe to enable PV EOI and
1810  * if yes do so.
1811  */
1812 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1813                                         struct kvm_lapic *apic)
1814 {
1815         if (!pv_eoi_enabled(vcpu) ||
1816             /* IRR set or many bits in ISR: could be nested. */
1817             apic->irr_pending ||
1818             /* Cache not set: could be safe but we don't bother. */
1819             apic->highest_isr_cache == -1 ||
1820             /* Need EOI to update ioapic. */
1821             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1822                 /*
1823                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1824                  * so we need not do anything here.
1825                  */
1826                 return;
1827         }
1828
1829         pv_eoi_set_pending(apic->vcpu);
1830 }
1831
1832 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1833 {
1834         u32 data, tpr;
1835         int max_irr, max_isr;
1836         struct kvm_lapic *apic = vcpu->arch.apic;
1837
1838         apic_sync_pv_eoi_to_guest(vcpu, apic);
1839
1840         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1841                 return;
1842
1843         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1844         max_irr = apic_find_highest_irr(apic);
1845         if (max_irr < 0)
1846                 max_irr = 0;
1847         max_isr = apic_find_highest_isr(apic);
1848         if (max_isr < 0)
1849                 max_isr = 0;
1850         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1851
1852         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1853                                 sizeof(u32));
1854 }
1855
1856 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1857 {
1858         if (vapic_addr) {
1859                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1860                                         &vcpu->arch.apic->vapic_cache,
1861                                         vapic_addr, sizeof(u32)))
1862                         return -EINVAL;
1863                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1864         } else {
1865                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1866         }
1867
1868         vcpu->arch.apic->vapic_addr = vapic_addr;
1869         return 0;
1870 }
1871
1872 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1873 {
1874         struct kvm_lapic *apic = vcpu->arch.apic;
1875         u32 reg = (msr - APIC_BASE_MSR) << 4;
1876
1877         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1878                 return 1;
1879
1880         /* if this is ICR write vector before command */
1881         if (msr == 0x830)
1882                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1883         return apic_reg_write(apic, reg, (u32)data);
1884 }
1885
1886 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1887 {
1888         struct kvm_lapic *apic = vcpu->arch.apic;
1889         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1890
1891         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1892                 return 1;
1893
1894         if (apic_reg_read(apic, reg, 4, &low))
1895                 return 1;
1896         if (msr == 0x830)
1897                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1898
1899         *data = (((u64)high) << 32) | low;
1900
1901         return 0;
1902 }
1903
1904 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1905 {
1906         struct kvm_lapic *apic = vcpu->arch.apic;
1907
1908         if (!kvm_vcpu_has_lapic(vcpu))
1909                 return 1;
1910
1911         /* if this is ICR write vector before command */
1912         if (reg == APIC_ICR)
1913                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1914         return apic_reg_write(apic, reg, (u32)data);
1915 }
1916
1917 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1918 {
1919         struct kvm_lapic *apic = vcpu->arch.apic;
1920         u32 low, high = 0;
1921
1922         if (!kvm_vcpu_has_lapic(vcpu))
1923                 return 1;
1924
1925         if (apic_reg_read(apic, reg, 4, &low))
1926                 return 1;
1927         if (reg == APIC_ICR)
1928                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1929
1930         *data = (((u64)high) << 32) | low;
1931
1932         return 0;
1933 }
1934
1935 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1936 {
1937         u64 addr = data & ~KVM_MSR_ENABLED;
1938         if (!IS_ALIGNED(addr, 4))
1939                 return 1;
1940
1941         vcpu->arch.pv_eoi.msr_val = data;
1942         if (!pv_eoi_enabled(vcpu))
1943                 return 0;
1944         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1945                                          addr, sizeof(u8));
1946 }
1947
1948 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1949 {
1950         struct kvm_lapic *apic = vcpu->arch.apic;
1951         unsigned int sipi_vector;
1952         unsigned long pe;
1953
1954         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1955                 return;
1956
1957         pe = xchg(&apic->pending_events, 0);
1958
1959         if (test_bit(KVM_APIC_INIT, &pe)) {
1960                 kvm_lapic_reset(vcpu);
1961                 kvm_vcpu_reset(vcpu);
1962                 if (kvm_vcpu_is_bsp(apic->vcpu))
1963                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1964                 else
1965                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1966         }
1967         if (test_bit(KVM_APIC_SIPI, &pe) &&
1968             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1969                 /* evaluate pending_events before reading the vector */
1970                 smp_rmb();
1971                 sipi_vector = apic->sipi_vector;
1972                 apic_debug("vcpu %d received sipi with vector # %x\n",
1973                          vcpu->vcpu_id, sipi_vector);
1974                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1975                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1976         }
1977 }
1978
1979 void kvm_lapic_init(void)
1980 {
1981         /* do not patch jump label more than once per second */
1982         jump_label_rate_limit(&apic_hw_disabled, HZ);
1983         jump_label_rate_limit(&apic_sw_disabled, HZ);
1984 }