arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define APIC_BROADCAST                  0xFF
  72 #define X2APIC_BROADCAST                0xFFFFFFFFul
  73
  74 #define VEC_POS(v) ((v) & (32 - 1))
  75 #define REG_POS(v) (((v) >> 5) << 4)
  76
  77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  78 {
  79         *((u32 *) (apic->regs + reg_off)) = val;
  80 }
  81
  82 static inline int apic_test_vector(int vec, void *bitmap)
  83 {
  84         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  88 {
  89         struct kvm_lapic *apic = vcpu->arch.apic;
  90
  91         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  92                 apic_test_vector(vector, apic->regs + APIC_IRR);
  93 }
  94
  95 static inline void apic_set_vector(int vec, void *bitmap)
  96 {
  97         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline void apic_clear_vector(int vec, void *bitmap)
 101 {
 102         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 106 {
 107         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 111 {
 112         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 struct static_key_deferred apic_hw_disabled __read_mostly;
 116 struct static_key_deferred apic_sw_disabled __read_mostly;
 117
 118 static inline int apic_enabled(struct kvm_lapic *apic)
 119 {
 120         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 121 }
 122
 123 #define LVT_MASK        \
 124         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 125
 126 #define LINT_MASK       \
 127         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 128          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 129
 130 static inline int kvm_apic_id(struct kvm_lapic *apic)
 131 {
 132         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 133 }
 134
 135 #define KVM_X2APIC_CID_BITS 0
 136
 137 static void recalculate_apic_map(struct kvm *kvm)
 138 {
 139         struct kvm_apic_map *new, *old = NULL;
 140         struct kvm_vcpu *vcpu;
 141         int i;
 142
 143         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 144
 145         mutex_lock(&kvm->arch.apic_map_lock);
 146
 147         if (!new)
 148                 goto out;
 149
 150         new->ldr_bits = 8;
 151         /* flat mode is default */
 152         new->cid_shift = 8;
 153         new->cid_mask = 0;
 154         new->lid_mask = 0xff;
 155         new->broadcast = APIC_BROADCAST;
 156
 157         kvm_for_each_vcpu(i, vcpu, kvm) {
 158                 struct kvm_lapic *apic = vcpu->arch.apic;
 159
 160                 if (!kvm_apic_present(vcpu))
 161                         continue;
 162
 163                 if (apic_x2apic_mode(apic)) {
 164                         new->ldr_bits = 32;
 165                         new->cid_shift = 16;
 166                         new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
 167                         new->lid_mask = 0xffff;
 168                         new->broadcast = X2APIC_BROADCAST;
 169                 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
 170                         if (kvm_apic_get_reg(apic, APIC_DFR) ==
 171                                                         APIC_DFR_CLUSTER) {
 172                                 new->cid_shift = 4;
 173                                 new->cid_mask = 0xf;
 174                                 new->lid_mask = 0xf;
 175                         } else {
 176                                 new->cid_shift = 8;
 177                                 new->cid_mask = 0;
 178                                 new->lid_mask = 0xff;
 179                         }
 180                 }
 181
 182                 /*
 183                  * All APICs have to be configured in the same mode by an OS.
 184                  * We take advatage of this while building logical id loockup
 185                  * table. After reset APICs are in software disabled mode, so if
 186                  * we find apic with different setting we assume this is the mode
 187                  * OS wants all apics to be in; build lookup table accordingly.
 188                  */
 189                 if (kvm_apic_sw_enabled(apic))
 190                         break;
 191         }
 192
 193         kvm_for_each_vcpu(i, vcpu, kvm) {
 194                 struct kvm_lapic *apic = vcpu->arch.apic;
 195                 u16 cid, lid;
 196                 u32 ldr;
 197
 198                 new->phys_map[kvm_apic_id(apic)] = apic;
 199
 200                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 201                 cid = apic_cluster_id(new, ldr);
 202                 lid = apic_logical_id(new, ldr);
 203
 204                 if (lid)
 205                         new->logical_map[cid][ffs(lid) - 1] = apic;
 206         }
 207 out:
 208         old = rcu_dereference_protected(kvm->arch.apic_map,
 209                         lockdep_is_held(&kvm->arch.apic_map_lock));
 210         rcu_assign_pointer(kvm->arch.apic_map, new);
 211         mutex_unlock(&kvm->arch.apic_map_lock);
 212
 213         if (old)
 214                 kfree_rcu(old, rcu);
 215
 216         kvm_vcpu_request_scan_ioapic(kvm);
 217 }
 218
 219 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 220 {
 221         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 222
 223         apic_set_reg(apic, APIC_SPIV, val);
 224
 225         if (enabled != apic->sw_enabled) {
 226                 apic->sw_enabled = enabled;
 227                 if (enabled) {
 228                         static_key_slow_dec_deferred(&apic_sw_disabled);
 229                         recalculate_apic_map(apic->vcpu->kvm);
 230                 } else
 231                         static_key_slow_inc(&apic_sw_disabled.key);
 232         }
 233 }
 234
 235 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 236 {
 237         apic_set_reg(apic, APIC_ID, id << 24);
 238         recalculate_apic_map(apic->vcpu->kvm);
 239 }
 240
 241 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 242 {
 243         apic_set_reg(apic, APIC_LDR, id);
 244         recalculate_apic_map(apic->vcpu->kvm);
 245 }
 246
 247 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 248 {
 249         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 250 }
 251
 252 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 253 {
 254         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 255 }
 256
 257 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 258 {
 259         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 260 }
 261
 262 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 263 {
 264         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 265 }
 266
 267 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 268 {
 269         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 270 }
 271
 272 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 273 {
 274         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 275 }
 276
 277 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 278 {
 279         struct kvm_lapic *apic = vcpu->arch.apic;
 280         struct kvm_cpuid_entry2 *feat;
 281         u32 v = APIC_VERSION;
 282
 283         if (!kvm_vcpu_has_lapic(vcpu))
 284                 return;
 285
 286         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 287         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 288                 v |= APIC_LVR_DIRECTED_EOI;
 289         apic_set_reg(apic, APIC_LVR, v);
 290 }
 291
 292 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 293         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 294         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 295         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 296         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 297         LVT_MASK                /* LVTERR */
 298 };
 299
 300 static int find_highest_vector(void *bitmap)
 301 {
 302         int vec;
 303         u32 *reg;
 304
 305         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 306              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 307                 reg = bitmap + REG_POS(vec);
 308                 if (*reg)
 309                         return fls(*reg) - 1 + vec;
 310         }
 311
 312         return -1;
 313 }
 314
 315 static u8 count_vectors(void *bitmap)
 316 {
 317         int vec;
 318         u32 *reg;
 319         u8 count = 0;
 320
 321         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 322                 reg = bitmap + REG_POS(vec);
 323                 count += hweight32(*reg);
 324         }
 325
 326         return count;
 327 }
 328
 329 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 330 {
 331         u32 i, pir_val;
 332         struct kvm_lapic *apic = vcpu->arch.apic;
 333
 334         for (i = 0; i <= 7; i++) {
 335                 pir_val = xchg(&pir[i], 0);
 336                 if (pir_val)
 337                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 338         }
 339 }
 340 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 341
 342 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 343 {
 344         apic_set_vector(vec, apic->regs + APIC_IRR);
 345         /*
 346          * irr_pending must be true if any interrupt is pending; set it after
 347          * APIC_IRR to avoid race with apic_clear_irr
 348          */
 349         apic->irr_pending = true;
 350 }
 351
 352 static inline int apic_search_irr(struct kvm_lapic *apic)
 353 {
 354         return find_highest_vector(apic->regs + APIC_IRR);
 355 }
 356
 357 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 358 {
 359         int result;
 360
 361         /*
 362          * Note that irr_pending is just a hint. It will be always
 363          * true with virtual interrupt delivery enabled.
 364          */
 365         if (!apic->irr_pending)
 366                 return -1;
 367
 368         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 369         result = apic_search_irr(apic);
 370         ASSERT(result == -1 || result >= 16);
 371
 372         return result;
 373 }
 374
 375 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 376 {
 377         struct kvm_vcpu *vcpu;
 378
 379         vcpu = apic->vcpu;
 380
 381         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
 382                 /* try to update RVI */
 383                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 384                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 385         } else {
 386                 apic->irr_pending = false;
 387                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 388                 if (apic_search_irr(apic) != -1)
 389                         apic->irr_pending = true;
 390         }
 391 }
 392
 393 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 394 {
 395         struct kvm_vcpu *vcpu;
 396
 397         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 398                 return;
 399
 400         vcpu = apic->vcpu;
 401
 402         /*
 403          * With APIC virtualization enabled, all caching is disabled
 404          * because the processor can modify ISR under the hood.  Instead
 405          * just set SVI.
 406          */
 407         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 408                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 409         else {
 410                 ++apic->isr_count;
 411                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 412                 /*
 413                  * ISR (in service register) bit is set when injecting an interrupt.
 414                  * The highest vector is injected. Thus the latest bit set matches
 415                  * the highest bit in ISR.
 416                  */
 417                 apic->highest_isr_cache = vec;
 418         }
 419 }
 420
 421 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 422 {
 423         int result;
 424
 425         /*
 426          * Note that isr_count is always 1, and highest_isr_cache
 427          * is always -1, with APIC virtualization enabled.
 428          */
 429         if (!apic->isr_count)
 430                 return -1;
 431         if (likely(apic->highest_isr_cache != -1))
 432                 return apic->highest_isr_cache;
 433
 434         result = find_highest_vector(apic->regs + APIC_ISR);
 435         ASSERT(result == -1 || result >= 16);
 436
 437         return result;
 438 }
 439
 440 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 441 {
 442         struct kvm_vcpu *vcpu;
 443         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 444                 return;
 445
 446         vcpu = apic->vcpu;
 447
 448         /*
 449          * We do get here for APIC virtualization enabled if the guest
 450          * uses the Hyper-V APIC enlightenment.  In this case we may need
 451          * to trigger a new interrupt delivery by writing the SVI field;
 452          * on the other hand isr_count and highest_isr_cache are unused
 453          * and must be left alone.
 454          */
 455         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 456                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 457                                                apic_find_highest_isr(apic));
 458         else {
 459                 --apic->isr_count;
 460                 BUG_ON(apic->isr_count < 0);
 461                 apic->highest_isr_cache = -1;
 462         }
 463 }
 464
 465 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 466 {
 467         int highest_irr;
 468
 469         /* This may race with setting of irr in __apic_accept_irq() and
 470          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 471          * will cause vmexit immediately and the value will be recalculated
 472          * on the next vmentry.
 473          */
 474         if (!kvm_vcpu_has_lapic(vcpu))
 475                 return 0;
 476         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 477
 478         return highest_irr;
 479 }
 480
 481 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 482                              int vector, int level, int trig_mode,
 483                              unsigned long *dest_map);
 484
 485 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 486                 unsigned long *dest_map)
 487 {
 488         struct kvm_lapic *apic = vcpu->arch.apic;
 489
 490         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 491                         irq->level, irq->trig_mode, dest_map);
 492 }
 493
 494 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 495 {
 496
 497         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 498                                       sizeof(val));
 499 }
 500
 501 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 502 {
 503
 504         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 505                                       sizeof(*val));
 506 }
 507
 508 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 509 {
 510         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 511 }
 512
 513 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 514 {
 515         u8 val;
 516         if (pv_eoi_get_user(vcpu, &val) < 0)
 517                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 518                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 519         return val & 0x1;
 520 }
 521
 522 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 523 {
 524         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 525                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 526                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 527                 return;
 528         }
 529         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 530 }
 531
 532 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 533 {
 534         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 535                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 536                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 537                 return;
 538         }
 539         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 540 }
 541
 542 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 543 {
 544         struct kvm_lapic *apic = vcpu->arch.apic;
 545         int i;
 546
 547         for (i = 0; i < 8; i++)
 548                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 549 }
 550
 551 static void apic_update_ppr(struct kvm_lapic *apic)
 552 {
 553         u32 tpr, isrv, ppr, old_ppr;
 554         int isr;
 555
 556         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 557         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 558         isr = apic_find_highest_isr(apic);
 559         isrv = (isr != -1) ? isr : 0;
 560
 561         if ((tpr & 0xf0) >= (isrv & 0xf0))
 562                 ppr = tpr & 0xff;
 563         else
 564                 ppr = isrv & 0xf0;
 565
 566         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 567                    apic, ppr, isr, isrv);
 568
 569         if (old_ppr != ppr) {
 570                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 571                 if (ppr < old_ppr)
 572                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 573         }
 574 }
 575
 576 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 577 {
 578         apic_set_reg(apic, APIC_TASKPRI, tpr);
 579         apic_update_ppr(apic);
 580 }
 581
 582 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 583 {
 584         return dest == (apic_x2apic_mode(apic) ?
 585                         X2APIC_BROADCAST : APIC_BROADCAST);
 586 }
 587
 588 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 589 {
 590         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 591 }
 592
 593 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 594 {
 595         int result = 0;
 596         u32 logical_id;
 597
 598         if (kvm_apic_broadcast(apic, mda))
 599                 return 1;
 600
 601         if (apic_x2apic_mode(apic)) {
 602                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 603                 return logical_id & mda;
 604         }
 605
 606         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 607
 608         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 609         case APIC_DFR_FLAT:
 610                 if (logical_id & mda)
 611                         result = 1;
 612                 break;
 613         case APIC_DFR_CLUSTER:
 614                 if (((logical_id >> 4) == (mda >> 0x4))
 615                     && (logical_id & mda & 0xf))
 616                         result = 1;
 617                 break;
 618         default:
 619                 apic_debug("Bad DFR vcpu %d: %08x\n",
 620                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 621                 break;
 622         }
 623
 624         return result;
 625 }
 626
 627 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 628                            int short_hand, unsigned int dest, int dest_mode)
 629 {
 630         int result = 0;
 631         struct kvm_lapic *target = vcpu->arch.apic;
 632
 633         apic_debug("target %p, source %p, dest 0x%x, "
 634                    "dest_mode 0x%x, short_hand 0x%x\n",
 635                    target, source, dest, dest_mode, short_hand);
 636
 637         ASSERT(target);
 638         switch (short_hand) {
 639         case APIC_DEST_NOSHORT:
 640                 if (dest_mode == 0)
 641                         /* Physical mode. */
 642                         result = kvm_apic_match_physical_addr(target, dest);
 643                 else
 644                         /* Logical mode. */
 645                         result = kvm_apic_match_logical_addr(target, dest);
 646                 break;
 647         case APIC_DEST_SELF:
 648                 result = (target == source);
 649                 break;
 650         case APIC_DEST_ALLINC:
 651                 result = 1;
 652                 break;
 653         case APIC_DEST_ALLBUT:
 654                 result = (target != source);
 655                 break;
 656         default:
 657                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 658                            short_hand);
 659                 break;
 660         }
 661
 662         return result;
 663 }
 664
 665 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 666                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 667 {
 668         struct kvm_apic_map *map;
 669         unsigned long bitmap = 1;
 670         struct kvm_lapic **dst;
 671         int i;
 672         bool ret = false;
 673
 674         *r = -1;
 675
 676         if (irq->shorthand == APIC_DEST_SELF) {
 677                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 678                 return true;
 679         }
 680
 681         if (irq->shorthand)
 682                 return false;
 683
 684         rcu_read_lock();
 685         map = rcu_dereference(kvm->arch.apic_map);
 686
 687         if (!map)
 688                 goto out;
 689
 690         if (irq->dest_id == map->broadcast)
 691                 goto out;
 692
 693         if (irq->dest_mode == 0) { /* physical mode */
 694                 if (irq->delivery_mode == APIC_DM_LOWEST)
 695                         goto out;
 696                 dst = &map->phys_map[irq->dest_id & 0xff];
 697         } else {
 698                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 699
 700                 dst = map->logical_map[apic_cluster_id(map, mda)];
 701
 702                 bitmap = apic_logical_id(map, mda);
 703
 704                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 705                         int l = -1;
 706                         for_each_set_bit(i, &bitmap, 16) {
 707                                 if (!dst[i])
 708                                         continue;
 709                                 if (l < 0)
 710                                         l = i;
 711                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 712                                         l = i;
 713                         }
 714
 715                         bitmap = (l >= 0) ? 1 << l : 0;
 716                 }
 717         }
 718
 719         for_each_set_bit(i, &bitmap, 16) {
 720                 if (!dst[i])
 721                         continue;
 722                 if (*r < 0)
 723                         *r = 0;
 724                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 725         }
 726
 727         ret = true;
 728 out:
 729         rcu_read_unlock();
 730         return ret;
 731 }
 732
 733 /*
 734  * Add a pending IRQ into lapic.
 735  * Return 1 if successfully added and 0 if discarded.
 736  */
 737 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 738                              int vector, int level, int trig_mode,
 739                              unsigned long *dest_map)
 740 {
 741         int result = 0;
 742         struct kvm_vcpu *vcpu = apic->vcpu;
 743
 744         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 745                                   trig_mode, vector);
 746         switch (delivery_mode) {
 747         case APIC_DM_LOWEST:
 748                 vcpu->arch.apic_arb_prio++;
 749         case APIC_DM_FIXED:
 750                 /* FIXME add logic for vcpu on reset */
 751                 if (unlikely(!apic_enabled(apic)))
 752                         break;
 753
 754                 result = 1;
 755
 756                 if (dest_map)
 757                         __set_bit(vcpu->vcpu_id, dest_map);
 758
 759                 if (kvm_x86_ops->deliver_posted_interrupt)
 760                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 761                 else {
 762                         apic_set_irr(vector, apic);
 763
 764                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 765                         kvm_vcpu_kick(vcpu);
 766                 }
 767                 break;
 768
 769         case APIC_DM_REMRD:
 770                 result = 1;
 771                 vcpu->arch.pv.pv_unhalted = 1;
 772                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 773                 kvm_vcpu_kick(vcpu);
 774                 break;
 775
 776         case APIC_DM_SMI:
 777                 apic_debug("Ignoring guest SMI\n");
 778                 break;
 779
 780         case APIC_DM_NMI:
 781                 result = 1;
 782                 kvm_inject_nmi(vcpu);
 783                 kvm_vcpu_kick(vcpu);
 784                 break;
 785
 786         case APIC_DM_INIT:
 787                 if (!trig_mode || level) {
 788                         result = 1;
 789                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 790                         apic->pending_events = (1UL << KVM_APIC_INIT);
 791                         /* make sure pending_events is visible before sending
 792                          * the request */
 793                         smp_wmb();
 794                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 795                         kvm_vcpu_kick(vcpu);
 796                 } else {
 797                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 798                                    vcpu->vcpu_id);
 799                 }
 800                 break;
 801
 802         case APIC_DM_STARTUP:
 803                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 804                            vcpu->vcpu_id, vector);
 805                 result = 1;
 806                 apic->sipi_vector = vector;
 807                 /* make sure sipi_vector is visible for the receiver */
 808                 smp_wmb();
 809                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 810                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 811                 kvm_vcpu_kick(vcpu);
 812                 break;
 813
 814         case APIC_DM_EXTINT:
 815                 /*
 816                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 817                  * before NMI watchdog was enabled. Already handled by
 818                  * kvm_apic_accept_pic_intr().
 819                  */
 820                 break;
 821
 822         default:
 823                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 824                        delivery_mode);
 825                 break;
 826         }
 827         return result;
 828 }
 829
 830 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 831 {
 832         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 833 }
 834
 835 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 836 {
 837         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 838             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 839                 int trigger_mode;
 840                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 841                         trigger_mode = IOAPIC_LEVEL_TRIG;
 842                 else
 843                         trigger_mode = IOAPIC_EDGE_TRIG;
 844                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 845         }
 846 }
 847
 848 static int apic_set_eoi(struct kvm_lapic *apic)
 849 {
 850         int vector = apic_find_highest_isr(apic);
 851
 852         trace_kvm_eoi(apic, vector);
 853
 854         /*
 855          * Not every write EOI will has corresponding ISR,
 856          * one example is when Kernel check timer on setup_IO_APIC
 857          */
 858         if (vector == -1)
 859                 return vector;
 860
 861         apic_clear_isr(vector, apic);
 862         apic_update_ppr(apic);
 863
 864         kvm_ioapic_send_eoi(apic, vector);
 865         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 866         return vector;
 867 }
 868
 869 /*
 870  * this interface assumes a trap-like exit, which has already finished
 871  * desired side effect including vISR and vPPR update.
 872  */
 873 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 874 {
 875         struct kvm_lapic *apic = vcpu->arch.apic;
 876
 877         trace_kvm_eoi(apic, vector);
 878
 879         kvm_ioapic_send_eoi(apic, vector);
 880         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 881 }
 882 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 883
 884 static void apic_send_ipi(struct kvm_lapic *apic)
 885 {
 886         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 887         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 888         struct kvm_lapic_irq irq;
 889
 890         irq.vector = icr_low & APIC_VECTOR_MASK;
 891         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 892         irq.dest_mode = icr_low & APIC_DEST_MASK;
 893         irq.level = icr_low & APIC_INT_ASSERT;
 894         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 895         irq.shorthand = icr_low & APIC_SHORT_MASK;
 896         if (apic_x2apic_mode(apic))
 897                 irq.dest_id = icr_high;
 898         else
 899                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 900
 901         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 902
 903         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 904                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 905                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 906                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 907                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 908                    irq.vector);
 909
 910         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 911 }
 912
 913 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 914 {
 915         ktime_t remaining;
 916         s64 ns;
 917         u32 tmcct;
 918
 919         ASSERT(apic != NULL);
 920
 921         /* if initial count is 0, current count should also be 0 */
 922         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 923                 apic->lapic_timer.period == 0)
 924                 return 0;
 925
 926         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 927         if (ktime_to_ns(remaining) < 0)
 928                 remaining = ktime_set(0, 0);
 929
 930         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 931         tmcct = div64_u64(ns,
 932                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 933
 934         return tmcct;
 935 }
 936
 937 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 938 {
 939         struct kvm_vcpu *vcpu = apic->vcpu;
 940         struct kvm_run *run = vcpu->run;
 941
 942         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 943         run->tpr_access.rip = kvm_rip_read(vcpu);
 944         run->tpr_access.is_write = write;
 945 }
 946
 947 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 948 {
 949         if (apic->vcpu->arch.tpr_access_reporting)
 950                 __report_tpr_access(apic, write);
 951 }
 952
 953 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 954 {
 955         u32 val = 0;
 956
 957         if (offset >= LAPIC_MMIO_LENGTH)
 958                 return 0;
 959
 960         switch (offset) {
 961         case APIC_ID:
 962                 if (apic_x2apic_mode(apic))
 963                         val = kvm_apic_id(apic);
 964                 else
 965                         val = kvm_apic_id(apic) << 24;
 966                 break;
 967         case APIC_ARBPRI:
 968                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 969                 break;
 970
 971         case APIC_TMCCT:        /* Timer CCR */
 972                 if (apic_lvtt_tscdeadline(apic))
 973                         return 0;
 974
 975                 val = apic_get_tmcct(apic);
 976                 break;
 977         case APIC_PROCPRI:
 978                 apic_update_ppr(apic);
 979                 val = kvm_apic_get_reg(apic, offset);
 980                 break;
 981         case APIC_TASKPRI:
 982                 report_tpr_access(apic, false);
 983                 /* fall thru */
 984         default:
 985                 val = kvm_apic_get_reg(apic, offset);
 986                 break;
 987         }
 988
 989         return val;
 990 }
 991
 992 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 993 {
 994         return container_of(dev, struct kvm_lapic, dev);
 995 }
 996
 997 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 998                 void *data)
 999 {
1000         unsigned char alignment = offset & 0xf;
1001         u32 result;
1002         /* this bitmask has a bit cleared for each reserved register */
1003         static const u64 rmask = 0x43ff01ffffffe70cULL;
1004
1005         if ((alignment + len) > 4) {
1006                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1007                            offset, len);
1008                 return 1;
1009         }
1010
1011         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1012                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1013                            offset);
1014                 return 1;
1015         }
1016
1017         result = __apic_read(apic, offset & ~0xf);
1018
1019         trace_kvm_apic_read(offset, result);
1020
1021         switch (len) {
1022         case 1:
1023         case 2:
1024         case 4:
1025                 memcpy(data, (char *)&result + alignment, len);
1026                 break;
1027         default:
1028                 printk(KERN_ERR "Local APIC read with len = %x, "
1029                        "should be 1,2, or 4 instead\n", len);
1030                 break;
1031         }
1032         return 0;
1033 }
1034
1035 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1036 {
1037         return kvm_apic_hw_enabled(apic) &&
1038             addr >= apic->base_address &&
1039             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1040 }
1041
1042 static int apic_mmio_read(struct kvm_io_device *this,
1043                            gpa_t address, int len, void *data)
1044 {
1045         struct kvm_lapic *apic = to_lapic(this);
1046         u32 offset = address - apic->base_address;
1047
1048         if (!apic_mmio_in_range(apic, address))
1049                 return -EOPNOTSUPP;
1050
1051         apic_reg_read(apic, offset, len, data);
1052
1053         return 0;
1054 }
1055
1056 static void update_divide_count(struct kvm_lapic *apic)
1057 {
1058         u32 tmp1, tmp2, tdcr;
1059
1060         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1061         tmp1 = tdcr & 0xf;
1062         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1063         apic->divide_count = 0x1 << (tmp2 & 0x7);
1064
1065         apic_debug("timer divide count is 0x%x\n",
1066                                    apic->divide_count);
1067 }
1068
1069 static void apic_timer_expired(struct kvm_lapic *apic)
1070 {
1071         struct kvm_vcpu *vcpu = apic->vcpu;
1072         wait_queue_head_t *q = &vcpu->wq;
1073
1074         /*
1075          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1076          * vcpu_enter_guest.
1077          */
1078         if (atomic_read(&apic->lapic_timer.pending))
1079                 return;
1080
1081         atomic_inc(&apic->lapic_timer.pending);
1082         /* FIXME: this code should not know anything about vcpus */
1083         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1084
1085         if (waitqueue_active(q))
1086                 wake_up_interruptible(q);
1087 }
1088
1089 static void start_apic_timer(struct kvm_lapic *apic)
1090 {
1091         ktime_t now;
1092         atomic_set(&apic->lapic_timer.pending, 0);
1093
1094         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1095                 /* lapic timer in oneshot or periodic mode */
1096                 now = apic->lapic_timer.timer.base->get_time();
1097                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1098                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1099
1100                 if (!apic->lapic_timer.period)
1101                         return;
1102                 /*
1103                  * Do not allow the guest to program periodic timers with small
1104                  * interval, since the hrtimers are not throttled by the host
1105                  * scheduler.
1106                  */
1107                 if (apic_lvtt_period(apic)) {
1108                         s64 min_period = min_timer_period_us * 1000LL;
1109
1110                         if (apic->lapic_timer.period < min_period) {
1111                                 pr_info_ratelimited(
1112                                     "kvm: vcpu %i: requested %lld ns "
1113                                     "lapic timer period limited to %lld ns\n",
1114                                     apic->vcpu->vcpu_id,
1115                                     apic->lapic_timer.period, min_period);
1116                                 apic->lapic_timer.period = min_period;
1117                         }
1118                 }
1119
1120                 hrtimer_start(&apic->lapic_timer.timer,
1121                               ktime_add_ns(now, apic->lapic_timer.period),
1122                               HRTIMER_MODE_ABS);
1123
1124                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1125                            PRIx64 ", "
1126                            "timer initial count 0x%x, period %lldns, "
1127                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1128                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1129                            kvm_apic_get_reg(apic, APIC_TMICT),
1130                            apic->lapic_timer.period,
1131                            ktime_to_ns(ktime_add_ns(now,
1132                                         apic->lapic_timer.period)));
1133         } else if (apic_lvtt_tscdeadline(apic)) {
1134                 /* lapic timer in tsc deadline mode */
1135                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1136                 u64 ns = 0;
1137                 struct kvm_vcpu *vcpu = apic->vcpu;
1138                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1139                 unsigned long flags;
1140
1141                 if (unlikely(!tscdeadline || !this_tsc_khz))
1142                         return;
1143
1144                 local_irq_save(flags);
1145
1146                 now = apic->lapic_timer.timer.base->get_time();
1147                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1148                 if (likely(tscdeadline > guest_tsc)) {
1149                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1150                         do_div(ns, this_tsc_khz);
1151                         hrtimer_start(&apic->lapic_timer.timer,
1152                                 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1153                 } else
1154                         apic_timer_expired(apic);
1155
1156                 local_irq_restore(flags);
1157         }
1158 }
1159
1160 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1161 {
1162         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1163
1164         if (apic_lvt_nmi_mode(lvt0_val)) {
1165                 if (!nmi_wd_enabled) {
1166                         apic_debug("Receive NMI setting on APIC_LVT0 "
1167                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1168                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1169                 }
1170         } else if (nmi_wd_enabled)
1171                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1172 }
1173
1174 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1175 {
1176         int ret = 0;
1177
1178         trace_kvm_apic_write(reg, val);
1179
1180         switch (reg) {
1181         case APIC_ID:           /* Local APIC ID */
1182                 if (!apic_x2apic_mode(apic))
1183                         kvm_apic_set_id(apic, val >> 24);
1184                 else
1185                         ret = 1;
1186                 break;
1187
1188         case APIC_TASKPRI:
1189                 report_tpr_access(apic, true);
1190                 apic_set_tpr(apic, val & 0xff);
1191                 break;
1192
1193         case APIC_EOI:
1194                 apic_set_eoi(apic);
1195                 break;
1196
1197         case APIC_LDR:
1198                 if (!apic_x2apic_mode(apic))
1199                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1200                 else
1201                         ret = 1;
1202                 break;
1203
1204         case APIC_DFR:
1205                 if (!apic_x2apic_mode(apic)) {
1206                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1207                         recalculate_apic_map(apic->vcpu->kvm);
1208                 } else
1209                         ret = 1;
1210                 break;
1211
1212         case APIC_SPIV: {
1213                 u32 mask = 0x3ff;
1214                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1215                         mask |= APIC_SPIV_DIRECTED_EOI;
1216                 apic_set_spiv(apic, val & mask);
1217                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1218                         int i;
1219                         u32 lvt_val;
1220
1221                         for (i = 0; i < APIC_LVT_NUM; i++) {
1222                                 lvt_val = kvm_apic_get_reg(apic,
1223                                                        APIC_LVTT + 0x10 * i);
1224                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1225                                              lvt_val | APIC_LVT_MASKED);
1226                         }
1227                         atomic_set(&apic->lapic_timer.pending, 0);
1228
1229                 }
1230                 break;
1231         }
1232         case APIC_ICR:
1233                 /* No delay here, so we always clear the pending bit */
1234                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1235                 apic_send_ipi(apic);
1236                 break;
1237
1238         case APIC_ICR2:
1239                 if (!apic_x2apic_mode(apic))
1240                         val &= 0xff000000;
1241                 apic_set_reg(apic, APIC_ICR2, val);
1242                 break;
1243
1244         case APIC_LVT0:
1245                 apic_manage_nmi_watchdog(apic, val);
1246         case APIC_LVTTHMR:
1247         case APIC_LVTPC:
1248         case APIC_LVT1:
1249         case APIC_LVTERR:
1250                 /* TODO: Check vector */
1251                 if (!kvm_apic_sw_enabled(apic))
1252                         val |= APIC_LVT_MASKED;
1253
1254                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1255                 apic_set_reg(apic, reg, val);
1256
1257                 break;
1258
1259         case APIC_LVTT: {
1260                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1261
1262                 if (apic->lapic_timer.timer_mode != timer_mode) {
1263                         apic->lapic_timer.timer_mode = timer_mode;
1264                         hrtimer_cancel(&apic->lapic_timer.timer);
1265                 }
1266
1267                 if (!kvm_apic_sw_enabled(apic))
1268                         val |= APIC_LVT_MASKED;
1269                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1270                 apic_set_reg(apic, APIC_LVTT, val);
1271                 break;
1272         }
1273
1274         case APIC_TMICT:
1275                 if (apic_lvtt_tscdeadline(apic))
1276                         break;
1277
1278                 hrtimer_cancel(&apic->lapic_timer.timer);
1279                 apic_set_reg(apic, APIC_TMICT, val);
1280                 start_apic_timer(apic);
1281                 break;
1282
1283         case APIC_TDCR:
1284                 if (val & 4)
1285                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1286                 apic_set_reg(apic, APIC_TDCR, val);
1287                 update_divide_count(apic);
1288                 break;
1289
1290         case APIC_ESR:
1291                 if (apic_x2apic_mode(apic) && val != 0) {
1292                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1293                         ret = 1;
1294                 }
1295                 break;
1296
1297         case APIC_SELF_IPI:
1298                 if (apic_x2apic_mode(apic)) {
1299                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1300                 } else
1301                         ret = 1;
1302                 break;
1303         default:
1304                 ret = 1;
1305                 break;
1306         }
1307         if (ret)
1308                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1309         return ret;
1310 }
1311
1312 static int apic_mmio_write(struct kvm_io_device *this,
1313                             gpa_t address, int len, const void *data)
1314 {
1315         struct kvm_lapic *apic = to_lapic(this);
1316         unsigned int offset = address - apic->base_address;
1317         u32 val;
1318
1319         if (!apic_mmio_in_range(apic, address))
1320                 return -EOPNOTSUPP;
1321
1322         /*
1323          * APIC register must be aligned on 128-bits boundary.
1324          * 32/64/128 bits registers must be accessed thru 32 bits.
1325          * Refer SDM 8.4.1
1326          */
1327         if (len != 4 || (offset & 0xf)) {
1328                 /* Don't shout loud, $infamous_os would cause only noise. */
1329                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1330                 return 0;
1331         }
1332
1333         val = *(u32*)data;
1334
1335         /* too common printing */
1336         if (offset != APIC_EOI)
1337                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1338                            "0x%x\n", __func__, offset, len, val);
1339
1340         apic_reg_write(apic, offset & 0xff0, val);
1341
1342         return 0;
1343 }
1344
1345 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1346 {
1347         if (kvm_vcpu_has_lapic(vcpu))
1348                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1349 }
1350 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1351
1352 /* emulate APIC access in a trap manner */
1353 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1354 {
1355         u32 val = 0;
1356
1357         /* hw has done the conditional check and inst decode */
1358         offset &= 0xff0;
1359
1360         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1361
1362         /* TODO: optimize to just emulate side effect w/o one more write */
1363         apic_reg_write(vcpu->arch.apic, offset, val);
1364 }
1365 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1366
1367 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1368 {
1369         struct kvm_lapic *apic = vcpu->arch.apic;
1370
1371         if (!vcpu->arch.apic)
1372                 return;
1373
1374         hrtimer_cancel(&apic->lapic_timer.timer);
1375
1376         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1377                 static_key_slow_dec_deferred(&apic_hw_disabled);
1378
1379         if (!apic->sw_enabled)
1380                 static_key_slow_dec_deferred(&apic_sw_disabled);
1381
1382         if (apic->regs)
1383                 free_page((unsigned long)apic->regs);
1384
1385         kfree(apic);
1386 }
1387
1388 /*
1389  *----------------------------------------------------------------------
1390  * LAPIC interface
1391  *----------------------------------------------------------------------
1392  */
1393
1394 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1395 {
1396         struct kvm_lapic *apic = vcpu->arch.apic;
1397
1398         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1399                         apic_lvtt_period(apic))
1400                 return 0;
1401
1402         return apic->lapic_timer.tscdeadline;
1403 }
1404
1405 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1406 {
1407         struct kvm_lapic *apic = vcpu->arch.apic;
1408
1409         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1410                         apic_lvtt_period(apic))
1411                 return;
1412
1413         hrtimer_cancel(&apic->lapic_timer.timer);
1414         apic->lapic_timer.tscdeadline = data;
1415         start_apic_timer(apic);
1416 }
1417
1418 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1419 {
1420         struct kvm_lapic *apic = vcpu->arch.apic;
1421
1422         if (!kvm_vcpu_has_lapic(vcpu))
1423                 return;
1424
1425         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1426                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1427 }
1428
1429 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1430 {
1431         u64 tpr;
1432
1433         if (!kvm_vcpu_has_lapic(vcpu))
1434                 return 0;
1435
1436         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1437
1438         return (tpr & 0xf0) >> 4;
1439 }
1440
1441 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1442 {
1443         u64 old_value = vcpu->arch.apic_base;
1444         struct kvm_lapic *apic = vcpu->arch.apic;
1445
1446         if (!apic) {
1447                 value |= MSR_IA32_APICBASE_BSP;
1448                 vcpu->arch.apic_base = value;
1449                 return;
1450         }
1451
1452         if (!kvm_vcpu_is_bsp(apic->vcpu))
1453                 value &= ~MSR_IA32_APICBASE_BSP;
1454         vcpu->arch.apic_base = value;
1455
1456         /* update jump label if enable bit changes */
1457         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1458                 if (value & MSR_IA32_APICBASE_ENABLE)
1459                         static_key_slow_dec_deferred(&apic_hw_disabled);
1460                 else
1461                         static_key_slow_inc(&apic_hw_disabled.key);
1462                 recalculate_apic_map(vcpu->kvm);
1463         }
1464
1465         if ((old_value ^ value) & X2APIC_ENABLE) {
1466                 if (value & X2APIC_ENABLE) {
1467                         u32 id = kvm_apic_id(apic);
1468                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1469                         kvm_apic_set_ldr(apic, ldr);
1470                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1471                 } else
1472                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1473         }
1474
1475         apic->base_address = apic->vcpu->arch.apic_base &
1476                              MSR_IA32_APICBASE_BASE;
1477
1478         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1479              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1480                 pr_warn_once("APIC base relocation is unsupported by KVM");
1481
1482         /* with FSB delivery interrupt, we can restart APIC functionality */
1483         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1484                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1485
1486 }
1487
1488 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1489 {
1490         struct kvm_lapic *apic;
1491         int i;
1492
1493         apic_debug("%s\n", __func__);
1494
1495         ASSERT(vcpu);
1496         apic = vcpu->arch.apic;
1497         ASSERT(apic != NULL);
1498
1499         /* Stop the timer in case it's a reset to an active apic */
1500         hrtimer_cancel(&apic->lapic_timer.timer);
1501
1502         kvm_apic_set_id(apic, vcpu->vcpu_id);
1503         kvm_apic_set_version(apic->vcpu);
1504
1505         for (i = 0; i < APIC_LVT_NUM; i++)
1506                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1507         apic->lapic_timer.timer_mode = 0;
1508         apic_set_reg(apic, APIC_LVT0,
1509                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1510
1511         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1512         apic_set_spiv(apic, 0xff);
1513         apic_set_reg(apic, APIC_TASKPRI, 0);
1514         kvm_apic_set_ldr(apic, 0);
1515         apic_set_reg(apic, APIC_ESR, 0);
1516         apic_set_reg(apic, APIC_ICR, 0);
1517         apic_set_reg(apic, APIC_ICR2, 0);
1518         apic_set_reg(apic, APIC_TDCR, 0);
1519         apic_set_reg(apic, APIC_TMICT, 0);
1520         for (i = 0; i < 8; i++) {
1521                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1522                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1523                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1524         }
1525         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1526         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1527         apic->highest_isr_cache = -1;
1528         update_divide_count(apic);
1529         atomic_set(&apic->lapic_timer.pending, 0);
1530         if (kvm_vcpu_is_bsp(vcpu))
1531                 kvm_lapic_set_base(vcpu,
1532                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1533         vcpu->arch.pv_eoi.msr_val = 0;
1534         apic_update_ppr(apic);
1535
1536         vcpu->arch.apic_arb_prio = 0;
1537         vcpu->arch.apic_attention = 0;
1538
1539         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1540                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1541                    vcpu, kvm_apic_id(apic),
1542                    vcpu->arch.apic_base, apic->base_address);
1543 }
1544
1545 /*
1546  *----------------------------------------------------------------------
1547  * timer interface
1548  *----------------------------------------------------------------------
1549  */
1550
1551 static bool lapic_is_periodic(struct kvm_lapic *apic)
1552 {
1553         return apic_lvtt_period(apic);
1554 }
1555
1556 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1557 {
1558         struct kvm_lapic *apic = vcpu->arch.apic;
1559
1560         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1561                         apic_lvt_enabled(apic, APIC_LVTT))
1562                 return atomic_read(&apic->lapic_timer.pending);
1563
1564         return 0;
1565 }
1566
1567 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1568 {
1569         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1570         int vector, mode, trig_mode;
1571
1572         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1573                 vector = reg & APIC_VECTOR_MASK;
1574                 mode = reg & APIC_MODE_MASK;
1575                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1576                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1577                                         NULL);
1578         }
1579         return 0;
1580 }
1581
1582 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1583 {
1584         struct kvm_lapic *apic = vcpu->arch.apic;
1585
1586         if (apic)
1587                 kvm_apic_local_deliver(apic, APIC_LVT0);
1588 }
1589
1590 static const struct kvm_io_device_ops apic_mmio_ops = {
1591         .read     = apic_mmio_read,
1592         .write    = apic_mmio_write,
1593 };
1594
1595 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1596 {
1597         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1598         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1599
1600         apic_timer_expired(apic);
1601
1602         if (lapic_is_periodic(apic)) {
1603                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1604                 return HRTIMER_RESTART;
1605         } else
1606                 return HRTIMER_NORESTART;
1607 }
1608
1609 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1610 {
1611         struct kvm_lapic *apic;
1612
1613         ASSERT(vcpu != NULL);
1614         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1615
1616         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1617         if (!apic)
1618                 goto nomem;
1619
1620         vcpu->arch.apic = apic;
1621
1622         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1623         if (!apic->regs) {
1624                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1625                        vcpu->vcpu_id);
1626                 goto nomem_free_apic;
1627         }
1628         apic->vcpu = vcpu;
1629
1630         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1631                      HRTIMER_MODE_ABS);
1632         apic->lapic_timer.timer.function = apic_timer_fn;
1633
1634         /*
1635          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1636          * thinking that APIC satet has changed.
1637          */
1638         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1639         kvm_lapic_set_base(vcpu,
1640                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1641
1642         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1643         kvm_lapic_reset(vcpu);
1644         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1645
1646         return 0;
1647 nomem_free_apic:
1648         kfree(apic);
1649 nomem:
1650         return -ENOMEM;
1651 }
1652
1653 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1654 {
1655         struct kvm_lapic *apic = vcpu->arch.apic;
1656         int highest_irr;
1657
1658         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1659                 return -1;
1660
1661         apic_update_ppr(apic);
1662         highest_irr = apic_find_highest_irr(apic);
1663         if ((highest_irr == -1) ||
1664             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1665                 return -1;
1666         return highest_irr;
1667 }
1668
1669 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1670 {
1671         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1672         int r = 0;
1673
1674         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1675                 r = 1;
1676         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1677             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1678                 r = 1;
1679         return r;
1680 }
1681
1682 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1683 {
1684         struct kvm_lapic *apic = vcpu->arch.apic;
1685
1686         if (!kvm_vcpu_has_lapic(vcpu))
1687                 return;
1688
1689         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1690                 kvm_apic_local_deliver(apic, APIC_LVTT);
1691                 if (apic_lvtt_tscdeadline(apic))
1692                         apic->lapic_timer.tscdeadline = 0;
1693                 atomic_set(&apic->lapic_timer.pending, 0);
1694         }
1695 }
1696
1697 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1698 {
1699         int vector = kvm_apic_has_interrupt(vcpu);
1700         struct kvm_lapic *apic = vcpu->arch.apic;
1701
1702         if (vector == -1)
1703                 return -1;
1704
1705         /*
1706          * We get here even with APIC virtualization enabled, if doing
1707          * nested virtualization and L1 runs with the "acknowledge interrupt
1708          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1709          * because the process would deliver it through the IDT.
1710          */
1711
1712         apic_set_isr(vector, apic);
1713         apic_update_ppr(apic);
1714         apic_clear_irr(vector, apic);
1715         return vector;
1716 }
1717
1718 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1719                 struct kvm_lapic_state *s)
1720 {
1721         struct kvm_lapic *apic = vcpu->arch.apic;
1722
1723         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1724         /* set SPIV separately to get count of SW disabled APICs right */
1725         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1726         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1727         /* call kvm_apic_set_id() to put apic into apic_map */
1728         kvm_apic_set_id(apic, kvm_apic_id(apic));
1729         kvm_apic_set_version(vcpu);
1730
1731         apic_update_ppr(apic);
1732         hrtimer_cancel(&apic->lapic_timer.timer);
1733         update_divide_count(apic);
1734         start_apic_timer(apic);
1735         apic->irr_pending = true;
1736         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1737                                 1 : count_vectors(apic->regs + APIC_ISR);
1738         apic->highest_isr_cache = -1;
1739         if (kvm_x86_ops->hwapic_irr_update)
1740                 kvm_x86_ops->hwapic_irr_update(vcpu,
1741                                 apic_find_highest_irr(apic));
1742         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1743         kvm_make_request(KVM_REQ_EVENT, vcpu);
1744         kvm_rtc_eoi_tracking_restore_one(vcpu);
1745 }
1746
1747 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1748 {
1749         struct hrtimer *timer;
1750
1751         if (!kvm_vcpu_has_lapic(vcpu))
1752                 return;
1753
1754         timer = &vcpu->arch.apic->lapic_timer.timer;
1755         if (hrtimer_cancel(timer))
1756                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1757 }
1758
1759 /*
1760  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1761  *
1762  * Detect whether guest triggered PV EOI since the
1763  * last entry. If yes, set EOI on guests's behalf.
1764  * Clear PV EOI in guest memory in any case.
1765  */
1766 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1767                                         struct kvm_lapic *apic)
1768 {
1769         bool pending;
1770         int vector;
1771         /*
1772          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1773          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1774          *
1775          * KVM_APIC_PV_EOI_PENDING is unset:
1776          *      -> host disabled PV EOI.
1777          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1778          *      -> host enabled PV EOI, guest did not execute EOI yet.
1779          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1780          *      -> host enabled PV EOI, guest executed EOI.
1781          */
1782         BUG_ON(!pv_eoi_enabled(vcpu));
1783         pending = pv_eoi_get_pending(vcpu);
1784         /*
1785          * Clear pending bit in any case: it will be set again on vmentry.
1786          * While this might not be ideal from performance point of view,
1787          * this makes sure pv eoi is only enabled when we know it's safe.
1788          */
1789         pv_eoi_clr_pending(vcpu);
1790         if (pending)
1791                 return;
1792         vector = apic_set_eoi(apic);
1793         trace_kvm_pv_eoi(apic, vector);
1794 }
1795
1796 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1797 {
1798         u32 data;
1799
1800         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1801                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1802
1803         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1804                 return;
1805
1806         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1807                                 sizeof(u32));
1808
1809         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1810 }
1811
1812 /*
1813  * apic_sync_pv_eoi_to_guest - called before vmentry
1814  *
1815  * Detect whether it's safe to enable PV EOI and
1816  * if yes do so.
1817  */
1818 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1819                                         struct kvm_lapic *apic)
1820 {
1821         if (!pv_eoi_enabled(vcpu) ||
1822             /* IRR set or many bits in ISR: could be nested. */
1823             apic->irr_pending ||
1824             /* Cache not set: could be safe but we don't bother. */
1825             apic->highest_isr_cache == -1 ||
1826             /* Need EOI to update ioapic. */
1827             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1828                 /*
1829                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1830                  * so we need not do anything here.
1831                  */
1832                 return;
1833         }
1834
1835         pv_eoi_set_pending(apic->vcpu);
1836 }
1837
1838 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1839 {
1840         u32 data, tpr;
1841         int max_irr, max_isr;
1842         struct kvm_lapic *apic = vcpu->arch.apic;
1843
1844         apic_sync_pv_eoi_to_guest(vcpu, apic);
1845
1846         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1847                 return;
1848
1849         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1850         max_irr = apic_find_highest_irr(apic);
1851         if (max_irr < 0)
1852                 max_irr = 0;
1853         max_isr = apic_find_highest_isr(apic);
1854         if (max_isr < 0)
1855                 max_isr = 0;
1856         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1857
1858         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1859                                 sizeof(u32));
1860 }
1861
1862 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1863 {
1864         if (vapic_addr) {
1865                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1866                                         &vcpu->arch.apic->vapic_cache,
1867                                         vapic_addr, sizeof(u32)))
1868                         return -EINVAL;
1869                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1870         } else {
1871                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1872         }
1873
1874         vcpu->arch.apic->vapic_addr = vapic_addr;
1875         return 0;
1876 }
1877
1878 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1879 {
1880         struct kvm_lapic *apic = vcpu->arch.apic;
1881         u32 reg = (msr - APIC_BASE_MSR) << 4;
1882
1883         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1884                 return 1;
1885
1886         /* if this is ICR write vector before command */
1887         if (msr == 0x830)
1888                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1889         return apic_reg_write(apic, reg, (u32)data);
1890 }
1891
1892 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1893 {
1894         struct kvm_lapic *apic = vcpu->arch.apic;
1895         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1896
1897         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1898                 return 1;
1899
1900         if (apic_reg_read(apic, reg, 4, &low))
1901                 return 1;
1902         if (msr == 0x830)
1903                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1904
1905         *data = (((u64)high) << 32) | low;
1906
1907         return 0;
1908 }
1909
1910 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1911 {
1912         struct kvm_lapic *apic = vcpu->arch.apic;
1913
1914         if (!kvm_vcpu_has_lapic(vcpu))
1915                 return 1;
1916
1917         /* if this is ICR write vector before command */
1918         if (reg == APIC_ICR)
1919                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1920         return apic_reg_write(apic, reg, (u32)data);
1921 }
1922
1923 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1924 {
1925         struct kvm_lapic *apic = vcpu->arch.apic;
1926         u32 low, high = 0;
1927
1928         if (!kvm_vcpu_has_lapic(vcpu))
1929                 return 1;
1930
1931         if (apic_reg_read(apic, reg, 4, &low))
1932                 return 1;
1933         if (reg == APIC_ICR)
1934                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1935
1936         *data = (((u64)high) << 32) | low;
1937
1938         return 0;
1939 }
1940
1941 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1942 {
1943         u64 addr = data & ~KVM_MSR_ENABLED;
1944         if (!IS_ALIGNED(addr, 4))
1945                 return 1;
1946
1947         vcpu->arch.pv_eoi.msr_val = data;
1948         if (!pv_eoi_enabled(vcpu))
1949                 return 0;
1950         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1951                                          addr, sizeof(u8));
1952 }
1953
1954 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1955 {
1956         struct kvm_lapic *apic = vcpu->arch.apic;
1957         unsigned int sipi_vector;
1958         unsigned long pe;
1959
1960         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1961                 return;
1962
1963         pe = xchg(&apic->pending_events, 0);
1964
1965         if (test_bit(KVM_APIC_INIT, &pe)) {
1966                 kvm_lapic_reset(vcpu);
1967                 kvm_vcpu_reset(vcpu);
1968                 if (kvm_vcpu_is_bsp(apic->vcpu))
1969                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1970                 else
1971                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1972         }
1973         if (test_bit(KVM_APIC_SIPI, &pe) &&
1974             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1975                 /* evaluate pending_events before reading the vector */
1976                 smp_rmb();
1977                 sipi_vector = apic->sipi_vector;
1978                 apic_debug("vcpu %d received sipi with vector # %x\n",
1979                          vcpu->vcpu_id, sipi_vector);
1980                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1981                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1982         }
1983 }
1984
1985 void kvm_lapic_init(void)
1986 {
1987         /* do not patch jump label more than once per second */
1988         jump_label_rate_limit(&apic_hw_disabled, HZ);
1989         jump_label_rate_limit(&apic_sw_disabled, HZ);
1990 }