arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define VEC_POS(v) ((v) & (32 - 1))
  72 #define REG_POS(v) (((v) >> 5) << 4)
  73
  74 static unsigned int min_timer_period_us = 500;
  75 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
  76
  77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  78 {
  79         *((u32 *) (apic->regs + reg_off)) = val;
  80 }
  81
  82 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  83 {
  84         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  88 {
  89         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  90 }
  91
  92 static inline int apic_test_vector(int vec, void *bitmap)
  93 {
  94         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  95 }
  96
  97 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  98 {
  99         struct kvm_lapic *apic = vcpu->arch.apic;
 100
 101         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
 102                 apic_test_vector(vector, apic->regs + APIC_IRR);
 103 }
 104
 105 static inline void apic_set_vector(int vec, void *bitmap)
 106 {
 107         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline void apic_clear_vector(int vec, void *bitmap)
 111 {
 112         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 116 {
 117         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 118 }
 119
 120 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 121 {
 122         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 123 }
 124
 125 struct static_key_deferred apic_hw_disabled __read_mostly;
 126 struct static_key_deferred apic_sw_disabled __read_mostly;
 127
 128 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 129 {
 130         if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
 131                 if (val & APIC_SPIV_APIC_ENABLED)
 132                         static_key_slow_dec_deferred(&apic_sw_disabled);
 133                 else
 134                         static_key_slow_inc(&apic_sw_disabled.key);
 135         }
 136         apic_set_reg(apic, APIC_SPIV, val);
 137 }
 138
 139 static inline int apic_enabled(struct kvm_lapic *apic)
 140 {
 141         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 142 }
 143
 144 #define LVT_MASK        \
 145         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 146
 147 #define LINT_MASK       \
 148         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 149          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 150
 151 static inline int kvm_apic_id(struct kvm_lapic *apic)
 152 {
 153         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 154 }
 155
 156 static void recalculate_apic_map(struct kvm *kvm)
 157 {
 158         struct kvm_apic_map *new, *old = NULL;
 159         struct kvm_vcpu *vcpu;
 160         int i;
 161
 162         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 163
 164         mutex_lock(&kvm->arch.apic_map_lock);
 165
 166         if (!new)
 167                 goto out;
 168
 169         new->ldr_bits = 8;
 170         /* flat mode is default */
 171         new->cid_shift = 8;
 172         new->cid_mask = 0;
 173         new->lid_mask = 0xff;
 174
 175         kvm_for_each_vcpu(i, vcpu, kvm) {
 176                 struct kvm_lapic *apic = vcpu->arch.apic;
 177                 u16 cid, lid;
 178                 u32 ldr;
 179
 180                 if (!kvm_apic_present(vcpu))
 181                         continue;
 182
 183                 /*
 184                  * All APICs have to be configured in the same mode by an OS.
 185                  * We take advatage of this while building logical id loockup
 186                  * table. After reset APICs are in xapic/flat mode, so if we
 187                  * find apic with different setting we assume this is the mode
 188                  * OS wants all apics to be in; build lookup table accordingly.
 189                  */
 190                 if (apic_x2apic_mode(apic)) {
 191                         new->ldr_bits = 32;
 192                         new->cid_shift = 16;
 193                         new->cid_mask = new->lid_mask = 0xffff;
 194                 } else if (kvm_apic_sw_enabled(apic) &&
 195                                 !new->cid_mask /* flat mode */ &&
 196                                 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
 197                         new->cid_shift = 4;
 198                         new->cid_mask = 0xf;
 199                         new->lid_mask = 0xf;
 200                 }
 201
 202                 new->phys_map[kvm_apic_id(apic)] = apic;
 203
 204                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 205                 cid = apic_cluster_id(new, ldr);
 206                 lid = apic_logical_id(new, ldr);
 207
 208                 if (lid)
 209                         new->logical_map[cid][ffs(lid) - 1] = apic;
 210         }
 211 out:
 212         old = rcu_dereference_protected(kvm->arch.apic_map,
 213                         lockdep_is_held(&kvm->arch.apic_map_lock));
 214         rcu_assign_pointer(kvm->arch.apic_map, new);
 215         mutex_unlock(&kvm->arch.apic_map_lock);
 216
 217         if (old)
 218                 kfree_rcu(old, rcu);
 219
 220         kvm_vcpu_request_scan_ioapic(kvm);
 221 }
 222
 223 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 224 {
 225         apic_set_reg(apic, APIC_ID, id << 24);
 226         recalculate_apic_map(apic->vcpu->kvm);
 227 }
 228
 229 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 230 {
 231         apic_set_reg(apic, APIC_LDR, id);
 232         recalculate_apic_map(apic->vcpu->kvm);
 233 }
 234
 235 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 236 {
 237         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 238 }
 239
 240 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 241 {
 242         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 243 }
 244
 245 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 246 {
 247         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 248                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 249 }
 250
 251 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 252 {
 253         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 254                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 255 }
 256
 257 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 258 {
 259         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 260                 apic->lapic_timer.timer_mode_mask) ==
 261                         APIC_LVT_TIMER_TSCDEADLINE);
 262 }
 263
 264 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 265 {
 266         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 267 }
 268
 269 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 270 {
 271         struct kvm_lapic *apic = vcpu->arch.apic;
 272         struct kvm_cpuid_entry2 *feat;
 273         u32 v = APIC_VERSION;
 274
 275         if (!kvm_vcpu_has_lapic(vcpu))
 276                 return;
 277
 278         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 279         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 280                 v |= APIC_LVR_DIRECTED_EOI;
 281         apic_set_reg(apic, APIC_LVR, v);
 282 }
 283
 284 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 285         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 286         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 287         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 288         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 289         LVT_MASK                /* LVTERR */
 290 };
 291
 292 static int find_highest_vector(void *bitmap)
 293 {
 294         int vec;
 295         u32 *reg;
 296
 297         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 298              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 299                 reg = bitmap + REG_POS(vec);
 300                 if (*reg)
 301                         return fls(*reg) - 1 + vec;
 302         }
 303
 304         return -1;
 305 }
 306
 307 static u8 count_vectors(void *bitmap)
 308 {
 309         int vec;
 310         u32 *reg;
 311         u8 count = 0;
 312
 313         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 314                 reg = bitmap + REG_POS(vec);
 315                 count += hweight32(*reg);
 316         }
 317
 318         return count;
 319 }
 320
 321 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 322 {
 323         u32 i, pir_val;
 324         struct kvm_lapic *apic = vcpu->arch.apic;
 325
 326         for (i = 0; i <= 7; i++) {
 327                 pir_val = xchg(&pir[i], 0);
 328                 if (pir_val)
 329                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 330         }
 331 }
 332 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 333
 334 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 335 {
 336         apic->irr_pending = true;
 337         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 338 }
 339
 340 static inline int apic_search_irr(struct kvm_lapic *apic)
 341 {
 342         return find_highest_vector(apic->regs + APIC_IRR);
 343 }
 344
 345 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 346 {
 347         int result;
 348
 349         /*
 350          * Note that irr_pending is just a hint. It will be always
 351          * true with virtual interrupt delivery enabled.
 352          */
 353         if (!apic->irr_pending)
 354                 return -1;
 355
 356         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 357         result = apic_search_irr(apic);
 358         ASSERT(result == -1 || result >= 16);
 359
 360         return result;
 361 }
 362
 363 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 364 {
 365         apic->irr_pending = false;
 366         apic_clear_vector(vec, apic->regs + APIC_IRR);
 367         if (apic_search_irr(apic) != -1)
 368                 apic->irr_pending = true;
 369 }
 370
 371 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 372 {
 373         if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 374                 ++apic->isr_count;
 375         BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 376         /*
 377          * ISR (in service register) bit is set when injecting an interrupt.
 378          * The highest vector is injected. Thus the latest bit set matches
 379          * the highest bit in ISR.
 380          */
 381         apic->highest_isr_cache = vec;
 382 }
 383
 384 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 385 {
 386         if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 387                 --apic->isr_count;
 388         BUG_ON(apic->isr_count < 0);
 389         apic->highest_isr_cache = -1;
 390 }
 391
 392 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 393 {
 394         int highest_irr;
 395
 396         /* This may race with setting of irr in __apic_accept_irq() and
 397          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 398          * will cause vmexit immediately and the value will be recalculated
 399          * on the next vmentry.
 400          */
 401         if (!kvm_vcpu_has_lapic(vcpu))
 402                 return 0;
 403         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 404
 405         return highest_irr;
 406 }
 407
 408 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 409                              int vector, int level, int trig_mode,
 410                              unsigned long *dest_map);
 411
 412 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 413                 unsigned long *dest_map)
 414 {
 415         struct kvm_lapic *apic = vcpu->arch.apic;
 416
 417         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 418                         irq->level, irq->trig_mode, dest_map);
 419 }
 420
 421 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 422 {
 423
 424         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 425                                       sizeof(val));
 426 }
 427
 428 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 429 {
 430
 431         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 432                                       sizeof(*val));
 433 }
 434
 435 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 436 {
 437         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 438 }
 439
 440 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 441 {
 442         u8 val;
 443         if (pv_eoi_get_user(vcpu, &val) < 0)
 444                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 445                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 446         return val & 0x1;
 447 }
 448
 449 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 450 {
 451         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 452                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 453                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 454                 return;
 455         }
 456         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 457 }
 458
 459 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 460 {
 461         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 462                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 463                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 464                 return;
 465         }
 466         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 467 }
 468
 469 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 470 {
 471         int result;
 472
 473         /* Note that isr_count is always 1 with vid enabled */
 474         if (!apic->isr_count)
 475                 return -1;
 476         if (likely(apic->highest_isr_cache != -1))
 477                 return apic->highest_isr_cache;
 478
 479         result = find_highest_vector(apic->regs + APIC_ISR);
 480         ASSERT(result == -1 || result >= 16);
 481
 482         return result;
 483 }
 484
 485 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 486 {
 487         struct kvm_lapic *apic = vcpu->arch.apic;
 488         int i;
 489
 490         for (i = 0; i < 8; i++)
 491                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 492 }
 493
 494 static void apic_update_ppr(struct kvm_lapic *apic)
 495 {
 496         u32 tpr, isrv, ppr, old_ppr;
 497         int isr;
 498
 499         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 500         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 501         isr = apic_find_highest_isr(apic);
 502         isrv = (isr != -1) ? isr : 0;
 503
 504         if ((tpr & 0xf0) >= (isrv & 0xf0))
 505                 ppr = tpr & 0xff;
 506         else
 507                 ppr = isrv & 0xf0;
 508
 509         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 510                    apic, ppr, isr, isrv);
 511
 512         if (old_ppr != ppr) {
 513                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 514                 if (ppr < old_ppr)
 515                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 516         }
 517 }
 518
 519 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 520 {
 521         apic_set_reg(apic, APIC_TASKPRI, tpr);
 522         apic_update_ppr(apic);
 523 }
 524
 525 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 526 {
 527         return dest == 0xff || kvm_apic_id(apic) == dest;
 528 }
 529
 530 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 531 {
 532         int result = 0;
 533         u32 logical_id;
 534
 535         if (apic_x2apic_mode(apic)) {
 536                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 537                 return logical_id & mda;
 538         }
 539
 540         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 541
 542         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 543         case APIC_DFR_FLAT:
 544                 if (logical_id & mda)
 545                         result = 1;
 546                 break;
 547         case APIC_DFR_CLUSTER:
 548                 if (((logical_id >> 4) == (mda >> 0x4))
 549                     && (logical_id & mda & 0xf))
 550                         result = 1;
 551                 break;
 552         default:
 553                 apic_debug("Bad DFR vcpu %d: %08x\n",
 554                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 555                 break;
 556         }
 557
 558         return result;
 559 }
 560
 561 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 562                            int short_hand, int dest, int dest_mode)
 563 {
 564         int result = 0;
 565         struct kvm_lapic *target = vcpu->arch.apic;
 566
 567         apic_debug("target %p, source %p, dest 0x%x, "
 568                    "dest_mode 0x%x, short_hand 0x%x\n",
 569                    target, source, dest, dest_mode, short_hand);
 570
 571         ASSERT(target);
 572         switch (short_hand) {
 573         case APIC_DEST_NOSHORT:
 574                 if (dest_mode == 0)
 575                         /* Physical mode. */
 576                         result = kvm_apic_match_physical_addr(target, dest);
 577                 else
 578                         /* Logical mode. */
 579                         result = kvm_apic_match_logical_addr(target, dest);
 580                 break;
 581         case APIC_DEST_SELF:
 582                 result = (target == source);
 583                 break;
 584         case APIC_DEST_ALLINC:
 585                 result = 1;
 586                 break;
 587         case APIC_DEST_ALLBUT:
 588                 result = (target != source);
 589                 break;
 590         default:
 591                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 592                            short_hand);
 593                 break;
 594         }
 595
 596         return result;
 597 }
 598
 599 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 600                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 601 {
 602         struct kvm_apic_map *map;
 603         unsigned long bitmap = 1;
 604         struct kvm_lapic **dst;
 605         int i;
 606         bool ret = false;
 607
 608         *r = -1;
 609
 610         if (irq->shorthand == APIC_DEST_SELF) {
 611                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 612                 return true;
 613         }
 614
 615         if (irq->shorthand)
 616                 return false;
 617
 618         rcu_read_lock();
 619         map = rcu_dereference(kvm->arch.apic_map);
 620
 621         if (!map)
 622                 goto out;
 623
 624         if (irq->dest_mode == 0) { /* physical mode */
 625                 if (irq->delivery_mode == APIC_DM_LOWEST ||
 626                                 irq->dest_id == 0xff)
 627                         goto out;
 628                 dst = &map->phys_map[irq->dest_id & 0xff];
 629         } else {
 630                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 631
 632                 dst = map->logical_map[apic_cluster_id(map, mda)];
 633
 634                 bitmap = apic_logical_id(map, mda);
 635
 636                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 637                         int l = -1;
 638                         for_each_set_bit(i, &bitmap, 16) {
 639                                 if (!dst[i])
 640                                         continue;
 641                                 if (l < 0)
 642                                         l = i;
 643                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 644                                         l = i;
 645                         }
 646
 647                         bitmap = (l >= 0) ? 1 << l : 0;
 648                 }
 649         }
 650
 651         for_each_set_bit(i, &bitmap, 16) {
 652                 if (!dst[i])
 653                         continue;
 654                 if (*r < 0)
 655                         *r = 0;
 656                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 657         }
 658
 659         ret = true;
 660 out:
 661         rcu_read_unlock();
 662         return ret;
 663 }
 664
 665 /*
 666  * Add a pending IRQ into lapic.
 667  * Return 1 if successfully added and 0 if discarded.
 668  */
 669 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 670                              int vector, int level, int trig_mode,
 671                              unsigned long *dest_map)
 672 {
 673         int result = 0;
 674         struct kvm_vcpu *vcpu = apic->vcpu;
 675
 676         switch (delivery_mode) {
 677         case APIC_DM_LOWEST:
 678                 vcpu->arch.apic_arb_prio++;
 679         case APIC_DM_FIXED:
 680                 /* FIXME add logic for vcpu on reset */
 681                 if (unlikely(!apic_enabled(apic)))
 682                         break;
 683
 684                 if (dest_map)
 685                         __set_bit(vcpu->vcpu_id, dest_map);
 686
 687                 if (kvm_x86_ops->deliver_posted_interrupt) {
 688                         result = 1;
 689                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 690                 } else {
 691                         result = !apic_test_and_set_irr(vector, apic);
 692
 693                         if (!result) {
 694                                 if (trig_mode)
 695                                         apic_debug("level trig mode repeatedly "
 696                                                 "for vector %d", vector);
 697                                 goto out;
 698                         }
 699
 700                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 701                         kvm_vcpu_kick(vcpu);
 702                 }
 703 out:
 704                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 705                                 trig_mode, vector, !result);
 706                 break;
 707
 708         case APIC_DM_REMRD:
 709                 apic_debug("Ignoring delivery mode 3\n");
 710                 break;
 711
 712         case APIC_DM_SMI:
 713                 apic_debug("Ignoring guest SMI\n");
 714                 break;
 715
 716         case APIC_DM_NMI:
 717                 result = 1;
 718                 kvm_inject_nmi(vcpu);
 719                 kvm_vcpu_kick(vcpu);
 720                 break;
 721
 722         case APIC_DM_INIT:
 723                 if (!trig_mode || level) {
 724                         result = 1;
 725                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 726                         apic->pending_events = (1UL << KVM_APIC_INIT);
 727                         /* make sure pending_events is visible before sending
 728                          * the request */
 729                         smp_wmb();
 730                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 731                         kvm_vcpu_kick(vcpu);
 732                 } else {
 733                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 734                                    vcpu->vcpu_id);
 735                 }
 736                 break;
 737
 738         case APIC_DM_STARTUP:
 739                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 740                            vcpu->vcpu_id, vector);
 741                 result = 1;
 742                 apic->sipi_vector = vector;
 743                 /* make sure sipi_vector is visible for the receiver */
 744                 smp_wmb();
 745                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 746                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 747                 kvm_vcpu_kick(vcpu);
 748                 break;
 749
 750         case APIC_DM_EXTINT:
 751                 /*
 752                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 753                  * before NMI watchdog was enabled. Already handled by
 754                  * kvm_apic_accept_pic_intr().
 755                  */
 756                 break;
 757
 758         default:
 759                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 760                        delivery_mode);
 761                 break;
 762         }
 763         return result;
 764 }
 765
 766 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 767 {
 768         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 769 }
 770
 771 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 772 {
 773         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 774             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 775                 int trigger_mode;
 776                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 777                         trigger_mode = IOAPIC_LEVEL_TRIG;
 778                 else
 779                         trigger_mode = IOAPIC_EDGE_TRIG;
 780                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 781         }
 782 }
 783
 784 static int apic_set_eoi(struct kvm_lapic *apic)
 785 {
 786         int vector = apic_find_highest_isr(apic);
 787
 788         trace_kvm_eoi(apic, vector);
 789
 790         /*
 791          * Not every write EOI will has corresponding ISR,
 792          * one example is when Kernel check timer on setup_IO_APIC
 793          */
 794         if (vector == -1)
 795                 return vector;
 796
 797         apic_clear_isr(vector, apic);
 798         apic_update_ppr(apic);
 799
 800         kvm_ioapic_send_eoi(apic, vector);
 801         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 802         return vector;
 803 }
 804
 805 /*
 806  * this interface assumes a trap-like exit, which has already finished
 807  * desired side effect including vISR and vPPR update.
 808  */
 809 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 810 {
 811         struct kvm_lapic *apic = vcpu->arch.apic;
 812
 813         trace_kvm_eoi(apic, vector);
 814
 815         kvm_ioapic_send_eoi(apic, vector);
 816         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 817 }
 818 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 819
 820 static void apic_send_ipi(struct kvm_lapic *apic)
 821 {
 822         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 823         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 824         struct kvm_lapic_irq irq;
 825
 826         irq.vector = icr_low & APIC_VECTOR_MASK;
 827         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 828         irq.dest_mode = icr_low & APIC_DEST_MASK;
 829         irq.level = icr_low & APIC_INT_ASSERT;
 830         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 831         irq.shorthand = icr_low & APIC_SHORT_MASK;
 832         if (apic_x2apic_mode(apic))
 833                 irq.dest_id = icr_high;
 834         else
 835                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 836
 837         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 838
 839         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 840                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 841                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 842                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 843                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 844                    irq.vector);
 845
 846         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 847 }
 848
 849 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 850 {
 851         ktime_t remaining;
 852         s64 ns;
 853         u32 tmcct;
 854
 855         ASSERT(apic != NULL);
 856
 857         /* if initial count is 0, current count should also be 0 */
 858         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 859                 apic->lapic_timer.period == 0)
 860                 return 0;
 861
 862         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 863         if (ktime_to_ns(remaining) < 0)
 864                 remaining = ktime_set(0, 0);
 865
 866         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 867         tmcct = div64_u64(ns,
 868                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 869
 870         return tmcct;
 871 }
 872
 873 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 874 {
 875         struct kvm_vcpu *vcpu = apic->vcpu;
 876         struct kvm_run *run = vcpu->run;
 877
 878         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 879         run->tpr_access.rip = kvm_rip_read(vcpu);
 880         run->tpr_access.is_write = write;
 881 }
 882
 883 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 884 {
 885         if (apic->vcpu->arch.tpr_access_reporting)
 886                 __report_tpr_access(apic, write);
 887 }
 888
 889 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 890 {
 891         u32 val = 0;
 892
 893         if (offset >= LAPIC_MMIO_LENGTH)
 894                 return 0;
 895
 896         switch (offset) {
 897         case APIC_ID:
 898                 if (apic_x2apic_mode(apic))
 899                         val = kvm_apic_id(apic);
 900                 else
 901                         val = kvm_apic_id(apic) << 24;
 902                 break;
 903         case APIC_ARBPRI:
 904                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 905                 break;
 906
 907         case APIC_TMCCT:        /* Timer CCR */
 908                 if (apic_lvtt_tscdeadline(apic))
 909                         return 0;
 910
 911                 val = apic_get_tmcct(apic);
 912                 break;
 913         case APIC_PROCPRI:
 914                 apic_update_ppr(apic);
 915                 val = kvm_apic_get_reg(apic, offset);
 916                 break;
 917         case APIC_TASKPRI:
 918                 report_tpr_access(apic, false);
 919                 /* fall thru */
 920         default:
 921                 val = kvm_apic_get_reg(apic, offset);
 922                 break;
 923         }
 924
 925         return val;
 926 }
 927
 928 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 929 {
 930         return container_of(dev, struct kvm_lapic, dev);
 931 }
 932
 933 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 934                 void *data)
 935 {
 936         unsigned char alignment = offset & 0xf;
 937         u32 result;
 938         /* this bitmask has a bit cleared for each reserved register */
 939         static const u64 rmask = 0x43ff01ffffffe70cULL;
 940
 941         if ((alignment + len) > 4) {
 942                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 943                            offset, len);
 944                 return 1;
 945         }
 946
 947         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 948                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 949                            offset);
 950                 return 1;
 951         }
 952
 953         result = __apic_read(apic, offset & ~0xf);
 954
 955         trace_kvm_apic_read(offset, result);
 956
 957         switch (len) {
 958         case 1:
 959         case 2:
 960         case 4:
 961                 memcpy(data, (char *)&result + alignment, len);
 962                 break;
 963         default:
 964                 printk(KERN_ERR "Local APIC read with len = %x, "
 965                        "should be 1,2, or 4 instead\n", len);
 966                 break;
 967         }
 968         return 0;
 969 }
 970
 971 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 972 {
 973         return kvm_apic_hw_enabled(apic) &&
 974             addr >= apic->base_address &&
 975             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 976 }
 977
 978 static int apic_mmio_read(struct kvm_io_device *this,
 979                            gpa_t address, int len, void *data)
 980 {
 981         struct kvm_lapic *apic = to_lapic(this);
 982         u32 offset = address - apic->base_address;
 983
 984         if (!apic_mmio_in_range(apic, address))
 985                 return -EOPNOTSUPP;
 986
 987         apic_reg_read(apic, offset, len, data);
 988
 989         return 0;
 990 }
 991
 992 static void update_divide_count(struct kvm_lapic *apic)
 993 {
 994         u32 tmp1, tmp2, tdcr;
 995
 996         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
 997         tmp1 = tdcr & 0xf;
 998         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 999         apic->divide_count = 0x1 << (tmp2 & 0x7);
1000
1001         apic_debug("timer divide count is 0x%x\n",
1002                                    apic->divide_count);
1003 }
1004
1005 static void start_apic_timer(struct kvm_lapic *apic)
1006 {
1007         ktime_t now;
1008         atomic_set(&apic->lapic_timer.pending, 0);
1009
1010         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1011                 /* lapic timer in oneshot or periodic mode */
1012                 now = apic->lapic_timer.timer.base->get_time();
1013                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1014                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1015
1016                 if (!apic->lapic_timer.period)
1017                         return;
1018                 /*
1019                  * Do not allow the guest to program periodic timers with small
1020                  * interval, since the hrtimers are not throttled by the host
1021                  * scheduler.
1022                  */
1023                 if (apic_lvtt_period(apic)) {
1024                         s64 min_period = min_timer_period_us * 1000LL;
1025
1026                         if (apic->lapic_timer.period < min_period) {
1027                                 pr_info_ratelimited(
1028                                     "kvm: vcpu %i: requested %lld ns "
1029                                     "lapic timer period limited to %lld ns\n",
1030                                     apic->vcpu->vcpu_id,
1031                                     apic->lapic_timer.period, min_period);
1032                                 apic->lapic_timer.period = min_period;
1033                         }
1034                 }
1035
1036                 hrtimer_start(&apic->lapic_timer.timer,
1037                               ktime_add_ns(now, apic->lapic_timer.period),
1038                               HRTIMER_MODE_ABS);
1039
1040                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1041                            PRIx64 ", "
1042                            "timer initial count 0x%x, period %lldns, "
1043                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1044                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1045                            kvm_apic_get_reg(apic, APIC_TMICT),
1046                            apic->lapic_timer.period,
1047                            ktime_to_ns(ktime_add_ns(now,
1048                                         apic->lapic_timer.period)));
1049         } else if (apic_lvtt_tscdeadline(apic)) {
1050                 /* lapic timer in tsc deadline mode */
1051                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1052                 u64 ns = 0;
1053                 struct kvm_vcpu *vcpu = apic->vcpu;
1054                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1055                 unsigned long flags;
1056
1057                 if (unlikely(!tscdeadline || !this_tsc_khz))
1058                         return;
1059
1060                 local_irq_save(flags);
1061
1062                 now = apic->lapic_timer.timer.base->get_time();
1063                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1064                 if (likely(tscdeadline > guest_tsc)) {
1065                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1066                         do_div(ns, this_tsc_khz);
1067                 }
1068                 hrtimer_start(&apic->lapic_timer.timer,
1069                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1070
1071                 local_irq_restore(flags);
1072         }
1073 }
1074
1075 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1076 {
1077         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1078
1079         if (apic_lvt_nmi_mode(lvt0_val)) {
1080                 if (!nmi_wd_enabled) {
1081                         apic_debug("Receive NMI setting on APIC_LVT0 "
1082                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1083                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1084                 }
1085         } else if (nmi_wd_enabled)
1086                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1087 }
1088
1089 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1090 {
1091         int ret = 0;
1092
1093         trace_kvm_apic_write(reg, val);
1094
1095         switch (reg) {
1096         case APIC_ID:           /* Local APIC ID */
1097                 if (!apic_x2apic_mode(apic))
1098                         kvm_apic_set_id(apic, val >> 24);
1099                 else
1100                         ret = 1;
1101                 break;
1102
1103         case APIC_TASKPRI:
1104                 report_tpr_access(apic, true);
1105                 apic_set_tpr(apic, val & 0xff);
1106                 break;
1107
1108         case APIC_EOI:
1109                 apic_set_eoi(apic);
1110                 break;
1111
1112         case APIC_LDR:
1113                 if (!apic_x2apic_mode(apic))
1114                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1115                 else
1116                         ret = 1;
1117                 break;
1118
1119         case APIC_DFR:
1120                 if (!apic_x2apic_mode(apic)) {
1121                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1122                         recalculate_apic_map(apic->vcpu->kvm);
1123                 } else
1124                         ret = 1;
1125                 break;
1126
1127         case APIC_SPIV: {
1128                 u32 mask = 0x3ff;
1129                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1130                         mask |= APIC_SPIV_DIRECTED_EOI;
1131                 apic_set_spiv(apic, val & mask);
1132                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1133                         int i;
1134                         u32 lvt_val;
1135
1136                         for (i = 0; i < APIC_LVT_NUM; i++) {
1137                                 lvt_val = kvm_apic_get_reg(apic,
1138                                                        APIC_LVTT + 0x10 * i);
1139                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1140                                              lvt_val | APIC_LVT_MASKED);
1141                         }
1142                         atomic_set(&apic->lapic_timer.pending, 0);
1143
1144                 }
1145                 break;
1146         }
1147         case APIC_ICR:
1148                 /* No delay here, so we always clear the pending bit */
1149                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1150                 apic_send_ipi(apic);
1151                 break;
1152
1153         case APIC_ICR2:
1154                 if (!apic_x2apic_mode(apic))
1155                         val &= 0xff000000;
1156                 apic_set_reg(apic, APIC_ICR2, val);
1157                 break;
1158
1159         case APIC_LVT0:
1160                 apic_manage_nmi_watchdog(apic, val);
1161         case APIC_LVTTHMR:
1162         case APIC_LVTPC:
1163         case APIC_LVT1:
1164         case APIC_LVTERR:
1165                 /* TODO: Check vector */
1166                 if (!kvm_apic_sw_enabled(apic))
1167                         val |= APIC_LVT_MASKED;
1168
1169                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1170                 apic_set_reg(apic, reg, val);
1171
1172                 break;
1173
1174         case APIC_LVTT:
1175                 if ((kvm_apic_get_reg(apic, APIC_LVTT) &
1176                     apic->lapic_timer.timer_mode_mask) !=
1177                    (val & apic->lapic_timer.timer_mode_mask))
1178                         hrtimer_cancel(&apic->lapic_timer.timer);
1179
1180                 if (!kvm_apic_sw_enabled(apic))
1181                         val |= APIC_LVT_MASKED;
1182                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1183                 apic_set_reg(apic, APIC_LVTT, val);
1184                 break;
1185
1186         case APIC_TMICT:
1187                 if (apic_lvtt_tscdeadline(apic))
1188                         break;
1189
1190                 hrtimer_cancel(&apic->lapic_timer.timer);
1191                 apic_set_reg(apic, APIC_TMICT, val);
1192                 start_apic_timer(apic);
1193                 break;
1194
1195         case APIC_TDCR:
1196                 if (val & 4)
1197                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1198                 apic_set_reg(apic, APIC_TDCR, val);
1199                 update_divide_count(apic);
1200                 break;
1201
1202         case APIC_ESR:
1203                 if (apic_x2apic_mode(apic) && val != 0) {
1204                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1205                         ret = 1;
1206                 }
1207                 break;
1208
1209         case APIC_SELF_IPI:
1210                 if (apic_x2apic_mode(apic)) {
1211                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1212                 } else
1213                         ret = 1;
1214                 break;
1215         default:
1216                 ret = 1;
1217                 break;
1218         }
1219         if (ret)
1220                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1221         return ret;
1222 }
1223
1224 static int apic_mmio_write(struct kvm_io_device *this,
1225                             gpa_t address, int len, const void *data)
1226 {
1227         struct kvm_lapic *apic = to_lapic(this);
1228         unsigned int offset = address - apic->base_address;
1229         u32 val;
1230
1231         if (!apic_mmio_in_range(apic, address))
1232                 return -EOPNOTSUPP;
1233
1234         /*
1235          * APIC register must be aligned on 128-bits boundary.
1236          * 32/64/128 bits registers must be accessed thru 32 bits.
1237          * Refer SDM 8.4.1
1238          */
1239         if (len != 4 || (offset & 0xf)) {
1240                 /* Don't shout loud, $infamous_os would cause only noise. */
1241                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1242                 return 0;
1243         }
1244
1245         val = *(u32*)data;
1246
1247         /* too common printing */
1248         if (offset != APIC_EOI)
1249                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1250                            "0x%x\n", __func__, offset, len, val);
1251
1252         apic_reg_write(apic, offset & 0xff0, val);
1253
1254         return 0;
1255 }
1256
1257 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1258 {
1259         if (kvm_vcpu_has_lapic(vcpu))
1260                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1261 }
1262 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1263
1264 /* emulate APIC access in a trap manner */
1265 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1266 {
1267         u32 val = 0;
1268
1269         /* hw has done the conditional check and inst decode */
1270         offset &= 0xff0;
1271
1272         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1273
1274         /* TODO: optimize to just emulate side effect w/o one more write */
1275         apic_reg_write(vcpu->arch.apic, offset, val);
1276 }
1277 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1278
1279 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1280 {
1281         struct kvm_lapic *apic = vcpu->arch.apic;
1282
1283         if (!vcpu->arch.apic)
1284                 return;
1285
1286         hrtimer_cancel(&apic->lapic_timer.timer);
1287
1288         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1289                 static_key_slow_dec_deferred(&apic_hw_disabled);
1290
1291         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
1292                 static_key_slow_dec_deferred(&apic_sw_disabled);
1293
1294         if (apic->regs)
1295                 free_page((unsigned long)apic->regs);
1296
1297         kfree(apic);
1298 }
1299
1300 /*
1301  *----------------------------------------------------------------------
1302  * LAPIC interface
1303  *----------------------------------------------------------------------
1304  */
1305
1306 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1307 {
1308         struct kvm_lapic *apic = vcpu->arch.apic;
1309
1310         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1311                         apic_lvtt_period(apic))
1312                 return 0;
1313
1314         return apic->lapic_timer.tscdeadline;
1315 }
1316
1317 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1318 {
1319         struct kvm_lapic *apic = vcpu->arch.apic;
1320
1321         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1322                         apic_lvtt_period(apic))
1323                 return;
1324
1325         hrtimer_cancel(&apic->lapic_timer.timer);
1326         apic->lapic_timer.tscdeadline = data;
1327         start_apic_timer(apic);
1328 }
1329
1330 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1331 {
1332         struct kvm_lapic *apic = vcpu->arch.apic;
1333
1334         if (!kvm_vcpu_has_lapic(vcpu))
1335                 return;
1336
1337         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1338                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1339 }
1340
1341 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1342 {
1343         u64 tpr;
1344
1345         if (!kvm_vcpu_has_lapic(vcpu))
1346                 return 0;
1347
1348         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1349
1350         return (tpr & 0xf0) >> 4;
1351 }
1352
1353 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1354 {
1355         u64 old_value = vcpu->arch.apic_base;
1356         struct kvm_lapic *apic = vcpu->arch.apic;
1357
1358         if (!apic) {
1359                 value |= MSR_IA32_APICBASE_BSP;
1360                 vcpu->arch.apic_base = value;
1361                 return;
1362         }
1363
1364         /* update jump label if enable bit changes */
1365         if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
1366                 if (value & MSR_IA32_APICBASE_ENABLE)
1367                         static_key_slow_dec_deferred(&apic_hw_disabled);
1368                 else
1369                         static_key_slow_inc(&apic_hw_disabled.key);
1370                 recalculate_apic_map(vcpu->kvm);
1371         }
1372
1373         if (!kvm_vcpu_is_bsp(apic->vcpu))
1374                 value &= ~MSR_IA32_APICBASE_BSP;
1375
1376         vcpu->arch.apic_base = value;
1377         if ((old_value ^ value) & X2APIC_ENABLE) {
1378                 if (value & X2APIC_ENABLE) {
1379                         u32 id = kvm_apic_id(apic);
1380                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1381                         kvm_apic_set_ldr(apic, ldr);
1382                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1383                 } else
1384                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1385         }
1386
1387         apic->base_address = apic->vcpu->arch.apic_base &
1388                              MSR_IA32_APICBASE_BASE;
1389
1390         /* with FSB delivery interrupt, we can restart APIC functionality */
1391         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1392                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1393
1394 }
1395
1396 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1397 {
1398         struct kvm_lapic *apic;
1399         int i;
1400
1401         apic_debug("%s\n", __func__);
1402
1403         ASSERT(vcpu);
1404         apic = vcpu->arch.apic;
1405         ASSERT(apic != NULL);
1406
1407         /* Stop the timer in case it's a reset to an active apic */
1408         hrtimer_cancel(&apic->lapic_timer.timer);
1409
1410         kvm_apic_set_id(apic, vcpu->vcpu_id);
1411         kvm_apic_set_version(apic->vcpu);
1412
1413         for (i = 0; i < APIC_LVT_NUM; i++)
1414                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1415         apic_set_reg(apic, APIC_LVT0,
1416                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1417
1418         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1419         apic_set_spiv(apic, 0xff);
1420         apic_set_reg(apic, APIC_TASKPRI, 0);
1421         kvm_apic_set_ldr(apic, 0);
1422         apic_set_reg(apic, APIC_ESR, 0);
1423         apic_set_reg(apic, APIC_ICR, 0);
1424         apic_set_reg(apic, APIC_ICR2, 0);
1425         apic_set_reg(apic, APIC_TDCR, 0);
1426         apic_set_reg(apic, APIC_TMICT, 0);
1427         for (i = 0; i < 8; i++) {
1428                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1429                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1430                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1431         }
1432         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1433         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1434         apic->highest_isr_cache = -1;
1435         update_divide_count(apic);
1436         atomic_set(&apic->lapic_timer.pending, 0);
1437         if (kvm_vcpu_is_bsp(vcpu))
1438                 kvm_lapic_set_base(vcpu,
1439                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1440         vcpu->arch.pv_eoi.msr_val = 0;
1441         apic_update_ppr(apic);
1442
1443         vcpu->arch.apic_arb_prio = 0;
1444         vcpu->arch.apic_attention = 0;
1445
1446         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1447                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1448                    vcpu, kvm_apic_id(apic),
1449                    vcpu->arch.apic_base, apic->base_address);
1450 }
1451
1452 /*
1453  *----------------------------------------------------------------------
1454  * timer interface
1455  *----------------------------------------------------------------------
1456  */
1457
1458 static bool lapic_is_periodic(struct kvm_lapic *apic)
1459 {
1460         return apic_lvtt_period(apic);
1461 }
1462
1463 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1464 {
1465         struct kvm_lapic *apic = vcpu->arch.apic;
1466
1467         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1468                         apic_lvt_enabled(apic, APIC_LVTT))
1469                 return atomic_read(&apic->lapic_timer.pending);
1470
1471         return 0;
1472 }
1473
1474 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1475 {
1476         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1477         int vector, mode, trig_mode;
1478
1479         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1480                 vector = reg & APIC_VECTOR_MASK;
1481                 mode = reg & APIC_MODE_MASK;
1482                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1483                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1484                                         NULL);
1485         }
1486         return 0;
1487 }
1488
1489 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1490 {
1491         struct kvm_lapic *apic = vcpu->arch.apic;
1492
1493         if (apic)
1494                 kvm_apic_local_deliver(apic, APIC_LVT0);
1495 }
1496
1497 static const struct kvm_io_device_ops apic_mmio_ops = {
1498         .read     = apic_mmio_read,
1499         .write    = apic_mmio_write,
1500 };
1501
1502 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1503 {
1504         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1505         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1506         struct kvm_vcpu *vcpu = apic->vcpu;
1507         wait_queue_head_t *q = &vcpu->wq;
1508
1509         /*
1510          * There is a race window between reading and incrementing, but we do
1511          * not care about potentially losing timer events in the !reinject
1512          * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1513          * in vcpu_enter_guest.
1514          */
1515         if (!atomic_read(&ktimer->pending)) {
1516                 atomic_inc(&ktimer->pending);
1517                 /* FIXME: this code should not know anything about vcpus */
1518                 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1519         }
1520
1521         if (waitqueue_active(q))
1522                 wake_up_interruptible(q);
1523
1524         if (lapic_is_periodic(apic)) {
1525                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1526                 return HRTIMER_RESTART;
1527         } else
1528                 return HRTIMER_NORESTART;
1529 }
1530
1531 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1532 {
1533         struct kvm_lapic *apic;
1534
1535         ASSERT(vcpu != NULL);
1536         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1537
1538         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1539         if (!apic)
1540                 goto nomem;
1541
1542         vcpu->arch.apic = apic;
1543
1544         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1545         if (!apic->regs) {
1546                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1547                        vcpu->vcpu_id);
1548                 goto nomem_free_apic;
1549         }
1550         apic->vcpu = vcpu;
1551
1552         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1553                      HRTIMER_MODE_ABS);
1554         apic->lapic_timer.timer.function = apic_timer_fn;
1555
1556         /*
1557          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1558          * thinking that APIC satet has changed.
1559          */
1560         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1561         kvm_lapic_set_base(vcpu,
1562                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1563
1564         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1565         kvm_lapic_reset(vcpu);
1566         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1567
1568         return 0;
1569 nomem_free_apic:
1570         kfree(apic);
1571 nomem:
1572         return -ENOMEM;
1573 }
1574
1575 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1576 {
1577         struct kvm_lapic *apic = vcpu->arch.apic;
1578         int highest_irr;
1579
1580         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1581                 return -1;
1582
1583         apic_update_ppr(apic);
1584         highest_irr = apic_find_highest_irr(apic);
1585         if ((highest_irr == -1) ||
1586             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1587                 return -1;
1588         return highest_irr;
1589 }
1590
1591 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1592 {
1593         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1594         int r = 0;
1595
1596         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1597                 r = 1;
1598         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1599             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1600                 r = 1;
1601         return r;
1602 }
1603
1604 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1605 {
1606         struct kvm_lapic *apic = vcpu->arch.apic;
1607
1608         if (!kvm_vcpu_has_lapic(vcpu))
1609                 return;
1610
1611         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1612                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1613                         atomic_dec(&apic->lapic_timer.pending);
1614         }
1615 }
1616
1617 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1618 {
1619         int vector = kvm_apic_has_interrupt(vcpu);
1620         struct kvm_lapic *apic = vcpu->arch.apic;
1621
1622         if (vector == -1)
1623                 return -1;
1624
1625         apic_set_isr(vector, apic);
1626         apic_update_ppr(apic);
1627         apic_clear_irr(vector, apic);
1628         return vector;
1629 }
1630
1631 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1632                 struct kvm_lapic_state *s)
1633 {
1634         struct kvm_lapic *apic = vcpu->arch.apic;
1635
1636         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1637         /* set SPIV separately to get count of SW disabled APICs right */
1638         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1639         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1640         /* call kvm_apic_set_id() to put apic into apic_map */
1641         kvm_apic_set_id(apic, kvm_apic_id(apic));
1642         kvm_apic_set_version(vcpu);
1643
1644         apic_update_ppr(apic);
1645         hrtimer_cancel(&apic->lapic_timer.timer);
1646         update_divide_count(apic);
1647         start_apic_timer(apic);
1648         apic->irr_pending = true;
1649         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1650                                 1 : count_vectors(apic->regs + APIC_ISR);
1651         apic->highest_isr_cache = -1;
1652         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1653         kvm_make_request(KVM_REQ_EVENT, vcpu);
1654         kvm_rtc_eoi_tracking_restore_one(vcpu);
1655 }
1656
1657 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1658 {
1659         struct hrtimer *timer;
1660
1661         if (!kvm_vcpu_has_lapic(vcpu))
1662                 return;
1663
1664         timer = &vcpu->arch.apic->lapic_timer.timer;
1665         if (hrtimer_cancel(timer))
1666                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1667 }
1668
1669 /*
1670  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1671  *
1672  * Detect whether guest triggered PV EOI since the
1673  * last entry. If yes, set EOI on guests's behalf.
1674  * Clear PV EOI in guest memory in any case.
1675  */
1676 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1677                                         struct kvm_lapic *apic)
1678 {
1679         bool pending;
1680         int vector;
1681         /*
1682          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1683          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1684          *
1685          * KVM_APIC_PV_EOI_PENDING is unset:
1686          *      -> host disabled PV EOI.
1687          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1688          *      -> host enabled PV EOI, guest did not execute EOI yet.
1689          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1690          *      -> host enabled PV EOI, guest executed EOI.
1691          */
1692         BUG_ON(!pv_eoi_enabled(vcpu));
1693         pending = pv_eoi_get_pending(vcpu);
1694         /*
1695          * Clear pending bit in any case: it will be set again on vmentry.
1696          * While this might not be ideal from performance point of view,
1697          * this makes sure pv eoi is only enabled when we know it's safe.
1698          */
1699         pv_eoi_clr_pending(vcpu);
1700         if (pending)
1701                 return;
1702         vector = apic_set_eoi(apic);
1703         trace_kvm_pv_eoi(apic, vector);
1704 }
1705
1706 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1707 {
1708         u32 data;
1709         void *vapic;
1710
1711         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1712                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1713
1714         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1715                 return;
1716
1717         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1718         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1719         kunmap_atomic(vapic);
1720
1721         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1722 }
1723
1724 /*
1725  * apic_sync_pv_eoi_to_guest - called before vmentry
1726  *
1727  * Detect whether it's safe to enable PV EOI and
1728  * if yes do so.
1729  */
1730 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1731                                         struct kvm_lapic *apic)
1732 {
1733         if (!pv_eoi_enabled(vcpu) ||
1734             /* IRR set or many bits in ISR: could be nested. */
1735             apic->irr_pending ||
1736             /* Cache not set: could be safe but we don't bother. */
1737             apic->highest_isr_cache == -1 ||
1738             /* Need EOI to update ioapic. */
1739             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1740                 /*
1741                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1742                  * so we need not do anything here.
1743                  */
1744                 return;
1745         }
1746
1747         pv_eoi_set_pending(apic->vcpu);
1748 }
1749
1750 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1751 {
1752         u32 data, tpr;
1753         int max_irr, max_isr;
1754         struct kvm_lapic *apic = vcpu->arch.apic;
1755         void *vapic;
1756
1757         apic_sync_pv_eoi_to_guest(vcpu, apic);
1758
1759         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1760                 return;
1761
1762         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1763         max_irr = apic_find_highest_irr(apic);
1764         if (max_irr < 0)
1765                 max_irr = 0;
1766         max_isr = apic_find_highest_isr(apic);
1767         if (max_isr < 0)
1768                 max_isr = 0;
1769         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1770
1771         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1772         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1773         kunmap_atomic(vapic);
1774 }
1775
1776 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1777 {
1778         vcpu->arch.apic->vapic_addr = vapic_addr;
1779         if (vapic_addr)
1780                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1781         else
1782                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1783 }
1784
1785 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1786 {
1787         struct kvm_lapic *apic = vcpu->arch.apic;
1788         u32 reg = (msr - APIC_BASE_MSR) << 4;
1789
1790         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1791                 return 1;
1792
1793         /* if this is ICR write vector before command */
1794         if (msr == 0x830)
1795                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1796         return apic_reg_write(apic, reg, (u32)data);
1797 }
1798
1799 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1800 {
1801         struct kvm_lapic *apic = vcpu->arch.apic;
1802         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1803
1804         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1805                 return 1;
1806
1807         if (apic_reg_read(apic, reg, 4, &low))
1808                 return 1;
1809         if (msr == 0x830)
1810                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1811
1812         *data = (((u64)high) << 32) | low;
1813
1814         return 0;
1815 }
1816
1817 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1818 {
1819         struct kvm_lapic *apic = vcpu->arch.apic;
1820
1821         if (!kvm_vcpu_has_lapic(vcpu))
1822                 return 1;
1823
1824         /* if this is ICR write vector before command */
1825         if (reg == APIC_ICR)
1826                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1827         return apic_reg_write(apic, reg, (u32)data);
1828 }
1829
1830 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1831 {
1832         struct kvm_lapic *apic = vcpu->arch.apic;
1833         u32 low, high = 0;
1834
1835         if (!kvm_vcpu_has_lapic(vcpu))
1836                 return 1;
1837
1838         if (apic_reg_read(apic, reg, 4, &low))
1839                 return 1;
1840         if (reg == APIC_ICR)
1841                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1842
1843         *data = (((u64)high) << 32) | low;
1844
1845         return 0;
1846 }
1847
1848 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1849 {
1850         u64 addr = data & ~KVM_MSR_ENABLED;
1851         if (!IS_ALIGNED(addr, 4))
1852                 return 1;
1853
1854         vcpu->arch.pv_eoi.msr_val = data;
1855         if (!pv_eoi_enabled(vcpu))
1856                 return 0;
1857         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1858                                          addr, sizeof(u8));
1859 }
1860
1861 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1862 {
1863         struct kvm_lapic *apic = vcpu->arch.apic;
1864         unsigned int sipi_vector;
1865         unsigned long pe;
1866
1867         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1868                 return;
1869
1870         pe = xchg(&apic->pending_events, 0);
1871
1872         if (test_bit(KVM_APIC_INIT, &pe)) {
1873                 kvm_lapic_reset(vcpu);
1874                 kvm_vcpu_reset(vcpu);
1875                 if (kvm_vcpu_is_bsp(apic->vcpu))
1876                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1877                 else
1878                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1879         }
1880         if (test_bit(KVM_APIC_SIPI, &pe) &&
1881             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1882                 /* evaluate pending_events before reading the vector */
1883                 smp_rmb();
1884                 sipi_vector = apic->sipi_vector;
1885                 pr_debug("vcpu %d received sipi with vector # %x\n",
1886                          vcpu->vcpu_id, sipi_vector);
1887                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1888                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1889         }
1890 }
1891
1892 void kvm_lapic_init(void)
1893 {
1894         /* do not patch jump label more than once per second */
1895         jump_label_rate_limit(&apic_hw_disabled, HZ);
1896         jump_label_rate_limit(&apic_sw_disabled, HZ);
1897 }