3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 #define APIC_BUS_CYCLE_NS 1
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
80 *((u32 *) (apic->regs + reg_off)) = val;
83 static inline int apic_test_vector(int vec, void *bitmap)
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
90 struct kvm_lapic *apic = vcpu->arch.apic;
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
96 static inline void apic_set_vector(int vec, void *bitmap)
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101 static inline void apic_clear_vector(int vec, void *bitmap)
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
116 struct static_key_deferred apic_hw_disabled __read_mostly;
117 struct static_key_deferred apic_sw_disabled __read_mostly;
119 static inline int apic_enabled(struct kvm_lapic *apic)
121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
131 static inline int kvm_apic_id(struct kvm_lapic *apic)
133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
136 /* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
141 return !(map->mode & (map->mode - 1));
145 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
158 static void recalculate_apic_map(struct kvm *kvm)
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
166 mutex_lock(&kvm->arch.apic_map_lock);
171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
176 if (!kvm_apic_present(vcpu))
179 aid = kvm_apic_id(apic);
180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
195 if (!kvm_apic_logical_map_valid(new))
198 apic_logical_id(new, ldr, &cid, &lid);
200 if (lid && cid < ARRAY_SIZE(new->logical_map))
201 new->logical_map[cid][ffs(lid) - 1] = apic;
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
212 kvm_vcpu_request_scan_ioapic(kvm);
215 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
219 apic_set_reg(apic, APIC_SPIV, val);
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
227 static_key_slow_inc(&apic_sw_disabled.key);
231 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
237 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
243 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
245 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
247 apic_set_reg(apic, APIC_ID, id << 24);
248 apic_set_reg(apic, APIC_LDR, ldr);
249 recalculate_apic_map(apic->vcpu->kvm);
252 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
254 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
257 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
259 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
262 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
267 static inline int apic_lvtt_period(struct kvm_lapic *apic)
269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
272 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
274 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
277 static inline int apic_lvt_nmi_mode(u32 lvt_val)
279 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
282 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
284 struct kvm_lapic *apic = vcpu->arch.apic;
285 struct kvm_cpuid_entry2 *feat;
286 u32 v = APIC_VERSION;
288 if (!kvm_vcpu_has_lapic(vcpu))
291 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
292 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
293 v |= APIC_LVR_DIRECTED_EOI;
294 apic_set_reg(apic, APIC_LVR, v);
297 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
298 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
299 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
300 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
301 LINT_MASK, LINT_MASK, /* LVT0-1 */
302 LVT_MASK /* LVTERR */
305 static int find_highest_vector(void *bitmap)
310 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
311 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
312 reg = bitmap + REG_POS(vec);
314 return fls(*reg) - 1 + vec;
320 static u8 count_vectors(void *bitmap)
326 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
327 reg = bitmap + REG_POS(vec);
328 count += hweight32(*reg);
334 void __kvm_apic_update_irr(u32 *pir, void *regs)
338 for (i = 0; i <= 7; i++) {
339 pir_val = xchg(&pir[i], 0);
341 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
344 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
346 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
348 struct kvm_lapic *apic = vcpu->arch.apic;
350 __kvm_apic_update_irr(pir, apic->regs);
352 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
354 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
356 apic_set_vector(vec, apic->regs + APIC_IRR);
358 * irr_pending must be true if any interrupt is pending; set it after
359 * APIC_IRR to avoid race with apic_clear_irr
361 apic->irr_pending = true;
364 static inline int apic_search_irr(struct kvm_lapic *apic)
366 return find_highest_vector(apic->regs + APIC_IRR);
369 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
374 * Note that irr_pending is just a hint. It will be always
375 * true with virtual interrupt delivery enabled.
377 if (!apic->irr_pending)
380 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
381 result = apic_search_irr(apic);
382 ASSERT(result == -1 || result >= 16);
387 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
389 struct kvm_vcpu *vcpu;
393 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
394 /* try to update RVI */
395 apic_clear_vector(vec, apic->regs + APIC_IRR);
396 kvm_make_request(KVM_REQ_EVENT, vcpu);
398 apic->irr_pending = false;
399 apic_clear_vector(vec, apic->regs + APIC_IRR);
400 if (apic_search_irr(apic) != -1)
401 apic->irr_pending = true;
405 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
407 struct kvm_vcpu *vcpu;
409 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
415 * With APIC virtualization enabled, all caching is disabled
416 * because the processor can modify ISR under the hood. Instead
419 if (unlikely(kvm_x86_ops->hwapic_isr_update))
420 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
423 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
425 * ISR (in service register) bit is set when injecting an interrupt.
426 * The highest vector is injected. Thus the latest bit set matches
427 * the highest bit in ISR.
429 apic->highest_isr_cache = vec;
433 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
438 * Note that isr_count is always 1, and highest_isr_cache
439 * is always -1, with APIC virtualization enabled.
441 if (!apic->isr_count)
443 if (likely(apic->highest_isr_cache != -1))
444 return apic->highest_isr_cache;
446 result = find_highest_vector(apic->regs + APIC_ISR);
447 ASSERT(result == -1 || result >= 16);
452 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
454 struct kvm_vcpu *vcpu;
455 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
461 * We do get here for APIC virtualization enabled if the guest
462 * uses the Hyper-V APIC enlightenment. In this case we may need
463 * to trigger a new interrupt delivery by writing the SVI field;
464 * on the other hand isr_count and highest_isr_cache are unused
465 * and must be left alone.
467 if (unlikely(kvm_x86_ops->hwapic_isr_update))
468 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
469 apic_find_highest_isr(apic));
472 BUG_ON(apic->isr_count < 0);
473 apic->highest_isr_cache = -1;
477 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
481 /* This may race with setting of irr in __apic_accept_irq() and
482 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
483 * will cause vmexit immediately and the value will be recalculated
484 * on the next vmentry.
486 if (!kvm_vcpu_has_lapic(vcpu))
488 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
493 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
494 int vector, int level, int trig_mode,
495 unsigned long *dest_map);
497 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
498 unsigned long *dest_map)
500 struct kvm_lapic *apic = vcpu->arch.apic;
502 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
503 irq->level, irq->trig_mode, dest_map);
506 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
509 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
513 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
516 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
520 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
522 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
525 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
528 if (pv_eoi_get_user(vcpu, &val) < 0)
529 apic_debug("Can't read EOI MSR value: 0x%llx\n",
530 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
534 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
536 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
537 apic_debug("Can't set EOI MSR value: 0x%llx\n",
538 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
541 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
544 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
546 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
547 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
548 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
551 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
554 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
556 struct kvm_lapic *apic = vcpu->arch.apic;
559 for (i = 0; i < 8; i++)
560 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
563 static void apic_update_ppr(struct kvm_lapic *apic)
565 u32 tpr, isrv, ppr, old_ppr;
568 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
569 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
570 isr = apic_find_highest_isr(apic);
571 isrv = (isr != -1) ? isr : 0;
573 if ((tpr & 0xf0) >= (isrv & 0xf0))
578 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
579 apic, ppr, isr, isrv);
581 if (old_ppr != ppr) {
582 apic_set_reg(apic, APIC_PROCPRI, ppr);
584 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
588 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
590 apic_set_reg(apic, APIC_TASKPRI, tpr);
591 apic_update_ppr(apic);
594 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
596 if (apic_x2apic_mode(apic))
597 return mda == X2APIC_BROADCAST;
599 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
602 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
604 if (kvm_apic_broadcast(apic, mda))
607 if (apic_x2apic_mode(apic))
608 return mda == kvm_apic_id(apic);
610 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
613 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
617 if (kvm_apic_broadcast(apic, mda))
620 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
622 if (apic_x2apic_mode(apic))
623 return ((logical_id >> 16) == (mda >> 16))
624 && (logical_id & mda & 0xffff) != 0;
626 logical_id = GET_APIC_LOGICAL_ID(logical_id);
627 mda = GET_APIC_DEST_FIELD(mda);
629 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
631 return (logical_id & mda) != 0;
632 case APIC_DFR_CLUSTER:
633 return ((logical_id >> 4) == (mda >> 4))
634 && (logical_id & mda & 0xf) != 0;
636 apic_debug("Bad DFR vcpu %d: %08x\n",
637 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
642 /* KVM APIC implementation has two quirks
643 * - dest always begins at 0 while xAPIC MDA has offset 24,
644 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
646 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
647 struct kvm_lapic *target)
649 bool ipi = source != NULL;
650 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
652 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
653 return X2APIC_BROADCAST;
655 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
658 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
659 int short_hand, unsigned int dest, int dest_mode)
661 struct kvm_lapic *target = vcpu->arch.apic;
662 u32 mda = kvm_apic_mda(dest, source, target);
664 apic_debug("target %p, source %p, dest 0x%x, "
665 "dest_mode 0x%x, short_hand 0x%x\n",
666 target, source, dest, dest_mode, short_hand);
669 switch (short_hand) {
670 case APIC_DEST_NOSHORT:
671 if (dest_mode == APIC_DEST_PHYSICAL)
672 return kvm_apic_match_physical_addr(target, mda);
674 return kvm_apic_match_logical_addr(target, mda);
676 return target == source;
677 case APIC_DEST_ALLINC:
679 case APIC_DEST_ALLBUT:
680 return target != source;
682 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
688 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
689 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
691 struct kvm_apic_map *map;
692 unsigned long bitmap = 1;
693 struct kvm_lapic **dst;
695 bool ret, x2apic_ipi;
699 if (irq->shorthand == APIC_DEST_SELF) {
700 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
707 x2apic_ipi = src && apic_x2apic_mode(src);
708 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
713 map = rcu_dereference(kvm->arch.apic_map);
720 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
721 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
724 dst = &map->phys_map[irq->dest_id];
728 if (!kvm_apic_logical_map_valid(map)) {
733 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
735 if (cid >= ARRAY_SIZE(map->logical_map))
738 dst = map->logical_map[cid];
740 if (kvm_lowest_prio_delivery(irq)) {
742 for_each_set_bit(i, &bitmap, 16) {
747 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
751 bitmap = (l >= 0) ? 1 << l : 0;
755 for_each_set_bit(i, &bitmap, 16) {
760 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
768 * Add a pending IRQ into lapic.
769 * Return 1 if successfully added and 0 if discarded.
771 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
772 int vector, int level, int trig_mode,
773 unsigned long *dest_map)
776 struct kvm_vcpu *vcpu = apic->vcpu;
778 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
780 switch (delivery_mode) {
782 vcpu->arch.apic_arb_prio++;
784 /* FIXME add logic for vcpu on reset */
785 if (unlikely(!apic_enabled(apic)))
791 __set_bit(vcpu->vcpu_id, dest_map);
793 if (kvm_x86_ops->deliver_posted_interrupt)
794 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
796 apic_set_irr(vector, apic);
798 kvm_make_request(KVM_REQ_EVENT, vcpu);
805 vcpu->arch.pv.pv_unhalted = 1;
806 kvm_make_request(KVM_REQ_EVENT, vcpu);
812 kvm_make_request(KVM_REQ_SMI, vcpu);
818 kvm_inject_nmi(vcpu);
823 if (!trig_mode || level) {
825 /* assumes that there are only KVM_APIC_INIT/SIPI */
826 apic->pending_events = (1UL << KVM_APIC_INIT);
827 /* make sure pending_events is visible before sending
830 kvm_make_request(KVM_REQ_EVENT, vcpu);
833 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
838 case APIC_DM_STARTUP:
839 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
840 vcpu->vcpu_id, vector);
842 apic->sipi_vector = vector;
843 /* make sure sipi_vector is visible for the receiver */
845 set_bit(KVM_APIC_SIPI, &apic->pending_events);
846 kvm_make_request(KVM_REQ_EVENT, vcpu);
852 * Should only be called by kvm_apic_local_deliver() with LVT0,
853 * before NMI watchdog was enabled. Already handled by
854 * kvm_apic_accept_pic_intr().
859 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
866 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
868 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
871 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
873 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
875 if (apic_test_vector(vector, apic->regs + APIC_TMR))
876 trigger_mode = IOAPIC_LEVEL_TRIG;
878 trigger_mode = IOAPIC_EDGE_TRIG;
879 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
883 static int apic_set_eoi(struct kvm_lapic *apic)
885 int vector = apic_find_highest_isr(apic);
887 trace_kvm_eoi(apic, vector);
890 * Not every write EOI will has corresponding ISR,
891 * one example is when Kernel check timer on setup_IO_APIC
896 apic_clear_isr(vector, apic);
897 apic_update_ppr(apic);
899 kvm_ioapic_send_eoi(apic, vector);
900 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
905 * this interface assumes a trap-like exit, which has already finished
906 * desired side effect including vISR and vPPR update.
908 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
910 struct kvm_lapic *apic = vcpu->arch.apic;
912 trace_kvm_eoi(apic, vector);
914 kvm_ioapic_send_eoi(apic, vector);
915 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
917 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
919 static void apic_send_ipi(struct kvm_lapic *apic)
921 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
922 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
923 struct kvm_lapic_irq irq;
925 irq.vector = icr_low & APIC_VECTOR_MASK;
926 irq.delivery_mode = icr_low & APIC_MODE_MASK;
927 irq.dest_mode = icr_low & APIC_DEST_MASK;
928 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
929 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
930 irq.shorthand = icr_low & APIC_SHORT_MASK;
931 irq.msi_redir_hint = false;
932 if (apic_x2apic_mode(apic))
933 irq.dest_id = icr_high;
935 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
937 trace_kvm_apic_ipi(icr_low, irq.dest_id);
939 apic_debug("icr_high 0x%x, icr_low 0x%x, "
940 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
941 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
942 "msi_redir_hint 0x%x\n",
943 icr_high, icr_low, irq.shorthand, irq.dest_id,
944 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
945 irq.vector, irq.msi_redir_hint);
947 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
950 static u32 apic_get_tmcct(struct kvm_lapic *apic)
956 ASSERT(apic != NULL);
958 /* if initial count is 0, current count should also be 0 */
959 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
960 apic->lapic_timer.period == 0)
963 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
964 if (ktime_to_ns(remaining) < 0)
965 remaining = ktime_set(0, 0);
967 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
968 tmcct = div64_u64(ns,
969 (APIC_BUS_CYCLE_NS * apic->divide_count));
974 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
976 struct kvm_vcpu *vcpu = apic->vcpu;
977 struct kvm_run *run = vcpu->run;
979 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
980 run->tpr_access.rip = kvm_rip_read(vcpu);
981 run->tpr_access.is_write = write;
984 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
986 if (apic->vcpu->arch.tpr_access_reporting)
987 __report_tpr_access(apic, write);
990 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
994 if (offset >= LAPIC_MMIO_LENGTH)
999 if (apic_x2apic_mode(apic))
1000 val = kvm_apic_id(apic);
1002 val = kvm_apic_id(apic) << 24;
1005 apic_debug("Access APIC ARBPRI register which is for P6\n");
1008 case APIC_TMCCT: /* Timer CCR */
1009 if (apic_lvtt_tscdeadline(apic))
1012 val = apic_get_tmcct(apic);
1015 apic_update_ppr(apic);
1016 val = kvm_apic_get_reg(apic, offset);
1019 report_tpr_access(apic, false);
1022 val = kvm_apic_get_reg(apic, offset);
1029 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1031 return container_of(dev, struct kvm_lapic, dev);
1034 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1037 unsigned char alignment = offset & 0xf;
1039 /* this bitmask has a bit cleared for each reserved register */
1040 static const u64 rmask = 0x43ff01ffffffe70cULL;
1042 if ((alignment + len) > 4) {
1043 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1048 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1049 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1054 result = __apic_read(apic, offset & ~0xf);
1056 trace_kvm_apic_read(offset, result);
1062 memcpy(data, (char *)&result + alignment, len);
1065 printk(KERN_ERR "Local APIC read with len = %x, "
1066 "should be 1,2, or 4 instead\n", len);
1072 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1074 return kvm_apic_hw_enabled(apic) &&
1075 addr >= apic->base_address &&
1076 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1079 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1080 gpa_t address, int len, void *data)
1082 struct kvm_lapic *apic = to_lapic(this);
1083 u32 offset = address - apic->base_address;
1085 if (!apic_mmio_in_range(apic, address))
1088 apic_reg_read(apic, offset, len, data);
1093 static void update_divide_count(struct kvm_lapic *apic)
1095 u32 tmp1, tmp2, tdcr;
1097 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1099 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1100 apic->divide_count = 0x1 << (tmp2 & 0x7);
1102 apic_debug("timer divide count is 0x%x\n",
1103 apic->divide_count);
1106 static void apic_update_lvtt(struct kvm_lapic *apic)
1108 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1109 apic->lapic_timer.timer_mode_mask;
1111 if (apic->lapic_timer.timer_mode != timer_mode) {
1112 apic->lapic_timer.timer_mode = timer_mode;
1113 hrtimer_cancel(&apic->lapic_timer.timer);
1117 static void apic_timer_expired(struct kvm_lapic *apic)
1119 struct kvm_vcpu *vcpu = apic->vcpu;
1120 wait_queue_head_t *q = &vcpu->wq;
1121 struct kvm_timer *ktimer = &apic->lapic_timer;
1123 if (atomic_read(&apic->lapic_timer.pending))
1126 atomic_inc(&apic->lapic_timer.pending);
1127 kvm_set_pending_timer(vcpu);
1129 if (waitqueue_active(q))
1130 wake_up_interruptible(q);
1132 if (apic_lvtt_tscdeadline(apic))
1133 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1137 * On APICv, this test will cause a busy wait
1138 * during a higher-priority task.
1141 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1143 struct kvm_lapic *apic = vcpu->arch.apic;
1144 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1146 if (kvm_apic_hw_enabled(apic)) {
1147 int vec = reg & APIC_VECTOR_MASK;
1148 void *bitmap = apic->regs + APIC_ISR;
1150 if (kvm_x86_ops->deliver_posted_interrupt)
1151 bitmap = apic->regs + APIC_IRR;
1153 if (apic_test_vector(vec, bitmap))
1159 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1161 struct kvm_lapic *apic = vcpu->arch.apic;
1162 u64 guest_tsc, tsc_deadline;
1164 if (!kvm_vcpu_has_lapic(vcpu))
1167 if (apic->lapic_timer.expired_tscdeadline == 0)
1170 if (!lapic_timer_int_injected(vcpu))
1173 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1174 apic->lapic_timer.expired_tscdeadline = 0;
1175 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1176 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1178 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1179 if (guest_tsc < tsc_deadline)
1180 __delay(tsc_deadline - guest_tsc);
1183 static void start_apic_timer(struct kvm_lapic *apic)
1187 atomic_set(&apic->lapic_timer.pending, 0);
1189 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1190 /* lapic timer in oneshot or periodic mode */
1191 now = apic->lapic_timer.timer.base->get_time();
1192 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1193 * APIC_BUS_CYCLE_NS * apic->divide_count;
1195 if (!apic->lapic_timer.period)
1198 * Do not allow the guest to program periodic timers with small
1199 * interval, since the hrtimers are not throttled by the host
1202 if (apic_lvtt_period(apic)) {
1203 s64 min_period = min_timer_period_us * 1000LL;
1205 if (apic->lapic_timer.period < min_period) {
1206 pr_info_ratelimited(
1207 "kvm: vcpu %i: requested %lld ns "
1208 "lapic timer period limited to %lld ns\n",
1209 apic->vcpu->vcpu_id,
1210 apic->lapic_timer.period, min_period);
1211 apic->lapic_timer.period = min_period;
1215 hrtimer_start(&apic->lapic_timer.timer,
1216 ktime_add_ns(now, apic->lapic_timer.period),
1219 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1221 "timer initial count 0x%x, period %lldns, "
1222 "expire @ 0x%016" PRIx64 ".\n", __func__,
1223 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1224 kvm_apic_get_reg(apic, APIC_TMICT),
1225 apic->lapic_timer.period,
1226 ktime_to_ns(ktime_add_ns(now,
1227 apic->lapic_timer.period)));
1228 } else if (apic_lvtt_tscdeadline(apic)) {
1229 /* lapic timer in tsc deadline mode */
1230 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1233 struct kvm_vcpu *vcpu = apic->vcpu;
1234 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1235 unsigned long flags;
1237 if (unlikely(!tscdeadline || !this_tsc_khz))
1240 local_irq_save(flags);
1242 now = apic->lapic_timer.timer.base->get_time();
1243 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1244 if (likely(tscdeadline > guest_tsc)) {
1245 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1246 do_div(ns, this_tsc_khz);
1247 expire = ktime_add_ns(now, ns);
1248 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1249 hrtimer_start(&apic->lapic_timer.timer,
1250 expire, HRTIMER_MODE_ABS);
1252 apic_timer_expired(apic);
1254 local_irq_restore(flags);
1258 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1260 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1262 if (apic_lvt_nmi_mode(lvt0_val)) {
1263 if (!nmi_wd_enabled) {
1264 apic_debug("Receive NMI setting on APIC_LVT0 "
1265 "for cpu %d\n", apic->vcpu->vcpu_id);
1266 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1268 } else if (nmi_wd_enabled)
1269 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1272 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1276 trace_kvm_apic_write(reg, val);
1279 case APIC_ID: /* Local APIC ID */
1280 if (!apic_x2apic_mode(apic))
1281 kvm_apic_set_id(apic, val >> 24);
1287 report_tpr_access(apic, true);
1288 apic_set_tpr(apic, val & 0xff);
1296 if (!apic_x2apic_mode(apic))
1297 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1303 if (!apic_x2apic_mode(apic)) {
1304 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1305 recalculate_apic_map(apic->vcpu->kvm);
1312 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1313 mask |= APIC_SPIV_DIRECTED_EOI;
1314 apic_set_spiv(apic, val & mask);
1315 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1319 for (i = 0; i < APIC_LVT_NUM; i++) {
1320 lvt_val = kvm_apic_get_reg(apic,
1321 APIC_LVTT + 0x10 * i);
1322 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1323 lvt_val | APIC_LVT_MASKED);
1325 apic_update_lvtt(apic);
1326 atomic_set(&apic->lapic_timer.pending, 0);
1332 /* No delay here, so we always clear the pending bit */
1333 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1334 apic_send_ipi(apic);
1338 if (!apic_x2apic_mode(apic))
1340 apic_set_reg(apic, APIC_ICR2, val);
1344 apic_manage_nmi_watchdog(apic, val);
1349 /* TODO: Check vector */
1350 if (!kvm_apic_sw_enabled(apic))
1351 val |= APIC_LVT_MASKED;
1353 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1354 apic_set_reg(apic, reg, val);
1359 if (!kvm_apic_sw_enabled(apic))
1360 val |= APIC_LVT_MASKED;
1361 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1362 apic_set_reg(apic, APIC_LVTT, val);
1363 apic_update_lvtt(apic);
1367 if (apic_lvtt_tscdeadline(apic))
1370 hrtimer_cancel(&apic->lapic_timer.timer);
1371 apic_set_reg(apic, APIC_TMICT, val);
1372 start_apic_timer(apic);
1377 apic_debug("KVM_WRITE:TDCR %x\n", val);
1378 apic_set_reg(apic, APIC_TDCR, val);
1379 update_divide_count(apic);
1383 if (apic_x2apic_mode(apic) && val != 0) {
1384 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1390 if (apic_x2apic_mode(apic)) {
1391 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1400 apic_debug("Local APIC Write to read-only register %x\n", reg);
1404 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1405 gpa_t address, int len, const void *data)
1407 struct kvm_lapic *apic = to_lapic(this);
1408 unsigned int offset = address - apic->base_address;
1411 if (!apic_mmio_in_range(apic, address))
1415 * APIC register must be aligned on 128-bits boundary.
1416 * 32/64/128 bits registers must be accessed thru 32 bits.
1419 if (len != 4 || (offset & 0xf)) {
1420 /* Don't shout loud, $infamous_os would cause only noise. */
1421 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1427 /* too common printing */
1428 if (offset != APIC_EOI)
1429 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1430 "0x%x\n", __func__, offset, len, val);
1432 apic_reg_write(apic, offset & 0xff0, val);
1437 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1439 if (kvm_vcpu_has_lapic(vcpu))
1440 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1442 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1444 /* emulate APIC access in a trap manner */
1445 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1449 /* hw has done the conditional check and inst decode */
1452 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1454 /* TODO: optimize to just emulate side effect w/o one more write */
1455 apic_reg_write(vcpu->arch.apic, offset, val);
1457 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1459 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1461 struct kvm_lapic *apic = vcpu->arch.apic;
1463 if (!vcpu->arch.apic)
1466 hrtimer_cancel(&apic->lapic_timer.timer);
1468 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1469 static_key_slow_dec_deferred(&apic_hw_disabled);
1471 if (!apic->sw_enabled)
1472 static_key_slow_dec_deferred(&apic_sw_disabled);
1475 free_page((unsigned long)apic->regs);
1481 *----------------------------------------------------------------------
1483 *----------------------------------------------------------------------
1486 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1488 struct kvm_lapic *apic = vcpu->arch.apic;
1490 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1491 apic_lvtt_period(apic))
1494 return apic->lapic_timer.tscdeadline;
1497 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1499 struct kvm_lapic *apic = vcpu->arch.apic;
1501 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1502 apic_lvtt_period(apic))
1505 hrtimer_cancel(&apic->lapic_timer.timer);
1506 apic->lapic_timer.tscdeadline = data;
1507 start_apic_timer(apic);
1510 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1512 struct kvm_lapic *apic = vcpu->arch.apic;
1514 if (!kvm_vcpu_has_lapic(vcpu))
1517 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1518 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1521 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1525 if (!kvm_vcpu_has_lapic(vcpu))
1528 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1530 return (tpr & 0xf0) >> 4;
1533 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1535 u64 old_value = vcpu->arch.apic_base;
1536 struct kvm_lapic *apic = vcpu->arch.apic;
1539 value |= MSR_IA32_APICBASE_BSP;
1540 vcpu->arch.apic_base = value;
1544 vcpu->arch.apic_base = value;
1546 /* update jump label if enable bit changes */
1547 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1548 if (value & MSR_IA32_APICBASE_ENABLE)
1549 static_key_slow_dec_deferred(&apic_hw_disabled);
1551 static_key_slow_inc(&apic_hw_disabled.key);
1552 recalculate_apic_map(vcpu->kvm);
1555 if ((old_value ^ value) & X2APIC_ENABLE) {
1556 if (value & X2APIC_ENABLE) {
1557 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1558 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1560 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1563 apic->base_address = apic->vcpu->arch.apic_base &
1564 MSR_IA32_APICBASE_BASE;
1566 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1567 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1568 pr_warn_once("APIC base relocation is unsupported by KVM");
1570 /* with FSB delivery interrupt, we can restart APIC functionality */
1571 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1572 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1576 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1578 struct kvm_lapic *apic;
1581 apic_debug("%s\n", __func__);
1584 apic = vcpu->arch.apic;
1585 ASSERT(apic != NULL);
1587 /* Stop the timer in case it's a reset to an active apic */
1588 hrtimer_cancel(&apic->lapic_timer.timer);
1591 kvm_apic_set_id(apic, vcpu->vcpu_id);
1592 kvm_apic_set_version(apic->vcpu);
1594 for (i = 0; i < APIC_LVT_NUM; i++)
1595 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1596 apic_update_lvtt(apic);
1597 if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_LINT0_REENABLED))
1598 apic_set_reg(apic, APIC_LVT0,
1599 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1601 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1602 apic_set_spiv(apic, 0xff);
1603 apic_set_reg(apic, APIC_TASKPRI, 0);
1604 if (!apic_x2apic_mode(apic))
1605 kvm_apic_set_ldr(apic, 0);
1606 apic_set_reg(apic, APIC_ESR, 0);
1607 apic_set_reg(apic, APIC_ICR, 0);
1608 apic_set_reg(apic, APIC_ICR2, 0);
1609 apic_set_reg(apic, APIC_TDCR, 0);
1610 apic_set_reg(apic, APIC_TMICT, 0);
1611 for (i = 0; i < 8; i++) {
1612 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1613 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1614 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1616 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1617 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1618 apic->highest_isr_cache = -1;
1619 update_divide_count(apic);
1620 atomic_set(&apic->lapic_timer.pending, 0);
1621 if (kvm_vcpu_is_bsp(vcpu))
1622 kvm_lapic_set_base(vcpu,
1623 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1624 vcpu->arch.pv_eoi.msr_val = 0;
1625 apic_update_ppr(apic);
1627 vcpu->arch.apic_arb_prio = 0;
1628 vcpu->arch.apic_attention = 0;
1630 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1631 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1632 vcpu, kvm_apic_id(apic),
1633 vcpu->arch.apic_base, apic->base_address);
1637 *----------------------------------------------------------------------
1639 *----------------------------------------------------------------------
1642 static bool lapic_is_periodic(struct kvm_lapic *apic)
1644 return apic_lvtt_period(apic);
1647 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1649 struct kvm_lapic *apic = vcpu->arch.apic;
1651 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1652 apic_lvt_enabled(apic, APIC_LVTT))
1653 return atomic_read(&apic->lapic_timer.pending);
1658 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1660 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1661 int vector, mode, trig_mode;
1663 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1664 vector = reg & APIC_VECTOR_MASK;
1665 mode = reg & APIC_MODE_MASK;
1666 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1667 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1673 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1675 struct kvm_lapic *apic = vcpu->arch.apic;
1678 kvm_apic_local_deliver(apic, APIC_LVT0);
1681 static const struct kvm_io_device_ops apic_mmio_ops = {
1682 .read = apic_mmio_read,
1683 .write = apic_mmio_write,
1686 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1688 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1689 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1691 apic_timer_expired(apic);
1693 if (lapic_is_periodic(apic)) {
1694 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1695 return HRTIMER_RESTART;
1697 return HRTIMER_NORESTART;
1700 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1702 struct kvm_lapic *apic;
1704 ASSERT(vcpu != NULL);
1705 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1707 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1711 vcpu->arch.apic = apic;
1713 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1715 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1717 goto nomem_free_apic;
1721 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1723 apic->lapic_timer.timer.function = apic_timer_fn;
1726 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1727 * thinking that APIC satet has changed.
1729 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1730 kvm_lapic_set_base(vcpu,
1731 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1733 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1734 kvm_lapic_reset(vcpu, false);
1735 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1744 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1746 struct kvm_lapic *apic = vcpu->arch.apic;
1749 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1752 apic_update_ppr(apic);
1753 highest_irr = apic_find_highest_irr(apic);
1754 if ((highest_irr == -1) ||
1755 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1760 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1762 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1765 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1767 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1768 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1773 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1775 struct kvm_lapic *apic = vcpu->arch.apic;
1777 if (!kvm_vcpu_has_lapic(vcpu))
1780 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1781 kvm_apic_local_deliver(apic, APIC_LVTT);
1782 if (apic_lvtt_tscdeadline(apic))
1783 apic->lapic_timer.tscdeadline = 0;
1784 atomic_set(&apic->lapic_timer.pending, 0);
1788 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1790 int vector = kvm_apic_has_interrupt(vcpu);
1791 struct kvm_lapic *apic = vcpu->arch.apic;
1797 * We get here even with APIC virtualization enabled, if doing
1798 * nested virtualization and L1 runs with the "acknowledge interrupt
1799 * on exit" mode. Then we cannot inject the interrupt via RVI,
1800 * because the process would deliver it through the IDT.
1803 apic_set_isr(vector, apic);
1804 apic_update_ppr(apic);
1805 apic_clear_irr(vector, apic);
1809 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1810 struct kvm_lapic_state *s)
1812 struct kvm_lapic *apic = vcpu->arch.apic;
1814 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1815 /* set SPIV separately to get count of SW disabled APICs right */
1816 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1817 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1818 /* call kvm_apic_set_id() to put apic into apic_map */
1819 kvm_apic_set_id(apic, kvm_apic_id(apic));
1820 kvm_apic_set_version(vcpu);
1822 apic_update_ppr(apic);
1823 hrtimer_cancel(&apic->lapic_timer.timer);
1824 apic_update_lvtt(apic);
1825 update_divide_count(apic);
1826 start_apic_timer(apic);
1827 apic->irr_pending = true;
1828 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1829 1 : count_vectors(apic->regs + APIC_ISR);
1830 apic->highest_isr_cache = -1;
1831 if (kvm_x86_ops->hwapic_irr_update)
1832 kvm_x86_ops->hwapic_irr_update(vcpu,
1833 apic_find_highest_irr(apic));
1834 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1835 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1836 apic_find_highest_isr(apic));
1837 kvm_make_request(KVM_REQ_EVENT, vcpu);
1838 kvm_rtc_eoi_tracking_restore_one(vcpu);
1841 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1843 struct hrtimer *timer;
1845 if (!kvm_vcpu_has_lapic(vcpu))
1848 timer = &vcpu->arch.apic->lapic_timer.timer;
1849 if (hrtimer_cancel(timer))
1850 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1854 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1856 * Detect whether guest triggered PV EOI since the
1857 * last entry. If yes, set EOI on guests's behalf.
1858 * Clear PV EOI in guest memory in any case.
1860 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1861 struct kvm_lapic *apic)
1866 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1867 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1869 * KVM_APIC_PV_EOI_PENDING is unset:
1870 * -> host disabled PV EOI.
1871 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1872 * -> host enabled PV EOI, guest did not execute EOI yet.
1873 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1874 * -> host enabled PV EOI, guest executed EOI.
1876 BUG_ON(!pv_eoi_enabled(vcpu));
1877 pending = pv_eoi_get_pending(vcpu);
1879 * Clear pending bit in any case: it will be set again on vmentry.
1880 * While this might not be ideal from performance point of view,
1881 * this makes sure pv eoi is only enabled when we know it's safe.
1883 pv_eoi_clr_pending(vcpu);
1886 vector = apic_set_eoi(apic);
1887 trace_kvm_pv_eoi(apic, vector);
1890 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1894 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1895 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1897 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1900 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1903 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1907 * apic_sync_pv_eoi_to_guest - called before vmentry
1909 * Detect whether it's safe to enable PV EOI and
1912 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1913 struct kvm_lapic *apic)
1915 if (!pv_eoi_enabled(vcpu) ||
1916 /* IRR set or many bits in ISR: could be nested. */
1917 apic->irr_pending ||
1918 /* Cache not set: could be safe but we don't bother. */
1919 apic->highest_isr_cache == -1 ||
1920 /* Need EOI to update ioapic. */
1921 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1923 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1924 * so we need not do anything here.
1929 pv_eoi_set_pending(apic->vcpu);
1932 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1935 int max_irr, max_isr;
1936 struct kvm_lapic *apic = vcpu->arch.apic;
1938 apic_sync_pv_eoi_to_guest(vcpu, apic);
1940 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1943 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1944 max_irr = apic_find_highest_irr(apic);
1947 max_isr = apic_find_highest_isr(apic);
1950 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1952 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1956 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1959 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1960 &vcpu->arch.apic->vapic_cache,
1961 vapic_addr, sizeof(u32)))
1963 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1965 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1968 vcpu->arch.apic->vapic_addr = vapic_addr;
1972 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1974 struct kvm_lapic *apic = vcpu->arch.apic;
1975 u32 reg = (msr - APIC_BASE_MSR) << 4;
1977 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1980 if (reg == APIC_ICR2)
1983 /* if this is ICR write vector before command */
1984 if (reg == APIC_ICR)
1985 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1986 return apic_reg_write(apic, reg, (u32)data);
1989 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1991 struct kvm_lapic *apic = vcpu->arch.apic;
1992 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1994 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1997 if (reg == APIC_DFR || reg == APIC_ICR2) {
1998 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2003 if (apic_reg_read(apic, reg, 4, &low))
2005 if (reg == APIC_ICR)
2006 apic_reg_read(apic, APIC_ICR2, 4, &high);
2008 *data = (((u64)high) << 32) | low;
2013 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2015 struct kvm_lapic *apic = vcpu->arch.apic;
2017 if (!kvm_vcpu_has_lapic(vcpu))
2020 /* if this is ICR write vector before command */
2021 if (reg == APIC_ICR)
2022 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2023 return apic_reg_write(apic, reg, (u32)data);
2026 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2028 struct kvm_lapic *apic = vcpu->arch.apic;
2031 if (!kvm_vcpu_has_lapic(vcpu))
2034 if (apic_reg_read(apic, reg, 4, &low))
2036 if (reg == APIC_ICR)
2037 apic_reg_read(apic, APIC_ICR2, 4, &high);
2039 *data = (((u64)high) << 32) | low;
2044 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2046 u64 addr = data & ~KVM_MSR_ENABLED;
2047 if (!IS_ALIGNED(addr, 4))
2050 vcpu->arch.pv_eoi.msr_val = data;
2051 if (!pv_eoi_enabled(vcpu))
2053 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2057 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2059 struct kvm_lapic *apic = vcpu->arch.apic;
2063 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2067 * INITs are latched while in SMM. Because an SMM CPU cannot
2068 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2069 * and delay processing of INIT until the next RSM.
2072 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2073 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2074 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2078 pe = xchg(&apic->pending_events, 0);
2079 if (test_bit(KVM_APIC_INIT, &pe)) {
2080 kvm_lapic_reset(vcpu, true);
2081 kvm_vcpu_reset(vcpu, true);
2082 if (kvm_vcpu_is_bsp(apic->vcpu))
2083 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2085 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2087 if (test_bit(KVM_APIC_SIPI, &pe) &&
2088 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2089 /* evaluate pending_events before reading the vector */
2091 sipi_vector = apic->sipi_vector;
2092 apic_debug("vcpu %d received sipi with vector # %x\n",
2093 vcpu->vcpu_id, sipi_vector);
2094 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2095 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2099 void kvm_lapic_init(void)
2101 /* do not patch jump label more than once per second */
2102 jump_label_rate_limit(&apic_hw_disabled, HZ);
2103 jump_label_rate_limit(&apic_sw_disabled, HZ);