2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
202 struct kvm_mmu_page *sp = page_header(__pa(sptep));
204 access &= ACC_WRITE_MASK | ACC_USER_MASK;
206 sp->mmio_cached = true;
207 trace_mark_mmio_spte(sptep, gfn, access);
208 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
211 static bool is_mmio_spte(u64 spte)
213 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
216 static gfn_t get_mmio_spte_gfn(u64 spte)
218 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
221 static unsigned get_mmio_spte_access(u64 spte)
223 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
226 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
228 if (unlikely(is_noslot_pfn(pfn))) {
229 mark_mmio_spte(sptep, gfn, access);
236 static inline u64 rsvd_bits(int s, int e)
238 return ((1ULL << (e - s + 1)) - 1) << s;
241 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
242 u64 dirty_mask, u64 nx_mask, u64 x_mask)
244 shadow_user_mask = user_mask;
245 shadow_accessed_mask = accessed_mask;
246 shadow_dirty_mask = dirty_mask;
247 shadow_nx_mask = nx_mask;
248 shadow_x_mask = x_mask;
250 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
252 static int is_cpuid_PSE36(void)
257 static int is_nx(struct kvm_vcpu *vcpu)
259 return vcpu->arch.efer & EFER_NX;
262 static int is_shadow_present_pte(u64 pte)
264 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
267 static int is_large_pte(u64 pte)
269 return pte & PT_PAGE_SIZE_MASK;
272 static int is_dirty_gpte(unsigned long pte)
274 return pte & PT_DIRTY_MASK;
277 static int is_rmap_spte(u64 pte)
279 return is_shadow_present_pte(pte);
282 static int is_last_spte(u64 pte, int level)
284 if (level == PT_PAGE_TABLE_LEVEL)
286 if (is_large_pte(pte))
291 static pfn_t spte_to_pfn(u64 pte)
293 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
296 static gfn_t pse36_gfn_delta(u32 gpte)
298 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
300 return (gpte & PT32_DIR_PSE36_MASK) << shift;
304 static void __set_spte(u64 *sptep, u64 spte)
309 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
314 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
316 return xchg(sptep, spte);
319 static u64 __get_spte_lockless(u64 *sptep)
321 return ACCESS_ONCE(*sptep);
324 static bool __check_direct_spte_mmio_pf(u64 spte)
326 /* It is valid if the spte is zapped. */
338 static void count_spte_clear(u64 *sptep, u64 spte)
340 struct kvm_mmu_page *sp = page_header(__pa(sptep));
342 if (is_shadow_present_pte(spte))
345 /* Ensure the spte is completely set before we increase the count */
347 sp->clear_spte_count++;
350 static void __set_spte(u64 *sptep, u64 spte)
352 union split_spte *ssptep, sspte;
354 ssptep = (union split_spte *)sptep;
355 sspte = (union split_spte)spte;
357 ssptep->spte_high = sspte.spte_high;
360 * If we map the spte from nonpresent to present, We should store
361 * the high bits firstly, then set present bit, so cpu can not
362 * fetch this spte while we are setting the spte.
366 ssptep->spte_low = sspte.spte_low;
369 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
371 union split_spte *ssptep, sspte;
373 ssptep = (union split_spte *)sptep;
374 sspte = (union split_spte)spte;
376 ssptep->spte_low = sspte.spte_low;
379 * If we map the spte from present to nonpresent, we should clear
380 * present bit firstly to avoid vcpu fetch the old high bits.
384 ssptep->spte_high = sspte.spte_high;
385 count_spte_clear(sptep, spte);
388 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
390 union split_spte *ssptep, sspte, orig;
392 ssptep = (union split_spte *)sptep;
393 sspte = (union split_spte)spte;
395 /* xchg acts as a barrier before the setting of the high bits */
396 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
397 orig.spte_high = ssptep->spte_high;
398 ssptep->spte_high = sspte.spte_high;
399 count_spte_clear(sptep, spte);
405 * The idea using the light way get the spte on x86_32 guest is from
406 * gup_get_pte(arch/x86/mm/gup.c).
407 * The difference is we can not catch the spte tlb flush if we leave
408 * guest mode, so we emulate it by increase clear_spte_count when spte
411 static u64 __get_spte_lockless(u64 *sptep)
413 struct kvm_mmu_page *sp = page_header(__pa(sptep));
414 union split_spte spte, *orig = (union split_spte *)sptep;
418 count = sp->clear_spte_count;
421 spte.spte_low = orig->spte_low;
424 spte.spte_high = orig->spte_high;
427 if (unlikely(spte.spte_low != orig->spte_low ||
428 count != sp->clear_spte_count))
434 static bool __check_direct_spte_mmio_pf(u64 spte)
436 union split_spte sspte = (union split_spte)spte;
437 u32 high_mmio_mask = shadow_mmio_mask >> 32;
439 /* It is valid if the spte is zapped. */
443 /* It is valid if the spte is being zapped. */
444 if (sspte.spte_low == 0ull &&
445 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
452 static bool spte_is_locklessly_modifiable(u64 spte)
454 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
455 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
458 static bool spte_has_volatile_bits(u64 spte)
461 * Always atomicly update spte if it can be updated
462 * out of mmu-lock, it can ensure dirty bit is not lost,
463 * also, it can help us to get a stable is_writable_pte()
464 * to ensure tlb flush is not missed.
466 if (spte_is_locklessly_modifiable(spte))
469 if (!shadow_accessed_mask)
472 if (!is_shadow_present_pte(spte))
475 if ((spte & shadow_accessed_mask) &&
476 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
482 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
484 return (old_spte & bit_mask) && !(new_spte & bit_mask);
487 /* Rules for using mmu_spte_set:
488 * Set the sptep from nonpresent to present.
489 * Note: the sptep being assigned *must* be either not present
490 * or in a state where the hardware will not attempt to update
493 static void mmu_spte_set(u64 *sptep, u64 new_spte)
495 WARN_ON(is_shadow_present_pte(*sptep));
496 __set_spte(sptep, new_spte);
499 /* Rules for using mmu_spte_update:
500 * Update the state bits, it means the mapped pfn is not changged.
502 * Whenever we overwrite a writable spte with a read-only one we
503 * should flush remote TLBs. Otherwise rmap_write_protect
504 * will find a read-only spte, even though the writable spte
505 * might be cached on a CPU's TLB, the return value indicates this
508 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
510 u64 old_spte = *sptep;
513 WARN_ON(!is_rmap_spte(new_spte));
515 if (!is_shadow_present_pte(old_spte)) {
516 mmu_spte_set(sptep, new_spte);
520 if (!spte_has_volatile_bits(old_spte))
521 __update_clear_spte_fast(sptep, new_spte);
523 old_spte = __update_clear_spte_slow(sptep, new_spte);
526 * For the spte updated out of mmu-lock is safe, since
527 * we always atomicly update it, see the comments in
528 * spte_has_volatile_bits().
530 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
533 if (!shadow_accessed_mask)
536 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
537 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
538 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
539 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
545 * Rules for using mmu_spte_clear_track_bits:
546 * It sets the sptep from present to nonpresent, and track the
547 * state bits, it is used to clear the last level sptep.
549 static int mmu_spte_clear_track_bits(u64 *sptep)
552 u64 old_spte = *sptep;
554 if (!spte_has_volatile_bits(old_spte))
555 __update_clear_spte_fast(sptep, 0ull);
557 old_spte = __update_clear_spte_slow(sptep, 0ull);
559 if (!is_rmap_spte(old_spte))
562 pfn = spte_to_pfn(old_spte);
565 * KVM does not hold the refcount of the page used by
566 * kvm mmu, before reclaiming the page, we should
567 * unmap it from mmu first.
569 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
571 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
572 kvm_set_pfn_accessed(pfn);
573 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
574 kvm_set_pfn_dirty(pfn);
579 * Rules for using mmu_spte_clear_no_track:
580 * Directly clear spte without caring the state bits of sptep,
581 * it is used to set the upper level spte.
583 static void mmu_spte_clear_no_track(u64 *sptep)
585 __update_clear_spte_fast(sptep, 0ull);
588 static u64 mmu_spte_get_lockless(u64 *sptep)
590 return __get_spte_lockless(sptep);
593 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
596 * Prevent page table teardown by making any free-er wait during
597 * kvm_flush_remote_tlbs() IPI to all active vcpus.
600 vcpu->mode = READING_SHADOW_PAGE_TABLES;
602 * Make sure a following spte read is not reordered ahead of the write
608 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
611 * Make sure the write to vcpu->mode is not reordered in front of
612 * reads to sptes. If it does, kvm_commit_zap_page() can see us
613 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
616 vcpu->mode = OUTSIDE_GUEST_MODE;
620 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
621 struct kmem_cache *base_cache, int min)
625 if (cache->nobjs >= min)
627 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
628 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
631 cache->objects[cache->nobjs++] = obj;
636 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
641 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
642 struct kmem_cache *cache)
645 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
648 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
653 if (cache->nobjs >= min)
655 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
656 page = (void *)__get_free_page(GFP_KERNEL);
659 cache->objects[cache->nobjs++] = page;
664 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
667 free_page((unsigned long)mc->objects[--mc->nobjs]);
670 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
674 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
675 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
678 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
681 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
682 mmu_page_header_cache, 4);
687 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
689 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
690 pte_list_desc_cache);
691 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
692 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
693 mmu_page_header_cache);
696 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
701 p = mc->objects[--mc->nobjs];
705 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
707 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
710 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
712 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
715 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
717 if (!sp->role.direct)
718 return sp->gfns[index];
720 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
723 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
726 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
728 sp->gfns[index] = gfn;
732 * Return the pointer to the large page information for a given gfn,
733 * handling slots that are not large page aligned.
735 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
736 struct kvm_memory_slot *slot,
741 idx = gfn_to_index(gfn, slot->base_gfn, level);
742 return &slot->arch.lpage_info[level - 2][idx];
745 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
747 struct kvm_memory_slot *slot;
748 struct kvm_lpage_info *linfo;
751 slot = gfn_to_memslot(kvm, gfn);
752 for (i = PT_DIRECTORY_LEVEL;
753 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
754 linfo = lpage_info_slot(gfn, slot, i);
755 linfo->write_count += 1;
757 kvm->arch.indirect_shadow_pages++;
760 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
762 struct kvm_memory_slot *slot;
763 struct kvm_lpage_info *linfo;
766 slot = gfn_to_memslot(kvm, gfn);
767 for (i = PT_DIRECTORY_LEVEL;
768 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
769 linfo = lpage_info_slot(gfn, slot, i);
770 linfo->write_count -= 1;
771 WARN_ON(linfo->write_count < 0);
773 kvm->arch.indirect_shadow_pages--;
776 static int has_wrprotected_page(struct kvm *kvm,
780 struct kvm_memory_slot *slot;
781 struct kvm_lpage_info *linfo;
783 slot = gfn_to_memslot(kvm, gfn);
785 linfo = lpage_info_slot(gfn, slot, level);
786 return linfo->write_count;
792 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
794 unsigned long page_size;
797 page_size = kvm_host_page_size(kvm, gfn);
799 for (i = PT_PAGE_TABLE_LEVEL;
800 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
801 if (page_size >= KVM_HPAGE_SIZE(i))
810 static struct kvm_memory_slot *
811 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
814 struct kvm_memory_slot *slot;
816 slot = gfn_to_memslot(vcpu->kvm, gfn);
817 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
818 (no_dirty_log && slot->dirty_bitmap))
824 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
826 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
829 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
831 int host_level, level, max_level;
833 host_level = host_mapping_level(vcpu->kvm, large_gfn);
835 if (host_level == PT_PAGE_TABLE_LEVEL)
838 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
840 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
841 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
848 * Pte mapping structures:
850 * If pte_list bit zero is zero, then pte_list point to the spte.
852 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
853 * pte_list_desc containing more mappings.
855 * Returns the number of pte entries before the spte was added or zero if
856 * the spte was not added.
859 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
860 unsigned long *pte_list)
862 struct pte_list_desc *desc;
866 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
867 *pte_list = (unsigned long)spte;
868 } else if (!(*pte_list & 1)) {
869 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
870 desc = mmu_alloc_pte_list_desc(vcpu);
871 desc->sptes[0] = (u64 *)*pte_list;
872 desc->sptes[1] = spte;
873 *pte_list = (unsigned long)desc | 1;
876 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
877 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
878 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
880 count += PTE_LIST_EXT;
882 if (desc->sptes[PTE_LIST_EXT-1]) {
883 desc->more = mmu_alloc_pte_list_desc(vcpu);
886 for (i = 0; desc->sptes[i]; ++i)
888 desc->sptes[i] = spte;
894 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
895 int i, struct pte_list_desc *prev_desc)
899 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
901 desc->sptes[i] = desc->sptes[j];
902 desc->sptes[j] = NULL;
905 if (!prev_desc && !desc->more)
906 *pte_list = (unsigned long)desc->sptes[0];
909 prev_desc->more = desc->more;
911 *pte_list = (unsigned long)desc->more | 1;
912 mmu_free_pte_list_desc(desc);
915 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
917 struct pte_list_desc *desc;
918 struct pte_list_desc *prev_desc;
922 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
924 } else if (!(*pte_list & 1)) {
925 rmap_printk("pte_list_remove: %p 1->0\n", spte);
926 if ((u64 *)*pte_list != spte) {
927 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
932 rmap_printk("pte_list_remove: %p many->many\n", spte);
933 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
936 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
937 if (desc->sptes[i] == spte) {
938 pte_list_desc_remove_entry(pte_list,
946 pr_err("pte_list_remove: %p many->many\n", spte);
951 typedef void (*pte_list_walk_fn) (u64 *spte);
952 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
954 struct pte_list_desc *desc;
960 if (!(*pte_list & 1))
961 return fn((u64 *)*pte_list);
963 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
965 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
971 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
972 struct kvm_memory_slot *slot)
976 idx = gfn_to_index(gfn, slot->base_gfn, level);
977 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
981 * Take gfn and return the reverse mapping to it.
983 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
985 struct kvm_memory_slot *slot;
987 slot = gfn_to_memslot(kvm, gfn);
988 return __gfn_to_rmap(gfn, level, slot);
991 static bool rmap_can_add(struct kvm_vcpu *vcpu)
993 struct kvm_mmu_memory_cache *cache;
995 cache = &vcpu->arch.mmu_pte_list_desc_cache;
996 return mmu_memory_cache_free_objects(cache);
999 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1001 struct kvm_mmu_page *sp;
1002 unsigned long *rmapp;
1004 sp = page_header(__pa(spte));
1005 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1006 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1007 return pte_list_add(vcpu, spte, rmapp);
1010 static void rmap_remove(struct kvm *kvm, u64 *spte)
1012 struct kvm_mmu_page *sp;
1014 unsigned long *rmapp;
1016 sp = page_header(__pa(spte));
1017 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1018 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1019 pte_list_remove(spte, rmapp);
1023 * Used by the following functions to iterate through the sptes linked by a
1024 * rmap. All fields are private and not assumed to be used outside.
1026 struct rmap_iterator {
1027 /* private fields */
1028 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1029 int pos; /* index of the sptep */
1033 * Iteration must be started by this function. This should also be used after
1034 * removing/dropping sptes from the rmap link because in such cases the
1035 * information in the itererator may not be valid.
1037 * Returns sptep if found, NULL otherwise.
1039 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1049 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1051 return iter->desc->sptes[iter->pos];
1055 * Must be used with a valid iterator: e.g. after rmap_get_first().
1057 * Returns sptep if found, NULL otherwise.
1059 static u64 *rmap_get_next(struct rmap_iterator *iter)
1062 if (iter->pos < PTE_LIST_EXT - 1) {
1066 sptep = iter->desc->sptes[iter->pos];
1071 iter->desc = iter->desc->more;
1075 /* desc->sptes[0] cannot be NULL */
1076 return iter->desc->sptes[iter->pos];
1083 static void drop_spte(struct kvm *kvm, u64 *sptep)
1085 if (mmu_spte_clear_track_bits(sptep))
1086 rmap_remove(kvm, sptep);
1090 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1092 if (is_large_pte(*sptep)) {
1093 WARN_ON(page_header(__pa(sptep))->role.level ==
1094 PT_PAGE_TABLE_LEVEL);
1095 drop_spte(kvm, sptep);
1103 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1105 if (__drop_large_spte(vcpu->kvm, sptep))
1106 kvm_flush_remote_tlbs(vcpu->kvm);
1110 * Write-protect on the specified @sptep, @pt_protect indicates whether
1111 * spte writ-protection is caused by protecting shadow page table.
1112 * @flush indicates whether tlb need be flushed.
1114 * Note: write protection is difference between drity logging and spte
1116 * - for dirty logging, the spte can be set to writable at anytime if
1117 * its dirty bitmap is properly set.
1118 * - for spte protection, the spte can be writable only after unsync-ing
1121 * Return true if the spte is dropped.
1124 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1128 if (!is_writable_pte(spte) &&
1129 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1132 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1134 if (__drop_large_spte(kvm, sptep)) {
1140 spte &= ~SPTE_MMU_WRITEABLE;
1141 spte = spte & ~PT_WRITABLE_MASK;
1143 *flush |= mmu_spte_update(sptep, spte);
1147 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1151 struct rmap_iterator iter;
1154 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1155 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1156 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1157 sptep = rmap_get_first(*rmapp, &iter);
1161 sptep = rmap_get_next(&iter);
1168 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1169 * @kvm: kvm instance
1170 * @slot: slot to protect
1171 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1172 * @mask: indicates which pages we should protect
1174 * Used when we do not need to care about huge page mappings: e.g. during dirty
1175 * logging we do not have any such mappings.
1177 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1178 struct kvm_memory_slot *slot,
1179 gfn_t gfn_offset, unsigned long mask)
1181 unsigned long *rmapp;
1184 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1185 PT_PAGE_TABLE_LEVEL, slot);
1186 __rmap_write_protect(kvm, rmapp, false);
1188 /* clear the first set bit */
1193 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1195 struct kvm_memory_slot *slot;
1196 unsigned long *rmapp;
1198 bool write_protected = false;
1200 slot = gfn_to_memslot(kvm, gfn);
1202 for (i = PT_PAGE_TABLE_LEVEL;
1203 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1204 rmapp = __gfn_to_rmap(gfn, i, slot);
1205 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1208 return write_protected;
1211 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1212 struct kvm_memory_slot *slot, unsigned long data)
1215 struct rmap_iterator iter;
1216 int need_tlb_flush = 0;
1218 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1219 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1220 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1222 drop_spte(kvm, sptep);
1226 return need_tlb_flush;
1229 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1230 struct kvm_memory_slot *slot, unsigned long data)
1233 struct rmap_iterator iter;
1236 pte_t *ptep = (pte_t *)data;
1239 WARN_ON(pte_huge(*ptep));
1240 new_pfn = pte_pfn(*ptep);
1242 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1243 BUG_ON(!is_shadow_present_pte(*sptep));
1244 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1248 if (pte_write(*ptep)) {
1249 drop_spte(kvm, sptep);
1250 sptep = rmap_get_first(*rmapp, &iter);
1252 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1253 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1255 new_spte &= ~PT_WRITABLE_MASK;
1256 new_spte &= ~SPTE_HOST_WRITEABLE;
1257 new_spte &= ~shadow_accessed_mask;
1259 mmu_spte_clear_track_bits(sptep);
1260 mmu_spte_set(sptep, new_spte);
1261 sptep = rmap_get_next(&iter);
1266 kvm_flush_remote_tlbs(kvm);
1271 static int kvm_handle_hva_range(struct kvm *kvm,
1272 unsigned long start,
1275 int (*handler)(struct kvm *kvm,
1276 unsigned long *rmapp,
1277 struct kvm_memory_slot *slot,
1278 unsigned long data))
1282 struct kvm_memslots *slots;
1283 struct kvm_memory_slot *memslot;
1285 slots = kvm_memslots(kvm);
1287 kvm_for_each_memslot(memslot, slots) {
1288 unsigned long hva_start, hva_end;
1289 gfn_t gfn_start, gfn_end;
1291 hva_start = max(start, memslot->userspace_addr);
1292 hva_end = min(end, memslot->userspace_addr +
1293 (memslot->npages << PAGE_SHIFT));
1294 if (hva_start >= hva_end)
1297 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1298 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1300 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1301 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1303 for (j = PT_PAGE_TABLE_LEVEL;
1304 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1305 unsigned long idx, idx_end;
1306 unsigned long *rmapp;
1309 * {idx(page_j) | page_j intersects with
1310 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1312 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1313 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1315 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1317 for (; idx <= idx_end; ++idx)
1318 ret |= handler(kvm, rmapp++, memslot, data);
1325 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1327 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1328 struct kvm_memory_slot *slot,
1329 unsigned long data))
1331 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1334 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1336 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1339 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1341 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1344 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1346 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1349 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1350 struct kvm_memory_slot *slot, unsigned long data)
1353 struct rmap_iterator uninitialized_var(iter);
1357 * In case of absence of EPT Access and Dirty Bits supports,
1358 * emulate the accessed bit for EPT, by checking if this page has
1359 * an EPT mapping, and clearing it if it does. On the next access,
1360 * a new EPT mapping will be established.
1361 * This has some overhead, but not as much as the cost of swapping
1362 * out actively used pages or breaking up actively used hugepages.
1364 if (!shadow_accessed_mask) {
1365 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1369 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1370 sptep = rmap_get_next(&iter)) {
1371 BUG_ON(!is_shadow_present_pte(*sptep));
1373 if (*sptep & shadow_accessed_mask) {
1375 clear_bit((ffs(shadow_accessed_mask) - 1),
1376 (unsigned long *)sptep);
1380 /* @data has hva passed to kvm_age_hva(). */
1381 trace_kvm_age_page(data, slot, young);
1385 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1386 struct kvm_memory_slot *slot, unsigned long data)
1389 struct rmap_iterator iter;
1393 * If there's no access bit in the secondary pte set by the
1394 * hardware it's up to gup-fast/gup to set the access bit in
1395 * the primary pte or in the page structure.
1397 if (!shadow_accessed_mask)
1400 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1401 sptep = rmap_get_next(&iter)) {
1402 BUG_ON(!is_shadow_present_pte(*sptep));
1404 if (*sptep & shadow_accessed_mask) {
1413 #define RMAP_RECYCLE_THRESHOLD 1000
1415 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1417 unsigned long *rmapp;
1418 struct kvm_mmu_page *sp;
1420 sp = page_header(__pa(spte));
1422 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1424 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1425 kvm_flush_remote_tlbs(vcpu->kvm);
1428 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1430 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1433 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1435 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1439 static int is_empty_shadow_page(u64 *spt)
1444 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1445 if (is_shadow_present_pte(*pos)) {
1446 printk(KERN_ERR "%s: %p %llx\n", __func__,
1455 * This value is the sum of all of the kvm instances's
1456 * kvm->arch.n_used_mmu_pages values. We need a global,
1457 * aggregate version in order to make the slab shrinker
1460 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1462 kvm->arch.n_used_mmu_pages += nr;
1463 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1466 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1468 ASSERT(is_empty_shadow_page(sp->spt));
1469 hlist_del(&sp->hash_link);
1470 list_del(&sp->link);
1471 free_page((unsigned long)sp->spt);
1472 if (!sp->role.direct)
1473 free_page((unsigned long)sp->gfns);
1474 kmem_cache_free(mmu_page_header_cache, sp);
1477 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1479 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1482 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1483 struct kvm_mmu_page *sp, u64 *parent_pte)
1488 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1491 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1494 pte_list_remove(parent_pte, &sp->parent_ptes);
1497 static void drop_parent_pte(struct kvm_mmu_page *sp,
1500 mmu_page_remove_parent_pte(sp, parent_pte);
1501 mmu_spte_clear_no_track(parent_pte);
1504 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
1506 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1507 u64 *parent_pte, int direct)
1509 struct kvm_mmu_page *sp;
1511 make_mmu_pages_available(vcpu);
1513 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1514 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1516 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1517 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1518 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1519 sp->parent_ptes = 0;
1520 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1521 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1525 static void mark_unsync(u64 *spte);
1526 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1528 pte_list_walk(&sp->parent_ptes, mark_unsync);
1531 static void mark_unsync(u64 *spte)
1533 struct kvm_mmu_page *sp;
1536 sp = page_header(__pa(spte));
1537 index = spte - sp->spt;
1538 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1540 if (sp->unsync_children++)
1542 kvm_mmu_mark_parents_unsync(sp);
1545 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1546 struct kvm_mmu_page *sp)
1551 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1555 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1556 struct kvm_mmu_page *sp, u64 *spte,
1562 #define KVM_PAGE_ARRAY_NR 16
1564 struct kvm_mmu_pages {
1565 struct mmu_page_and_offset {
1566 struct kvm_mmu_page *sp;
1568 } page[KVM_PAGE_ARRAY_NR];
1572 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1578 for (i=0; i < pvec->nr; i++)
1579 if (pvec->page[i].sp == sp)
1582 pvec->page[pvec->nr].sp = sp;
1583 pvec->page[pvec->nr].idx = idx;
1585 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1588 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1589 struct kvm_mmu_pages *pvec)
1591 int i, ret, nr_unsync_leaf = 0;
1593 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1594 struct kvm_mmu_page *child;
1595 u64 ent = sp->spt[i];
1597 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1598 goto clear_child_bitmap;
1600 child = page_header(ent & PT64_BASE_ADDR_MASK);
1602 if (child->unsync_children) {
1603 if (mmu_pages_add(pvec, child, i))
1606 ret = __mmu_unsync_walk(child, pvec);
1608 goto clear_child_bitmap;
1610 nr_unsync_leaf += ret;
1613 } else if (child->unsync) {
1615 if (mmu_pages_add(pvec, child, i))
1618 goto clear_child_bitmap;
1623 __clear_bit(i, sp->unsync_child_bitmap);
1624 sp->unsync_children--;
1625 WARN_ON((int)sp->unsync_children < 0);
1629 return nr_unsync_leaf;
1632 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1633 struct kvm_mmu_pages *pvec)
1635 if (!sp->unsync_children)
1638 mmu_pages_add(pvec, sp, 0);
1639 return __mmu_unsync_walk(sp, pvec);
1642 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1644 WARN_ON(!sp->unsync);
1645 trace_kvm_mmu_sync_page(sp);
1647 --kvm->stat.mmu_unsync;
1650 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1651 struct list_head *invalid_list);
1652 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1653 struct list_head *invalid_list);
1655 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1656 hlist_for_each_entry(_sp, \
1657 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1658 if ((_sp)->gfn != (_gfn)) {} else
1660 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1661 for_each_gfn_sp(_kvm, _sp, _gfn) \
1662 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1664 /* @sp->gfn should be write-protected at the call site */
1665 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1666 struct list_head *invalid_list, bool clear_unsync)
1668 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1669 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1674 kvm_unlink_unsync_page(vcpu->kvm, sp);
1676 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1677 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1681 kvm_mmu_flush_tlb(vcpu);
1685 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1686 struct kvm_mmu_page *sp)
1688 LIST_HEAD(invalid_list);
1691 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1693 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1698 #ifdef CONFIG_KVM_MMU_AUDIT
1699 #include "mmu_audit.c"
1701 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1702 static void mmu_audit_disable(void) { }
1705 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1706 struct list_head *invalid_list)
1708 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1711 /* @gfn should be write-protected at the call site */
1712 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1714 struct kvm_mmu_page *s;
1715 LIST_HEAD(invalid_list);
1718 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1722 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1723 kvm_unlink_unsync_page(vcpu->kvm, s);
1724 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1725 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1726 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1732 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1734 kvm_mmu_flush_tlb(vcpu);
1737 struct mmu_page_path {
1738 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1739 unsigned int idx[PT64_ROOT_LEVEL-1];
1742 #define for_each_sp(pvec, sp, parents, i) \
1743 for (i = mmu_pages_next(&pvec, &parents, -1), \
1744 sp = pvec.page[i].sp; \
1745 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1746 i = mmu_pages_next(&pvec, &parents, i))
1748 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1749 struct mmu_page_path *parents,
1754 for (n = i+1; n < pvec->nr; n++) {
1755 struct kvm_mmu_page *sp = pvec->page[n].sp;
1757 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1758 parents->idx[0] = pvec->page[n].idx;
1762 parents->parent[sp->role.level-2] = sp;
1763 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1769 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1771 struct kvm_mmu_page *sp;
1772 unsigned int level = 0;
1775 unsigned int idx = parents->idx[level];
1777 sp = parents->parent[level];
1781 --sp->unsync_children;
1782 WARN_ON((int)sp->unsync_children < 0);
1783 __clear_bit(idx, sp->unsync_child_bitmap);
1785 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1788 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1789 struct mmu_page_path *parents,
1790 struct kvm_mmu_pages *pvec)
1792 parents->parent[parent->role.level-1] = NULL;
1796 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1797 struct kvm_mmu_page *parent)
1800 struct kvm_mmu_page *sp;
1801 struct mmu_page_path parents;
1802 struct kvm_mmu_pages pages;
1803 LIST_HEAD(invalid_list);
1805 kvm_mmu_pages_init(parent, &parents, &pages);
1806 while (mmu_unsync_walk(parent, &pages)) {
1807 bool protected = false;
1809 for_each_sp(pages, sp, parents, i)
1810 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1813 kvm_flush_remote_tlbs(vcpu->kvm);
1815 for_each_sp(pages, sp, parents, i) {
1816 kvm_sync_page(vcpu, sp, &invalid_list);
1817 mmu_pages_clear_parents(&parents);
1819 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1820 cond_resched_lock(&vcpu->kvm->mmu_lock);
1821 kvm_mmu_pages_init(parent, &parents, &pages);
1825 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1829 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1833 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1835 sp->write_flooding_count = 0;
1838 static void clear_sp_write_flooding_count(u64 *spte)
1840 struct kvm_mmu_page *sp = page_header(__pa(spte));
1842 __clear_sp_write_flooding_count(sp);
1845 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1853 union kvm_mmu_page_role role;
1855 struct kvm_mmu_page *sp;
1856 bool need_sync = false;
1858 role = vcpu->arch.mmu.base_role;
1860 role.direct = direct;
1863 role.access = access;
1864 if (!vcpu->arch.mmu.direct_map
1865 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1866 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1867 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1868 role.quadrant = quadrant;
1870 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1871 if (!need_sync && sp->unsync)
1874 if (sp->role.word != role.word)
1877 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1880 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1881 if (sp->unsync_children) {
1882 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1883 kvm_mmu_mark_parents_unsync(sp);
1884 } else if (sp->unsync)
1885 kvm_mmu_mark_parents_unsync(sp);
1887 __clear_sp_write_flooding_count(sp);
1888 trace_kvm_mmu_get_page(sp, false);
1891 ++vcpu->kvm->stat.mmu_cache_miss;
1892 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1897 hlist_add_head(&sp->hash_link,
1898 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1900 if (rmap_write_protect(vcpu->kvm, gfn))
1901 kvm_flush_remote_tlbs(vcpu->kvm);
1902 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1903 kvm_sync_pages(vcpu, gfn);
1905 account_shadowed(vcpu->kvm, gfn);
1907 init_shadow_page_table(sp);
1908 trace_kvm_mmu_get_page(sp, true);
1912 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1913 struct kvm_vcpu *vcpu, u64 addr)
1915 iterator->addr = addr;
1916 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1917 iterator->level = vcpu->arch.mmu.shadow_root_level;
1919 if (iterator->level == PT64_ROOT_LEVEL &&
1920 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1921 !vcpu->arch.mmu.direct_map)
1924 if (iterator->level == PT32E_ROOT_LEVEL) {
1925 iterator->shadow_addr
1926 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1927 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1929 if (!iterator->shadow_addr)
1930 iterator->level = 0;
1934 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1936 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1939 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1940 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1944 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1947 if (is_last_spte(spte, iterator->level)) {
1948 iterator->level = 0;
1952 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1956 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1958 return __shadow_walk_next(iterator, *iterator->sptep);
1961 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1965 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
1966 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
1968 mmu_spte_set(sptep, spte);
1971 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1972 unsigned direct_access)
1974 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1975 struct kvm_mmu_page *child;
1978 * For the direct sp, if the guest pte's dirty bit
1979 * changed form clean to dirty, it will corrupt the
1980 * sp's access: allow writable in the read-only sp,
1981 * so we should update the spte at this point to get
1982 * a new sp with the correct access.
1984 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1985 if (child->role.access == direct_access)
1988 drop_parent_pte(child, sptep);
1989 kvm_flush_remote_tlbs(vcpu->kvm);
1993 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1997 struct kvm_mmu_page *child;
2000 if (is_shadow_present_pte(pte)) {
2001 if (is_last_spte(pte, sp->role.level)) {
2002 drop_spte(kvm, spte);
2003 if (is_large_pte(pte))
2006 child = page_header(pte & PT64_BASE_ADDR_MASK);
2007 drop_parent_pte(child, spte);
2012 if (is_mmio_spte(pte))
2013 mmu_spte_clear_no_track(spte);
2018 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2019 struct kvm_mmu_page *sp)
2023 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2024 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2027 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2029 mmu_page_remove_parent_pte(sp, parent_pte);
2032 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2035 struct rmap_iterator iter;
2037 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2038 drop_parent_pte(sp, sptep);
2041 static int mmu_zap_unsync_children(struct kvm *kvm,
2042 struct kvm_mmu_page *parent,
2043 struct list_head *invalid_list)
2046 struct mmu_page_path parents;
2047 struct kvm_mmu_pages pages;
2049 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2052 kvm_mmu_pages_init(parent, &parents, &pages);
2053 while (mmu_unsync_walk(parent, &pages)) {
2054 struct kvm_mmu_page *sp;
2056 for_each_sp(pages, sp, parents, i) {
2057 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2058 mmu_pages_clear_parents(&parents);
2061 kvm_mmu_pages_init(parent, &parents, &pages);
2067 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2068 struct list_head *invalid_list)
2072 trace_kvm_mmu_prepare_zap_page(sp);
2073 ++kvm->stat.mmu_shadow_zapped;
2074 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2075 kvm_mmu_page_unlink_children(kvm, sp);
2076 kvm_mmu_unlink_parents(kvm, sp);
2077 if (!sp->role.invalid && !sp->role.direct)
2078 unaccount_shadowed(kvm, sp->gfn);
2080 kvm_unlink_unsync_page(kvm, sp);
2081 if (!sp->root_count) {
2084 list_move(&sp->link, invalid_list);
2085 kvm_mod_used_mmu_pages(kvm, -1);
2087 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2088 kvm_reload_remote_mmus(kvm);
2091 sp->role.invalid = 1;
2095 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2096 struct list_head *invalid_list)
2098 struct kvm_mmu_page *sp, *nsp;
2100 if (list_empty(invalid_list))
2104 * wmb: make sure everyone sees our modifications to the page tables
2105 * rmb: make sure we see changes to vcpu->mode
2110 * Wait for all vcpus to exit guest mode and/or lockless shadow
2113 kvm_flush_remote_tlbs(kvm);
2115 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2116 WARN_ON(!sp->role.invalid || sp->root_count);
2117 kvm_mmu_free_page(sp);
2121 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2122 struct list_head *invalid_list)
2124 struct kvm_mmu_page *sp;
2126 if (list_empty(&kvm->arch.active_mmu_pages))
2129 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2130 struct kvm_mmu_page, link);
2131 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2137 * Changing the number of mmu pages allocated to the vm
2138 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2140 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2142 LIST_HEAD(invalid_list);
2144 spin_lock(&kvm->mmu_lock);
2146 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2147 /* Need to free some mmu pages to achieve the goal. */
2148 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2149 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2152 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2153 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2156 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2158 spin_unlock(&kvm->mmu_lock);
2161 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2163 struct kvm_mmu_page *sp;
2164 LIST_HEAD(invalid_list);
2167 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2169 spin_lock(&kvm->mmu_lock);
2170 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2171 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2174 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2176 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2177 spin_unlock(&kvm->mmu_lock);
2181 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2184 * The function is based on mtrr_type_lookup() in
2185 * arch/x86/kernel/cpu/mtrr/generic.c
2187 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2192 u8 prev_match, curr_match;
2193 int num_var_ranges = KVM_NR_VAR_MTRR;
2195 if (!mtrr_state->enabled)
2198 /* Make end inclusive end, instead of exclusive */
2201 /* Look in fixed ranges. Just return the type as per start */
2202 if (mtrr_state->have_fixed && (start < 0x100000)) {
2205 if (start < 0x80000) {
2207 idx += (start >> 16);
2208 return mtrr_state->fixed_ranges[idx];
2209 } else if (start < 0xC0000) {
2211 idx += ((start - 0x80000) >> 14);
2212 return mtrr_state->fixed_ranges[idx];
2213 } else if (start < 0x1000000) {
2215 idx += ((start - 0xC0000) >> 12);
2216 return mtrr_state->fixed_ranges[idx];
2221 * Look in variable ranges
2222 * Look of multiple ranges matching this address and pick type
2223 * as per MTRR precedence
2225 if (!(mtrr_state->enabled & 2))
2226 return mtrr_state->def_type;
2229 for (i = 0; i < num_var_ranges; ++i) {
2230 unsigned short start_state, end_state;
2232 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2235 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2236 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2237 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2238 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2240 start_state = ((start & mask) == (base & mask));
2241 end_state = ((end & mask) == (base & mask));
2242 if (start_state != end_state)
2245 if ((start & mask) != (base & mask))
2248 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2249 if (prev_match == 0xFF) {
2250 prev_match = curr_match;
2254 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2255 curr_match == MTRR_TYPE_UNCACHABLE)
2256 return MTRR_TYPE_UNCACHABLE;
2258 if ((prev_match == MTRR_TYPE_WRBACK &&
2259 curr_match == MTRR_TYPE_WRTHROUGH) ||
2260 (prev_match == MTRR_TYPE_WRTHROUGH &&
2261 curr_match == MTRR_TYPE_WRBACK)) {
2262 prev_match = MTRR_TYPE_WRTHROUGH;
2263 curr_match = MTRR_TYPE_WRTHROUGH;
2266 if (prev_match != curr_match)
2267 return MTRR_TYPE_UNCACHABLE;
2270 if (prev_match != 0xFF)
2273 return mtrr_state->def_type;
2276 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2280 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2281 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2282 if (mtrr == 0xfe || mtrr == 0xff)
2283 mtrr = MTRR_TYPE_WRBACK;
2286 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2288 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2290 trace_kvm_mmu_unsync_page(sp);
2291 ++vcpu->kvm->stat.mmu_unsync;
2294 kvm_mmu_mark_parents_unsync(sp);
2297 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2299 struct kvm_mmu_page *s;
2301 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2304 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2305 __kvm_unsync_page(vcpu, s);
2309 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2312 struct kvm_mmu_page *s;
2313 bool need_unsync = false;
2315 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2319 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2326 kvm_unsync_pages(vcpu, gfn);
2330 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2331 unsigned pte_access, int level,
2332 gfn_t gfn, pfn_t pfn, bool speculative,
2333 bool can_unsync, bool host_writable)
2338 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2341 spte = PT_PRESENT_MASK;
2343 spte |= shadow_accessed_mask;
2345 if (pte_access & ACC_EXEC_MASK)
2346 spte |= shadow_x_mask;
2348 spte |= shadow_nx_mask;
2350 if (pte_access & ACC_USER_MASK)
2351 spte |= shadow_user_mask;
2353 if (level > PT_PAGE_TABLE_LEVEL)
2354 spte |= PT_PAGE_SIZE_MASK;
2356 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2357 kvm_is_mmio_pfn(pfn));
2360 spte |= SPTE_HOST_WRITEABLE;
2362 pte_access &= ~ACC_WRITE_MASK;
2364 spte |= (u64)pfn << PAGE_SHIFT;
2366 if (pte_access & ACC_WRITE_MASK) {
2369 * Other vcpu creates new sp in the window between
2370 * mapping_level() and acquiring mmu-lock. We can
2371 * allow guest to retry the access, the mapping can
2372 * be fixed if guest refault.
2374 if (level > PT_PAGE_TABLE_LEVEL &&
2375 has_wrprotected_page(vcpu->kvm, gfn, level))
2378 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2381 * Optimization: for pte sync, if spte was writable the hash
2382 * lookup is unnecessary (and expensive). Write protection
2383 * is responsibility of mmu_get_page / kvm_sync_page.
2384 * Same reasoning can be applied to dirty page accounting.
2386 if (!can_unsync && is_writable_pte(*sptep))
2389 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2390 pgprintk("%s: found shadow page for %llx, marking ro\n",
2393 pte_access &= ~ACC_WRITE_MASK;
2394 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2398 if (pte_access & ACC_WRITE_MASK)
2399 mark_page_dirty(vcpu->kvm, gfn);
2402 if (mmu_spte_update(sptep, spte))
2403 kvm_flush_remote_tlbs(vcpu->kvm);
2408 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2409 unsigned pte_access, int write_fault, int *emulate,
2410 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2413 int was_rmapped = 0;
2416 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2417 *sptep, write_fault, gfn);
2419 if (is_rmap_spte(*sptep)) {
2421 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2422 * the parent of the now unreachable PTE.
2424 if (level > PT_PAGE_TABLE_LEVEL &&
2425 !is_large_pte(*sptep)) {
2426 struct kvm_mmu_page *child;
2429 child = page_header(pte & PT64_BASE_ADDR_MASK);
2430 drop_parent_pte(child, sptep);
2431 kvm_flush_remote_tlbs(vcpu->kvm);
2432 } else if (pfn != spte_to_pfn(*sptep)) {
2433 pgprintk("hfn old %llx new %llx\n",
2434 spte_to_pfn(*sptep), pfn);
2435 drop_spte(vcpu->kvm, sptep);
2436 kvm_flush_remote_tlbs(vcpu->kvm);
2441 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2442 true, host_writable)) {
2445 kvm_mmu_flush_tlb(vcpu);
2448 if (unlikely(is_mmio_spte(*sptep) && emulate))
2451 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2452 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2453 is_large_pte(*sptep)? "2MB" : "4kB",
2454 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2456 if (!was_rmapped && is_large_pte(*sptep))
2457 ++vcpu->kvm->stat.lpages;
2459 if (is_shadow_present_pte(*sptep)) {
2461 rmap_count = rmap_add(vcpu, sptep, gfn);
2462 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2463 rmap_recycle(vcpu, sptep, gfn);
2467 kvm_release_pfn_clean(pfn);
2470 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2472 mmu_free_roots(vcpu);
2475 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2479 bit7 = (gpte >> 7) & 1;
2480 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2483 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2486 struct kvm_memory_slot *slot;
2488 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2490 return KVM_PFN_ERR_FAULT;
2492 return gfn_to_pfn_memslot_atomic(slot, gfn);
2495 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2496 struct kvm_mmu_page *sp, u64 *spte,
2499 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2502 if (!is_present_gpte(gpte))
2505 if (!(gpte & PT_ACCESSED_MASK))
2511 drop_spte(vcpu->kvm, spte);
2515 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2516 struct kvm_mmu_page *sp,
2517 u64 *start, u64 *end)
2519 struct page *pages[PTE_PREFETCH_NUM];
2520 unsigned access = sp->role.access;
2524 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2525 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2528 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2532 for (i = 0; i < ret; i++, gfn++, start++)
2533 mmu_set_spte(vcpu, start, access, 0, NULL,
2534 sp->role.level, gfn, page_to_pfn(pages[i]),
2540 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2541 struct kvm_mmu_page *sp, u64 *sptep)
2543 u64 *spte, *start = NULL;
2546 WARN_ON(!sp->role.direct);
2548 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2551 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2552 if (is_shadow_present_pte(*spte) || spte == sptep) {
2555 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2563 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2565 struct kvm_mmu_page *sp;
2568 * Since it's no accessed bit on EPT, it's no way to
2569 * distinguish between actually accessed translations
2570 * and prefetched, so disable pte prefetch if EPT is
2573 if (!shadow_accessed_mask)
2576 sp = page_header(__pa(sptep));
2577 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2580 __direct_pte_prefetch(vcpu, sp, sptep);
2583 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2584 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2587 struct kvm_shadow_walk_iterator iterator;
2588 struct kvm_mmu_page *sp;
2592 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2593 if (iterator.level == level) {
2594 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2595 write, &emulate, level, gfn, pfn,
2596 prefault, map_writable);
2597 direct_pte_prefetch(vcpu, iterator.sptep);
2598 ++vcpu->stat.pf_fixed;
2602 if (!is_shadow_present_pte(*iterator.sptep)) {
2603 u64 base_addr = iterator.addr;
2605 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2606 pseudo_gfn = base_addr >> PAGE_SHIFT;
2607 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2609 1, ACC_ALL, iterator.sptep);
2611 link_shadow_page(iterator.sptep, sp);
2617 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2621 info.si_signo = SIGBUS;
2623 info.si_code = BUS_MCEERR_AR;
2624 info.si_addr = (void __user *)address;
2625 info.si_addr_lsb = PAGE_SHIFT;
2627 send_sig_info(SIGBUS, &info, tsk);
2630 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2633 * Do not cache the mmio info caused by writing the readonly gfn
2634 * into the spte otherwise read access on readonly gfn also can
2635 * caused mmio page fault and treat it as mmio access.
2636 * Return 1 to tell kvm to emulate it.
2638 if (pfn == KVM_PFN_ERR_RO_FAULT)
2641 if (pfn == KVM_PFN_ERR_HWPOISON) {
2642 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2649 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2650 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2654 int level = *levelp;
2657 * Check if it's a transparent hugepage. If this would be an
2658 * hugetlbfs page, level wouldn't be set to
2659 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2662 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2663 level == PT_PAGE_TABLE_LEVEL &&
2664 PageTransCompound(pfn_to_page(pfn)) &&
2665 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2668 * mmu_notifier_retry was successful and we hold the
2669 * mmu_lock here, so the pmd can't become splitting
2670 * from under us, and in turn
2671 * __split_huge_page_refcount() can't run from under
2672 * us and we can safely transfer the refcount from
2673 * PG_tail to PG_head as we switch the pfn to tail to
2676 *levelp = level = PT_DIRECTORY_LEVEL;
2677 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2678 VM_BUG_ON((gfn & mask) != (pfn & mask));
2682 kvm_release_pfn_clean(pfn);
2690 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2691 pfn_t pfn, unsigned access, int *ret_val)
2695 /* The pfn is invalid, report the error! */
2696 if (unlikely(is_error_pfn(pfn))) {
2697 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2701 if (unlikely(is_noslot_pfn(pfn)))
2702 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2709 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2712 * #PF can be fast only if the shadow page table is present and it
2713 * is caused by write-protect, that means we just need change the
2714 * W bit of the spte which can be done out of mmu-lock.
2716 if (!(error_code & PFERR_PRESENT_MASK) ||
2717 !(error_code & PFERR_WRITE_MASK))
2724 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2726 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2729 WARN_ON(!sp->role.direct);
2732 * The gfn of direct spte is stable since it is calculated
2735 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2737 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2738 mark_page_dirty(vcpu->kvm, gfn);
2745 * - true: let the vcpu to access on the same address again.
2746 * - false: let the real page fault path to fix it.
2748 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2751 struct kvm_shadow_walk_iterator iterator;
2755 if (!page_fault_can_be_fast(vcpu, error_code))
2758 walk_shadow_page_lockless_begin(vcpu);
2759 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2760 if (!is_shadow_present_pte(spte) || iterator.level < level)
2764 * If the mapping has been changed, let the vcpu fault on the
2765 * same address again.
2767 if (!is_rmap_spte(spte)) {
2772 if (!is_last_spte(spte, level))
2776 * Check if it is a spurious fault caused by TLB lazily flushed.
2778 * Need not check the access of upper level table entries since
2779 * they are always ACC_ALL.
2781 if (is_writable_pte(spte)) {
2787 * Currently, to simplify the code, only the spte write-protected
2788 * by dirty-log can be fast fixed.
2790 if (!spte_is_locklessly_modifiable(spte))
2794 * Currently, fast page fault only works for direct mapping since
2795 * the gfn is not stable for indirect shadow page.
2796 * See Documentation/virtual/kvm/locking.txt to get more detail.
2798 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2800 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2802 walk_shadow_page_lockless_end(vcpu);
2807 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2808 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2810 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2811 gfn_t gfn, bool prefault)
2817 unsigned long mmu_seq;
2818 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2820 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2821 if (likely(!force_pt_level)) {
2822 level = mapping_level(vcpu, gfn);
2824 * This path builds a PAE pagetable - so we can map
2825 * 2mb pages at maximum. Therefore check if the level
2826 * is larger than that.
2828 if (level > PT_DIRECTORY_LEVEL)
2829 level = PT_DIRECTORY_LEVEL;
2831 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2833 level = PT_PAGE_TABLE_LEVEL;
2835 if (fast_page_fault(vcpu, v, level, error_code))
2838 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2841 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2844 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2847 spin_lock(&vcpu->kvm->mmu_lock);
2848 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2850 if (likely(!force_pt_level))
2851 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2852 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2854 spin_unlock(&vcpu->kvm->mmu_lock);
2860 spin_unlock(&vcpu->kvm->mmu_lock);
2861 kvm_release_pfn_clean(pfn);
2866 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2869 struct kvm_mmu_page *sp;
2870 LIST_HEAD(invalid_list);
2872 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2874 spin_lock(&vcpu->kvm->mmu_lock);
2875 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2876 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2877 vcpu->arch.mmu.direct_map)) {
2878 hpa_t root = vcpu->arch.mmu.root_hpa;
2880 sp = page_header(root);
2882 if (!sp->root_count && sp->role.invalid) {
2883 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2884 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2886 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2887 spin_unlock(&vcpu->kvm->mmu_lock);
2890 for (i = 0; i < 4; ++i) {
2891 hpa_t root = vcpu->arch.mmu.pae_root[i];
2894 root &= PT64_BASE_ADDR_MASK;
2895 sp = page_header(root);
2897 if (!sp->root_count && sp->role.invalid)
2898 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2901 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2903 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2904 spin_unlock(&vcpu->kvm->mmu_lock);
2905 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2908 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2912 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2913 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2920 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2922 struct kvm_mmu_page *sp;
2925 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2926 spin_lock(&vcpu->kvm->mmu_lock);
2927 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2930 spin_unlock(&vcpu->kvm->mmu_lock);
2931 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2932 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2933 for (i = 0; i < 4; ++i) {
2934 hpa_t root = vcpu->arch.mmu.pae_root[i];
2936 ASSERT(!VALID_PAGE(root));
2937 spin_lock(&vcpu->kvm->mmu_lock);
2938 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2940 PT32_ROOT_LEVEL, 1, ACC_ALL,
2942 root = __pa(sp->spt);
2944 spin_unlock(&vcpu->kvm->mmu_lock);
2945 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2947 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2954 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2956 struct kvm_mmu_page *sp;
2961 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2963 if (mmu_check_root(vcpu, root_gfn))
2967 * Do we shadow a long mode page table? If so we need to
2968 * write-protect the guests page table root.
2970 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2971 hpa_t root = vcpu->arch.mmu.root_hpa;
2973 ASSERT(!VALID_PAGE(root));
2975 spin_lock(&vcpu->kvm->mmu_lock);
2976 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2978 root = __pa(sp->spt);
2980 spin_unlock(&vcpu->kvm->mmu_lock);
2981 vcpu->arch.mmu.root_hpa = root;
2986 * We shadow a 32 bit page table. This may be a legacy 2-level
2987 * or a PAE 3-level page table. In either case we need to be aware that
2988 * the shadow page table may be a PAE or a long mode page table.
2990 pm_mask = PT_PRESENT_MASK;
2991 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2992 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2994 for (i = 0; i < 4; ++i) {
2995 hpa_t root = vcpu->arch.mmu.pae_root[i];
2997 ASSERT(!VALID_PAGE(root));
2998 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2999 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3000 if (!is_present_gpte(pdptr)) {
3001 vcpu->arch.mmu.pae_root[i] = 0;
3004 root_gfn = pdptr >> PAGE_SHIFT;
3005 if (mmu_check_root(vcpu, root_gfn))
3008 spin_lock(&vcpu->kvm->mmu_lock);
3009 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3012 root = __pa(sp->spt);
3014 spin_unlock(&vcpu->kvm->mmu_lock);
3016 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3018 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3021 * If we shadow a 32 bit page table with a long mode page
3022 * table we enter this path.
3024 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3025 if (vcpu->arch.mmu.lm_root == NULL) {
3027 * The additional page necessary for this is only
3028 * allocated on demand.
3033 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3034 if (lm_root == NULL)
3037 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3039 vcpu->arch.mmu.lm_root = lm_root;
3042 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3048 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3050 if (vcpu->arch.mmu.direct_map)
3051 return mmu_alloc_direct_roots(vcpu);
3053 return mmu_alloc_shadow_roots(vcpu);
3056 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3059 struct kvm_mmu_page *sp;
3061 if (vcpu->arch.mmu.direct_map)
3064 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3067 vcpu_clear_mmio_info(vcpu, ~0ul);
3068 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3069 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3070 hpa_t root = vcpu->arch.mmu.root_hpa;
3071 sp = page_header(root);
3072 mmu_sync_children(vcpu, sp);
3073 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3076 for (i = 0; i < 4; ++i) {
3077 hpa_t root = vcpu->arch.mmu.pae_root[i];
3079 if (root && VALID_PAGE(root)) {
3080 root &= PT64_BASE_ADDR_MASK;
3081 sp = page_header(root);
3082 mmu_sync_children(vcpu, sp);
3085 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3088 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3090 spin_lock(&vcpu->kvm->mmu_lock);
3091 mmu_sync_roots(vcpu);
3092 spin_unlock(&vcpu->kvm->mmu_lock);
3095 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3096 u32 access, struct x86_exception *exception)
3099 exception->error_code = 0;
3103 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3105 struct x86_exception *exception)
3108 exception->error_code = 0;
3109 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3112 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3115 return vcpu_match_mmio_gpa(vcpu, addr);
3117 return vcpu_match_mmio_gva(vcpu, addr);
3122 * On direct hosts, the last spte is only allows two states
3123 * for mmio page fault:
3124 * - It is the mmio spte
3125 * - It is zapped or it is being zapped.
3127 * This function completely checks the spte when the last spte
3128 * is not the mmio spte.
3130 static bool check_direct_spte_mmio_pf(u64 spte)
3132 return __check_direct_spte_mmio_pf(spte);
3135 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3137 struct kvm_shadow_walk_iterator iterator;
3140 walk_shadow_page_lockless_begin(vcpu);
3141 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3142 if (!is_shadow_present_pte(spte))
3144 walk_shadow_page_lockless_end(vcpu);
3150 * If it is a real mmio page fault, return 1 and emulat the instruction
3151 * directly, return 0 to let CPU fault again on the address, -1 is
3152 * returned if bug is detected.
3154 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3158 if (quickly_check_mmio_pf(vcpu, addr, direct))
3161 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3163 if (is_mmio_spte(spte)) {
3164 gfn_t gfn = get_mmio_spte_gfn(spte);
3165 unsigned access = get_mmio_spte_access(spte);
3170 trace_handle_mmio_page_fault(addr, gfn, access);
3171 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3176 * It's ok if the gva is remapped by other cpus on shadow guest,
3177 * it's a BUG if the gfn is not a mmio page.
3179 if (direct && !check_direct_spte_mmio_pf(spte))
3183 * If the page table is zapped by other cpus, let CPU fault again on
3188 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3190 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3191 u32 error_code, bool direct)
3195 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3200 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3201 u32 error_code, bool prefault)
3206 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3208 if (unlikely(error_code & PFERR_RSVD_MASK))
3209 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3211 r = mmu_topup_memory_caches(vcpu);
3216 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3218 gfn = gva >> PAGE_SHIFT;
3220 return nonpaging_map(vcpu, gva & PAGE_MASK,
3221 error_code, gfn, prefault);
3224 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3226 struct kvm_arch_async_pf arch;
3228 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3230 arch.direct_map = vcpu->arch.mmu.direct_map;
3231 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3233 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3236 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3238 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3239 kvm_event_needs_reinjection(vcpu)))
3242 return kvm_x86_ops->interrupt_allowed(vcpu);
3245 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3246 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3250 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3253 return false; /* *pfn has correct page already */
3255 if (!prefault && can_do_async_pf(vcpu)) {
3256 trace_kvm_try_async_get_page(gva, gfn);
3257 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3258 trace_kvm_async_pf_doublefault(gva, gfn);
3259 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3261 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3265 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3270 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3277 gfn_t gfn = gpa >> PAGE_SHIFT;
3278 unsigned long mmu_seq;
3279 int write = error_code & PFERR_WRITE_MASK;
3283 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3285 if (unlikely(error_code & PFERR_RSVD_MASK))
3286 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3288 r = mmu_topup_memory_caches(vcpu);
3292 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3293 if (likely(!force_pt_level)) {
3294 level = mapping_level(vcpu, gfn);
3295 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3297 level = PT_PAGE_TABLE_LEVEL;
3299 if (fast_page_fault(vcpu, gpa, level, error_code))
3302 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3305 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3308 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3311 spin_lock(&vcpu->kvm->mmu_lock);
3312 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3314 if (likely(!force_pt_level))
3315 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3316 r = __direct_map(vcpu, gpa, write, map_writable,
3317 level, gfn, pfn, prefault);
3318 spin_unlock(&vcpu->kvm->mmu_lock);
3323 spin_unlock(&vcpu->kvm->mmu_lock);
3324 kvm_release_pfn_clean(pfn);
3328 static void nonpaging_free(struct kvm_vcpu *vcpu)
3330 mmu_free_roots(vcpu);
3333 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3334 struct kvm_mmu *context)
3336 context->new_cr3 = nonpaging_new_cr3;
3337 context->page_fault = nonpaging_page_fault;
3338 context->gva_to_gpa = nonpaging_gva_to_gpa;
3339 context->free = nonpaging_free;
3340 context->sync_page = nonpaging_sync_page;
3341 context->invlpg = nonpaging_invlpg;
3342 context->update_pte = nonpaging_update_pte;
3343 context->root_level = 0;
3344 context->shadow_root_level = PT32E_ROOT_LEVEL;
3345 context->root_hpa = INVALID_PAGE;
3346 context->direct_map = true;
3347 context->nx = false;
3351 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3353 ++vcpu->stat.tlb_flush;
3354 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3357 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3359 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3360 mmu_free_roots(vcpu);
3363 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3365 return kvm_read_cr3(vcpu);
3368 static void inject_page_fault(struct kvm_vcpu *vcpu,
3369 struct x86_exception *fault)
3371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3374 static void paging_free(struct kvm_vcpu *vcpu)
3376 nonpaging_free(vcpu);
3379 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3383 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3385 mask = (unsigned)~ACC_WRITE_MASK;
3386 /* Allow write access to dirty gptes */
3387 mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3391 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3394 if (unlikely(is_mmio_spte(*sptep))) {
3395 if (gfn != get_mmio_spte_gfn(*sptep)) {
3396 mmu_spte_clear_no_track(sptep);
3401 mark_mmio_spte(sptep, gfn, access);
3408 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3412 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3413 access &= ~(gpte >> PT64_NX_SHIFT);
3418 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3423 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3424 return mmu->last_pte_bitmap & (1 << index);
3428 #include "paging_tmpl.h"
3432 #include "paging_tmpl.h"
3435 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3436 struct kvm_mmu *context)
3438 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3439 u64 exb_bit_rsvd = 0;
3442 exb_bit_rsvd = rsvd_bits(63, 63);
3443 switch (context->root_level) {
3444 case PT32_ROOT_LEVEL:
3445 /* no rsvd bits for 2 level 4K page table entries */
3446 context->rsvd_bits_mask[0][1] = 0;
3447 context->rsvd_bits_mask[0][0] = 0;
3448 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3450 if (!is_pse(vcpu)) {
3451 context->rsvd_bits_mask[1][1] = 0;
3455 if (is_cpuid_PSE36())
3456 /* 36bits PSE 4MB page */
3457 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3459 /* 32 bits PSE 4MB page */
3460 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3462 case PT32E_ROOT_LEVEL:
3463 context->rsvd_bits_mask[0][2] =
3464 rsvd_bits(maxphyaddr, 63) |
3465 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3466 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3467 rsvd_bits(maxphyaddr, 62); /* PDE */
3468 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3469 rsvd_bits(maxphyaddr, 62); /* PTE */
3470 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3471 rsvd_bits(maxphyaddr, 62) |
3472 rsvd_bits(13, 20); /* large page */
3473 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3475 case PT64_ROOT_LEVEL:
3476 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3477 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3478 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3479 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3480 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3481 rsvd_bits(maxphyaddr, 51);
3482 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3483 rsvd_bits(maxphyaddr, 51);
3484 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3485 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3486 rsvd_bits(maxphyaddr, 51) |
3488 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3489 rsvd_bits(maxphyaddr, 51) |
3490 rsvd_bits(13, 20); /* large page */
3491 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3496 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3498 unsigned bit, byte, pfec;
3500 bool fault, x, w, u, wf, uf, ff, smep;
3502 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3503 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3506 wf = pfec & PFERR_WRITE_MASK;
3507 uf = pfec & PFERR_USER_MASK;
3508 ff = pfec & PFERR_FETCH_MASK;
3509 for (bit = 0; bit < 8; ++bit) {
3510 x = bit & ACC_EXEC_MASK;
3511 w = bit & ACC_WRITE_MASK;
3512 u = bit & ACC_USER_MASK;
3514 /* Not really needed: !nx will cause pte.nx to fault */
3516 /* Allow supervisor writes if !cr0.wp */
3517 w |= !is_write_protection(vcpu) && !uf;
3518 /* Disallow supervisor fetches of user code if cr4.smep */
3519 x &= !(smep && u && !uf);
3521 fault = (ff && !x) || (uf && !u) || (wf && !w);
3522 map |= fault << bit;
3524 mmu->permissions[byte] = map;
3528 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3531 unsigned level, root_level = mmu->root_level;
3532 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3534 if (root_level == PT32E_ROOT_LEVEL)
3536 /* PT_PAGE_TABLE_LEVEL always terminates */
3537 map = 1 | (1 << ps_set_index);
3538 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3539 if (level <= PT_PDPE_LEVEL
3540 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3541 map |= 1 << (ps_set_index | (level - 1));
3543 mmu->last_pte_bitmap = map;
3546 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3547 struct kvm_mmu *context,
3550 context->nx = is_nx(vcpu);
3551 context->root_level = level;
3553 reset_rsvds_bits_mask(vcpu, context);
3554 update_permission_bitmask(vcpu, context);
3555 update_last_pte_bitmap(vcpu, context);
3557 ASSERT(is_pae(vcpu));
3558 context->new_cr3 = paging_new_cr3;
3559 context->page_fault = paging64_page_fault;
3560 context->gva_to_gpa = paging64_gva_to_gpa;
3561 context->sync_page = paging64_sync_page;
3562 context->invlpg = paging64_invlpg;
3563 context->update_pte = paging64_update_pte;
3564 context->free = paging_free;
3565 context->shadow_root_level = level;
3566 context->root_hpa = INVALID_PAGE;
3567 context->direct_map = false;
3571 static int paging64_init_context(struct kvm_vcpu *vcpu,
3572 struct kvm_mmu *context)
3574 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3577 static int paging32_init_context(struct kvm_vcpu *vcpu,
3578 struct kvm_mmu *context)
3580 context->nx = false;
3581 context->root_level = PT32_ROOT_LEVEL;
3583 reset_rsvds_bits_mask(vcpu, context);
3584 update_permission_bitmask(vcpu, context);
3585 update_last_pte_bitmap(vcpu, context);
3587 context->new_cr3 = paging_new_cr3;
3588 context->page_fault = paging32_page_fault;
3589 context->gva_to_gpa = paging32_gva_to_gpa;
3590 context->free = paging_free;
3591 context->sync_page = paging32_sync_page;
3592 context->invlpg = paging32_invlpg;
3593 context->update_pte = paging32_update_pte;
3594 context->shadow_root_level = PT32E_ROOT_LEVEL;
3595 context->root_hpa = INVALID_PAGE;
3596 context->direct_map = false;
3600 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3601 struct kvm_mmu *context)
3603 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3606 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3608 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3610 context->base_role.word = 0;
3611 context->new_cr3 = nonpaging_new_cr3;
3612 context->page_fault = tdp_page_fault;
3613 context->free = nonpaging_free;
3614 context->sync_page = nonpaging_sync_page;
3615 context->invlpg = nonpaging_invlpg;
3616 context->update_pte = nonpaging_update_pte;
3617 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3618 context->root_hpa = INVALID_PAGE;
3619 context->direct_map = true;
3620 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3621 context->get_cr3 = get_cr3;
3622 context->get_pdptr = kvm_pdptr_read;
3623 context->inject_page_fault = kvm_inject_page_fault;
3625 if (!is_paging(vcpu)) {
3626 context->nx = false;
3627 context->gva_to_gpa = nonpaging_gva_to_gpa;
3628 context->root_level = 0;
3629 } else if (is_long_mode(vcpu)) {
3630 context->nx = is_nx(vcpu);
3631 context->root_level = PT64_ROOT_LEVEL;
3632 reset_rsvds_bits_mask(vcpu, context);
3633 context->gva_to_gpa = paging64_gva_to_gpa;
3634 } else if (is_pae(vcpu)) {
3635 context->nx = is_nx(vcpu);
3636 context->root_level = PT32E_ROOT_LEVEL;
3637 reset_rsvds_bits_mask(vcpu, context);
3638 context->gva_to_gpa = paging64_gva_to_gpa;
3640 context->nx = false;
3641 context->root_level = PT32_ROOT_LEVEL;
3642 reset_rsvds_bits_mask(vcpu, context);
3643 context->gva_to_gpa = paging32_gva_to_gpa;
3646 update_permission_bitmask(vcpu, context);
3647 update_last_pte_bitmap(vcpu, context);
3652 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3655 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3657 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3659 if (!is_paging(vcpu))
3660 r = nonpaging_init_context(vcpu, context);
3661 else if (is_long_mode(vcpu))
3662 r = paging64_init_context(vcpu, context);
3663 else if (is_pae(vcpu))
3664 r = paging32E_init_context(vcpu, context);
3666 r = paging32_init_context(vcpu, context);
3668 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3669 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3670 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3671 vcpu->arch.mmu.base_role.smep_andnot_wp
3672 = smep && !is_write_protection(vcpu);
3676 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3678 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3680 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3682 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3683 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3684 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3685 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3690 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3692 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3694 g_context->get_cr3 = get_cr3;
3695 g_context->get_pdptr = kvm_pdptr_read;
3696 g_context->inject_page_fault = kvm_inject_page_fault;
3699 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3700 * translation of l2_gpa to l1_gpa addresses is done using the
3701 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3702 * functions between mmu and nested_mmu are swapped.
3704 if (!is_paging(vcpu)) {
3705 g_context->nx = false;
3706 g_context->root_level = 0;
3707 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3708 } else if (is_long_mode(vcpu)) {
3709 g_context->nx = is_nx(vcpu);
3710 g_context->root_level = PT64_ROOT_LEVEL;
3711 reset_rsvds_bits_mask(vcpu, g_context);
3712 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3713 } else if (is_pae(vcpu)) {
3714 g_context->nx = is_nx(vcpu);
3715 g_context->root_level = PT32E_ROOT_LEVEL;
3716 reset_rsvds_bits_mask(vcpu, g_context);
3717 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3719 g_context->nx = false;
3720 g_context->root_level = PT32_ROOT_LEVEL;
3721 reset_rsvds_bits_mask(vcpu, g_context);
3722 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3725 update_permission_bitmask(vcpu, g_context);
3726 update_last_pte_bitmap(vcpu, g_context);
3731 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3733 if (mmu_is_nested(vcpu))
3734 return init_kvm_nested_mmu(vcpu);
3735 else if (tdp_enabled)
3736 return init_kvm_tdp_mmu(vcpu);
3738 return init_kvm_softmmu(vcpu);
3741 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3744 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3745 /* mmu.free() should set root_hpa = INVALID_PAGE */
3746 vcpu->arch.mmu.free(vcpu);
3749 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3751 destroy_kvm_mmu(vcpu);
3752 return init_kvm_mmu(vcpu);
3754 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3756 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3760 r = mmu_topup_memory_caches(vcpu);
3763 r = mmu_alloc_roots(vcpu);
3764 spin_lock(&vcpu->kvm->mmu_lock);
3765 mmu_sync_roots(vcpu);
3766 spin_unlock(&vcpu->kvm->mmu_lock);
3769 /* set_cr3() should ensure TLB has been flushed */
3770 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3774 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3776 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3778 mmu_free_roots(vcpu);
3780 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3782 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3783 struct kvm_mmu_page *sp, u64 *spte,
3786 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3787 ++vcpu->kvm->stat.mmu_pde_zapped;
3791 ++vcpu->kvm->stat.mmu_pte_updated;
3792 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3795 static bool need_remote_flush(u64 old, u64 new)
3797 if (!is_shadow_present_pte(old))
3799 if (!is_shadow_present_pte(new))
3801 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3803 old ^= PT64_NX_MASK;
3804 new ^= PT64_NX_MASK;
3805 return (old & ~new & PT64_PERM_MASK) != 0;
3808 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3809 bool remote_flush, bool local_flush)
3815 kvm_flush_remote_tlbs(vcpu->kvm);
3816 else if (local_flush)
3817 kvm_mmu_flush_tlb(vcpu);
3820 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3821 const u8 *new, int *bytes)
3827 * Assume that the pte write on a page table of the same type
3828 * as the current vcpu paging mode since we update the sptes only
3829 * when they have the same mode.
3831 if (is_pae(vcpu) && *bytes == 4) {
3832 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3835 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3838 new = (const u8 *)&gentry;
3843 gentry = *(const u32 *)new;
3846 gentry = *(const u64 *)new;
3857 * If we're seeing too many writes to a page, it may no longer be a page table,
3858 * or we may be forking, in which case it is better to unmap the page.
3860 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3863 * Skip write-flooding detected for the sp whose level is 1, because
3864 * it can become unsync, then the guest page is not write-protected.
3866 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3869 return ++sp->write_flooding_count >= 3;
3873 * Misaligned accesses are too much trouble to fix up; also, they usually
3874 * indicate a page is not used as a page table.
3876 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3879 unsigned offset, pte_size, misaligned;
3881 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3882 gpa, bytes, sp->role.word);
3884 offset = offset_in_page(gpa);
3885 pte_size = sp->role.cr4_pae ? 8 : 4;
3888 * Sometimes, the OS only writes the last one bytes to update status
3889 * bits, for example, in linux, andb instruction is used in clear_bit().
3891 if (!(offset & (pte_size - 1)) && bytes == 1)
3894 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3895 misaligned |= bytes < 4;
3900 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3902 unsigned page_offset, quadrant;
3906 page_offset = offset_in_page(gpa);
3907 level = sp->role.level;
3909 if (!sp->role.cr4_pae) {
3910 page_offset <<= 1; /* 32->64 */
3912 * A 32-bit pde maps 4MB while the shadow pdes map
3913 * only 2MB. So we need to double the offset again
3914 * and zap two pdes instead of one.
3916 if (level == PT32_ROOT_LEVEL) {
3917 page_offset &= ~7; /* kill rounding error */
3921 quadrant = page_offset >> PAGE_SHIFT;
3922 page_offset &= ~PAGE_MASK;
3923 if (quadrant != sp->role.quadrant)
3927 spte = &sp->spt[page_offset / sizeof(*spte)];
3931 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3932 const u8 *new, int bytes)
3934 gfn_t gfn = gpa >> PAGE_SHIFT;
3935 union kvm_mmu_page_role mask = { .word = 0 };
3936 struct kvm_mmu_page *sp;
3937 LIST_HEAD(invalid_list);
3938 u64 entry, gentry, *spte;
3940 bool remote_flush, local_flush, zap_page;
3943 * If we don't have indirect shadow pages, it means no page is
3944 * write-protected, so we can exit simply.
3946 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3949 zap_page = remote_flush = local_flush = false;
3951 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3953 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3956 * No need to care whether allocation memory is successful
3957 * or not since pte prefetch is skiped if it does not have
3958 * enough objects in the cache.
3960 mmu_topup_memory_caches(vcpu);
3962 spin_lock(&vcpu->kvm->mmu_lock);
3963 ++vcpu->kvm->stat.mmu_pte_write;
3964 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3966 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3967 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
3968 if (detect_write_misaligned(sp, gpa, bytes) ||
3969 detect_write_flooding(sp)) {
3970 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3972 ++vcpu->kvm->stat.mmu_flooded;
3976 spte = get_written_sptes(sp, gpa, &npte);
3983 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3985 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3986 & mask.word) && rmap_can_add(vcpu))
3987 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3988 if (need_remote_flush(entry, *spte))
3989 remote_flush = true;
3993 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3994 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3995 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3996 spin_unlock(&vcpu->kvm->mmu_lock);
3999 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4004 if (vcpu->arch.mmu.direct_map)
4007 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4009 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4013 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4015 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4017 LIST_HEAD(invalid_list);
4019 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4022 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4023 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4026 ++vcpu->kvm->stat.mmu_recycled;
4028 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4031 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4033 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4034 return vcpu_match_mmio_gpa(vcpu, addr);
4036 return vcpu_match_mmio_gva(vcpu, addr);
4039 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4040 void *insn, int insn_len)
4042 int r, emulation_type = EMULTYPE_RETRY;
4043 enum emulation_result er;
4045 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4054 if (is_mmio_page_fault(vcpu, cr2))
4057 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4062 case EMULATE_DO_MMIO:
4063 ++vcpu->stat.mmio_exits;
4073 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4075 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4077 vcpu->arch.mmu.invlpg(vcpu, gva);
4078 kvm_mmu_flush_tlb(vcpu);
4079 ++vcpu->stat.invlpg;
4081 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4083 void kvm_enable_tdp(void)
4087 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4089 void kvm_disable_tdp(void)
4091 tdp_enabled = false;
4093 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4095 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4097 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4098 if (vcpu->arch.mmu.lm_root != NULL)
4099 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4102 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4110 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4111 * Therefore we need to allocate shadow page tables in the first
4112 * 4GB of memory, which happens to fit the DMA32 zone.
4114 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4118 vcpu->arch.mmu.pae_root = page_address(page);
4119 for (i = 0; i < 4; ++i)
4120 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4125 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4129 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4130 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4131 vcpu->arch.mmu.translate_gpa = translate_gpa;
4132 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4134 return alloc_mmu_pages(vcpu);
4137 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4140 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4142 return init_kvm_mmu(vcpu);
4145 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4147 struct kvm_memory_slot *memslot;
4151 memslot = id_to_memslot(kvm->memslots, slot);
4152 last_gfn = memslot->base_gfn + memslot->npages - 1;
4154 spin_lock(&kvm->mmu_lock);
4156 for (i = PT_PAGE_TABLE_LEVEL;
4157 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4158 unsigned long *rmapp;
4159 unsigned long last_index, index;
4161 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4162 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4164 for (index = 0; index <= last_index; ++index, ++rmapp) {
4166 __rmap_write_protect(kvm, rmapp, false);
4168 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4169 kvm_flush_remote_tlbs(kvm);
4170 cond_resched_lock(&kvm->mmu_lock);
4175 kvm_flush_remote_tlbs(kvm);
4176 spin_unlock(&kvm->mmu_lock);
4179 void kvm_mmu_zap_all(struct kvm *kvm)
4181 struct kvm_mmu_page *sp, *node;
4182 LIST_HEAD(invalid_list);
4184 spin_lock(&kvm->mmu_lock);
4186 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4187 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4190 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4191 spin_unlock(&kvm->mmu_lock);
4194 void kvm_mmu_zap_mmio_sptes(struct kvm *kvm)
4196 struct kvm_mmu_page *sp, *node;
4197 LIST_HEAD(invalid_list);
4199 spin_lock(&kvm->mmu_lock);
4201 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
4202 if (!sp->mmio_cached)
4204 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4208 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4209 spin_unlock(&kvm->mmu_lock);
4212 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4215 int nr_to_scan = sc->nr_to_scan;
4217 if (nr_to_scan == 0)
4220 raw_spin_lock(&kvm_lock);
4222 list_for_each_entry(kvm, &vm_list, vm_list) {
4224 LIST_HEAD(invalid_list);
4227 * Never scan more than sc->nr_to_scan VM instances.
4228 * Will not hit this condition practically since we do not try
4229 * to shrink more than one VM and it is very unlikely to see
4230 * !n_used_mmu_pages so many times.
4235 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4236 * here. We may skip a VM instance errorneosly, but we do not
4237 * want to shrink a VM that only started to populate its MMU
4240 if (!kvm->arch.n_used_mmu_pages)
4243 idx = srcu_read_lock(&kvm->srcu);
4244 spin_lock(&kvm->mmu_lock);
4246 prepare_zap_oldest_mmu_page(kvm, &invalid_list);
4247 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4249 spin_unlock(&kvm->mmu_lock);
4250 srcu_read_unlock(&kvm->srcu, idx);
4252 list_move_tail(&kvm->vm_list, &vm_list);
4256 raw_spin_unlock(&kvm_lock);
4259 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4262 static struct shrinker mmu_shrinker = {
4263 .shrink = mmu_shrink,
4264 .seeks = DEFAULT_SEEKS * 10,
4267 static void mmu_destroy_caches(void)
4269 if (pte_list_desc_cache)
4270 kmem_cache_destroy(pte_list_desc_cache);
4271 if (mmu_page_header_cache)
4272 kmem_cache_destroy(mmu_page_header_cache);
4275 int kvm_mmu_module_init(void)
4277 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4278 sizeof(struct pte_list_desc),
4280 if (!pte_list_desc_cache)
4283 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4284 sizeof(struct kvm_mmu_page),
4286 if (!mmu_page_header_cache)
4289 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4292 register_shrinker(&mmu_shrinker);
4297 mmu_destroy_caches();
4302 * Caculate mmu pages needed for kvm.
4304 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4306 unsigned int nr_mmu_pages;
4307 unsigned int nr_pages = 0;
4308 struct kvm_memslots *slots;
4309 struct kvm_memory_slot *memslot;
4311 slots = kvm_memslots(kvm);
4313 kvm_for_each_memslot(memslot, slots)
4314 nr_pages += memslot->npages;
4316 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4317 nr_mmu_pages = max(nr_mmu_pages,
4318 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4320 return nr_mmu_pages;
4323 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4325 struct kvm_shadow_walk_iterator iterator;
4329 walk_shadow_page_lockless_begin(vcpu);
4330 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4331 sptes[iterator.level-1] = spte;
4333 if (!is_shadow_present_pte(spte))
4336 walk_shadow_page_lockless_end(vcpu);
4340 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4342 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4346 destroy_kvm_mmu(vcpu);
4347 free_mmu_pages(vcpu);
4348 mmu_free_memory_caches(vcpu);
4351 void kvm_mmu_module_exit(void)
4353 mmu_destroy_caches();
4354 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4355 unregister_shrinker(&mmu_shrinker);
4356 mmu_audit_disable();