2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
52 bool tdp_enabled = false;
56 AUDIT_POST_PAGE_FAULT,
67 module_param(dbg, bool, 0644);
69 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
70 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define MMU_WARN_ON(x) WARN_ON(x)
73 #define pgprintk(x...) do { } while (0)
74 #define rmap_printk(x...) do { } while (0)
75 #define MMU_WARN_ON(x) do { } while (0)
78 #define PTE_PREFETCH_NUM 8
80 #define PT_FIRST_AVAIL_BITS_SHIFT 10
81 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
83 #define PT64_LEVEL_BITS 9
85 #define PT64_LEVEL_SHIFT(level) \
86 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
88 #define PT64_INDEX(address, level)\
89 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
92 #define PT32_LEVEL_BITS 10
94 #define PT32_LEVEL_SHIFT(level) \
95 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
97 #define PT32_LVL_OFFSET_MASK(level) \
98 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
99 * PT32_LEVEL_BITS))) - 1))
101 #define PT32_INDEX(address, level)\
102 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
105 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
106 #define PT64_DIR_BASE_ADDR_MASK \
107 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
108 #define PT64_LVL_ADDR_MASK(level) \
109 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
110 * PT64_LEVEL_BITS))) - 1))
111 #define PT64_LVL_OFFSET_MASK(level) \
112 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT64_LEVEL_BITS))) - 1))
115 #define PT32_BASE_ADDR_MASK PAGE_MASK
116 #define PT32_DIR_BASE_ADDR_MASK \
117 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
118 #define PT32_LVL_ADDR_MASK(level) \
119 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
120 * PT32_LEVEL_BITS))) - 1))
122 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
123 | shadow_x_mask | shadow_nx_mask)
125 #define ACC_EXEC_MASK 1
126 #define ACC_WRITE_MASK PT_WRITABLE_MASK
127 #define ACC_USER_MASK PT_USER_MASK
128 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
130 #include <trace/events/kvm.h>
132 #define CREATE_TRACE_POINTS
133 #include "mmutrace.h"
135 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
136 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
138 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
140 /* make pte_list_desc fit well in cache line */
141 #define PTE_LIST_EXT 3
143 struct pte_list_desc {
144 u64 *sptes[PTE_LIST_EXT];
145 struct pte_list_desc *more;
148 struct kvm_shadow_walk_iterator {
156 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
157 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
158 shadow_walk_okay(&(_walker)); \
159 shadow_walk_next(&(_walker)))
161 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
162 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
163 shadow_walk_okay(&(_walker)) && \
164 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
165 __shadow_walk_next(&(_walker), spte))
167 static struct kmem_cache *pte_list_desc_cache;
168 static struct kmem_cache *mmu_page_header_cache;
169 static struct percpu_counter kvm_total_used_mmu_pages;
171 static u64 __read_mostly shadow_nx_mask;
172 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
173 static u64 __read_mostly shadow_user_mask;
174 static u64 __read_mostly shadow_accessed_mask;
175 static u64 __read_mostly shadow_dirty_mask;
176 static u64 __read_mostly shadow_mmio_mask;
178 static void mmu_spte_set(u64 *sptep, u64 spte);
179 static void mmu_free_roots(struct kvm_vcpu *vcpu);
181 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
183 shadow_mmio_mask = mmio_mask;
185 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
188 * the low bit of the generation number is always presumed to be zero.
189 * This disables mmio caching during memslot updates. The concept is
190 * similar to a seqcount but instead of retrying the access we just punt
191 * and ignore the cache.
193 * spte bits 3-11 are used as bits 1-9 of the generation number,
194 * the bits 52-61 are used as bits 10-19 of the generation number.
196 #define MMIO_SPTE_GEN_LOW_SHIFT 2
197 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
199 #define MMIO_GEN_SHIFT 20
200 #define MMIO_GEN_LOW_SHIFT 10
201 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
202 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
204 static u64 generation_mmio_spte_mask(unsigned int gen)
208 WARN_ON(gen & ~MMIO_GEN_MASK);
210 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
211 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
215 static unsigned int get_mmio_spte_generation(u64 spte)
219 spte &= ~shadow_mmio_mask;
221 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
222 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
226 static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
228 return kvm_memslots(kvm)->generation & MMIO_GEN_MASK;
231 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
234 unsigned int gen = kvm_current_mmio_generation(kvm);
235 u64 mask = generation_mmio_spte_mask(gen);
237 access &= ACC_WRITE_MASK | ACC_USER_MASK;
238 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
240 trace_mark_mmio_spte(sptep, gfn, access, gen);
241 mmu_spte_set(sptep, mask);
244 static bool is_mmio_spte(u64 spte)
246 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
249 static gfn_t get_mmio_spte_gfn(u64 spte)
251 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
252 return (spte & ~mask) >> PAGE_SHIFT;
255 static unsigned get_mmio_spte_access(u64 spte)
257 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
258 return (spte & ~mask) & ~PAGE_MASK;
261 static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
262 pfn_t pfn, unsigned access)
264 if (unlikely(is_noslot_pfn(pfn))) {
265 mark_mmio_spte(kvm, sptep, gfn, access);
272 static bool check_mmio_spte(struct kvm *kvm, u64 spte)
274 unsigned int kvm_gen, spte_gen;
276 kvm_gen = kvm_current_mmio_generation(kvm);
277 spte_gen = get_mmio_spte_generation(spte);
279 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
280 return likely(kvm_gen == spte_gen);
283 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
284 u64 dirty_mask, u64 nx_mask, u64 x_mask)
286 shadow_user_mask = user_mask;
287 shadow_accessed_mask = accessed_mask;
288 shadow_dirty_mask = dirty_mask;
289 shadow_nx_mask = nx_mask;
290 shadow_x_mask = x_mask;
292 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
294 static int is_cpuid_PSE36(void)
299 static int is_nx(struct kvm_vcpu *vcpu)
301 return vcpu->arch.efer & EFER_NX;
304 static int is_shadow_present_pte(u64 pte)
306 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
309 static int is_large_pte(u64 pte)
311 return pte & PT_PAGE_SIZE_MASK;
314 static int is_rmap_spte(u64 pte)
316 return is_shadow_present_pte(pte);
319 static int is_last_spte(u64 pte, int level)
321 if (level == PT_PAGE_TABLE_LEVEL)
323 if (is_large_pte(pte))
328 static pfn_t spte_to_pfn(u64 pte)
330 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
333 static gfn_t pse36_gfn_delta(u32 gpte)
335 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
337 return (gpte & PT32_DIR_PSE36_MASK) << shift;
341 static void __set_spte(u64 *sptep, u64 spte)
346 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
351 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
353 return xchg(sptep, spte);
356 static u64 __get_spte_lockless(u64 *sptep)
358 return ACCESS_ONCE(*sptep);
361 static bool __check_direct_spte_mmio_pf(u64 spte)
363 /* It is valid if the spte is zapped. */
375 static void count_spte_clear(u64 *sptep, u64 spte)
377 struct kvm_mmu_page *sp = page_header(__pa(sptep));
379 if (is_shadow_present_pte(spte))
382 /* Ensure the spte is completely set before we increase the count */
384 sp->clear_spte_count++;
387 static void __set_spte(u64 *sptep, u64 spte)
389 union split_spte *ssptep, sspte;
391 ssptep = (union split_spte *)sptep;
392 sspte = (union split_spte)spte;
394 ssptep->spte_high = sspte.spte_high;
397 * If we map the spte from nonpresent to present, We should store
398 * the high bits firstly, then set present bit, so cpu can not
399 * fetch this spte while we are setting the spte.
403 ssptep->spte_low = sspte.spte_low;
406 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
408 union split_spte *ssptep, sspte;
410 ssptep = (union split_spte *)sptep;
411 sspte = (union split_spte)spte;
413 ssptep->spte_low = sspte.spte_low;
416 * If we map the spte from present to nonpresent, we should clear
417 * present bit firstly to avoid vcpu fetch the old high bits.
421 ssptep->spte_high = sspte.spte_high;
422 count_spte_clear(sptep, spte);
425 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
427 union split_spte *ssptep, sspte, orig;
429 ssptep = (union split_spte *)sptep;
430 sspte = (union split_spte)spte;
432 /* xchg acts as a barrier before the setting of the high bits */
433 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
434 orig.spte_high = ssptep->spte_high;
435 ssptep->spte_high = sspte.spte_high;
436 count_spte_clear(sptep, spte);
442 * The idea using the light way get the spte on x86_32 guest is from
443 * gup_get_pte(arch/x86/mm/gup.c).
445 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
446 * coalesces them and we are running out of the MMU lock. Therefore
447 * we need to protect against in-progress updates of the spte.
449 * Reading the spte while an update is in progress may get the old value
450 * for the high part of the spte. The race is fine for a present->non-present
451 * change (because the high part of the spte is ignored for non-present spte),
452 * but for a present->present change we must reread the spte.
454 * All such changes are done in two steps (present->non-present and
455 * non-present->present), hence it is enough to count the number of
456 * present->non-present updates: if it changed while reading the spte,
457 * we might have hit the race. This is done using clear_spte_count.
459 static u64 __get_spte_lockless(u64 *sptep)
461 struct kvm_mmu_page *sp = page_header(__pa(sptep));
462 union split_spte spte, *orig = (union split_spte *)sptep;
466 count = sp->clear_spte_count;
469 spte.spte_low = orig->spte_low;
472 spte.spte_high = orig->spte_high;
475 if (unlikely(spte.spte_low != orig->spte_low ||
476 count != sp->clear_spte_count))
482 static bool __check_direct_spte_mmio_pf(u64 spte)
484 union split_spte sspte = (union split_spte)spte;
485 u32 high_mmio_mask = shadow_mmio_mask >> 32;
487 /* It is valid if the spte is zapped. */
491 /* It is valid if the spte is being zapped. */
492 if (sspte.spte_low == 0ull &&
493 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
500 static bool spte_is_locklessly_modifiable(u64 spte)
502 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
503 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
506 static bool spte_has_volatile_bits(u64 spte)
509 * Always atomicly update spte if it can be updated
510 * out of mmu-lock, it can ensure dirty bit is not lost,
511 * also, it can help us to get a stable is_writable_pte()
512 * to ensure tlb flush is not missed.
514 if (spte_is_locklessly_modifiable(spte))
517 if (!shadow_accessed_mask)
520 if (!is_shadow_present_pte(spte))
523 if ((spte & shadow_accessed_mask) &&
524 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
530 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
532 return (old_spte & bit_mask) && !(new_spte & bit_mask);
535 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
537 return (old_spte & bit_mask) != (new_spte & bit_mask);
540 /* Rules for using mmu_spte_set:
541 * Set the sptep from nonpresent to present.
542 * Note: the sptep being assigned *must* be either not present
543 * or in a state where the hardware will not attempt to update
546 static void mmu_spte_set(u64 *sptep, u64 new_spte)
548 WARN_ON(is_shadow_present_pte(*sptep));
549 __set_spte(sptep, new_spte);
552 /* Rules for using mmu_spte_update:
553 * Update the state bits, it means the mapped pfn is not changged.
555 * Whenever we overwrite a writable spte with a read-only one we
556 * should flush remote TLBs. Otherwise rmap_write_protect
557 * will find a read-only spte, even though the writable spte
558 * might be cached on a CPU's TLB, the return value indicates this
561 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
563 u64 old_spte = *sptep;
566 WARN_ON(!is_rmap_spte(new_spte));
568 if (!is_shadow_present_pte(old_spte)) {
569 mmu_spte_set(sptep, new_spte);
573 if (!spte_has_volatile_bits(old_spte))
574 __update_clear_spte_fast(sptep, new_spte);
576 old_spte = __update_clear_spte_slow(sptep, new_spte);
579 * For the spte updated out of mmu-lock is safe, since
580 * we always atomicly update it, see the comments in
581 * spte_has_volatile_bits().
583 if (spte_is_locklessly_modifiable(old_spte) &&
584 !is_writable_pte(new_spte))
587 if (!shadow_accessed_mask)
591 * Flush TLB when accessed/dirty bits are changed in the page tables,
592 * to guarantee consistency between TLB and page tables.
594 if (spte_is_bit_changed(old_spte, new_spte,
595 shadow_accessed_mask | shadow_dirty_mask))
598 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
599 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
600 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
601 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
607 * Rules for using mmu_spte_clear_track_bits:
608 * It sets the sptep from present to nonpresent, and track the
609 * state bits, it is used to clear the last level sptep.
611 static int mmu_spte_clear_track_bits(u64 *sptep)
614 u64 old_spte = *sptep;
616 if (!spte_has_volatile_bits(old_spte))
617 __update_clear_spte_fast(sptep, 0ull);
619 old_spte = __update_clear_spte_slow(sptep, 0ull);
621 if (!is_rmap_spte(old_spte))
624 pfn = spte_to_pfn(old_spte);
627 * KVM does not hold the refcount of the page used by
628 * kvm mmu, before reclaiming the page, we should
629 * unmap it from mmu first.
631 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
633 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
634 kvm_set_pfn_accessed(pfn);
635 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
636 kvm_set_pfn_dirty(pfn);
641 * Rules for using mmu_spte_clear_no_track:
642 * Directly clear spte without caring the state bits of sptep,
643 * it is used to set the upper level spte.
645 static void mmu_spte_clear_no_track(u64 *sptep)
647 __update_clear_spte_fast(sptep, 0ull);
650 static u64 mmu_spte_get_lockless(u64 *sptep)
652 return __get_spte_lockless(sptep);
655 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
658 * Prevent page table teardown by making any free-er wait during
659 * kvm_flush_remote_tlbs() IPI to all active vcpus.
662 vcpu->mode = READING_SHADOW_PAGE_TABLES;
664 * Make sure a following spte read is not reordered ahead of the write
670 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
673 * Make sure the write to vcpu->mode is not reordered in front of
674 * reads to sptes. If it does, kvm_commit_zap_page() can see us
675 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
678 vcpu->mode = OUTSIDE_GUEST_MODE;
682 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
683 struct kmem_cache *base_cache, int min)
687 if (cache->nobjs >= min)
689 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
690 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
693 cache->objects[cache->nobjs++] = obj;
698 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
703 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
704 struct kmem_cache *cache)
707 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
710 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
715 if (cache->nobjs >= min)
717 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
718 page = (void *)__get_free_page(GFP_KERNEL);
721 cache->objects[cache->nobjs++] = page;
726 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
729 free_page((unsigned long)mc->objects[--mc->nobjs]);
732 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
736 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
737 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
740 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
743 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
744 mmu_page_header_cache, 4);
749 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
751 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
752 pte_list_desc_cache);
753 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
754 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
755 mmu_page_header_cache);
758 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
763 p = mc->objects[--mc->nobjs];
767 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
769 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
772 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
774 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
777 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
779 if (!sp->role.direct)
780 return sp->gfns[index];
782 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
785 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
788 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
790 sp->gfns[index] = gfn;
794 * Return the pointer to the large page information for a given gfn,
795 * handling slots that are not large page aligned.
797 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
798 struct kvm_memory_slot *slot,
803 idx = gfn_to_index(gfn, slot->base_gfn, level);
804 return &slot->arch.lpage_info[level - 2][idx];
807 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
809 struct kvm_memory_slot *slot;
810 struct kvm_lpage_info *linfo;
813 slot = gfn_to_memslot(kvm, gfn);
814 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
815 linfo = lpage_info_slot(gfn, slot, i);
816 linfo->write_count += 1;
818 kvm->arch.indirect_shadow_pages++;
821 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
823 struct kvm_memory_slot *slot;
824 struct kvm_lpage_info *linfo;
827 slot = gfn_to_memslot(kvm, gfn);
828 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
829 linfo = lpage_info_slot(gfn, slot, i);
830 linfo->write_count -= 1;
831 WARN_ON(linfo->write_count < 0);
833 kvm->arch.indirect_shadow_pages--;
836 static int has_wrprotected_page(struct kvm *kvm,
840 struct kvm_memory_slot *slot;
841 struct kvm_lpage_info *linfo;
843 slot = gfn_to_memslot(kvm, gfn);
845 linfo = lpage_info_slot(gfn, slot, level);
846 return linfo->write_count;
852 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
854 unsigned long page_size;
857 page_size = kvm_host_page_size(kvm, gfn);
859 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
860 if (page_size >= KVM_HPAGE_SIZE(i))
869 static struct kvm_memory_slot *
870 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
873 struct kvm_memory_slot *slot;
875 slot = gfn_to_memslot(vcpu->kvm, gfn);
876 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
877 (no_dirty_log && slot->dirty_bitmap))
883 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
885 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
888 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
890 int host_level, level, max_level;
892 host_level = host_mapping_level(vcpu->kvm, large_gfn);
894 if (host_level == PT_PAGE_TABLE_LEVEL)
897 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
899 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
900 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
907 * Pte mapping structures:
909 * If pte_list bit zero is zero, then pte_list point to the spte.
911 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
912 * pte_list_desc containing more mappings.
914 * Returns the number of pte entries before the spte was added or zero if
915 * the spte was not added.
918 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
919 unsigned long *pte_list)
921 struct pte_list_desc *desc;
925 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
926 *pte_list = (unsigned long)spte;
927 } else if (!(*pte_list & 1)) {
928 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
929 desc = mmu_alloc_pte_list_desc(vcpu);
930 desc->sptes[0] = (u64 *)*pte_list;
931 desc->sptes[1] = spte;
932 *pte_list = (unsigned long)desc | 1;
935 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
936 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
937 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
939 count += PTE_LIST_EXT;
941 if (desc->sptes[PTE_LIST_EXT-1]) {
942 desc->more = mmu_alloc_pte_list_desc(vcpu);
945 for (i = 0; desc->sptes[i]; ++i)
947 desc->sptes[i] = spte;
953 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
954 int i, struct pte_list_desc *prev_desc)
958 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
960 desc->sptes[i] = desc->sptes[j];
961 desc->sptes[j] = NULL;
964 if (!prev_desc && !desc->more)
965 *pte_list = (unsigned long)desc->sptes[0];
968 prev_desc->more = desc->more;
970 *pte_list = (unsigned long)desc->more | 1;
971 mmu_free_pte_list_desc(desc);
974 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
976 struct pte_list_desc *desc;
977 struct pte_list_desc *prev_desc;
981 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
983 } else if (!(*pte_list & 1)) {
984 rmap_printk("pte_list_remove: %p 1->0\n", spte);
985 if ((u64 *)*pte_list != spte) {
986 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
991 rmap_printk("pte_list_remove: %p many->many\n", spte);
992 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
995 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
996 if (desc->sptes[i] == spte) {
997 pte_list_desc_remove_entry(pte_list,
1005 pr_err("pte_list_remove: %p many->many\n", spte);
1010 typedef void (*pte_list_walk_fn) (u64 *spte);
1011 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1013 struct pte_list_desc *desc;
1019 if (!(*pte_list & 1))
1020 return fn((u64 *)*pte_list);
1022 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1024 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1030 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1031 struct kvm_memory_slot *slot)
1035 idx = gfn_to_index(gfn, slot->base_gfn, level);
1036 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1040 * Take gfn and return the reverse mapping to it.
1042 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1044 struct kvm_memory_slot *slot;
1046 slot = gfn_to_memslot(kvm, gfn);
1047 return __gfn_to_rmap(gfn, level, slot);
1050 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1052 struct kvm_mmu_memory_cache *cache;
1054 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1055 return mmu_memory_cache_free_objects(cache);
1058 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1060 struct kvm_mmu_page *sp;
1061 unsigned long *rmapp;
1063 sp = page_header(__pa(spte));
1064 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1065 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1066 return pte_list_add(vcpu, spte, rmapp);
1069 static void rmap_remove(struct kvm *kvm, u64 *spte)
1071 struct kvm_mmu_page *sp;
1073 unsigned long *rmapp;
1075 sp = page_header(__pa(spte));
1076 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1077 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1078 pte_list_remove(spte, rmapp);
1082 * Used by the following functions to iterate through the sptes linked by a
1083 * rmap. All fields are private and not assumed to be used outside.
1085 struct rmap_iterator {
1086 /* private fields */
1087 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1088 int pos; /* index of the sptep */
1092 * Iteration must be started by this function. This should also be used after
1093 * removing/dropping sptes from the rmap link because in such cases the
1094 * information in the itererator may not be valid.
1096 * Returns sptep if found, NULL otherwise.
1098 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1108 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1110 return iter->desc->sptes[iter->pos];
1114 * Must be used with a valid iterator: e.g. after rmap_get_first().
1116 * Returns sptep if found, NULL otherwise.
1118 static u64 *rmap_get_next(struct rmap_iterator *iter)
1121 if (iter->pos < PTE_LIST_EXT - 1) {
1125 sptep = iter->desc->sptes[iter->pos];
1130 iter->desc = iter->desc->more;
1134 /* desc->sptes[0] cannot be NULL */
1135 return iter->desc->sptes[iter->pos];
1142 #define for_each_rmap_spte(_rmap_, _iter_, _spte_) \
1143 for (_spte_ = rmap_get_first(*_rmap_, _iter_); \
1144 _spte_ && ({BUG_ON(!is_shadow_present_pte(*_spte_)); 1;}); \
1145 _spte_ = rmap_get_next(_iter_))
1147 static void drop_spte(struct kvm *kvm, u64 *sptep)
1149 if (mmu_spte_clear_track_bits(sptep))
1150 rmap_remove(kvm, sptep);
1154 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1156 if (is_large_pte(*sptep)) {
1157 WARN_ON(page_header(__pa(sptep))->role.level ==
1158 PT_PAGE_TABLE_LEVEL);
1159 drop_spte(kvm, sptep);
1167 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1169 if (__drop_large_spte(vcpu->kvm, sptep))
1170 kvm_flush_remote_tlbs(vcpu->kvm);
1174 * Write-protect on the specified @sptep, @pt_protect indicates whether
1175 * spte write-protection is caused by protecting shadow page table.
1177 * Note: write protection is difference between dirty logging and spte
1179 * - for dirty logging, the spte can be set to writable at anytime if
1180 * its dirty bitmap is properly set.
1181 * - for spte protection, the spte can be writable only after unsync-ing
1184 * Return true if tlb need be flushed.
1186 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1190 if (!is_writable_pte(spte) &&
1191 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1194 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1197 spte &= ~SPTE_MMU_WRITEABLE;
1198 spte = spte & ~PT_WRITABLE_MASK;
1200 return mmu_spte_update(sptep, spte);
1203 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1207 struct rmap_iterator iter;
1210 for_each_rmap_spte(rmapp, &iter, sptep)
1211 flush |= spte_write_protect(kvm, sptep, pt_protect);
1216 static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep)
1220 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1222 spte &= ~shadow_dirty_mask;
1224 return mmu_spte_update(sptep, spte);
1227 static bool __rmap_clear_dirty(struct kvm *kvm, unsigned long *rmapp)
1230 struct rmap_iterator iter;
1233 for_each_rmap_spte(rmapp, &iter, sptep)
1234 flush |= spte_clear_dirty(kvm, sptep);
1239 static bool spte_set_dirty(struct kvm *kvm, u64 *sptep)
1243 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1245 spte |= shadow_dirty_mask;
1247 return mmu_spte_update(sptep, spte);
1250 static bool __rmap_set_dirty(struct kvm *kvm, unsigned long *rmapp)
1253 struct rmap_iterator iter;
1256 for_each_rmap_spte(rmapp, &iter, sptep)
1257 flush |= spte_set_dirty(kvm, sptep);
1263 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1264 * @kvm: kvm instance
1265 * @slot: slot to protect
1266 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1267 * @mask: indicates which pages we should protect
1269 * Used when we do not need to care about huge page mappings: e.g. during dirty
1270 * logging we do not have any such mappings.
1272 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1273 struct kvm_memory_slot *slot,
1274 gfn_t gfn_offset, unsigned long mask)
1276 unsigned long *rmapp;
1279 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1280 PT_PAGE_TABLE_LEVEL, slot);
1281 __rmap_write_protect(kvm, rmapp, false);
1283 /* clear the first set bit */
1289 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1290 * @kvm: kvm instance
1291 * @slot: slot to clear D-bit
1292 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1293 * @mask: indicates which pages we should clear D-bit
1295 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1297 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1298 struct kvm_memory_slot *slot,
1299 gfn_t gfn_offset, unsigned long mask)
1301 unsigned long *rmapp;
1304 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1305 PT_PAGE_TABLE_LEVEL, slot);
1306 __rmap_clear_dirty(kvm, rmapp);
1308 /* clear the first set bit */
1312 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1315 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1318 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1319 * enable dirty logging for them.
1321 * Used when we do not need to care about huge page mappings: e.g. during dirty
1322 * logging we do not have any such mappings.
1324 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1325 struct kvm_memory_slot *slot,
1326 gfn_t gfn_offset, unsigned long mask)
1328 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1329 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1332 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1335 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1337 struct kvm_memory_slot *slot;
1338 unsigned long *rmapp;
1340 bool write_protected = false;
1342 slot = gfn_to_memslot(kvm, gfn);
1344 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1345 rmapp = __gfn_to_rmap(gfn, i, slot);
1346 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1349 return write_protected;
1352 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1353 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1357 struct rmap_iterator iter;
1358 int need_tlb_flush = 0;
1360 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1361 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1362 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx gfn %llx (%d)\n",
1363 sptep, *sptep, gfn, level);
1365 drop_spte(kvm, sptep);
1369 return need_tlb_flush;
1372 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1373 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1377 struct rmap_iterator iter;
1380 pte_t *ptep = (pte_t *)data;
1383 WARN_ON(pte_huge(*ptep));
1384 new_pfn = pte_pfn(*ptep);
1387 for_each_rmap_spte(rmapp, &iter, sptep) {
1388 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1389 sptep, *sptep, gfn, level);
1393 if (pte_write(*ptep)) {
1394 drop_spte(kvm, sptep);
1397 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1398 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1400 new_spte &= ~PT_WRITABLE_MASK;
1401 new_spte &= ~SPTE_HOST_WRITEABLE;
1402 new_spte &= ~shadow_accessed_mask;
1404 mmu_spte_clear_track_bits(sptep);
1405 mmu_spte_set(sptep, new_spte);
1410 kvm_flush_remote_tlbs(kvm);
1415 struct slot_rmap_walk_iterator {
1417 struct kvm_memory_slot *slot;
1423 /* output fields. */
1425 unsigned long *rmap;
1428 /* private field. */
1429 unsigned long *end_rmap;
1433 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1435 iterator->level = level;
1436 iterator->gfn = iterator->start_gfn;
1437 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1438 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1443 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1444 struct kvm_memory_slot *slot, int start_level,
1445 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1447 iterator->slot = slot;
1448 iterator->start_level = start_level;
1449 iterator->end_level = end_level;
1450 iterator->start_gfn = start_gfn;
1451 iterator->end_gfn = end_gfn;
1453 rmap_walk_init_level(iterator, iterator->start_level);
1456 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1458 return !!iterator->rmap;
1461 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1463 if (++iterator->rmap <= iterator->end_rmap) {
1464 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1468 if (++iterator->level > iterator->end_level) {
1469 iterator->rmap = NULL;
1473 rmap_walk_init_level(iterator, iterator->level);
1476 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1477 _start_gfn, _end_gfn, _iter_) \
1478 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1479 _end_level_, _start_gfn, _end_gfn); \
1480 slot_rmap_walk_okay(_iter_); \
1481 slot_rmap_walk_next(_iter_))
1483 static int kvm_handle_hva_range(struct kvm *kvm,
1484 unsigned long start,
1487 int (*handler)(struct kvm *kvm,
1488 unsigned long *rmapp,
1489 struct kvm_memory_slot *slot,
1492 unsigned long data))
1494 struct kvm_memslots *slots;
1495 struct kvm_memory_slot *memslot;
1496 struct slot_rmap_walk_iterator iterator;
1499 slots = kvm_memslots(kvm);
1501 kvm_for_each_memslot(memslot, slots) {
1502 unsigned long hva_start, hva_end;
1503 gfn_t gfn_start, gfn_end;
1505 hva_start = max(start, memslot->userspace_addr);
1506 hva_end = min(end, memslot->userspace_addr +
1507 (memslot->npages << PAGE_SHIFT));
1508 if (hva_start >= hva_end)
1511 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1512 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1514 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1515 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1517 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1518 PT_MAX_HUGEPAGE_LEVEL, gfn_start, gfn_end - 1,
1520 ret |= handler(kvm, iterator.rmap, memslot,
1521 iterator.gfn, iterator.level, data);
1527 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1529 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1530 struct kvm_memory_slot *slot,
1531 gfn_t gfn, int level,
1532 unsigned long data))
1534 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1537 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1539 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1542 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1544 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1547 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1549 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1552 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1553 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1557 struct rmap_iterator uninitialized_var(iter);
1560 BUG_ON(!shadow_accessed_mask);
1562 for_each_rmap_spte(rmapp, &iter, sptep)
1563 if (*sptep & shadow_accessed_mask) {
1565 clear_bit((ffs(shadow_accessed_mask) - 1),
1566 (unsigned long *)sptep);
1569 trace_kvm_age_page(gfn, level, slot, young);
1573 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1574 struct kvm_memory_slot *slot, gfn_t gfn,
1575 int level, unsigned long data)
1578 struct rmap_iterator iter;
1582 * If there's no access bit in the secondary pte set by the
1583 * hardware it's up to gup-fast/gup to set the access bit in
1584 * the primary pte or in the page structure.
1586 if (!shadow_accessed_mask)
1589 for_each_rmap_spte(rmapp, &iter, sptep)
1590 if (*sptep & shadow_accessed_mask) {
1598 #define RMAP_RECYCLE_THRESHOLD 1000
1600 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1602 unsigned long *rmapp;
1603 struct kvm_mmu_page *sp;
1605 sp = page_header(__pa(spte));
1607 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1609 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, gfn, sp->role.level, 0);
1610 kvm_flush_remote_tlbs(vcpu->kvm);
1613 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1616 * In case of absence of EPT Access and Dirty Bits supports,
1617 * emulate the accessed bit for EPT, by checking if this page has
1618 * an EPT mapping, and clearing it if it does. On the next access,
1619 * a new EPT mapping will be established.
1620 * This has some overhead, but not as much as the cost of swapping
1621 * out actively used pages or breaking up actively used hugepages.
1623 if (!shadow_accessed_mask) {
1625 * We are holding the kvm->mmu_lock, and we are blowing up
1626 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1627 * This is correct as long as we don't decouple the mmu_lock
1628 * protected regions (like invalidate_range_start|end does).
1630 kvm->mmu_notifier_seq++;
1631 return kvm_handle_hva_range(kvm, start, end, 0,
1635 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1638 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1640 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1644 static int is_empty_shadow_page(u64 *spt)
1649 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1650 if (is_shadow_present_pte(*pos)) {
1651 printk(KERN_ERR "%s: %p %llx\n", __func__,
1660 * This value is the sum of all of the kvm instances's
1661 * kvm->arch.n_used_mmu_pages values. We need a global,
1662 * aggregate version in order to make the slab shrinker
1665 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1667 kvm->arch.n_used_mmu_pages += nr;
1668 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1671 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1673 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1674 hlist_del(&sp->hash_link);
1675 list_del(&sp->link);
1676 free_page((unsigned long)sp->spt);
1677 if (!sp->role.direct)
1678 free_page((unsigned long)sp->gfns);
1679 kmem_cache_free(mmu_page_header_cache, sp);
1682 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1684 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1687 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1688 struct kvm_mmu_page *sp, u64 *parent_pte)
1693 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1696 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1699 pte_list_remove(parent_pte, &sp->parent_ptes);
1702 static void drop_parent_pte(struct kvm_mmu_page *sp,
1705 mmu_page_remove_parent_pte(sp, parent_pte);
1706 mmu_spte_clear_no_track(parent_pte);
1709 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1710 u64 *parent_pte, int direct)
1712 struct kvm_mmu_page *sp;
1714 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1715 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1717 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1718 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1721 * The active_mmu_pages list is the FIFO list, do not move the
1722 * page until it is zapped. kvm_zap_obsolete_pages depends on
1723 * this feature. See the comments in kvm_zap_obsolete_pages().
1725 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1726 sp->parent_ptes = 0;
1727 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1728 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1732 static void mark_unsync(u64 *spte);
1733 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1735 pte_list_walk(&sp->parent_ptes, mark_unsync);
1738 static void mark_unsync(u64 *spte)
1740 struct kvm_mmu_page *sp;
1743 sp = page_header(__pa(spte));
1744 index = spte - sp->spt;
1745 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1747 if (sp->unsync_children++)
1749 kvm_mmu_mark_parents_unsync(sp);
1752 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1753 struct kvm_mmu_page *sp)
1758 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1762 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1763 struct kvm_mmu_page *sp, u64 *spte,
1769 #define KVM_PAGE_ARRAY_NR 16
1771 struct kvm_mmu_pages {
1772 struct mmu_page_and_offset {
1773 struct kvm_mmu_page *sp;
1775 } page[KVM_PAGE_ARRAY_NR];
1779 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1785 for (i=0; i < pvec->nr; i++)
1786 if (pvec->page[i].sp == sp)
1789 pvec->page[pvec->nr].sp = sp;
1790 pvec->page[pvec->nr].idx = idx;
1792 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1795 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1796 struct kvm_mmu_pages *pvec)
1798 int i, ret, nr_unsync_leaf = 0;
1800 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1801 struct kvm_mmu_page *child;
1802 u64 ent = sp->spt[i];
1804 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1805 goto clear_child_bitmap;
1807 child = page_header(ent & PT64_BASE_ADDR_MASK);
1809 if (child->unsync_children) {
1810 if (mmu_pages_add(pvec, child, i))
1813 ret = __mmu_unsync_walk(child, pvec);
1815 goto clear_child_bitmap;
1817 nr_unsync_leaf += ret;
1820 } else if (child->unsync) {
1822 if (mmu_pages_add(pvec, child, i))
1825 goto clear_child_bitmap;
1830 __clear_bit(i, sp->unsync_child_bitmap);
1831 sp->unsync_children--;
1832 WARN_ON((int)sp->unsync_children < 0);
1836 return nr_unsync_leaf;
1839 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1840 struct kvm_mmu_pages *pvec)
1842 if (!sp->unsync_children)
1845 mmu_pages_add(pvec, sp, 0);
1846 return __mmu_unsync_walk(sp, pvec);
1849 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1851 WARN_ON(!sp->unsync);
1852 trace_kvm_mmu_sync_page(sp);
1854 --kvm->stat.mmu_unsync;
1857 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1858 struct list_head *invalid_list);
1859 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1860 struct list_head *invalid_list);
1863 * NOTE: we should pay more attention on the zapped-obsolete page
1864 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1865 * since it has been deleted from active_mmu_pages but still can be found
1868 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1869 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1870 * all the obsolete pages.
1872 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1873 hlist_for_each_entry(_sp, \
1874 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1875 if ((_sp)->gfn != (_gfn)) {} else
1877 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1878 for_each_gfn_sp(_kvm, _sp, _gfn) \
1879 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1881 /* @sp->gfn should be write-protected at the call site */
1882 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1883 struct list_head *invalid_list, bool clear_unsync)
1885 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1886 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1891 kvm_unlink_unsync_page(vcpu->kvm, sp);
1893 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1894 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1898 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1902 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1903 struct kvm_mmu_page *sp)
1905 LIST_HEAD(invalid_list);
1908 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1910 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1915 #ifdef CONFIG_KVM_MMU_AUDIT
1916 #include "mmu_audit.c"
1918 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1919 static void mmu_audit_disable(void) { }
1922 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1923 struct list_head *invalid_list)
1925 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1928 /* @gfn should be write-protected at the call site */
1929 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1931 struct kvm_mmu_page *s;
1932 LIST_HEAD(invalid_list);
1935 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1939 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1940 kvm_unlink_unsync_page(vcpu->kvm, s);
1941 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1942 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1943 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1949 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1951 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1954 struct mmu_page_path {
1955 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1956 unsigned int idx[PT64_ROOT_LEVEL-1];
1959 #define for_each_sp(pvec, sp, parents, i) \
1960 for (i = mmu_pages_next(&pvec, &parents, -1), \
1961 sp = pvec.page[i].sp; \
1962 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1963 i = mmu_pages_next(&pvec, &parents, i))
1965 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1966 struct mmu_page_path *parents,
1971 for (n = i+1; n < pvec->nr; n++) {
1972 struct kvm_mmu_page *sp = pvec->page[n].sp;
1974 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1975 parents->idx[0] = pvec->page[n].idx;
1979 parents->parent[sp->role.level-2] = sp;
1980 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1986 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1988 struct kvm_mmu_page *sp;
1989 unsigned int level = 0;
1992 unsigned int idx = parents->idx[level];
1994 sp = parents->parent[level];
1998 --sp->unsync_children;
1999 WARN_ON((int)sp->unsync_children < 0);
2000 __clear_bit(idx, sp->unsync_child_bitmap);
2002 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
2005 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
2006 struct mmu_page_path *parents,
2007 struct kvm_mmu_pages *pvec)
2009 parents->parent[parent->role.level-1] = NULL;
2013 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2014 struct kvm_mmu_page *parent)
2017 struct kvm_mmu_page *sp;
2018 struct mmu_page_path parents;
2019 struct kvm_mmu_pages pages;
2020 LIST_HEAD(invalid_list);
2022 kvm_mmu_pages_init(parent, &parents, &pages);
2023 while (mmu_unsync_walk(parent, &pages)) {
2024 bool protected = false;
2026 for_each_sp(pages, sp, parents, i)
2027 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
2030 kvm_flush_remote_tlbs(vcpu->kvm);
2032 for_each_sp(pages, sp, parents, i) {
2033 kvm_sync_page(vcpu, sp, &invalid_list);
2034 mmu_pages_clear_parents(&parents);
2036 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2037 cond_resched_lock(&vcpu->kvm->mmu_lock);
2038 kvm_mmu_pages_init(parent, &parents, &pages);
2042 static void init_shadow_page_table(struct kvm_mmu_page *sp)
2046 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2050 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2052 sp->write_flooding_count = 0;
2055 static void clear_sp_write_flooding_count(u64 *spte)
2057 struct kvm_mmu_page *sp = page_header(__pa(spte));
2059 __clear_sp_write_flooding_count(sp);
2062 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2064 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2067 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2075 union kvm_mmu_page_role role;
2077 struct kvm_mmu_page *sp;
2078 bool need_sync = false;
2080 role = vcpu->arch.mmu.base_role;
2082 role.direct = direct;
2085 role.access = access;
2086 if (!vcpu->arch.mmu.direct_map
2087 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2088 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2089 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2090 role.quadrant = quadrant;
2092 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
2093 if (is_obsolete_sp(vcpu->kvm, sp))
2096 if (!need_sync && sp->unsync)
2099 if (sp->role.word != role.word)
2102 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
2105 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
2106 if (sp->unsync_children) {
2107 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2108 kvm_mmu_mark_parents_unsync(sp);
2109 } else if (sp->unsync)
2110 kvm_mmu_mark_parents_unsync(sp);
2112 __clear_sp_write_flooding_count(sp);
2113 trace_kvm_mmu_get_page(sp, false);
2116 ++vcpu->kvm->stat.mmu_cache_miss;
2117 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
2122 hlist_add_head(&sp->hash_link,
2123 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2125 if (rmap_write_protect(vcpu->kvm, gfn))
2126 kvm_flush_remote_tlbs(vcpu->kvm);
2127 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2128 kvm_sync_pages(vcpu, gfn);
2130 account_shadowed(vcpu->kvm, gfn);
2132 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2133 init_shadow_page_table(sp);
2134 trace_kvm_mmu_get_page(sp, true);
2138 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2139 struct kvm_vcpu *vcpu, u64 addr)
2141 iterator->addr = addr;
2142 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2143 iterator->level = vcpu->arch.mmu.shadow_root_level;
2145 if (iterator->level == PT64_ROOT_LEVEL &&
2146 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2147 !vcpu->arch.mmu.direct_map)
2150 if (iterator->level == PT32E_ROOT_LEVEL) {
2151 iterator->shadow_addr
2152 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2153 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2155 if (!iterator->shadow_addr)
2156 iterator->level = 0;
2160 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2162 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2165 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2166 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2170 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2173 if (is_last_spte(spte, iterator->level)) {
2174 iterator->level = 0;
2178 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2182 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2184 return __shadow_walk_next(iterator, *iterator->sptep);
2187 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed)
2191 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2192 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2194 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2195 shadow_user_mask | shadow_x_mask;
2198 spte |= shadow_accessed_mask;
2200 mmu_spte_set(sptep, spte);
2203 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2204 unsigned direct_access)
2206 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2207 struct kvm_mmu_page *child;
2210 * For the direct sp, if the guest pte's dirty bit
2211 * changed form clean to dirty, it will corrupt the
2212 * sp's access: allow writable in the read-only sp,
2213 * so we should update the spte at this point to get
2214 * a new sp with the correct access.
2216 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2217 if (child->role.access == direct_access)
2220 drop_parent_pte(child, sptep);
2221 kvm_flush_remote_tlbs(vcpu->kvm);
2225 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2229 struct kvm_mmu_page *child;
2232 if (is_shadow_present_pte(pte)) {
2233 if (is_last_spte(pte, sp->role.level)) {
2234 drop_spte(kvm, spte);
2235 if (is_large_pte(pte))
2238 child = page_header(pte & PT64_BASE_ADDR_MASK);
2239 drop_parent_pte(child, spte);
2244 if (is_mmio_spte(pte))
2245 mmu_spte_clear_no_track(spte);
2250 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2251 struct kvm_mmu_page *sp)
2255 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2256 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2259 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2261 mmu_page_remove_parent_pte(sp, parent_pte);
2264 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2267 struct rmap_iterator iter;
2269 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2270 drop_parent_pte(sp, sptep);
2273 static int mmu_zap_unsync_children(struct kvm *kvm,
2274 struct kvm_mmu_page *parent,
2275 struct list_head *invalid_list)
2278 struct mmu_page_path parents;
2279 struct kvm_mmu_pages pages;
2281 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2284 kvm_mmu_pages_init(parent, &parents, &pages);
2285 while (mmu_unsync_walk(parent, &pages)) {
2286 struct kvm_mmu_page *sp;
2288 for_each_sp(pages, sp, parents, i) {
2289 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2290 mmu_pages_clear_parents(&parents);
2293 kvm_mmu_pages_init(parent, &parents, &pages);
2299 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2300 struct list_head *invalid_list)
2304 trace_kvm_mmu_prepare_zap_page(sp);
2305 ++kvm->stat.mmu_shadow_zapped;
2306 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2307 kvm_mmu_page_unlink_children(kvm, sp);
2308 kvm_mmu_unlink_parents(kvm, sp);
2310 if (!sp->role.invalid && !sp->role.direct)
2311 unaccount_shadowed(kvm, sp->gfn);
2314 kvm_unlink_unsync_page(kvm, sp);
2315 if (!sp->root_count) {
2318 list_move(&sp->link, invalid_list);
2319 kvm_mod_used_mmu_pages(kvm, -1);
2321 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2324 * The obsolete pages can not be used on any vcpus.
2325 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2327 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2328 kvm_reload_remote_mmus(kvm);
2331 sp->role.invalid = 1;
2335 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2336 struct list_head *invalid_list)
2338 struct kvm_mmu_page *sp, *nsp;
2340 if (list_empty(invalid_list))
2344 * wmb: make sure everyone sees our modifications to the page tables
2345 * rmb: make sure we see changes to vcpu->mode
2350 * Wait for all vcpus to exit guest mode and/or lockless shadow
2353 kvm_flush_remote_tlbs(kvm);
2355 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2356 WARN_ON(!sp->role.invalid || sp->root_count);
2357 kvm_mmu_free_page(sp);
2361 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2362 struct list_head *invalid_list)
2364 struct kvm_mmu_page *sp;
2366 if (list_empty(&kvm->arch.active_mmu_pages))
2369 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2370 struct kvm_mmu_page, link);
2371 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2377 * Changing the number of mmu pages allocated to the vm
2378 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2380 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2382 LIST_HEAD(invalid_list);
2384 spin_lock(&kvm->mmu_lock);
2386 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2387 /* Need to free some mmu pages to achieve the goal. */
2388 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2389 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2392 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2393 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2396 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2398 spin_unlock(&kvm->mmu_lock);
2401 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2403 struct kvm_mmu_page *sp;
2404 LIST_HEAD(invalid_list);
2407 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2409 spin_lock(&kvm->mmu_lock);
2410 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2411 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2414 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2416 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2417 spin_unlock(&kvm->mmu_lock);
2421 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2424 * The function is based on mtrr_type_lookup() in
2425 * arch/x86/kernel/cpu/mtrr/generic.c
2427 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2432 u8 prev_match, curr_match;
2433 int num_var_ranges = KVM_NR_VAR_MTRR;
2435 if (!mtrr_state->enabled)
2438 /* Make end inclusive end, instead of exclusive */
2441 /* Look in fixed ranges. Just return the type as per start */
2442 if (mtrr_state->have_fixed && (start < 0x100000)) {
2445 if (start < 0x80000) {
2447 idx += (start >> 16);
2448 return mtrr_state->fixed_ranges[idx];
2449 } else if (start < 0xC0000) {
2451 idx += ((start - 0x80000) >> 14);
2452 return mtrr_state->fixed_ranges[idx];
2453 } else if (start < 0x1000000) {
2455 idx += ((start - 0xC0000) >> 12);
2456 return mtrr_state->fixed_ranges[idx];
2461 * Look in variable ranges
2462 * Look of multiple ranges matching this address and pick type
2463 * as per MTRR precedence
2465 if (!(mtrr_state->enabled & 2))
2466 return mtrr_state->def_type;
2469 for (i = 0; i < num_var_ranges; ++i) {
2470 unsigned short start_state, end_state;
2472 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2475 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2476 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2477 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2478 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2480 start_state = ((start & mask) == (base & mask));
2481 end_state = ((end & mask) == (base & mask));
2482 if (start_state != end_state)
2485 if ((start & mask) != (base & mask))
2488 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2489 if (prev_match == 0xFF) {
2490 prev_match = curr_match;
2494 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2495 curr_match == MTRR_TYPE_UNCACHABLE)
2496 return MTRR_TYPE_UNCACHABLE;
2498 if ((prev_match == MTRR_TYPE_WRBACK &&
2499 curr_match == MTRR_TYPE_WRTHROUGH) ||
2500 (prev_match == MTRR_TYPE_WRTHROUGH &&
2501 curr_match == MTRR_TYPE_WRBACK)) {
2502 prev_match = MTRR_TYPE_WRTHROUGH;
2503 curr_match = MTRR_TYPE_WRTHROUGH;
2506 if (prev_match != curr_match)
2507 return MTRR_TYPE_UNCACHABLE;
2510 if (prev_match != 0xFF)
2513 return mtrr_state->def_type;
2516 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2520 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2521 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2522 if (mtrr == 0xfe || mtrr == 0xff)
2523 mtrr = MTRR_TYPE_WRBACK;
2526 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2528 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2530 trace_kvm_mmu_unsync_page(sp);
2531 ++vcpu->kvm->stat.mmu_unsync;
2534 kvm_mmu_mark_parents_unsync(sp);
2537 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2539 struct kvm_mmu_page *s;
2541 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2544 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2545 __kvm_unsync_page(vcpu, s);
2549 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2552 struct kvm_mmu_page *s;
2553 bool need_unsync = false;
2555 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2559 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2566 kvm_unsync_pages(vcpu, gfn);
2570 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2571 unsigned pte_access, int level,
2572 gfn_t gfn, pfn_t pfn, bool speculative,
2573 bool can_unsync, bool host_writable)
2578 if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2581 spte = PT_PRESENT_MASK;
2583 spte |= shadow_accessed_mask;
2585 if (pte_access & ACC_EXEC_MASK)
2586 spte |= shadow_x_mask;
2588 spte |= shadow_nx_mask;
2590 if (pte_access & ACC_USER_MASK)
2591 spte |= shadow_user_mask;
2593 if (level > PT_PAGE_TABLE_LEVEL)
2594 spte |= PT_PAGE_SIZE_MASK;
2596 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2597 kvm_is_reserved_pfn(pfn));
2600 spte |= SPTE_HOST_WRITEABLE;
2602 pte_access &= ~ACC_WRITE_MASK;
2604 spte |= (u64)pfn << PAGE_SHIFT;
2606 if (pte_access & ACC_WRITE_MASK) {
2609 * Other vcpu creates new sp in the window between
2610 * mapping_level() and acquiring mmu-lock. We can
2611 * allow guest to retry the access, the mapping can
2612 * be fixed if guest refault.
2614 if (level > PT_PAGE_TABLE_LEVEL &&
2615 has_wrprotected_page(vcpu->kvm, gfn, level))
2618 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2621 * Optimization: for pte sync, if spte was writable the hash
2622 * lookup is unnecessary (and expensive). Write protection
2623 * is responsibility of mmu_get_page / kvm_sync_page.
2624 * Same reasoning can be applied to dirty page accounting.
2626 if (!can_unsync && is_writable_pte(*sptep))
2629 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2630 pgprintk("%s: found shadow page for %llx, marking ro\n",
2633 pte_access &= ~ACC_WRITE_MASK;
2634 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2638 if (pte_access & ACC_WRITE_MASK) {
2639 mark_page_dirty(vcpu->kvm, gfn);
2640 spte |= shadow_dirty_mask;
2644 if (mmu_spte_update(sptep, spte))
2645 kvm_flush_remote_tlbs(vcpu->kvm);
2650 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2651 unsigned pte_access, int write_fault, int *emulate,
2652 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2655 int was_rmapped = 0;
2658 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2659 *sptep, write_fault, gfn);
2661 if (is_rmap_spte(*sptep)) {
2663 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2664 * the parent of the now unreachable PTE.
2666 if (level > PT_PAGE_TABLE_LEVEL &&
2667 !is_large_pte(*sptep)) {
2668 struct kvm_mmu_page *child;
2671 child = page_header(pte & PT64_BASE_ADDR_MASK);
2672 drop_parent_pte(child, sptep);
2673 kvm_flush_remote_tlbs(vcpu->kvm);
2674 } else if (pfn != spte_to_pfn(*sptep)) {
2675 pgprintk("hfn old %llx new %llx\n",
2676 spte_to_pfn(*sptep), pfn);
2677 drop_spte(vcpu->kvm, sptep);
2678 kvm_flush_remote_tlbs(vcpu->kvm);
2683 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2684 true, host_writable)) {
2687 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2690 if (unlikely(is_mmio_spte(*sptep) && emulate))
2693 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2694 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2695 is_large_pte(*sptep)? "2MB" : "4kB",
2696 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2698 if (!was_rmapped && is_large_pte(*sptep))
2699 ++vcpu->kvm->stat.lpages;
2701 if (is_shadow_present_pte(*sptep)) {
2703 rmap_count = rmap_add(vcpu, sptep, gfn);
2704 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2705 rmap_recycle(vcpu, sptep, gfn);
2709 kvm_release_pfn_clean(pfn);
2712 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2715 struct kvm_memory_slot *slot;
2717 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2719 return KVM_PFN_ERR_FAULT;
2721 return gfn_to_pfn_memslot_atomic(slot, gfn);
2724 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2725 struct kvm_mmu_page *sp,
2726 u64 *start, u64 *end)
2728 struct page *pages[PTE_PREFETCH_NUM];
2729 unsigned access = sp->role.access;
2733 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2734 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2737 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2741 for (i = 0; i < ret; i++, gfn++, start++)
2742 mmu_set_spte(vcpu, start, access, 0, NULL,
2743 sp->role.level, gfn, page_to_pfn(pages[i]),
2749 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2750 struct kvm_mmu_page *sp, u64 *sptep)
2752 u64 *spte, *start = NULL;
2755 WARN_ON(!sp->role.direct);
2757 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2760 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2761 if (is_shadow_present_pte(*spte) || spte == sptep) {
2764 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2772 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2774 struct kvm_mmu_page *sp;
2777 * Since it's no accessed bit on EPT, it's no way to
2778 * distinguish between actually accessed translations
2779 * and prefetched, so disable pte prefetch if EPT is
2782 if (!shadow_accessed_mask)
2785 sp = page_header(__pa(sptep));
2786 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2789 __direct_pte_prefetch(vcpu, sp, sptep);
2792 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2793 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2796 struct kvm_shadow_walk_iterator iterator;
2797 struct kvm_mmu_page *sp;
2801 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2804 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2805 if (iterator.level == level) {
2806 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2807 write, &emulate, level, gfn, pfn,
2808 prefault, map_writable);
2809 direct_pte_prefetch(vcpu, iterator.sptep);
2810 ++vcpu->stat.pf_fixed;
2814 drop_large_spte(vcpu, iterator.sptep);
2815 if (!is_shadow_present_pte(*iterator.sptep)) {
2816 u64 base_addr = iterator.addr;
2818 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2819 pseudo_gfn = base_addr >> PAGE_SHIFT;
2820 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2822 1, ACC_ALL, iterator.sptep);
2824 link_shadow_page(iterator.sptep, sp, true);
2830 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2834 info.si_signo = SIGBUS;
2836 info.si_code = BUS_MCEERR_AR;
2837 info.si_addr = (void __user *)address;
2838 info.si_addr_lsb = PAGE_SHIFT;
2840 send_sig_info(SIGBUS, &info, tsk);
2843 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2846 * Do not cache the mmio info caused by writing the readonly gfn
2847 * into the spte otherwise read access on readonly gfn also can
2848 * caused mmio page fault and treat it as mmio access.
2849 * Return 1 to tell kvm to emulate it.
2851 if (pfn == KVM_PFN_ERR_RO_FAULT)
2854 if (pfn == KVM_PFN_ERR_HWPOISON) {
2855 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2862 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2863 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2867 int level = *levelp;
2870 * Check if it's a transparent hugepage. If this would be an
2871 * hugetlbfs page, level wouldn't be set to
2872 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2875 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2876 level == PT_PAGE_TABLE_LEVEL &&
2877 PageTransCompound(pfn_to_page(pfn)) &&
2878 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2881 * mmu_notifier_retry was successful and we hold the
2882 * mmu_lock here, so the pmd can't become splitting
2883 * from under us, and in turn
2884 * __split_huge_page_refcount() can't run from under
2885 * us and we can safely transfer the refcount from
2886 * PG_tail to PG_head as we switch the pfn to tail to
2889 *levelp = level = PT_DIRECTORY_LEVEL;
2890 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2891 VM_BUG_ON((gfn & mask) != (pfn & mask));
2895 kvm_release_pfn_clean(pfn);
2903 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2904 pfn_t pfn, unsigned access, int *ret_val)
2908 /* The pfn is invalid, report the error! */
2909 if (unlikely(is_error_pfn(pfn))) {
2910 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2914 if (unlikely(is_noslot_pfn(pfn)))
2915 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2922 static bool page_fault_can_be_fast(u32 error_code)
2925 * Do not fix the mmio spte with invalid generation number which
2926 * need to be updated by slow page fault path.
2928 if (unlikely(error_code & PFERR_RSVD_MASK))
2932 * #PF can be fast only if the shadow page table is present and it
2933 * is caused by write-protect, that means we just need change the
2934 * W bit of the spte which can be done out of mmu-lock.
2936 if (!(error_code & PFERR_PRESENT_MASK) ||
2937 !(error_code & PFERR_WRITE_MASK))
2944 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2945 u64 *sptep, u64 spte)
2949 WARN_ON(!sp->role.direct);
2952 * The gfn of direct spte is stable since it is calculated
2955 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2958 * Theoretically we could also set dirty bit (and flush TLB) here in
2959 * order to eliminate unnecessary PML logging. See comments in
2960 * set_spte. But fast_page_fault is very unlikely to happen with PML
2961 * enabled, so we do not do this. This might result in the same GPA
2962 * to be logged in PML buffer again when the write really happens, and
2963 * eventually to be called by mark_page_dirty twice. But it's also no
2964 * harm. This also avoids the TLB flush needed after setting dirty bit
2965 * so non-PML cases won't be impacted.
2967 * Compare with set_spte where instead shadow_dirty_mask is set.
2969 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2970 mark_page_dirty(vcpu->kvm, gfn);
2977 * - true: let the vcpu to access on the same address again.
2978 * - false: let the real page fault path to fix it.
2980 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2983 struct kvm_shadow_walk_iterator iterator;
2984 struct kvm_mmu_page *sp;
2988 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2991 if (!page_fault_can_be_fast(error_code))
2994 walk_shadow_page_lockless_begin(vcpu);
2995 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2996 if (!is_shadow_present_pte(spte) || iterator.level < level)
3000 * If the mapping has been changed, let the vcpu fault on the
3001 * same address again.
3003 if (!is_rmap_spte(spte)) {
3008 sp = page_header(__pa(iterator.sptep));
3009 if (!is_last_spte(spte, sp->role.level))
3013 * Check if it is a spurious fault caused by TLB lazily flushed.
3015 * Need not check the access of upper level table entries since
3016 * they are always ACC_ALL.
3018 if (is_writable_pte(spte)) {
3024 * Currently, to simplify the code, only the spte write-protected
3025 * by dirty-log can be fast fixed.
3027 if (!spte_is_locklessly_modifiable(spte))
3031 * Do not fix write-permission on the large spte since we only dirty
3032 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
3033 * that means other pages are missed if its slot is dirty-logged.
3035 * Instead, we let the slow page fault path create a normal spte to
3038 * See the comments in kvm_arch_commit_memory_region().
3040 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3044 * Currently, fast page fault only works for direct mapping since
3045 * the gfn is not stable for indirect shadow page.
3046 * See Documentation/virtual/kvm/locking.txt to get more detail.
3048 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
3050 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3052 walk_shadow_page_lockless_end(vcpu);
3057 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3058 gva_t gva, pfn_t *pfn, bool write, bool *writable);
3059 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3061 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3062 gfn_t gfn, bool prefault)
3068 unsigned long mmu_seq;
3069 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3071 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3072 if (likely(!force_pt_level)) {
3073 level = mapping_level(vcpu, gfn);
3075 * This path builds a PAE pagetable - so we can map
3076 * 2mb pages at maximum. Therefore check if the level
3077 * is larger than that.
3079 if (level > PT_DIRECTORY_LEVEL)
3080 level = PT_DIRECTORY_LEVEL;
3082 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3084 level = PT_PAGE_TABLE_LEVEL;
3086 if (fast_page_fault(vcpu, v, level, error_code))
3089 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3092 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3095 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3098 spin_lock(&vcpu->kvm->mmu_lock);
3099 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3101 make_mmu_pages_available(vcpu);
3102 if (likely(!force_pt_level))
3103 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3104 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
3106 spin_unlock(&vcpu->kvm->mmu_lock);
3112 spin_unlock(&vcpu->kvm->mmu_lock);
3113 kvm_release_pfn_clean(pfn);
3118 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3121 struct kvm_mmu_page *sp;
3122 LIST_HEAD(invalid_list);
3124 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3127 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3128 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3129 vcpu->arch.mmu.direct_map)) {
3130 hpa_t root = vcpu->arch.mmu.root_hpa;
3132 spin_lock(&vcpu->kvm->mmu_lock);
3133 sp = page_header(root);
3135 if (!sp->root_count && sp->role.invalid) {
3136 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3137 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3139 spin_unlock(&vcpu->kvm->mmu_lock);
3140 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3144 spin_lock(&vcpu->kvm->mmu_lock);
3145 for (i = 0; i < 4; ++i) {
3146 hpa_t root = vcpu->arch.mmu.pae_root[i];
3149 root &= PT64_BASE_ADDR_MASK;
3150 sp = page_header(root);
3152 if (!sp->root_count && sp->role.invalid)
3153 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3156 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3158 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3159 spin_unlock(&vcpu->kvm->mmu_lock);
3160 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3163 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3167 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3168 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3175 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3177 struct kvm_mmu_page *sp;
3180 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3181 spin_lock(&vcpu->kvm->mmu_lock);
3182 make_mmu_pages_available(vcpu);
3183 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3186 spin_unlock(&vcpu->kvm->mmu_lock);
3187 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3188 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3189 for (i = 0; i < 4; ++i) {
3190 hpa_t root = vcpu->arch.mmu.pae_root[i];
3192 MMU_WARN_ON(VALID_PAGE(root));
3193 spin_lock(&vcpu->kvm->mmu_lock);
3194 make_mmu_pages_available(vcpu);
3195 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3197 PT32_ROOT_LEVEL, 1, ACC_ALL,
3199 root = __pa(sp->spt);
3201 spin_unlock(&vcpu->kvm->mmu_lock);
3202 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3204 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3211 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3213 struct kvm_mmu_page *sp;
3218 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3220 if (mmu_check_root(vcpu, root_gfn))
3224 * Do we shadow a long mode page table? If so we need to
3225 * write-protect the guests page table root.
3227 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3228 hpa_t root = vcpu->arch.mmu.root_hpa;
3230 MMU_WARN_ON(VALID_PAGE(root));
3232 spin_lock(&vcpu->kvm->mmu_lock);
3233 make_mmu_pages_available(vcpu);
3234 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3236 root = __pa(sp->spt);
3238 spin_unlock(&vcpu->kvm->mmu_lock);
3239 vcpu->arch.mmu.root_hpa = root;
3244 * We shadow a 32 bit page table. This may be a legacy 2-level
3245 * or a PAE 3-level page table. In either case we need to be aware that
3246 * the shadow page table may be a PAE or a long mode page table.
3248 pm_mask = PT_PRESENT_MASK;
3249 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3250 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3252 for (i = 0; i < 4; ++i) {
3253 hpa_t root = vcpu->arch.mmu.pae_root[i];
3255 MMU_WARN_ON(VALID_PAGE(root));
3256 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3257 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3258 if (!is_present_gpte(pdptr)) {
3259 vcpu->arch.mmu.pae_root[i] = 0;
3262 root_gfn = pdptr >> PAGE_SHIFT;
3263 if (mmu_check_root(vcpu, root_gfn))
3266 spin_lock(&vcpu->kvm->mmu_lock);
3267 make_mmu_pages_available(vcpu);
3268 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3271 root = __pa(sp->spt);
3273 spin_unlock(&vcpu->kvm->mmu_lock);
3275 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3277 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3280 * If we shadow a 32 bit page table with a long mode page
3281 * table we enter this path.
3283 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3284 if (vcpu->arch.mmu.lm_root == NULL) {
3286 * The additional page necessary for this is only
3287 * allocated on demand.
3292 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3293 if (lm_root == NULL)
3296 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3298 vcpu->arch.mmu.lm_root = lm_root;
3301 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3307 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3309 if (vcpu->arch.mmu.direct_map)
3310 return mmu_alloc_direct_roots(vcpu);
3312 return mmu_alloc_shadow_roots(vcpu);
3315 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3318 struct kvm_mmu_page *sp;
3320 if (vcpu->arch.mmu.direct_map)
3323 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3326 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3327 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3328 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3329 hpa_t root = vcpu->arch.mmu.root_hpa;
3330 sp = page_header(root);
3331 mmu_sync_children(vcpu, sp);
3332 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3335 for (i = 0; i < 4; ++i) {
3336 hpa_t root = vcpu->arch.mmu.pae_root[i];
3338 if (root && VALID_PAGE(root)) {
3339 root &= PT64_BASE_ADDR_MASK;
3340 sp = page_header(root);
3341 mmu_sync_children(vcpu, sp);
3344 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3347 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3349 spin_lock(&vcpu->kvm->mmu_lock);
3350 mmu_sync_roots(vcpu);
3351 spin_unlock(&vcpu->kvm->mmu_lock);
3353 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3355 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3356 u32 access, struct x86_exception *exception)
3359 exception->error_code = 0;
3363 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3365 struct x86_exception *exception)
3368 exception->error_code = 0;
3369 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3372 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3375 return vcpu_match_mmio_gpa(vcpu, addr);
3377 return vcpu_match_mmio_gva(vcpu, addr);
3382 * On direct hosts, the last spte is only allows two states
3383 * for mmio page fault:
3384 * - It is the mmio spte
3385 * - It is zapped or it is being zapped.
3387 * This function completely checks the spte when the last spte
3388 * is not the mmio spte.
3390 static bool check_direct_spte_mmio_pf(u64 spte)
3392 return __check_direct_spte_mmio_pf(spte);
3395 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3397 struct kvm_shadow_walk_iterator iterator;
3400 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3403 walk_shadow_page_lockless_begin(vcpu);
3404 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3405 if (!is_shadow_present_pte(spte))
3407 walk_shadow_page_lockless_end(vcpu);
3412 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3416 if (quickly_check_mmio_pf(vcpu, addr, direct))
3417 return RET_MMIO_PF_EMULATE;
3419 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3421 if (is_mmio_spte(spte)) {
3422 gfn_t gfn = get_mmio_spte_gfn(spte);
3423 unsigned access = get_mmio_spte_access(spte);
3425 if (!check_mmio_spte(vcpu->kvm, spte))
3426 return RET_MMIO_PF_INVALID;
3431 trace_handle_mmio_page_fault(addr, gfn, access);
3432 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3433 return RET_MMIO_PF_EMULATE;
3437 * It's ok if the gva is remapped by other cpus on shadow guest,
3438 * it's a BUG if the gfn is not a mmio page.
3440 if (direct && !check_direct_spte_mmio_pf(spte))
3441 return RET_MMIO_PF_BUG;
3444 * If the page table is zapped by other cpus, let CPU fault again on
3447 return RET_MMIO_PF_RETRY;
3449 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3451 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3452 u32 error_code, bool direct)
3456 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3457 WARN_ON(ret == RET_MMIO_PF_BUG);
3461 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3462 u32 error_code, bool prefault)
3467 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3469 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3470 r = handle_mmio_page_fault(vcpu, gva, error_code, true);
3472 if (likely(r != RET_MMIO_PF_INVALID))
3476 r = mmu_topup_memory_caches(vcpu);
3480 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3482 gfn = gva >> PAGE_SHIFT;
3484 return nonpaging_map(vcpu, gva & PAGE_MASK,
3485 error_code, gfn, prefault);
3488 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3490 struct kvm_arch_async_pf arch;
3492 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3494 arch.direct_map = vcpu->arch.mmu.direct_map;
3495 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3497 return kvm_setup_async_pf(vcpu, gva, gfn_to_hva(vcpu->kvm, gfn), &arch);
3500 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3502 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3503 kvm_event_needs_reinjection(vcpu)))
3506 return kvm_x86_ops->interrupt_allowed(vcpu);
3509 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3510 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3514 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3517 return false; /* *pfn has correct page already */
3519 if (!prefault && can_do_async_pf(vcpu)) {
3520 trace_kvm_try_async_get_page(gva, gfn);
3521 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3522 trace_kvm_async_pf_doublefault(gva, gfn);
3523 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3525 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3529 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3534 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3541 gfn_t gfn = gpa >> PAGE_SHIFT;
3542 unsigned long mmu_seq;
3543 int write = error_code & PFERR_WRITE_MASK;
3546 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3548 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3549 r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
3551 if (likely(r != RET_MMIO_PF_INVALID))
3555 r = mmu_topup_memory_caches(vcpu);
3559 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3560 if (likely(!force_pt_level)) {
3561 level = mapping_level(vcpu, gfn);
3562 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3564 level = PT_PAGE_TABLE_LEVEL;
3566 if (fast_page_fault(vcpu, gpa, level, error_code))
3569 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3572 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3575 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3578 spin_lock(&vcpu->kvm->mmu_lock);
3579 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3581 make_mmu_pages_available(vcpu);
3582 if (likely(!force_pt_level))
3583 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3584 r = __direct_map(vcpu, gpa, write, map_writable,
3585 level, gfn, pfn, prefault);
3586 spin_unlock(&vcpu->kvm->mmu_lock);
3591 spin_unlock(&vcpu->kvm->mmu_lock);
3592 kvm_release_pfn_clean(pfn);
3596 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3597 struct kvm_mmu *context)
3599 context->page_fault = nonpaging_page_fault;
3600 context->gva_to_gpa = nonpaging_gva_to_gpa;
3601 context->sync_page = nonpaging_sync_page;
3602 context->invlpg = nonpaging_invlpg;
3603 context->update_pte = nonpaging_update_pte;
3604 context->root_level = 0;
3605 context->shadow_root_level = PT32E_ROOT_LEVEL;
3606 context->root_hpa = INVALID_PAGE;
3607 context->direct_map = true;
3608 context->nx = false;
3611 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3613 mmu_free_roots(vcpu);
3616 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3618 return kvm_read_cr3(vcpu);
3621 static void inject_page_fault(struct kvm_vcpu *vcpu,
3622 struct x86_exception *fault)
3624 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3627 static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3628 unsigned access, int *nr_present)
3630 if (unlikely(is_mmio_spte(*sptep))) {
3631 if (gfn != get_mmio_spte_gfn(*sptep)) {
3632 mmu_spte_clear_no_track(sptep);
3637 mark_mmio_spte(kvm, sptep, gfn, access);
3644 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3649 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3650 return mmu->last_pte_bitmap & (1 << index);
3653 #define PTTYPE_EPT 18 /* arbitrary */
3654 #define PTTYPE PTTYPE_EPT
3655 #include "paging_tmpl.h"
3659 #include "paging_tmpl.h"
3663 #include "paging_tmpl.h"
3666 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3667 struct kvm_mmu *context)
3669 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3670 u64 exb_bit_rsvd = 0;
3671 u64 gbpages_bit_rsvd = 0;
3672 u64 nonleaf_bit8_rsvd = 0;
3674 context->bad_mt_xwr = 0;
3677 exb_bit_rsvd = rsvd_bits(63, 63);
3678 if (!guest_cpuid_has_gbpages(vcpu))
3679 gbpages_bit_rsvd = rsvd_bits(7, 7);
3682 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3683 * leaf entries) on AMD CPUs only.
3685 if (guest_cpuid_is_amd(vcpu))
3686 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3688 switch (context->root_level) {
3689 case PT32_ROOT_LEVEL:
3690 /* no rsvd bits for 2 level 4K page table entries */
3691 context->rsvd_bits_mask[0][1] = 0;
3692 context->rsvd_bits_mask[0][0] = 0;
3693 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3695 if (!is_pse(vcpu)) {
3696 context->rsvd_bits_mask[1][1] = 0;
3700 if (is_cpuid_PSE36())
3701 /* 36bits PSE 4MB page */
3702 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3704 /* 32 bits PSE 4MB page */
3705 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3707 case PT32E_ROOT_LEVEL:
3708 context->rsvd_bits_mask[0][2] =
3709 rsvd_bits(maxphyaddr, 63) |
3710 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3711 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3712 rsvd_bits(maxphyaddr, 62); /* PDE */
3713 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3714 rsvd_bits(maxphyaddr, 62); /* PTE */
3715 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3716 rsvd_bits(maxphyaddr, 62) |
3717 rsvd_bits(13, 20); /* large page */
3718 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3720 case PT64_ROOT_LEVEL:
3721 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3722 nonleaf_bit8_rsvd | rsvd_bits(7, 7) | rsvd_bits(maxphyaddr, 51);
3723 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3724 nonleaf_bit8_rsvd | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51);
3725 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3726 rsvd_bits(maxphyaddr, 51);
3727 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3728 rsvd_bits(maxphyaddr, 51);
3729 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3730 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3731 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3733 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3734 rsvd_bits(maxphyaddr, 51) |
3735 rsvd_bits(13, 20); /* large page */
3736 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3741 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3742 struct kvm_mmu *context, bool execonly)
3744 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3747 context->rsvd_bits_mask[0][3] =
3748 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3749 context->rsvd_bits_mask[0][2] =
3750 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3751 context->rsvd_bits_mask[0][1] =
3752 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3753 context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3756 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3757 context->rsvd_bits_mask[1][2] =
3758 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3759 context->rsvd_bits_mask[1][1] =
3760 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3761 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3763 for (pte = 0; pte < 64; pte++) {
3764 int rwx_bits = pte & 7;
3766 if (mt == 0x2 || mt == 0x3 || mt == 0x7 ||
3767 rwx_bits == 0x2 || rwx_bits == 0x6 ||
3768 (rwx_bits == 0x4 && !execonly))
3769 context->bad_mt_xwr |= (1ull << pte);
3773 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3774 struct kvm_mmu *mmu, bool ept)
3776 unsigned bit, byte, pfec;
3778 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3780 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3781 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3782 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3785 wf = pfec & PFERR_WRITE_MASK;
3786 uf = pfec & PFERR_USER_MASK;
3787 ff = pfec & PFERR_FETCH_MASK;
3789 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3790 * subject to SMAP restrictions, and cleared otherwise. The
3791 * bit is only meaningful if the SMAP bit is set in CR4.
3793 smapf = !(pfec & PFERR_RSVD_MASK);
3794 for (bit = 0; bit < 8; ++bit) {
3795 x = bit & ACC_EXEC_MASK;
3796 w = bit & ACC_WRITE_MASK;
3797 u = bit & ACC_USER_MASK;
3800 /* Not really needed: !nx will cause pte.nx to fault */
3802 /* Allow supervisor writes if !cr0.wp */
3803 w |= !is_write_protection(vcpu) && !uf;
3804 /* Disallow supervisor fetches of user code if cr4.smep */
3805 x &= !(cr4_smep && u && !uf);
3808 * SMAP:kernel-mode data accesses from user-mode
3809 * mappings should fault. A fault is considered
3810 * as a SMAP violation if all of the following
3811 * conditions are ture:
3812 * - X86_CR4_SMAP is set in CR4
3813 * - An user page is accessed
3814 * - Page fault in kernel mode
3815 * - if CPL = 3 or X86_EFLAGS_AC is clear
3817 * Here, we cover the first three conditions.
3818 * The fourth is computed dynamically in
3819 * permission_fault() and is in smapf.
3821 * Also, SMAP does not affect instruction
3822 * fetches, add the !ff check here to make it
3825 smap = cr4_smap && u && !uf && !ff;
3827 /* Not really needed: no U/S accesses on ept */
3830 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3832 map |= fault << bit;
3834 mmu->permissions[byte] = map;
3838 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3841 unsigned level, root_level = mmu->root_level;
3842 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3844 if (root_level == PT32E_ROOT_LEVEL)
3846 /* PT_PAGE_TABLE_LEVEL always terminates */
3847 map = 1 | (1 << ps_set_index);
3848 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3849 if (level <= PT_PDPE_LEVEL
3850 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3851 map |= 1 << (ps_set_index | (level - 1));
3853 mmu->last_pte_bitmap = map;
3856 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3857 struct kvm_mmu *context,
3860 context->nx = is_nx(vcpu);
3861 context->root_level = level;
3863 reset_rsvds_bits_mask(vcpu, context);
3864 update_permission_bitmask(vcpu, context, false);
3865 update_last_pte_bitmap(vcpu, context);
3867 MMU_WARN_ON(!is_pae(vcpu));
3868 context->page_fault = paging64_page_fault;
3869 context->gva_to_gpa = paging64_gva_to_gpa;
3870 context->sync_page = paging64_sync_page;
3871 context->invlpg = paging64_invlpg;
3872 context->update_pte = paging64_update_pte;
3873 context->shadow_root_level = level;
3874 context->root_hpa = INVALID_PAGE;
3875 context->direct_map = false;
3878 static void paging64_init_context(struct kvm_vcpu *vcpu,
3879 struct kvm_mmu *context)
3881 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3884 static void paging32_init_context(struct kvm_vcpu *vcpu,
3885 struct kvm_mmu *context)
3887 context->nx = false;
3888 context->root_level = PT32_ROOT_LEVEL;
3890 reset_rsvds_bits_mask(vcpu, context);
3891 update_permission_bitmask(vcpu, context, false);
3892 update_last_pte_bitmap(vcpu, context);
3894 context->page_fault = paging32_page_fault;
3895 context->gva_to_gpa = paging32_gva_to_gpa;
3896 context->sync_page = paging32_sync_page;
3897 context->invlpg = paging32_invlpg;
3898 context->update_pte = paging32_update_pte;
3899 context->shadow_root_level = PT32E_ROOT_LEVEL;
3900 context->root_hpa = INVALID_PAGE;
3901 context->direct_map = false;
3904 static void paging32E_init_context(struct kvm_vcpu *vcpu,
3905 struct kvm_mmu *context)
3907 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3910 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3912 struct kvm_mmu *context = &vcpu->arch.mmu;
3914 context->base_role.word = 0;
3915 context->page_fault = tdp_page_fault;
3916 context->sync_page = nonpaging_sync_page;
3917 context->invlpg = nonpaging_invlpg;
3918 context->update_pte = nonpaging_update_pte;
3919 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3920 context->root_hpa = INVALID_PAGE;
3921 context->direct_map = true;
3922 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3923 context->get_cr3 = get_cr3;
3924 context->get_pdptr = kvm_pdptr_read;
3925 context->inject_page_fault = kvm_inject_page_fault;
3927 if (!is_paging(vcpu)) {
3928 context->nx = false;
3929 context->gva_to_gpa = nonpaging_gva_to_gpa;
3930 context->root_level = 0;
3931 } else if (is_long_mode(vcpu)) {
3932 context->nx = is_nx(vcpu);
3933 context->root_level = PT64_ROOT_LEVEL;
3934 reset_rsvds_bits_mask(vcpu, context);
3935 context->gva_to_gpa = paging64_gva_to_gpa;
3936 } else if (is_pae(vcpu)) {
3937 context->nx = is_nx(vcpu);
3938 context->root_level = PT32E_ROOT_LEVEL;
3939 reset_rsvds_bits_mask(vcpu, context);
3940 context->gva_to_gpa = paging64_gva_to_gpa;
3942 context->nx = false;
3943 context->root_level = PT32_ROOT_LEVEL;
3944 reset_rsvds_bits_mask(vcpu, context);
3945 context->gva_to_gpa = paging32_gva_to_gpa;
3948 update_permission_bitmask(vcpu, context, false);
3949 update_last_pte_bitmap(vcpu, context);
3952 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
3954 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3955 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3956 struct kvm_mmu *context = &vcpu->arch.mmu;
3958 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
3960 if (!is_paging(vcpu))
3961 nonpaging_init_context(vcpu, context);
3962 else if (is_long_mode(vcpu))
3963 paging64_init_context(vcpu, context);
3964 else if (is_pae(vcpu))
3965 paging32E_init_context(vcpu, context);
3967 paging32_init_context(vcpu, context);
3969 context->base_role.nxe = is_nx(vcpu);
3970 context->base_role.cr4_pae = !!is_pae(vcpu);
3971 context->base_role.cr0_wp = is_write_protection(vcpu);
3972 context->base_role.smep_andnot_wp
3973 = smep && !is_write_protection(vcpu);
3974 context->base_role.smap_andnot_wp
3975 = smap && !is_write_protection(vcpu);
3977 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3979 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
3981 struct kvm_mmu *context = &vcpu->arch.mmu;
3983 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
3985 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3988 context->page_fault = ept_page_fault;
3989 context->gva_to_gpa = ept_gva_to_gpa;
3990 context->sync_page = ept_sync_page;
3991 context->invlpg = ept_invlpg;
3992 context->update_pte = ept_update_pte;
3993 context->root_level = context->shadow_root_level;
3994 context->root_hpa = INVALID_PAGE;
3995 context->direct_map = false;
3997 update_permission_bitmask(vcpu, context, true);
3998 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4000 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4002 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4004 struct kvm_mmu *context = &vcpu->arch.mmu;
4006 kvm_init_shadow_mmu(vcpu);
4007 context->set_cr3 = kvm_x86_ops->set_cr3;
4008 context->get_cr3 = get_cr3;
4009 context->get_pdptr = kvm_pdptr_read;
4010 context->inject_page_fault = kvm_inject_page_fault;
4013 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4015 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4017 g_context->get_cr3 = get_cr3;
4018 g_context->get_pdptr = kvm_pdptr_read;
4019 g_context->inject_page_fault = kvm_inject_page_fault;
4022 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
4023 * translation of l2_gpa to l1_gpa addresses is done using the
4024 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
4025 * functions between mmu and nested_mmu are swapped.
4027 if (!is_paging(vcpu)) {
4028 g_context->nx = false;
4029 g_context->root_level = 0;
4030 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4031 } else if (is_long_mode(vcpu)) {
4032 g_context->nx = is_nx(vcpu);
4033 g_context->root_level = PT64_ROOT_LEVEL;
4034 reset_rsvds_bits_mask(vcpu, g_context);
4035 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4036 } else if (is_pae(vcpu)) {
4037 g_context->nx = is_nx(vcpu);
4038 g_context->root_level = PT32E_ROOT_LEVEL;
4039 reset_rsvds_bits_mask(vcpu, g_context);
4040 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4042 g_context->nx = false;
4043 g_context->root_level = PT32_ROOT_LEVEL;
4044 reset_rsvds_bits_mask(vcpu, g_context);
4045 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4048 update_permission_bitmask(vcpu, g_context, false);
4049 update_last_pte_bitmap(vcpu, g_context);
4052 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4054 if (mmu_is_nested(vcpu))
4055 init_kvm_nested_mmu(vcpu);
4056 else if (tdp_enabled)
4057 init_kvm_tdp_mmu(vcpu);
4059 init_kvm_softmmu(vcpu);
4062 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4064 kvm_mmu_unload(vcpu);
4067 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4069 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4073 r = mmu_topup_memory_caches(vcpu);
4076 r = mmu_alloc_roots(vcpu);
4077 kvm_mmu_sync_roots(vcpu);
4080 /* set_cr3() should ensure TLB has been flushed */
4081 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4085 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4087 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4089 mmu_free_roots(vcpu);
4090 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4092 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4094 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4095 struct kvm_mmu_page *sp, u64 *spte,
4098 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4099 ++vcpu->kvm->stat.mmu_pde_zapped;
4103 ++vcpu->kvm->stat.mmu_pte_updated;
4104 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4107 static bool need_remote_flush(u64 old, u64 new)
4109 if (!is_shadow_present_pte(old))
4111 if (!is_shadow_present_pte(new))
4113 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4115 old ^= shadow_nx_mask;
4116 new ^= shadow_nx_mask;
4117 return (old & ~new & PT64_PERM_MASK) != 0;
4120 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
4121 bool remote_flush, bool local_flush)
4127 kvm_flush_remote_tlbs(vcpu->kvm);
4128 else if (local_flush)
4129 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4132 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4133 const u8 *new, int *bytes)
4139 * Assume that the pte write on a page table of the same type
4140 * as the current vcpu paging mode since we update the sptes only
4141 * when they have the same mode.
4143 if (is_pae(vcpu) && *bytes == 4) {
4144 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4147 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
4150 new = (const u8 *)&gentry;
4155 gentry = *(const u32 *)new;
4158 gentry = *(const u64 *)new;
4169 * If we're seeing too many writes to a page, it may no longer be a page table,
4170 * or we may be forking, in which case it is better to unmap the page.
4172 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4175 * Skip write-flooding detected for the sp whose level is 1, because
4176 * it can become unsync, then the guest page is not write-protected.
4178 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4181 return ++sp->write_flooding_count >= 3;
4185 * Misaligned accesses are too much trouble to fix up; also, they usually
4186 * indicate a page is not used as a page table.
4188 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4191 unsigned offset, pte_size, misaligned;
4193 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4194 gpa, bytes, sp->role.word);
4196 offset = offset_in_page(gpa);
4197 pte_size = sp->role.cr4_pae ? 8 : 4;
4200 * Sometimes, the OS only writes the last one bytes to update status
4201 * bits, for example, in linux, andb instruction is used in clear_bit().
4203 if (!(offset & (pte_size - 1)) && bytes == 1)
4206 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4207 misaligned |= bytes < 4;
4212 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4214 unsigned page_offset, quadrant;
4218 page_offset = offset_in_page(gpa);
4219 level = sp->role.level;
4221 if (!sp->role.cr4_pae) {
4222 page_offset <<= 1; /* 32->64 */
4224 * A 32-bit pde maps 4MB while the shadow pdes map
4225 * only 2MB. So we need to double the offset again
4226 * and zap two pdes instead of one.
4228 if (level == PT32_ROOT_LEVEL) {
4229 page_offset &= ~7; /* kill rounding error */
4233 quadrant = page_offset >> PAGE_SHIFT;
4234 page_offset &= ~PAGE_MASK;
4235 if (quadrant != sp->role.quadrant)
4239 spte = &sp->spt[page_offset / sizeof(*spte)];
4243 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4244 const u8 *new, int bytes)
4246 gfn_t gfn = gpa >> PAGE_SHIFT;
4247 struct kvm_mmu_page *sp;
4248 LIST_HEAD(invalid_list);
4249 u64 entry, gentry, *spte;
4251 bool remote_flush, local_flush, zap_page;
4252 union kvm_mmu_page_role mask = (union kvm_mmu_page_role) {
4256 .smep_andnot_wp = 1,
4257 .smap_andnot_wp = 1,
4261 * If we don't have indirect shadow pages, it means no page is
4262 * write-protected, so we can exit simply.
4264 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4267 zap_page = remote_flush = local_flush = false;
4269 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4271 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4274 * No need to care whether allocation memory is successful
4275 * or not since pte prefetch is skiped if it does not have
4276 * enough objects in the cache.
4278 mmu_topup_memory_caches(vcpu);
4280 spin_lock(&vcpu->kvm->mmu_lock);
4281 ++vcpu->kvm->stat.mmu_pte_write;
4282 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4284 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4285 if (detect_write_misaligned(sp, gpa, bytes) ||
4286 detect_write_flooding(sp)) {
4287 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4289 ++vcpu->kvm->stat.mmu_flooded;
4293 spte = get_written_sptes(sp, gpa, &npte);
4300 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4302 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4303 & mask.word) && rmap_can_add(vcpu))
4304 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4305 if (need_remote_flush(entry, *spte))
4306 remote_flush = true;
4310 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4311 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4312 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4313 spin_unlock(&vcpu->kvm->mmu_lock);
4316 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4321 if (vcpu->arch.mmu.direct_map)
4324 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4326 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4330 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4332 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4334 LIST_HEAD(invalid_list);
4336 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4339 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4340 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4343 ++vcpu->kvm->stat.mmu_recycled;
4345 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4348 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4350 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4351 return vcpu_match_mmio_gpa(vcpu, addr);
4353 return vcpu_match_mmio_gva(vcpu, addr);
4356 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4357 void *insn, int insn_len)
4359 int r, emulation_type = EMULTYPE_RETRY;
4360 enum emulation_result er;
4362 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4371 if (is_mmio_page_fault(vcpu, cr2))
4374 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4379 case EMULATE_USER_EXIT:
4380 ++vcpu->stat.mmio_exits;
4390 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4392 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4394 vcpu->arch.mmu.invlpg(vcpu, gva);
4395 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4396 ++vcpu->stat.invlpg;
4398 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4400 void kvm_enable_tdp(void)
4404 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4406 void kvm_disable_tdp(void)
4408 tdp_enabled = false;
4410 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4412 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4414 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4415 if (vcpu->arch.mmu.lm_root != NULL)
4416 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4419 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4425 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4426 * Therefore we need to allocate shadow page tables in the first
4427 * 4GB of memory, which happens to fit the DMA32 zone.
4429 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4433 vcpu->arch.mmu.pae_root = page_address(page);
4434 for (i = 0; i < 4; ++i)
4435 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4440 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4442 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4443 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4444 vcpu->arch.mmu.translate_gpa = translate_gpa;
4445 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4447 return alloc_mmu_pages(vcpu);
4450 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4452 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4457 /* The return value indicates if tlb flush on all vcpus is needed. */
4458 typedef bool (*slot_level_handler) (struct kvm *kvm, unsigned long *rmap);
4460 /* The caller should hold mmu-lock before calling this function. */
4462 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4463 slot_level_handler fn, int start_level, int end_level,
4464 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4466 struct slot_rmap_walk_iterator iterator;
4469 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4470 end_gfn, &iterator) {
4472 flush |= fn(kvm, iterator.rmap);
4474 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4475 if (flush && lock_flush_tlb) {
4476 kvm_flush_remote_tlbs(kvm);
4479 cond_resched_lock(&kvm->mmu_lock);
4483 if (flush && lock_flush_tlb) {
4484 kvm_flush_remote_tlbs(kvm);
4492 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4493 slot_level_handler fn, int start_level, int end_level,
4494 bool lock_flush_tlb)
4496 return slot_handle_level_range(kvm, memslot, fn, start_level,
4497 end_level, memslot->base_gfn,
4498 memslot->base_gfn + memslot->npages - 1,
4503 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4504 slot_level_handler fn, bool lock_flush_tlb)
4506 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4507 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4511 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4512 slot_level_handler fn, bool lock_flush_tlb)
4514 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4515 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4519 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4520 slot_level_handler fn, bool lock_flush_tlb)
4522 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4523 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4526 static bool slot_rmap_write_protect(struct kvm *kvm, unsigned long *rmapp)
4528 return __rmap_write_protect(kvm, rmapp, false);
4531 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4532 struct kvm_memory_slot *memslot)
4536 spin_lock(&kvm->mmu_lock);
4537 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4539 spin_unlock(&kvm->mmu_lock);
4542 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4543 * which do tlb flush out of mmu-lock should be serialized by
4544 * kvm->slots_lock otherwise tlb flush would be missed.
4546 lockdep_assert_held(&kvm->slots_lock);
4549 * We can flush all the TLBs out of the mmu lock without TLB
4550 * corruption since we just change the spte from writable to
4551 * readonly so that we only need to care the case of changing
4552 * spte from present to present (changing the spte from present
4553 * to nonpresent will flush all the TLBs immediately), in other
4554 * words, the only case we care is mmu_spte_update() where we
4555 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4556 * instead of PT_WRITABLE_MASK, that means it does not depend
4557 * on PT_WRITABLE_MASK anymore.
4560 kvm_flush_remote_tlbs(kvm);
4563 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4564 unsigned long *rmapp)
4567 struct rmap_iterator iter;
4568 int need_tlb_flush = 0;
4570 struct kvm_mmu_page *sp;
4573 for_each_rmap_spte(rmapp, &iter, sptep) {
4574 sp = page_header(__pa(sptep));
4575 pfn = spte_to_pfn(*sptep);
4578 * We cannot do huge page mapping for indirect shadow pages,
4579 * which are found on the last rmap (level = 1) when not using
4580 * tdp; such shadow pages are synced with the page table in
4581 * the guest, and the guest page table is using 4K page size
4582 * mapping if the indirect sp has level = 1.
4584 if (sp->role.direct &&
4585 !kvm_is_reserved_pfn(pfn) &&
4586 PageTransCompound(pfn_to_page(pfn))) {
4587 drop_spte(kvm, sptep);
4593 return need_tlb_flush;
4596 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4597 struct kvm_memory_slot *memslot)
4599 spin_lock(&kvm->mmu_lock);
4600 slot_handle_leaf(kvm, memslot, kvm_mmu_zap_collapsible_spte, true);
4601 spin_unlock(&kvm->mmu_lock);
4604 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4605 struct kvm_memory_slot *memslot)
4609 spin_lock(&kvm->mmu_lock);
4610 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4611 spin_unlock(&kvm->mmu_lock);
4613 lockdep_assert_held(&kvm->slots_lock);
4616 * It's also safe to flush TLBs out of mmu lock here as currently this
4617 * function is only used for dirty logging, in which case flushing TLB
4618 * out of mmu lock also guarantees no dirty pages will be lost in
4622 kvm_flush_remote_tlbs(kvm);
4624 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4626 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4627 struct kvm_memory_slot *memslot)
4631 spin_lock(&kvm->mmu_lock);
4632 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4634 spin_unlock(&kvm->mmu_lock);
4636 /* see kvm_mmu_slot_remove_write_access */
4637 lockdep_assert_held(&kvm->slots_lock);
4640 kvm_flush_remote_tlbs(kvm);
4642 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4644 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4645 struct kvm_memory_slot *memslot)
4649 spin_lock(&kvm->mmu_lock);
4650 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4651 spin_unlock(&kvm->mmu_lock);
4653 lockdep_assert_held(&kvm->slots_lock);
4655 /* see kvm_mmu_slot_leaf_clear_dirty */
4657 kvm_flush_remote_tlbs(kvm);
4659 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4661 #define BATCH_ZAP_PAGES 10
4662 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4664 struct kvm_mmu_page *sp, *node;
4668 list_for_each_entry_safe_reverse(sp, node,
4669 &kvm->arch.active_mmu_pages, link) {
4673 * No obsolete page exists before new created page since
4674 * active_mmu_pages is the FIFO list.
4676 if (!is_obsolete_sp(kvm, sp))
4680 * Since we are reversely walking the list and the invalid
4681 * list will be moved to the head, skip the invalid page
4682 * can help us to avoid the infinity list walking.
4684 if (sp->role.invalid)
4688 * Need not flush tlb since we only zap the sp with invalid
4689 * generation number.
4691 if (batch >= BATCH_ZAP_PAGES &&
4692 cond_resched_lock(&kvm->mmu_lock)) {
4697 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4698 &kvm->arch.zapped_obsolete_pages);
4706 * Should flush tlb before free page tables since lockless-walking
4707 * may use the pages.
4709 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4713 * Fast invalidate all shadow pages and use lock-break technique
4714 * to zap obsolete pages.
4716 * It's required when memslot is being deleted or VM is being
4717 * destroyed, in these cases, we should ensure that KVM MMU does
4718 * not use any resource of the being-deleted slot or all slots
4719 * after calling the function.
4721 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4723 spin_lock(&kvm->mmu_lock);
4724 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4725 kvm->arch.mmu_valid_gen++;
4728 * Notify all vcpus to reload its shadow page table
4729 * and flush TLB. Then all vcpus will switch to new
4730 * shadow page table with the new mmu_valid_gen.
4732 * Note: we should do this under the protection of
4733 * mmu-lock, otherwise, vcpu would purge shadow page
4734 * but miss tlb flush.
4736 kvm_reload_remote_mmus(kvm);
4738 kvm_zap_obsolete_pages(kvm);
4739 spin_unlock(&kvm->mmu_lock);
4742 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4744 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4747 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
4750 * The very rare case: if the generation-number is round,
4751 * zap all shadow pages.
4753 if (unlikely(kvm_current_mmio_generation(kvm) == 0)) {
4754 printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
4755 kvm_mmu_invalidate_zap_all_pages(kvm);
4759 static unsigned long
4760 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4763 int nr_to_scan = sc->nr_to_scan;
4764 unsigned long freed = 0;
4766 spin_lock(&kvm_lock);
4768 list_for_each_entry(kvm, &vm_list, vm_list) {
4770 LIST_HEAD(invalid_list);
4773 * Never scan more than sc->nr_to_scan VM instances.
4774 * Will not hit this condition practically since we do not try
4775 * to shrink more than one VM and it is very unlikely to see
4776 * !n_used_mmu_pages so many times.
4781 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4782 * here. We may skip a VM instance errorneosly, but we do not
4783 * want to shrink a VM that only started to populate its MMU
4786 if (!kvm->arch.n_used_mmu_pages &&
4787 !kvm_has_zapped_obsolete_pages(kvm))
4790 idx = srcu_read_lock(&kvm->srcu);
4791 spin_lock(&kvm->mmu_lock);
4793 if (kvm_has_zapped_obsolete_pages(kvm)) {
4794 kvm_mmu_commit_zap_page(kvm,
4795 &kvm->arch.zapped_obsolete_pages);
4799 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
4801 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4804 spin_unlock(&kvm->mmu_lock);
4805 srcu_read_unlock(&kvm->srcu, idx);
4808 * unfair on small ones
4809 * per-vm shrinkers cry out
4810 * sadness comes quickly
4812 list_move_tail(&kvm->vm_list, &vm_list);
4816 spin_unlock(&kvm_lock);
4820 static unsigned long
4821 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
4823 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4826 static struct shrinker mmu_shrinker = {
4827 .count_objects = mmu_shrink_count,
4828 .scan_objects = mmu_shrink_scan,
4829 .seeks = DEFAULT_SEEKS * 10,
4832 static void mmu_destroy_caches(void)
4834 if (pte_list_desc_cache)
4835 kmem_cache_destroy(pte_list_desc_cache);
4836 if (mmu_page_header_cache)
4837 kmem_cache_destroy(mmu_page_header_cache);
4840 int kvm_mmu_module_init(void)
4842 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4843 sizeof(struct pte_list_desc),
4845 if (!pte_list_desc_cache)
4848 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4849 sizeof(struct kvm_mmu_page),
4851 if (!mmu_page_header_cache)
4854 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
4857 register_shrinker(&mmu_shrinker);
4862 mmu_destroy_caches();
4867 * Caculate mmu pages needed for kvm.
4869 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4871 unsigned int nr_mmu_pages;
4872 unsigned int nr_pages = 0;
4873 struct kvm_memslots *slots;
4874 struct kvm_memory_slot *memslot;
4876 slots = kvm_memslots(kvm);
4878 kvm_for_each_memslot(memslot, slots)
4879 nr_pages += memslot->npages;
4881 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4882 nr_mmu_pages = max(nr_mmu_pages,
4883 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4885 return nr_mmu_pages;
4888 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4890 struct kvm_shadow_walk_iterator iterator;
4894 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4897 walk_shadow_page_lockless_begin(vcpu);
4898 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4899 sptes[iterator.level-1] = spte;
4901 if (!is_shadow_present_pte(spte))
4904 walk_shadow_page_lockless_end(vcpu);
4908 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4910 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4912 kvm_mmu_unload(vcpu);
4913 free_mmu_pages(vcpu);
4914 mmu_free_memory_caches(vcpu);
4917 void kvm_mmu_module_exit(void)
4919 mmu_destroy_caches();
4920 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4921 unregister_shrinker(&mmu_shrinker);
4922 mmu_audit_disable();