2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
202 access &= ACC_WRITE_MASK | ACC_USER_MASK;
204 trace_mark_mmio_spte(sptep, gfn, access);
205 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
208 static bool is_mmio_spte(u64 spte)
210 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
213 static gfn_t get_mmio_spte_gfn(u64 spte)
215 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
218 static unsigned get_mmio_spte_access(u64 spte)
220 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
223 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
225 if (unlikely(is_noslot_pfn(pfn))) {
226 mark_mmio_spte(sptep, gfn, access);
233 static inline u64 rsvd_bits(int s, int e)
235 return ((1ULL << (e - s + 1)) - 1) << s;
238 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
239 u64 dirty_mask, u64 nx_mask, u64 x_mask)
241 shadow_user_mask = user_mask;
242 shadow_accessed_mask = accessed_mask;
243 shadow_dirty_mask = dirty_mask;
244 shadow_nx_mask = nx_mask;
245 shadow_x_mask = x_mask;
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
249 static int is_cpuid_PSE36(void)
254 static int is_nx(struct kvm_vcpu *vcpu)
256 return vcpu->arch.efer & EFER_NX;
259 static int is_shadow_present_pte(u64 pte)
261 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
264 static int is_large_pte(u64 pte)
266 return pte & PT_PAGE_SIZE_MASK;
269 static int is_dirty_gpte(unsigned long pte)
271 return pte & PT_DIRTY_MASK;
274 static int is_rmap_spte(u64 pte)
276 return is_shadow_present_pte(pte);
279 static int is_last_spte(u64 pte, int level)
281 if (level == PT_PAGE_TABLE_LEVEL)
283 if (is_large_pte(pte))
288 static pfn_t spte_to_pfn(u64 pte)
290 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
293 static gfn_t pse36_gfn_delta(u32 gpte)
295 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
297 return (gpte & PT32_DIR_PSE36_MASK) << shift;
301 static void __set_spte(u64 *sptep, u64 spte)
306 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
311 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
313 return xchg(sptep, spte);
316 static u64 __get_spte_lockless(u64 *sptep)
318 return ACCESS_ONCE(*sptep);
321 static bool __check_direct_spte_mmio_pf(u64 spte)
323 /* It is valid if the spte is zapped. */
335 static void count_spte_clear(u64 *sptep, u64 spte)
337 struct kvm_mmu_page *sp = page_header(__pa(sptep));
339 if (is_shadow_present_pte(spte))
342 /* Ensure the spte is completely set before we increase the count */
344 sp->clear_spte_count++;
347 static void __set_spte(u64 *sptep, u64 spte)
349 union split_spte *ssptep, sspte;
351 ssptep = (union split_spte *)sptep;
352 sspte = (union split_spte)spte;
354 ssptep->spte_high = sspte.spte_high;
357 * If we map the spte from nonpresent to present, We should store
358 * the high bits firstly, then set present bit, so cpu can not
359 * fetch this spte while we are setting the spte.
363 ssptep->spte_low = sspte.spte_low;
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
368 union split_spte *ssptep, sspte;
370 ssptep = (union split_spte *)sptep;
371 sspte = (union split_spte)spte;
373 ssptep->spte_low = sspte.spte_low;
376 * If we map the spte from present to nonpresent, we should clear
377 * present bit firstly to avoid vcpu fetch the old high bits.
381 ssptep->spte_high = sspte.spte_high;
382 count_spte_clear(sptep, spte);
385 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
387 union split_spte *ssptep, sspte, orig;
389 ssptep = (union split_spte *)sptep;
390 sspte = (union split_spte)spte;
392 /* xchg acts as a barrier before the setting of the high bits */
393 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
394 orig.spte_high = ssptep->spte_high;
395 ssptep->spte_high = sspte.spte_high;
396 count_spte_clear(sptep, spte);
402 * The idea using the light way get the spte on x86_32 guest is from
403 * gup_get_pte(arch/x86/mm/gup.c).
404 * The difference is we can not catch the spte tlb flush if we leave
405 * guest mode, so we emulate it by increase clear_spte_count when spte
408 static u64 __get_spte_lockless(u64 *sptep)
410 struct kvm_mmu_page *sp = page_header(__pa(sptep));
411 union split_spte spte, *orig = (union split_spte *)sptep;
415 count = sp->clear_spte_count;
418 spte.spte_low = orig->spte_low;
421 spte.spte_high = orig->spte_high;
424 if (unlikely(spte.spte_low != orig->spte_low ||
425 count != sp->clear_spte_count))
431 static bool __check_direct_spte_mmio_pf(u64 spte)
433 union split_spte sspte = (union split_spte)spte;
434 u32 high_mmio_mask = shadow_mmio_mask >> 32;
436 /* It is valid if the spte is zapped. */
440 /* It is valid if the spte is being zapped. */
441 if (sspte.spte_low == 0ull &&
442 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
449 static bool spte_is_locklessly_modifiable(u64 spte)
451 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
452 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
455 static bool spte_has_volatile_bits(u64 spte)
458 * Always atomicly update spte if it can be updated
459 * out of mmu-lock, it can ensure dirty bit is not lost,
460 * also, it can help us to get a stable is_writable_pte()
461 * to ensure tlb flush is not missed.
463 if (spte_is_locklessly_modifiable(spte))
466 if (!shadow_accessed_mask)
469 if (!is_shadow_present_pte(spte))
472 if ((spte & shadow_accessed_mask) &&
473 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
479 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
481 return (old_spte & bit_mask) && !(new_spte & bit_mask);
484 /* Rules for using mmu_spte_set:
485 * Set the sptep from nonpresent to present.
486 * Note: the sptep being assigned *must* be either not present
487 * or in a state where the hardware will not attempt to update
490 static void mmu_spte_set(u64 *sptep, u64 new_spte)
492 WARN_ON(is_shadow_present_pte(*sptep));
493 __set_spte(sptep, new_spte);
496 /* Rules for using mmu_spte_update:
497 * Update the state bits, it means the mapped pfn is not changged.
499 * Whenever we overwrite a writable spte with a read-only one we
500 * should flush remote TLBs. Otherwise rmap_write_protect
501 * will find a read-only spte, even though the writable spte
502 * might be cached on a CPU's TLB, the return value indicates this
505 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
507 u64 old_spte = *sptep;
510 WARN_ON(!is_rmap_spte(new_spte));
512 if (!is_shadow_present_pte(old_spte)) {
513 mmu_spte_set(sptep, new_spte);
517 if (!spte_has_volatile_bits(old_spte))
518 __update_clear_spte_fast(sptep, new_spte);
520 old_spte = __update_clear_spte_slow(sptep, new_spte);
523 * For the spte updated out of mmu-lock is safe, since
524 * we always atomicly update it, see the comments in
525 * spte_has_volatile_bits().
527 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
530 if (!shadow_accessed_mask)
533 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
534 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
535 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
536 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
542 * Rules for using mmu_spte_clear_track_bits:
543 * It sets the sptep from present to nonpresent, and track the
544 * state bits, it is used to clear the last level sptep.
546 static int mmu_spte_clear_track_bits(u64 *sptep)
549 u64 old_spte = *sptep;
551 if (!spte_has_volatile_bits(old_spte))
552 __update_clear_spte_fast(sptep, 0ull);
554 old_spte = __update_clear_spte_slow(sptep, 0ull);
556 if (!is_rmap_spte(old_spte))
559 pfn = spte_to_pfn(old_spte);
562 * KVM does not hold the refcount of the page used by
563 * kvm mmu, before reclaiming the page, we should
564 * unmap it from mmu first.
566 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
568 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
569 kvm_set_pfn_accessed(pfn);
570 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
571 kvm_set_pfn_dirty(pfn);
576 * Rules for using mmu_spte_clear_no_track:
577 * Directly clear spte without caring the state bits of sptep,
578 * it is used to set the upper level spte.
580 static void mmu_spte_clear_no_track(u64 *sptep)
582 __update_clear_spte_fast(sptep, 0ull);
585 static u64 mmu_spte_get_lockless(u64 *sptep)
587 return __get_spte_lockless(sptep);
590 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
593 * Prevent page table teardown by making any free-er wait during
594 * kvm_flush_remote_tlbs() IPI to all active vcpus.
597 vcpu->mode = READING_SHADOW_PAGE_TABLES;
599 * Make sure a following spte read is not reordered ahead of the write
605 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
608 * Make sure the write to vcpu->mode is not reordered in front of
609 * reads to sptes. If it does, kvm_commit_zap_page() can see us
610 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
613 vcpu->mode = OUTSIDE_GUEST_MODE;
617 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
618 struct kmem_cache *base_cache, int min)
622 if (cache->nobjs >= min)
624 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
625 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
628 cache->objects[cache->nobjs++] = obj;
633 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
638 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
639 struct kmem_cache *cache)
642 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
645 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
650 if (cache->nobjs >= min)
652 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
653 page = (void *)__get_free_page(GFP_KERNEL);
656 cache->objects[cache->nobjs++] = page;
661 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
664 free_page((unsigned long)mc->objects[--mc->nobjs]);
667 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
671 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
672 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
675 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
678 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
679 mmu_page_header_cache, 4);
684 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
686 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
687 pte_list_desc_cache);
688 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
689 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
690 mmu_page_header_cache);
693 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
698 p = mc->objects[--mc->nobjs];
702 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
704 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
707 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
709 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
712 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
714 if (!sp->role.direct)
715 return sp->gfns[index];
717 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
720 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
723 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
725 sp->gfns[index] = gfn;
729 * Return the pointer to the large page information for a given gfn,
730 * handling slots that are not large page aligned.
732 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
733 struct kvm_memory_slot *slot,
738 idx = gfn_to_index(gfn, slot->base_gfn, level);
739 return &slot->arch.lpage_info[level - 2][idx];
742 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
744 struct kvm_memory_slot *slot;
745 struct kvm_lpage_info *linfo;
748 slot = gfn_to_memslot(kvm, gfn);
749 for (i = PT_DIRECTORY_LEVEL;
750 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
751 linfo = lpage_info_slot(gfn, slot, i);
752 linfo->write_count += 1;
754 kvm->arch.indirect_shadow_pages++;
757 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
759 struct kvm_memory_slot *slot;
760 struct kvm_lpage_info *linfo;
763 slot = gfn_to_memslot(kvm, gfn);
764 for (i = PT_DIRECTORY_LEVEL;
765 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
766 linfo = lpage_info_slot(gfn, slot, i);
767 linfo->write_count -= 1;
768 WARN_ON(linfo->write_count < 0);
770 kvm->arch.indirect_shadow_pages--;
773 static int has_wrprotected_page(struct kvm *kvm,
777 struct kvm_memory_slot *slot;
778 struct kvm_lpage_info *linfo;
780 slot = gfn_to_memslot(kvm, gfn);
782 linfo = lpage_info_slot(gfn, slot, level);
783 return linfo->write_count;
789 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
791 unsigned long page_size;
794 page_size = kvm_host_page_size(kvm, gfn);
796 for (i = PT_PAGE_TABLE_LEVEL;
797 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
798 if (page_size >= KVM_HPAGE_SIZE(i))
807 static struct kvm_memory_slot *
808 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
811 struct kvm_memory_slot *slot;
813 slot = gfn_to_memslot(vcpu->kvm, gfn);
814 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
815 (no_dirty_log && slot->dirty_bitmap))
821 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
823 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
826 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
828 int host_level, level, max_level;
830 host_level = host_mapping_level(vcpu->kvm, large_gfn);
832 if (host_level == PT_PAGE_TABLE_LEVEL)
835 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
837 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
838 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
845 * Pte mapping structures:
847 * If pte_list bit zero is zero, then pte_list point to the spte.
849 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
850 * pte_list_desc containing more mappings.
852 * Returns the number of pte entries before the spte was added or zero if
853 * the spte was not added.
856 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
857 unsigned long *pte_list)
859 struct pte_list_desc *desc;
863 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
864 *pte_list = (unsigned long)spte;
865 } else if (!(*pte_list & 1)) {
866 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
867 desc = mmu_alloc_pte_list_desc(vcpu);
868 desc->sptes[0] = (u64 *)*pte_list;
869 desc->sptes[1] = spte;
870 *pte_list = (unsigned long)desc | 1;
873 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
874 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
875 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
877 count += PTE_LIST_EXT;
879 if (desc->sptes[PTE_LIST_EXT-1]) {
880 desc->more = mmu_alloc_pte_list_desc(vcpu);
883 for (i = 0; desc->sptes[i]; ++i)
885 desc->sptes[i] = spte;
891 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
892 int i, struct pte_list_desc *prev_desc)
896 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
898 desc->sptes[i] = desc->sptes[j];
899 desc->sptes[j] = NULL;
902 if (!prev_desc && !desc->more)
903 *pte_list = (unsigned long)desc->sptes[0];
906 prev_desc->more = desc->more;
908 *pte_list = (unsigned long)desc->more | 1;
909 mmu_free_pte_list_desc(desc);
912 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
914 struct pte_list_desc *desc;
915 struct pte_list_desc *prev_desc;
919 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
921 } else if (!(*pte_list & 1)) {
922 rmap_printk("pte_list_remove: %p 1->0\n", spte);
923 if ((u64 *)*pte_list != spte) {
924 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
929 rmap_printk("pte_list_remove: %p many->many\n", spte);
930 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
933 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
934 if (desc->sptes[i] == spte) {
935 pte_list_desc_remove_entry(pte_list,
943 pr_err("pte_list_remove: %p many->many\n", spte);
948 typedef void (*pte_list_walk_fn) (u64 *spte);
949 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
951 struct pte_list_desc *desc;
957 if (!(*pte_list & 1))
958 return fn((u64 *)*pte_list);
960 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
962 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
968 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
969 struct kvm_memory_slot *slot)
973 idx = gfn_to_index(gfn, slot->base_gfn, level);
974 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
978 * Take gfn and return the reverse mapping to it.
980 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
982 struct kvm_memory_slot *slot;
984 slot = gfn_to_memslot(kvm, gfn);
985 return __gfn_to_rmap(gfn, level, slot);
988 static bool rmap_can_add(struct kvm_vcpu *vcpu)
990 struct kvm_mmu_memory_cache *cache;
992 cache = &vcpu->arch.mmu_pte_list_desc_cache;
993 return mmu_memory_cache_free_objects(cache);
996 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
998 struct kvm_mmu_page *sp;
999 unsigned long *rmapp;
1001 sp = page_header(__pa(spte));
1002 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1003 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1004 return pte_list_add(vcpu, spte, rmapp);
1007 static void rmap_remove(struct kvm *kvm, u64 *spte)
1009 struct kvm_mmu_page *sp;
1011 unsigned long *rmapp;
1013 sp = page_header(__pa(spte));
1014 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1015 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1016 pte_list_remove(spte, rmapp);
1020 * Used by the following functions to iterate through the sptes linked by a
1021 * rmap. All fields are private and not assumed to be used outside.
1023 struct rmap_iterator {
1024 /* private fields */
1025 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1026 int pos; /* index of the sptep */
1030 * Iteration must be started by this function. This should also be used after
1031 * removing/dropping sptes from the rmap link because in such cases the
1032 * information in the itererator may not be valid.
1034 * Returns sptep if found, NULL otherwise.
1036 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1046 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1048 return iter->desc->sptes[iter->pos];
1052 * Must be used with a valid iterator: e.g. after rmap_get_first().
1054 * Returns sptep if found, NULL otherwise.
1056 static u64 *rmap_get_next(struct rmap_iterator *iter)
1059 if (iter->pos < PTE_LIST_EXT - 1) {
1063 sptep = iter->desc->sptes[iter->pos];
1068 iter->desc = iter->desc->more;
1072 /* desc->sptes[0] cannot be NULL */
1073 return iter->desc->sptes[iter->pos];
1080 static void drop_spte(struct kvm *kvm, u64 *sptep)
1082 if (mmu_spte_clear_track_bits(sptep))
1083 rmap_remove(kvm, sptep);
1087 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1089 if (is_large_pte(*sptep)) {
1090 WARN_ON(page_header(__pa(sptep))->role.level ==
1091 PT_PAGE_TABLE_LEVEL);
1092 drop_spte(kvm, sptep);
1100 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1102 if (__drop_large_spte(vcpu->kvm, sptep))
1103 kvm_flush_remote_tlbs(vcpu->kvm);
1107 * Write-protect on the specified @sptep, @pt_protect indicates whether
1108 * spte writ-protection is caused by protecting shadow page table.
1109 * @flush indicates whether tlb need be flushed.
1111 * Note: write protection is difference between drity logging and spte
1113 * - for dirty logging, the spte can be set to writable at anytime if
1114 * its dirty bitmap is properly set.
1115 * - for spte protection, the spte can be writable only after unsync-ing
1118 * Return true if the spte is dropped.
1121 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1125 if (!is_writable_pte(spte) &&
1126 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1129 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1131 if (__drop_large_spte(kvm, sptep)) {
1137 spte &= ~SPTE_MMU_WRITEABLE;
1138 spte = spte & ~PT_WRITABLE_MASK;
1140 *flush |= mmu_spte_update(sptep, spte);
1144 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1148 struct rmap_iterator iter;
1151 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1152 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1153 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1154 sptep = rmap_get_first(*rmapp, &iter);
1158 sptep = rmap_get_next(&iter);
1165 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1166 * @kvm: kvm instance
1167 * @slot: slot to protect
1168 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1169 * @mask: indicates which pages we should protect
1171 * Used when we do not need to care about huge page mappings: e.g. during dirty
1172 * logging we do not have any such mappings.
1174 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1175 struct kvm_memory_slot *slot,
1176 gfn_t gfn_offset, unsigned long mask)
1178 unsigned long *rmapp;
1181 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1182 PT_PAGE_TABLE_LEVEL, slot);
1183 __rmap_write_protect(kvm, rmapp, false);
1185 /* clear the first set bit */
1190 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1192 struct kvm_memory_slot *slot;
1193 unsigned long *rmapp;
1195 bool write_protected = false;
1197 slot = gfn_to_memslot(kvm, gfn);
1199 for (i = PT_PAGE_TABLE_LEVEL;
1200 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1201 rmapp = __gfn_to_rmap(gfn, i, slot);
1202 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1205 return write_protected;
1208 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1209 struct kvm_memory_slot *slot, unsigned long data)
1212 struct rmap_iterator iter;
1213 int need_tlb_flush = 0;
1215 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1216 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1217 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1219 drop_spte(kvm, sptep);
1223 return need_tlb_flush;
1226 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1227 struct kvm_memory_slot *slot, unsigned long data)
1230 struct rmap_iterator iter;
1233 pte_t *ptep = (pte_t *)data;
1236 WARN_ON(pte_huge(*ptep));
1237 new_pfn = pte_pfn(*ptep);
1239 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1240 BUG_ON(!is_shadow_present_pte(*sptep));
1241 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1245 if (pte_write(*ptep)) {
1246 drop_spte(kvm, sptep);
1247 sptep = rmap_get_first(*rmapp, &iter);
1249 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1250 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1252 new_spte &= ~PT_WRITABLE_MASK;
1253 new_spte &= ~SPTE_HOST_WRITEABLE;
1254 new_spte &= ~shadow_accessed_mask;
1256 mmu_spte_clear_track_bits(sptep);
1257 mmu_spte_set(sptep, new_spte);
1258 sptep = rmap_get_next(&iter);
1263 kvm_flush_remote_tlbs(kvm);
1268 static int kvm_handle_hva_range(struct kvm *kvm,
1269 unsigned long start,
1272 int (*handler)(struct kvm *kvm,
1273 unsigned long *rmapp,
1274 struct kvm_memory_slot *slot,
1275 unsigned long data))
1279 struct kvm_memslots *slots;
1280 struct kvm_memory_slot *memslot;
1282 slots = kvm_memslots(kvm);
1284 kvm_for_each_memslot(memslot, slots) {
1285 unsigned long hva_start, hva_end;
1286 gfn_t gfn_start, gfn_end;
1288 hva_start = max(start, memslot->userspace_addr);
1289 hva_end = min(end, memslot->userspace_addr +
1290 (memslot->npages << PAGE_SHIFT));
1291 if (hva_start >= hva_end)
1294 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1295 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1297 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1298 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1300 for (j = PT_PAGE_TABLE_LEVEL;
1301 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1302 unsigned long idx, idx_end;
1303 unsigned long *rmapp;
1306 * {idx(page_j) | page_j intersects with
1307 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1309 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1310 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1312 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1314 for (; idx <= idx_end; ++idx)
1315 ret |= handler(kvm, rmapp++, memslot, data);
1322 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1324 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1325 struct kvm_memory_slot *slot,
1326 unsigned long data))
1328 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1331 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1333 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1336 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1338 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1341 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1343 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1346 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1347 struct kvm_memory_slot *slot, unsigned long data)
1350 struct rmap_iterator uninitialized_var(iter);
1354 * In case of absence of EPT Access and Dirty Bits supports,
1355 * emulate the accessed bit for EPT, by checking if this page has
1356 * an EPT mapping, and clearing it if it does. On the next access,
1357 * a new EPT mapping will be established.
1358 * This has some overhead, but not as much as the cost of swapping
1359 * out actively used pages or breaking up actively used hugepages.
1361 if (!shadow_accessed_mask) {
1362 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1366 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1367 sptep = rmap_get_next(&iter)) {
1368 BUG_ON(!is_shadow_present_pte(*sptep));
1370 if (*sptep & shadow_accessed_mask) {
1372 clear_bit((ffs(shadow_accessed_mask) - 1),
1373 (unsigned long *)sptep);
1377 /* @data has hva passed to kvm_age_hva(). */
1378 trace_kvm_age_page(data, slot, young);
1382 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1383 struct kvm_memory_slot *slot, unsigned long data)
1386 struct rmap_iterator iter;
1390 * If there's no access bit in the secondary pte set by the
1391 * hardware it's up to gup-fast/gup to set the access bit in
1392 * the primary pte or in the page structure.
1394 if (!shadow_accessed_mask)
1397 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1398 sptep = rmap_get_next(&iter)) {
1399 BUG_ON(!is_shadow_present_pte(*sptep));
1401 if (*sptep & shadow_accessed_mask) {
1410 #define RMAP_RECYCLE_THRESHOLD 1000
1412 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1414 unsigned long *rmapp;
1415 struct kvm_mmu_page *sp;
1417 sp = page_header(__pa(spte));
1419 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1421 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1422 kvm_flush_remote_tlbs(vcpu->kvm);
1425 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1427 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1430 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1432 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1436 static int is_empty_shadow_page(u64 *spt)
1441 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1442 if (is_shadow_present_pte(*pos)) {
1443 printk(KERN_ERR "%s: %p %llx\n", __func__,
1452 * This value is the sum of all of the kvm instances's
1453 * kvm->arch.n_used_mmu_pages values. We need a global,
1454 * aggregate version in order to make the slab shrinker
1457 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1459 kvm->arch.n_used_mmu_pages += nr;
1460 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1463 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1465 ASSERT(is_empty_shadow_page(sp->spt));
1466 hlist_del(&sp->hash_link);
1467 list_del(&sp->link);
1468 free_page((unsigned long)sp->spt);
1469 if (!sp->role.direct)
1470 free_page((unsigned long)sp->gfns);
1471 kmem_cache_free(mmu_page_header_cache, sp);
1474 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1476 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1479 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1480 struct kvm_mmu_page *sp, u64 *parent_pte)
1485 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1488 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1491 pte_list_remove(parent_pte, &sp->parent_ptes);
1494 static void drop_parent_pte(struct kvm_mmu_page *sp,
1497 mmu_page_remove_parent_pte(sp, parent_pte);
1498 mmu_spte_clear_no_track(parent_pte);
1501 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1502 u64 *parent_pte, int direct)
1504 struct kvm_mmu_page *sp;
1505 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1506 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1508 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1509 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1510 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1511 sp->parent_ptes = 0;
1512 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1513 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1517 static void mark_unsync(u64 *spte);
1518 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1520 pte_list_walk(&sp->parent_ptes, mark_unsync);
1523 static void mark_unsync(u64 *spte)
1525 struct kvm_mmu_page *sp;
1528 sp = page_header(__pa(spte));
1529 index = spte - sp->spt;
1530 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1532 if (sp->unsync_children++)
1534 kvm_mmu_mark_parents_unsync(sp);
1537 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1538 struct kvm_mmu_page *sp)
1543 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1547 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1548 struct kvm_mmu_page *sp, u64 *spte,
1554 #define KVM_PAGE_ARRAY_NR 16
1556 struct kvm_mmu_pages {
1557 struct mmu_page_and_offset {
1558 struct kvm_mmu_page *sp;
1560 } page[KVM_PAGE_ARRAY_NR];
1564 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1570 for (i=0; i < pvec->nr; i++)
1571 if (pvec->page[i].sp == sp)
1574 pvec->page[pvec->nr].sp = sp;
1575 pvec->page[pvec->nr].idx = idx;
1577 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1580 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1581 struct kvm_mmu_pages *pvec)
1583 int i, ret, nr_unsync_leaf = 0;
1585 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1586 struct kvm_mmu_page *child;
1587 u64 ent = sp->spt[i];
1589 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1590 goto clear_child_bitmap;
1592 child = page_header(ent & PT64_BASE_ADDR_MASK);
1594 if (child->unsync_children) {
1595 if (mmu_pages_add(pvec, child, i))
1598 ret = __mmu_unsync_walk(child, pvec);
1600 goto clear_child_bitmap;
1602 nr_unsync_leaf += ret;
1605 } else if (child->unsync) {
1607 if (mmu_pages_add(pvec, child, i))
1610 goto clear_child_bitmap;
1615 __clear_bit(i, sp->unsync_child_bitmap);
1616 sp->unsync_children--;
1617 WARN_ON((int)sp->unsync_children < 0);
1621 return nr_unsync_leaf;
1624 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1625 struct kvm_mmu_pages *pvec)
1627 if (!sp->unsync_children)
1630 mmu_pages_add(pvec, sp, 0);
1631 return __mmu_unsync_walk(sp, pvec);
1634 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1636 WARN_ON(!sp->unsync);
1637 trace_kvm_mmu_sync_page(sp);
1639 --kvm->stat.mmu_unsync;
1642 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1643 struct list_head *invalid_list);
1644 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1645 struct list_head *invalid_list);
1647 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1648 hlist_for_each_entry(sp, pos, \
1649 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1650 if ((sp)->gfn != (gfn)) {} else
1652 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1653 hlist_for_each_entry(sp, pos, \
1654 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1655 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1656 (sp)->role.invalid) {} else
1658 /* @sp->gfn should be write-protected at the call site */
1659 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1660 struct list_head *invalid_list, bool clear_unsync)
1662 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1663 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1668 kvm_unlink_unsync_page(vcpu->kvm, sp);
1670 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1671 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1675 kvm_mmu_flush_tlb(vcpu);
1679 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1680 struct kvm_mmu_page *sp)
1682 LIST_HEAD(invalid_list);
1685 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1687 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1692 #ifdef CONFIG_KVM_MMU_AUDIT
1693 #include "mmu_audit.c"
1695 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1696 static void mmu_audit_disable(void) { }
1699 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1700 struct list_head *invalid_list)
1702 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1705 /* @gfn should be write-protected at the call site */
1706 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1708 struct kvm_mmu_page *s;
1709 struct hlist_node *node;
1710 LIST_HEAD(invalid_list);
1713 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1717 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1718 kvm_unlink_unsync_page(vcpu->kvm, s);
1719 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1720 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1721 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1727 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1729 kvm_mmu_flush_tlb(vcpu);
1732 struct mmu_page_path {
1733 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1734 unsigned int idx[PT64_ROOT_LEVEL-1];
1737 #define for_each_sp(pvec, sp, parents, i) \
1738 for (i = mmu_pages_next(&pvec, &parents, -1), \
1739 sp = pvec.page[i].sp; \
1740 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1741 i = mmu_pages_next(&pvec, &parents, i))
1743 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1744 struct mmu_page_path *parents,
1749 for (n = i+1; n < pvec->nr; n++) {
1750 struct kvm_mmu_page *sp = pvec->page[n].sp;
1752 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1753 parents->idx[0] = pvec->page[n].idx;
1757 parents->parent[sp->role.level-2] = sp;
1758 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1764 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1766 struct kvm_mmu_page *sp;
1767 unsigned int level = 0;
1770 unsigned int idx = parents->idx[level];
1772 sp = parents->parent[level];
1776 --sp->unsync_children;
1777 WARN_ON((int)sp->unsync_children < 0);
1778 __clear_bit(idx, sp->unsync_child_bitmap);
1780 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1783 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1784 struct mmu_page_path *parents,
1785 struct kvm_mmu_pages *pvec)
1787 parents->parent[parent->role.level-1] = NULL;
1791 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1792 struct kvm_mmu_page *parent)
1795 struct kvm_mmu_page *sp;
1796 struct mmu_page_path parents;
1797 struct kvm_mmu_pages pages;
1798 LIST_HEAD(invalid_list);
1800 kvm_mmu_pages_init(parent, &parents, &pages);
1801 while (mmu_unsync_walk(parent, &pages)) {
1802 bool protected = false;
1804 for_each_sp(pages, sp, parents, i)
1805 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1808 kvm_flush_remote_tlbs(vcpu->kvm);
1810 for_each_sp(pages, sp, parents, i) {
1811 kvm_sync_page(vcpu, sp, &invalid_list);
1812 mmu_pages_clear_parents(&parents);
1814 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1815 cond_resched_lock(&vcpu->kvm->mmu_lock);
1816 kvm_mmu_pages_init(parent, &parents, &pages);
1820 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1824 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1828 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1830 sp->write_flooding_count = 0;
1833 static void clear_sp_write_flooding_count(u64 *spte)
1835 struct kvm_mmu_page *sp = page_header(__pa(spte));
1837 __clear_sp_write_flooding_count(sp);
1840 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1848 union kvm_mmu_page_role role;
1850 struct kvm_mmu_page *sp;
1851 struct hlist_node *node;
1852 bool need_sync = false;
1854 role = vcpu->arch.mmu.base_role;
1856 role.direct = direct;
1859 role.access = access;
1860 if (!vcpu->arch.mmu.direct_map
1861 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1862 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1863 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1864 role.quadrant = quadrant;
1866 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1867 if (!need_sync && sp->unsync)
1870 if (sp->role.word != role.word)
1873 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1876 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1877 if (sp->unsync_children) {
1878 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1879 kvm_mmu_mark_parents_unsync(sp);
1880 } else if (sp->unsync)
1881 kvm_mmu_mark_parents_unsync(sp);
1883 __clear_sp_write_flooding_count(sp);
1884 trace_kvm_mmu_get_page(sp, false);
1887 ++vcpu->kvm->stat.mmu_cache_miss;
1888 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1893 hlist_add_head(&sp->hash_link,
1894 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1896 if (rmap_write_protect(vcpu->kvm, gfn))
1897 kvm_flush_remote_tlbs(vcpu->kvm);
1898 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1899 kvm_sync_pages(vcpu, gfn);
1901 account_shadowed(vcpu->kvm, gfn);
1903 init_shadow_page_table(sp);
1904 trace_kvm_mmu_get_page(sp, true);
1908 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1909 struct kvm_vcpu *vcpu, u64 addr)
1911 iterator->addr = addr;
1912 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1913 iterator->level = vcpu->arch.mmu.shadow_root_level;
1915 if (iterator->level == PT64_ROOT_LEVEL &&
1916 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1917 !vcpu->arch.mmu.direct_map)
1920 if (iterator->level == PT32E_ROOT_LEVEL) {
1921 iterator->shadow_addr
1922 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1923 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1925 if (!iterator->shadow_addr)
1926 iterator->level = 0;
1930 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1932 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1935 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1936 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1940 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1943 if (is_last_spte(spte, iterator->level)) {
1944 iterator->level = 0;
1948 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1952 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1954 return __shadow_walk_next(iterator, *iterator->sptep);
1957 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1961 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
1962 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
1964 mmu_spte_set(sptep, spte);
1967 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1968 unsigned direct_access)
1970 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1971 struct kvm_mmu_page *child;
1974 * For the direct sp, if the guest pte's dirty bit
1975 * changed form clean to dirty, it will corrupt the
1976 * sp's access: allow writable in the read-only sp,
1977 * so we should update the spte at this point to get
1978 * a new sp with the correct access.
1980 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1981 if (child->role.access == direct_access)
1984 drop_parent_pte(child, sptep);
1985 kvm_flush_remote_tlbs(vcpu->kvm);
1989 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1993 struct kvm_mmu_page *child;
1996 if (is_shadow_present_pte(pte)) {
1997 if (is_last_spte(pte, sp->role.level)) {
1998 drop_spte(kvm, spte);
1999 if (is_large_pte(pte))
2002 child = page_header(pte & PT64_BASE_ADDR_MASK);
2003 drop_parent_pte(child, spte);
2008 if (is_mmio_spte(pte))
2009 mmu_spte_clear_no_track(spte);
2014 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2015 struct kvm_mmu_page *sp)
2019 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2020 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2023 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2025 mmu_page_remove_parent_pte(sp, parent_pte);
2028 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2031 struct rmap_iterator iter;
2033 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2034 drop_parent_pte(sp, sptep);
2037 static int mmu_zap_unsync_children(struct kvm *kvm,
2038 struct kvm_mmu_page *parent,
2039 struct list_head *invalid_list)
2042 struct mmu_page_path parents;
2043 struct kvm_mmu_pages pages;
2045 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2048 kvm_mmu_pages_init(parent, &parents, &pages);
2049 while (mmu_unsync_walk(parent, &pages)) {
2050 struct kvm_mmu_page *sp;
2052 for_each_sp(pages, sp, parents, i) {
2053 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2054 mmu_pages_clear_parents(&parents);
2057 kvm_mmu_pages_init(parent, &parents, &pages);
2063 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2064 struct list_head *invalid_list)
2068 trace_kvm_mmu_prepare_zap_page(sp);
2069 ++kvm->stat.mmu_shadow_zapped;
2070 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2071 kvm_mmu_page_unlink_children(kvm, sp);
2072 kvm_mmu_unlink_parents(kvm, sp);
2073 if (!sp->role.invalid && !sp->role.direct)
2074 unaccount_shadowed(kvm, sp->gfn);
2076 kvm_unlink_unsync_page(kvm, sp);
2077 if (!sp->root_count) {
2080 list_move(&sp->link, invalid_list);
2081 kvm_mod_used_mmu_pages(kvm, -1);
2083 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2084 kvm_reload_remote_mmus(kvm);
2087 sp->role.invalid = 1;
2091 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2092 struct list_head *invalid_list)
2094 struct kvm_mmu_page *sp;
2096 if (list_empty(invalid_list))
2100 * wmb: make sure everyone sees our modifications to the page tables
2101 * rmb: make sure we see changes to vcpu->mode
2106 * Wait for all vcpus to exit guest mode and/or lockless shadow
2109 kvm_flush_remote_tlbs(kvm);
2112 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2113 WARN_ON(!sp->role.invalid || sp->root_count);
2114 kvm_mmu_free_page(sp);
2115 } while (!list_empty(invalid_list));
2119 * Changing the number of mmu pages allocated to the vm
2120 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2122 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2124 LIST_HEAD(invalid_list);
2126 * If we set the number of mmu pages to be smaller be than the
2127 * number of actived pages , we must to free some mmu pages before we
2131 spin_lock(&kvm->mmu_lock);
2133 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2134 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2135 !list_empty(&kvm->arch.active_mmu_pages)) {
2136 struct kvm_mmu_page *page;
2138 page = container_of(kvm->arch.active_mmu_pages.prev,
2139 struct kvm_mmu_page, link);
2140 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2142 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2143 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2146 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2148 spin_unlock(&kvm->mmu_lock);
2151 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2153 struct kvm_mmu_page *sp;
2154 struct hlist_node *node;
2155 LIST_HEAD(invalid_list);
2158 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2160 spin_lock(&kvm->mmu_lock);
2161 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2162 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2165 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2167 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2168 spin_unlock(&kvm->mmu_lock);
2172 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2175 * The function is based on mtrr_type_lookup() in
2176 * arch/x86/kernel/cpu/mtrr/generic.c
2178 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2183 u8 prev_match, curr_match;
2184 int num_var_ranges = KVM_NR_VAR_MTRR;
2186 if (!mtrr_state->enabled)
2189 /* Make end inclusive end, instead of exclusive */
2192 /* Look in fixed ranges. Just return the type as per start */
2193 if (mtrr_state->have_fixed && (start < 0x100000)) {
2196 if (start < 0x80000) {
2198 idx += (start >> 16);
2199 return mtrr_state->fixed_ranges[idx];
2200 } else if (start < 0xC0000) {
2202 idx += ((start - 0x80000) >> 14);
2203 return mtrr_state->fixed_ranges[idx];
2204 } else if (start < 0x1000000) {
2206 idx += ((start - 0xC0000) >> 12);
2207 return mtrr_state->fixed_ranges[idx];
2212 * Look in variable ranges
2213 * Look of multiple ranges matching this address and pick type
2214 * as per MTRR precedence
2216 if (!(mtrr_state->enabled & 2))
2217 return mtrr_state->def_type;
2220 for (i = 0; i < num_var_ranges; ++i) {
2221 unsigned short start_state, end_state;
2223 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2226 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2227 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2228 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2229 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2231 start_state = ((start & mask) == (base & mask));
2232 end_state = ((end & mask) == (base & mask));
2233 if (start_state != end_state)
2236 if ((start & mask) != (base & mask))
2239 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2240 if (prev_match == 0xFF) {
2241 prev_match = curr_match;
2245 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2246 curr_match == MTRR_TYPE_UNCACHABLE)
2247 return MTRR_TYPE_UNCACHABLE;
2249 if ((prev_match == MTRR_TYPE_WRBACK &&
2250 curr_match == MTRR_TYPE_WRTHROUGH) ||
2251 (prev_match == MTRR_TYPE_WRTHROUGH &&
2252 curr_match == MTRR_TYPE_WRBACK)) {
2253 prev_match = MTRR_TYPE_WRTHROUGH;
2254 curr_match = MTRR_TYPE_WRTHROUGH;
2257 if (prev_match != curr_match)
2258 return MTRR_TYPE_UNCACHABLE;
2261 if (prev_match != 0xFF)
2264 return mtrr_state->def_type;
2267 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2271 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2272 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2273 if (mtrr == 0xfe || mtrr == 0xff)
2274 mtrr = MTRR_TYPE_WRBACK;
2277 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2279 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2281 trace_kvm_mmu_unsync_page(sp);
2282 ++vcpu->kvm->stat.mmu_unsync;
2285 kvm_mmu_mark_parents_unsync(sp);
2288 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2290 struct kvm_mmu_page *s;
2291 struct hlist_node *node;
2293 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2296 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2297 __kvm_unsync_page(vcpu, s);
2301 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2304 struct kvm_mmu_page *s;
2305 struct hlist_node *node;
2306 bool need_unsync = false;
2308 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2312 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2319 kvm_unsync_pages(vcpu, gfn);
2323 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2324 unsigned pte_access, int level,
2325 gfn_t gfn, pfn_t pfn, bool speculative,
2326 bool can_unsync, bool host_writable)
2331 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2334 spte = PT_PRESENT_MASK;
2336 spte |= shadow_accessed_mask;
2338 if (pte_access & ACC_EXEC_MASK)
2339 spte |= shadow_x_mask;
2341 spte |= shadow_nx_mask;
2343 if (pte_access & ACC_USER_MASK)
2344 spte |= shadow_user_mask;
2346 if (level > PT_PAGE_TABLE_LEVEL)
2347 spte |= PT_PAGE_SIZE_MASK;
2349 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2350 kvm_is_mmio_pfn(pfn));
2353 spte |= SPTE_HOST_WRITEABLE;
2355 pte_access &= ~ACC_WRITE_MASK;
2357 spte |= (u64)pfn << PAGE_SHIFT;
2359 if (pte_access & ACC_WRITE_MASK) {
2362 * Other vcpu creates new sp in the window between
2363 * mapping_level() and acquiring mmu-lock. We can
2364 * allow guest to retry the access, the mapping can
2365 * be fixed if guest refault.
2367 if (level > PT_PAGE_TABLE_LEVEL &&
2368 has_wrprotected_page(vcpu->kvm, gfn, level))
2371 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2374 * Optimization: for pte sync, if spte was writable the hash
2375 * lookup is unnecessary (and expensive). Write protection
2376 * is responsibility of mmu_get_page / kvm_sync_page.
2377 * Same reasoning can be applied to dirty page accounting.
2379 if (!can_unsync && is_writable_pte(*sptep))
2382 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2383 pgprintk("%s: found shadow page for %llx, marking ro\n",
2386 pte_access &= ~ACC_WRITE_MASK;
2387 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2391 if (pte_access & ACC_WRITE_MASK)
2392 mark_page_dirty(vcpu->kvm, gfn);
2395 if (mmu_spte_update(sptep, spte))
2396 kvm_flush_remote_tlbs(vcpu->kvm);
2401 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2402 unsigned pte_access, int write_fault, int *emulate,
2403 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2406 int was_rmapped = 0;
2409 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2410 *sptep, write_fault, gfn);
2412 if (is_rmap_spte(*sptep)) {
2414 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2415 * the parent of the now unreachable PTE.
2417 if (level > PT_PAGE_TABLE_LEVEL &&
2418 !is_large_pte(*sptep)) {
2419 struct kvm_mmu_page *child;
2422 child = page_header(pte & PT64_BASE_ADDR_MASK);
2423 drop_parent_pte(child, sptep);
2424 kvm_flush_remote_tlbs(vcpu->kvm);
2425 } else if (pfn != spte_to_pfn(*sptep)) {
2426 pgprintk("hfn old %llx new %llx\n",
2427 spte_to_pfn(*sptep), pfn);
2428 drop_spte(vcpu->kvm, sptep);
2429 kvm_flush_remote_tlbs(vcpu->kvm);
2434 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2435 true, host_writable)) {
2438 kvm_mmu_flush_tlb(vcpu);
2441 if (unlikely(is_mmio_spte(*sptep) && emulate))
2444 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2445 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2446 is_large_pte(*sptep)? "2MB" : "4kB",
2447 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2449 if (!was_rmapped && is_large_pte(*sptep))
2450 ++vcpu->kvm->stat.lpages;
2452 if (is_shadow_present_pte(*sptep)) {
2454 rmap_count = rmap_add(vcpu, sptep, gfn);
2455 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2456 rmap_recycle(vcpu, sptep, gfn);
2460 kvm_release_pfn_clean(pfn);
2463 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2465 mmu_free_roots(vcpu);
2468 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2472 bit7 = (gpte >> 7) & 1;
2473 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2476 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2479 struct kvm_memory_slot *slot;
2481 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2483 return KVM_PFN_ERR_FAULT;
2485 return gfn_to_pfn_memslot_atomic(slot, gfn);
2488 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2489 struct kvm_mmu_page *sp, u64 *spte,
2492 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2495 if (!is_present_gpte(gpte))
2498 if (!(gpte & PT_ACCESSED_MASK))
2504 drop_spte(vcpu->kvm, spte);
2508 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2509 struct kvm_mmu_page *sp,
2510 u64 *start, u64 *end)
2512 struct page *pages[PTE_PREFETCH_NUM];
2513 unsigned access = sp->role.access;
2517 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2518 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2521 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2525 for (i = 0; i < ret; i++, gfn++, start++)
2526 mmu_set_spte(vcpu, start, access, 0, NULL,
2527 sp->role.level, gfn, page_to_pfn(pages[i]),
2533 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2534 struct kvm_mmu_page *sp, u64 *sptep)
2536 u64 *spte, *start = NULL;
2539 WARN_ON(!sp->role.direct);
2541 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2544 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2545 if (is_shadow_present_pte(*spte) || spte == sptep) {
2548 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2556 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2558 struct kvm_mmu_page *sp;
2561 * Since it's no accessed bit on EPT, it's no way to
2562 * distinguish between actually accessed translations
2563 * and prefetched, so disable pte prefetch if EPT is
2566 if (!shadow_accessed_mask)
2569 sp = page_header(__pa(sptep));
2570 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2573 __direct_pte_prefetch(vcpu, sp, sptep);
2576 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2577 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2580 struct kvm_shadow_walk_iterator iterator;
2581 struct kvm_mmu_page *sp;
2585 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2586 if (iterator.level == level) {
2587 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2588 write, &emulate, level, gfn, pfn,
2589 prefault, map_writable);
2590 direct_pte_prefetch(vcpu, iterator.sptep);
2591 ++vcpu->stat.pf_fixed;
2595 if (!is_shadow_present_pte(*iterator.sptep)) {
2596 u64 base_addr = iterator.addr;
2598 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2599 pseudo_gfn = base_addr >> PAGE_SHIFT;
2600 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2602 1, ACC_ALL, iterator.sptep);
2604 link_shadow_page(iterator.sptep, sp);
2610 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2614 info.si_signo = SIGBUS;
2616 info.si_code = BUS_MCEERR_AR;
2617 info.si_addr = (void __user *)address;
2618 info.si_addr_lsb = PAGE_SHIFT;
2620 send_sig_info(SIGBUS, &info, tsk);
2623 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2626 * Do not cache the mmio info caused by writing the readonly gfn
2627 * into the spte otherwise read access on readonly gfn also can
2628 * caused mmio page fault and treat it as mmio access.
2629 * Return 1 to tell kvm to emulate it.
2631 if (pfn == KVM_PFN_ERR_RO_FAULT)
2634 if (pfn == KVM_PFN_ERR_HWPOISON) {
2635 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2642 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2643 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2647 int level = *levelp;
2650 * Check if it's a transparent hugepage. If this would be an
2651 * hugetlbfs page, level wouldn't be set to
2652 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2655 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2656 level == PT_PAGE_TABLE_LEVEL &&
2657 PageTransCompound(pfn_to_page(pfn)) &&
2658 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2661 * mmu_notifier_retry was successful and we hold the
2662 * mmu_lock here, so the pmd can't become splitting
2663 * from under us, and in turn
2664 * __split_huge_page_refcount() can't run from under
2665 * us and we can safely transfer the refcount from
2666 * PG_tail to PG_head as we switch the pfn to tail to
2669 *levelp = level = PT_DIRECTORY_LEVEL;
2670 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2671 VM_BUG_ON((gfn & mask) != (pfn & mask));
2675 kvm_release_pfn_clean(pfn);
2683 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2684 pfn_t pfn, unsigned access, int *ret_val)
2688 /* The pfn is invalid, report the error! */
2689 if (unlikely(is_error_pfn(pfn))) {
2690 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2694 if (unlikely(is_noslot_pfn(pfn)))
2695 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2702 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2705 * #PF can be fast only if the shadow page table is present and it
2706 * is caused by write-protect, that means we just need change the
2707 * W bit of the spte which can be done out of mmu-lock.
2709 if (!(error_code & PFERR_PRESENT_MASK) ||
2710 !(error_code & PFERR_WRITE_MASK))
2717 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2719 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2722 WARN_ON(!sp->role.direct);
2725 * The gfn of direct spte is stable since it is calculated
2728 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2730 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2731 mark_page_dirty(vcpu->kvm, gfn);
2738 * - true: let the vcpu to access on the same address again.
2739 * - false: let the real page fault path to fix it.
2741 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2744 struct kvm_shadow_walk_iterator iterator;
2748 if (!page_fault_can_be_fast(vcpu, error_code))
2751 walk_shadow_page_lockless_begin(vcpu);
2752 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2753 if (!is_shadow_present_pte(spte) || iterator.level < level)
2757 * If the mapping has been changed, let the vcpu fault on the
2758 * same address again.
2760 if (!is_rmap_spte(spte)) {
2765 if (!is_last_spte(spte, level))
2769 * Check if it is a spurious fault caused by TLB lazily flushed.
2771 * Need not check the access of upper level table entries since
2772 * they are always ACC_ALL.
2774 if (is_writable_pte(spte)) {
2780 * Currently, to simplify the code, only the spte write-protected
2781 * by dirty-log can be fast fixed.
2783 if (!spte_is_locklessly_modifiable(spte))
2787 * Currently, fast page fault only works for direct mapping since
2788 * the gfn is not stable for indirect shadow page.
2789 * See Documentation/virtual/kvm/locking.txt to get more detail.
2791 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2793 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2795 walk_shadow_page_lockless_end(vcpu);
2800 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2801 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2803 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2804 gfn_t gfn, bool prefault)
2810 unsigned long mmu_seq;
2811 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2813 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2814 if (likely(!force_pt_level)) {
2815 level = mapping_level(vcpu, gfn);
2817 * This path builds a PAE pagetable - so we can map
2818 * 2mb pages at maximum. Therefore check if the level
2819 * is larger than that.
2821 if (level > PT_DIRECTORY_LEVEL)
2822 level = PT_DIRECTORY_LEVEL;
2824 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2826 level = PT_PAGE_TABLE_LEVEL;
2828 if (fast_page_fault(vcpu, v, level, error_code))
2831 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2834 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2837 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2840 spin_lock(&vcpu->kvm->mmu_lock);
2841 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2843 kvm_mmu_free_some_pages(vcpu);
2844 if (likely(!force_pt_level))
2845 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2846 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2848 spin_unlock(&vcpu->kvm->mmu_lock);
2854 spin_unlock(&vcpu->kvm->mmu_lock);
2855 kvm_release_pfn_clean(pfn);
2860 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2863 struct kvm_mmu_page *sp;
2864 LIST_HEAD(invalid_list);
2866 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2868 spin_lock(&vcpu->kvm->mmu_lock);
2869 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2870 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2871 vcpu->arch.mmu.direct_map)) {
2872 hpa_t root = vcpu->arch.mmu.root_hpa;
2874 sp = page_header(root);
2876 if (!sp->root_count && sp->role.invalid) {
2877 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2878 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2880 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2881 spin_unlock(&vcpu->kvm->mmu_lock);
2884 for (i = 0; i < 4; ++i) {
2885 hpa_t root = vcpu->arch.mmu.pae_root[i];
2888 root &= PT64_BASE_ADDR_MASK;
2889 sp = page_header(root);
2891 if (!sp->root_count && sp->role.invalid)
2892 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2895 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2897 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2898 spin_unlock(&vcpu->kvm->mmu_lock);
2899 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2902 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2906 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2907 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2914 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2916 struct kvm_mmu_page *sp;
2919 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2920 spin_lock(&vcpu->kvm->mmu_lock);
2921 kvm_mmu_free_some_pages(vcpu);
2922 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2925 spin_unlock(&vcpu->kvm->mmu_lock);
2926 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2927 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2928 for (i = 0; i < 4; ++i) {
2929 hpa_t root = vcpu->arch.mmu.pae_root[i];
2931 ASSERT(!VALID_PAGE(root));
2932 spin_lock(&vcpu->kvm->mmu_lock);
2933 kvm_mmu_free_some_pages(vcpu);
2934 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2936 PT32_ROOT_LEVEL, 1, ACC_ALL,
2938 root = __pa(sp->spt);
2940 spin_unlock(&vcpu->kvm->mmu_lock);
2941 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2943 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2950 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2952 struct kvm_mmu_page *sp;
2957 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2959 if (mmu_check_root(vcpu, root_gfn))
2963 * Do we shadow a long mode page table? If so we need to
2964 * write-protect the guests page table root.
2966 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2967 hpa_t root = vcpu->arch.mmu.root_hpa;
2969 ASSERT(!VALID_PAGE(root));
2971 spin_lock(&vcpu->kvm->mmu_lock);
2972 kvm_mmu_free_some_pages(vcpu);
2973 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2975 root = __pa(sp->spt);
2977 spin_unlock(&vcpu->kvm->mmu_lock);
2978 vcpu->arch.mmu.root_hpa = root;
2983 * We shadow a 32 bit page table. This may be a legacy 2-level
2984 * or a PAE 3-level page table. In either case we need to be aware that
2985 * the shadow page table may be a PAE or a long mode page table.
2987 pm_mask = PT_PRESENT_MASK;
2988 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2989 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2991 for (i = 0; i < 4; ++i) {
2992 hpa_t root = vcpu->arch.mmu.pae_root[i];
2994 ASSERT(!VALID_PAGE(root));
2995 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2996 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2997 if (!is_present_gpte(pdptr)) {
2998 vcpu->arch.mmu.pae_root[i] = 0;
3001 root_gfn = pdptr >> PAGE_SHIFT;
3002 if (mmu_check_root(vcpu, root_gfn))
3005 spin_lock(&vcpu->kvm->mmu_lock);
3006 kvm_mmu_free_some_pages(vcpu);
3007 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3010 root = __pa(sp->spt);
3012 spin_unlock(&vcpu->kvm->mmu_lock);
3014 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3016 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3019 * If we shadow a 32 bit page table with a long mode page
3020 * table we enter this path.
3022 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3023 if (vcpu->arch.mmu.lm_root == NULL) {
3025 * The additional page necessary for this is only
3026 * allocated on demand.
3031 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3032 if (lm_root == NULL)
3035 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3037 vcpu->arch.mmu.lm_root = lm_root;
3040 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3046 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3048 if (vcpu->arch.mmu.direct_map)
3049 return mmu_alloc_direct_roots(vcpu);
3051 return mmu_alloc_shadow_roots(vcpu);
3054 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3057 struct kvm_mmu_page *sp;
3059 if (vcpu->arch.mmu.direct_map)
3062 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3065 vcpu_clear_mmio_info(vcpu, ~0ul);
3066 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3067 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3068 hpa_t root = vcpu->arch.mmu.root_hpa;
3069 sp = page_header(root);
3070 mmu_sync_children(vcpu, sp);
3071 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3074 for (i = 0; i < 4; ++i) {
3075 hpa_t root = vcpu->arch.mmu.pae_root[i];
3077 if (root && VALID_PAGE(root)) {
3078 root &= PT64_BASE_ADDR_MASK;
3079 sp = page_header(root);
3080 mmu_sync_children(vcpu, sp);
3083 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3086 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3088 spin_lock(&vcpu->kvm->mmu_lock);
3089 mmu_sync_roots(vcpu);
3090 spin_unlock(&vcpu->kvm->mmu_lock);
3093 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3094 u32 access, struct x86_exception *exception)
3097 exception->error_code = 0;
3101 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3103 struct x86_exception *exception)
3106 exception->error_code = 0;
3107 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3110 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3113 return vcpu_match_mmio_gpa(vcpu, addr);
3115 return vcpu_match_mmio_gva(vcpu, addr);
3120 * On direct hosts, the last spte is only allows two states
3121 * for mmio page fault:
3122 * - It is the mmio spte
3123 * - It is zapped or it is being zapped.
3125 * This function completely checks the spte when the last spte
3126 * is not the mmio spte.
3128 static bool check_direct_spte_mmio_pf(u64 spte)
3130 return __check_direct_spte_mmio_pf(spte);
3133 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3135 struct kvm_shadow_walk_iterator iterator;
3138 walk_shadow_page_lockless_begin(vcpu);
3139 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3140 if (!is_shadow_present_pte(spte))
3142 walk_shadow_page_lockless_end(vcpu);
3148 * If it is a real mmio page fault, return 1 and emulat the instruction
3149 * directly, return 0 to let CPU fault again on the address, -1 is
3150 * returned if bug is detected.
3152 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3156 if (quickly_check_mmio_pf(vcpu, addr, direct))
3159 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3161 if (is_mmio_spte(spte)) {
3162 gfn_t gfn = get_mmio_spte_gfn(spte);
3163 unsigned access = get_mmio_spte_access(spte);
3168 trace_handle_mmio_page_fault(addr, gfn, access);
3169 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3174 * It's ok if the gva is remapped by other cpus on shadow guest,
3175 * it's a BUG if the gfn is not a mmio page.
3177 if (direct && !check_direct_spte_mmio_pf(spte))
3181 * If the page table is zapped by other cpus, let CPU fault again on
3186 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3188 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3189 u32 error_code, bool direct)
3193 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3198 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3199 u32 error_code, bool prefault)
3204 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3206 if (unlikely(error_code & PFERR_RSVD_MASK))
3207 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3209 r = mmu_topup_memory_caches(vcpu);
3214 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3216 gfn = gva >> PAGE_SHIFT;
3218 return nonpaging_map(vcpu, gva & PAGE_MASK,
3219 error_code, gfn, prefault);
3222 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3224 struct kvm_arch_async_pf arch;
3226 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3228 arch.direct_map = vcpu->arch.mmu.direct_map;
3229 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3231 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3234 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3236 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3237 kvm_event_needs_reinjection(vcpu)))
3240 return kvm_x86_ops->interrupt_allowed(vcpu);
3243 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3244 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3248 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3251 return false; /* *pfn has correct page already */
3253 if (!prefault && can_do_async_pf(vcpu)) {
3254 trace_kvm_try_async_get_page(gva, gfn);
3255 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3256 trace_kvm_async_pf_doublefault(gva, gfn);
3257 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3259 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3263 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3268 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3275 gfn_t gfn = gpa >> PAGE_SHIFT;
3276 unsigned long mmu_seq;
3277 int write = error_code & PFERR_WRITE_MASK;
3281 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3283 if (unlikely(error_code & PFERR_RSVD_MASK))
3284 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3286 r = mmu_topup_memory_caches(vcpu);
3290 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3291 if (likely(!force_pt_level)) {
3292 level = mapping_level(vcpu, gfn);
3293 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3295 level = PT_PAGE_TABLE_LEVEL;
3297 if (fast_page_fault(vcpu, gpa, level, error_code))
3300 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3303 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3306 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3309 spin_lock(&vcpu->kvm->mmu_lock);
3310 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3312 kvm_mmu_free_some_pages(vcpu);
3313 if (likely(!force_pt_level))
3314 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3315 r = __direct_map(vcpu, gpa, write, map_writable,
3316 level, gfn, pfn, prefault);
3317 spin_unlock(&vcpu->kvm->mmu_lock);
3322 spin_unlock(&vcpu->kvm->mmu_lock);
3323 kvm_release_pfn_clean(pfn);
3327 static void nonpaging_free(struct kvm_vcpu *vcpu)
3329 mmu_free_roots(vcpu);
3332 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3333 struct kvm_mmu *context)
3335 context->new_cr3 = nonpaging_new_cr3;
3336 context->page_fault = nonpaging_page_fault;
3337 context->gva_to_gpa = nonpaging_gva_to_gpa;
3338 context->free = nonpaging_free;
3339 context->sync_page = nonpaging_sync_page;
3340 context->invlpg = nonpaging_invlpg;
3341 context->update_pte = nonpaging_update_pte;
3342 context->root_level = 0;
3343 context->shadow_root_level = PT32E_ROOT_LEVEL;
3344 context->root_hpa = INVALID_PAGE;
3345 context->direct_map = true;
3346 context->nx = false;
3350 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3352 ++vcpu->stat.tlb_flush;
3353 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3356 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3358 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3359 mmu_free_roots(vcpu);
3362 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3364 return kvm_read_cr3(vcpu);
3367 static void inject_page_fault(struct kvm_vcpu *vcpu,
3368 struct x86_exception *fault)
3370 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3373 static void paging_free(struct kvm_vcpu *vcpu)
3375 nonpaging_free(vcpu);
3378 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3382 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3384 mask = (unsigned)~ACC_WRITE_MASK;
3385 /* Allow write access to dirty gptes */
3386 mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3390 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3393 if (unlikely(is_mmio_spte(*sptep))) {
3394 if (gfn != get_mmio_spte_gfn(*sptep)) {
3395 mmu_spte_clear_no_track(sptep);
3400 mark_mmio_spte(sptep, gfn, access);
3407 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3411 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3412 access &= ~(gpte >> PT64_NX_SHIFT);
3417 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3422 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3423 return mmu->last_pte_bitmap & (1 << index);
3427 #include "paging_tmpl.h"
3431 #include "paging_tmpl.h"
3434 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3435 struct kvm_mmu *context)
3437 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3438 u64 exb_bit_rsvd = 0;
3441 exb_bit_rsvd = rsvd_bits(63, 63);
3442 switch (context->root_level) {
3443 case PT32_ROOT_LEVEL:
3444 /* no rsvd bits for 2 level 4K page table entries */
3445 context->rsvd_bits_mask[0][1] = 0;
3446 context->rsvd_bits_mask[0][0] = 0;
3447 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3449 if (!is_pse(vcpu)) {
3450 context->rsvd_bits_mask[1][1] = 0;
3454 if (is_cpuid_PSE36())
3455 /* 36bits PSE 4MB page */
3456 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3458 /* 32 bits PSE 4MB page */
3459 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3461 case PT32E_ROOT_LEVEL:
3462 context->rsvd_bits_mask[0][2] =
3463 rsvd_bits(maxphyaddr, 63) |
3464 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3465 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3466 rsvd_bits(maxphyaddr, 62); /* PDE */
3467 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3468 rsvd_bits(maxphyaddr, 62); /* PTE */
3469 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3470 rsvd_bits(maxphyaddr, 62) |
3471 rsvd_bits(13, 20); /* large page */
3472 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3474 case PT64_ROOT_LEVEL:
3475 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3476 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3477 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3478 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3479 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3480 rsvd_bits(maxphyaddr, 51);
3481 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3482 rsvd_bits(maxphyaddr, 51);
3483 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3484 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3485 rsvd_bits(maxphyaddr, 51) |
3487 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3488 rsvd_bits(maxphyaddr, 51) |
3489 rsvd_bits(13, 20); /* large page */
3490 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3495 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3497 unsigned bit, byte, pfec;
3499 bool fault, x, w, u, wf, uf, ff, smep;
3501 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3502 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3505 wf = pfec & PFERR_WRITE_MASK;
3506 uf = pfec & PFERR_USER_MASK;
3507 ff = pfec & PFERR_FETCH_MASK;
3508 for (bit = 0; bit < 8; ++bit) {
3509 x = bit & ACC_EXEC_MASK;
3510 w = bit & ACC_WRITE_MASK;
3511 u = bit & ACC_USER_MASK;
3513 /* Not really needed: !nx will cause pte.nx to fault */
3515 /* Allow supervisor writes if !cr0.wp */
3516 w |= !is_write_protection(vcpu) && !uf;
3517 /* Disallow supervisor fetches of user code if cr4.smep */
3518 x &= !(smep && u && !uf);
3520 fault = (ff && !x) || (uf && !u) || (wf && !w);
3521 map |= fault << bit;
3523 mmu->permissions[byte] = map;
3527 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3530 unsigned level, root_level = mmu->root_level;
3531 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3533 if (root_level == PT32E_ROOT_LEVEL)
3535 /* PT_PAGE_TABLE_LEVEL always terminates */
3536 map = 1 | (1 << ps_set_index);
3537 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3538 if (level <= PT_PDPE_LEVEL
3539 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3540 map |= 1 << (ps_set_index | (level - 1));
3542 mmu->last_pte_bitmap = map;
3545 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3546 struct kvm_mmu *context,
3549 context->nx = is_nx(vcpu);
3550 context->root_level = level;
3552 reset_rsvds_bits_mask(vcpu, context);
3553 update_permission_bitmask(vcpu, context);
3554 update_last_pte_bitmap(vcpu, context);
3556 ASSERT(is_pae(vcpu));
3557 context->new_cr3 = paging_new_cr3;
3558 context->page_fault = paging64_page_fault;
3559 context->gva_to_gpa = paging64_gva_to_gpa;
3560 context->sync_page = paging64_sync_page;
3561 context->invlpg = paging64_invlpg;
3562 context->update_pte = paging64_update_pte;
3563 context->free = paging_free;
3564 context->shadow_root_level = level;
3565 context->root_hpa = INVALID_PAGE;
3566 context->direct_map = false;
3570 static int paging64_init_context(struct kvm_vcpu *vcpu,
3571 struct kvm_mmu *context)
3573 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3576 static int paging32_init_context(struct kvm_vcpu *vcpu,
3577 struct kvm_mmu *context)
3579 context->nx = false;
3580 context->root_level = PT32_ROOT_LEVEL;
3582 reset_rsvds_bits_mask(vcpu, context);
3583 update_permission_bitmask(vcpu, context);
3584 update_last_pte_bitmap(vcpu, context);
3586 context->new_cr3 = paging_new_cr3;
3587 context->page_fault = paging32_page_fault;
3588 context->gva_to_gpa = paging32_gva_to_gpa;
3589 context->free = paging_free;
3590 context->sync_page = paging32_sync_page;
3591 context->invlpg = paging32_invlpg;
3592 context->update_pte = paging32_update_pte;
3593 context->shadow_root_level = PT32E_ROOT_LEVEL;
3594 context->root_hpa = INVALID_PAGE;
3595 context->direct_map = false;
3599 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3600 struct kvm_mmu *context)
3602 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3605 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3607 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3609 context->base_role.word = 0;
3610 context->new_cr3 = nonpaging_new_cr3;
3611 context->page_fault = tdp_page_fault;
3612 context->free = nonpaging_free;
3613 context->sync_page = nonpaging_sync_page;
3614 context->invlpg = nonpaging_invlpg;
3615 context->update_pte = nonpaging_update_pte;
3616 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3617 context->root_hpa = INVALID_PAGE;
3618 context->direct_map = true;
3619 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3620 context->get_cr3 = get_cr3;
3621 context->get_pdptr = kvm_pdptr_read;
3622 context->inject_page_fault = kvm_inject_page_fault;
3624 if (!is_paging(vcpu)) {
3625 context->nx = false;
3626 context->gva_to_gpa = nonpaging_gva_to_gpa;
3627 context->root_level = 0;
3628 } else if (is_long_mode(vcpu)) {
3629 context->nx = is_nx(vcpu);
3630 context->root_level = PT64_ROOT_LEVEL;
3631 reset_rsvds_bits_mask(vcpu, context);
3632 context->gva_to_gpa = paging64_gva_to_gpa;
3633 } else if (is_pae(vcpu)) {
3634 context->nx = is_nx(vcpu);
3635 context->root_level = PT32E_ROOT_LEVEL;
3636 reset_rsvds_bits_mask(vcpu, context);
3637 context->gva_to_gpa = paging64_gva_to_gpa;
3639 context->nx = false;
3640 context->root_level = PT32_ROOT_LEVEL;
3641 reset_rsvds_bits_mask(vcpu, context);
3642 context->gva_to_gpa = paging32_gva_to_gpa;
3645 update_permission_bitmask(vcpu, context);
3646 update_last_pte_bitmap(vcpu, context);
3651 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3654 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3656 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3658 if (!is_paging(vcpu))
3659 r = nonpaging_init_context(vcpu, context);
3660 else if (is_long_mode(vcpu))
3661 r = paging64_init_context(vcpu, context);
3662 else if (is_pae(vcpu))
3663 r = paging32E_init_context(vcpu, context);
3665 r = paging32_init_context(vcpu, context);
3667 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3668 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3669 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3670 vcpu->arch.mmu.base_role.smep_andnot_wp
3671 = smep && !is_write_protection(vcpu);
3675 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3677 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3679 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3681 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3682 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3683 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3684 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3689 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3691 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3693 g_context->get_cr3 = get_cr3;
3694 g_context->get_pdptr = kvm_pdptr_read;
3695 g_context->inject_page_fault = kvm_inject_page_fault;
3698 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3699 * translation of l2_gpa to l1_gpa addresses is done using the
3700 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3701 * functions between mmu and nested_mmu are swapped.
3703 if (!is_paging(vcpu)) {
3704 g_context->nx = false;
3705 g_context->root_level = 0;
3706 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3707 } else if (is_long_mode(vcpu)) {
3708 g_context->nx = is_nx(vcpu);
3709 g_context->root_level = PT64_ROOT_LEVEL;
3710 reset_rsvds_bits_mask(vcpu, g_context);
3711 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3712 } else if (is_pae(vcpu)) {
3713 g_context->nx = is_nx(vcpu);
3714 g_context->root_level = PT32E_ROOT_LEVEL;
3715 reset_rsvds_bits_mask(vcpu, g_context);
3716 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3718 g_context->nx = false;
3719 g_context->root_level = PT32_ROOT_LEVEL;
3720 reset_rsvds_bits_mask(vcpu, g_context);
3721 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3724 update_permission_bitmask(vcpu, g_context);
3725 update_last_pte_bitmap(vcpu, g_context);
3730 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3732 if (mmu_is_nested(vcpu))
3733 return init_kvm_nested_mmu(vcpu);
3734 else if (tdp_enabled)
3735 return init_kvm_tdp_mmu(vcpu);
3737 return init_kvm_softmmu(vcpu);
3740 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3743 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3744 /* mmu.free() should set root_hpa = INVALID_PAGE */
3745 vcpu->arch.mmu.free(vcpu);
3748 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3750 destroy_kvm_mmu(vcpu);
3751 return init_kvm_mmu(vcpu);
3753 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3755 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3759 r = mmu_topup_memory_caches(vcpu);
3762 r = mmu_alloc_roots(vcpu);
3763 spin_lock(&vcpu->kvm->mmu_lock);
3764 mmu_sync_roots(vcpu);
3765 spin_unlock(&vcpu->kvm->mmu_lock);
3768 /* set_cr3() should ensure TLB has been flushed */
3769 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3773 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3775 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3777 mmu_free_roots(vcpu);
3779 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3781 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3782 struct kvm_mmu_page *sp, u64 *spte,
3785 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3786 ++vcpu->kvm->stat.mmu_pde_zapped;
3790 ++vcpu->kvm->stat.mmu_pte_updated;
3791 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3794 static bool need_remote_flush(u64 old, u64 new)
3796 if (!is_shadow_present_pte(old))
3798 if (!is_shadow_present_pte(new))
3800 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3802 old ^= PT64_NX_MASK;
3803 new ^= PT64_NX_MASK;
3804 return (old & ~new & PT64_PERM_MASK) != 0;
3807 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3808 bool remote_flush, bool local_flush)
3814 kvm_flush_remote_tlbs(vcpu->kvm);
3815 else if (local_flush)
3816 kvm_mmu_flush_tlb(vcpu);
3819 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3820 const u8 *new, int *bytes)
3826 * Assume that the pte write on a page table of the same type
3827 * as the current vcpu paging mode since we update the sptes only
3828 * when they have the same mode.
3830 if (is_pae(vcpu) && *bytes == 4) {
3831 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3834 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3837 new = (const u8 *)&gentry;
3842 gentry = *(const u32 *)new;
3845 gentry = *(const u64 *)new;
3856 * If we're seeing too many writes to a page, it may no longer be a page table,
3857 * or we may be forking, in which case it is better to unmap the page.
3859 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3862 * Skip write-flooding detected for the sp whose level is 1, because
3863 * it can become unsync, then the guest page is not write-protected.
3865 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3868 return ++sp->write_flooding_count >= 3;
3872 * Misaligned accesses are too much trouble to fix up; also, they usually
3873 * indicate a page is not used as a page table.
3875 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3878 unsigned offset, pte_size, misaligned;
3880 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3881 gpa, bytes, sp->role.word);
3883 offset = offset_in_page(gpa);
3884 pte_size = sp->role.cr4_pae ? 8 : 4;
3887 * Sometimes, the OS only writes the last one bytes to update status
3888 * bits, for example, in linux, andb instruction is used in clear_bit().
3890 if (!(offset & (pte_size - 1)) && bytes == 1)
3893 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3894 misaligned |= bytes < 4;
3899 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3901 unsigned page_offset, quadrant;
3905 page_offset = offset_in_page(gpa);
3906 level = sp->role.level;
3908 if (!sp->role.cr4_pae) {
3909 page_offset <<= 1; /* 32->64 */
3911 * A 32-bit pde maps 4MB while the shadow pdes map
3912 * only 2MB. So we need to double the offset again
3913 * and zap two pdes instead of one.
3915 if (level == PT32_ROOT_LEVEL) {
3916 page_offset &= ~7; /* kill rounding error */
3920 quadrant = page_offset >> PAGE_SHIFT;
3921 page_offset &= ~PAGE_MASK;
3922 if (quadrant != sp->role.quadrant)
3926 spte = &sp->spt[page_offset / sizeof(*spte)];
3930 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3931 const u8 *new, int bytes)
3933 gfn_t gfn = gpa >> PAGE_SHIFT;
3934 union kvm_mmu_page_role mask = { .word = 0 };
3935 struct kvm_mmu_page *sp;
3936 struct hlist_node *node;
3937 LIST_HEAD(invalid_list);
3938 u64 entry, gentry, *spte;
3940 bool remote_flush, local_flush, zap_page;
3943 * If we don't have indirect shadow pages, it means no page is
3944 * write-protected, so we can exit simply.
3946 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3949 zap_page = remote_flush = local_flush = false;
3951 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3953 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3956 * No need to care whether allocation memory is successful
3957 * or not since pte prefetch is skiped if it does not have
3958 * enough objects in the cache.
3960 mmu_topup_memory_caches(vcpu);
3962 spin_lock(&vcpu->kvm->mmu_lock);
3963 ++vcpu->kvm->stat.mmu_pte_write;
3964 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3966 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3967 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3968 if (detect_write_misaligned(sp, gpa, bytes) ||
3969 detect_write_flooding(sp)) {
3970 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3972 ++vcpu->kvm->stat.mmu_flooded;
3976 spte = get_written_sptes(sp, gpa, &npte);
3983 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3985 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3986 & mask.word) && rmap_can_add(vcpu))
3987 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3988 if (need_remote_flush(entry, *spte))
3989 remote_flush = true;
3993 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3994 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3995 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3996 spin_unlock(&vcpu->kvm->mmu_lock);
3999 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4004 if (vcpu->arch.mmu.direct_map)
4007 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4009 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4013 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4015 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
4017 LIST_HEAD(invalid_list);
4019 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
4020 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4021 struct kvm_mmu_page *sp;
4023 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4024 struct kvm_mmu_page, link);
4025 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4026 ++vcpu->kvm->stat.mmu_recycled;
4028 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4031 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4033 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4034 return vcpu_match_mmio_gpa(vcpu, addr);
4036 return vcpu_match_mmio_gva(vcpu, addr);
4039 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4040 void *insn, int insn_len)
4042 int r, emulation_type = EMULTYPE_RETRY;
4043 enum emulation_result er;
4045 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4054 if (is_mmio_page_fault(vcpu, cr2))
4057 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4062 case EMULATE_DO_MMIO:
4063 ++vcpu->stat.mmio_exits;
4073 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4075 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4077 vcpu->arch.mmu.invlpg(vcpu, gva);
4078 kvm_mmu_flush_tlb(vcpu);
4079 ++vcpu->stat.invlpg;
4081 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4083 void kvm_enable_tdp(void)
4087 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4089 void kvm_disable_tdp(void)
4091 tdp_enabled = false;
4093 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4095 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4097 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4098 if (vcpu->arch.mmu.lm_root != NULL)
4099 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4102 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4110 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4111 * Therefore we need to allocate shadow page tables in the first
4112 * 4GB of memory, which happens to fit the DMA32 zone.
4114 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4118 vcpu->arch.mmu.pae_root = page_address(page);
4119 for (i = 0; i < 4; ++i)
4120 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4125 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4129 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4130 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4131 vcpu->arch.mmu.translate_gpa = translate_gpa;
4132 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4134 return alloc_mmu_pages(vcpu);
4137 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4140 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4142 return init_kvm_mmu(vcpu);
4145 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4147 struct kvm_memory_slot *memslot;
4151 memslot = id_to_memslot(kvm->memslots, slot);
4152 last_gfn = memslot->base_gfn + memslot->npages - 1;
4154 spin_lock(&kvm->mmu_lock);
4156 for (i = PT_PAGE_TABLE_LEVEL;
4157 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4158 unsigned long *rmapp;
4159 unsigned long last_index, index;
4161 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4162 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4164 for (index = 0; index <= last_index; ++index, ++rmapp) {
4166 __rmap_write_protect(kvm, rmapp, false);
4168 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4169 kvm_flush_remote_tlbs(kvm);
4170 cond_resched_lock(&kvm->mmu_lock);
4175 kvm_flush_remote_tlbs(kvm);
4176 spin_unlock(&kvm->mmu_lock);
4179 void kvm_mmu_zap_all(struct kvm *kvm)
4181 struct kvm_mmu_page *sp, *node;
4182 LIST_HEAD(invalid_list);
4184 spin_lock(&kvm->mmu_lock);
4186 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4187 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4190 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4191 spin_unlock(&kvm->mmu_lock);
4194 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
4195 struct list_head *invalid_list)
4197 struct kvm_mmu_page *page;
4199 if (list_empty(&kvm->arch.active_mmu_pages))
4202 page = container_of(kvm->arch.active_mmu_pages.prev,
4203 struct kvm_mmu_page, link);
4204 kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
4207 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4210 int nr_to_scan = sc->nr_to_scan;
4212 if (nr_to_scan == 0)
4215 raw_spin_lock(&kvm_lock);
4217 list_for_each_entry(kvm, &vm_list, vm_list) {
4219 LIST_HEAD(invalid_list);
4222 * Never scan more than sc->nr_to_scan VM instances.
4223 * Will not hit this condition practically since we do not try
4224 * to shrink more than one VM and it is very unlikely to see
4225 * !n_used_mmu_pages so many times.
4230 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4231 * here. We may skip a VM instance errorneosly, but we do not
4232 * want to shrink a VM that only started to populate its MMU
4235 if (!kvm->arch.n_used_mmu_pages)
4238 idx = srcu_read_lock(&kvm->srcu);
4239 spin_lock(&kvm->mmu_lock);
4241 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
4242 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4244 spin_unlock(&kvm->mmu_lock);
4245 srcu_read_unlock(&kvm->srcu, idx);
4247 list_move_tail(&kvm->vm_list, &vm_list);
4251 raw_spin_unlock(&kvm_lock);
4254 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4257 static struct shrinker mmu_shrinker = {
4258 .shrink = mmu_shrink,
4259 .seeks = DEFAULT_SEEKS * 10,
4262 static void mmu_destroy_caches(void)
4264 if (pte_list_desc_cache)
4265 kmem_cache_destroy(pte_list_desc_cache);
4266 if (mmu_page_header_cache)
4267 kmem_cache_destroy(mmu_page_header_cache);
4270 int kvm_mmu_module_init(void)
4272 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4273 sizeof(struct pte_list_desc),
4275 if (!pte_list_desc_cache)
4278 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4279 sizeof(struct kvm_mmu_page),
4281 if (!mmu_page_header_cache)
4284 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4287 register_shrinker(&mmu_shrinker);
4292 mmu_destroy_caches();
4297 * Caculate mmu pages needed for kvm.
4299 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4301 unsigned int nr_mmu_pages;
4302 unsigned int nr_pages = 0;
4303 struct kvm_memslots *slots;
4304 struct kvm_memory_slot *memslot;
4306 slots = kvm_memslots(kvm);
4308 kvm_for_each_memslot(memslot, slots)
4309 nr_pages += memslot->npages;
4311 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4312 nr_mmu_pages = max(nr_mmu_pages,
4313 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4315 return nr_mmu_pages;
4318 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4320 struct kvm_shadow_walk_iterator iterator;
4324 walk_shadow_page_lockless_begin(vcpu);
4325 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4326 sptes[iterator.level-1] = spte;
4328 if (!is_shadow_present_pte(spte))
4331 walk_shadow_page_lockless_end(vcpu);
4335 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4337 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4341 destroy_kvm_mmu(vcpu);
4342 free_mmu_pages(vcpu);
4343 mmu_free_memory_caches(vcpu);
4346 void kvm_mmu_module_exit(void)
4348 mmu_destroy_caches();
4349 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4350 unregister_shrinker(&mmu_shrinker);
4351 mmu_audit_disable();