2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
54 #error Invalid PTTYPE value
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61 * The guest_walker structure emulates the behavior of the hardware page
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
68 pt_element_t ptes[PT_MAX_FULL_LEVELS];
69 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
70 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
71 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
75 struct x86_exception fault;
78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
83 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
84 pt_element_t __user *ptep_user, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
92 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
93 /* Check if the user is doing something meaningless. */
94 if (unlikely(npages != 1))
97 table = kmap_atomic(page);
98 ret = CMPXCHG(&table[index], orig_pte, new_pte);
101 kvm_release_page_dirty(page);
103 return (ret != orig_pte);
106 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
108 struct guest_walker *walker,
111 unsigned level, index;
112 pt_element_t pte, orig_pte;
113 pt_element_t __user *ptep_user;
117 for (level = walker->max_level; level >= walker->level; --level) {
118 pte = orig_pte = walker->ptes[level - 1];
119 table_gfn = walker->table_gfn[level - 1];
120 ptep_user = walker->ptep_user[level - 1];
121 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
122 if (!(pte & PT_ACCESSED_MASK)) {
123 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
124 pte |= PT_ACCESSED_MASK;
126 if (level == walker->level && write_fault && !is_dirty_gpte(pte)) {
127 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
128 pte |= PT_DIRTY_MASK;
133 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
137 mark_page_dirty(vcpu->kvm, table_gfn);
138 walker->ptes[level] = pte;
144 * Fetch a guest pte for a guest virtual address
146 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
147 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
148 gva_t addr, u32 access)
152 pt_element_t __user *uninitialized_var(ptep_user);
154 unsigned index, pt_access, pte_access, accessed_dirty;
157 const int write_fault = access & PFERR_WRITE_MASK;
158 const int user_fault = access & PFERR_USER_MASK;
159 const int fetch_fault = access & PFERR_FETCH_MASK;
164 trace_kvm_mmu_pagetable_walk(addr, access);
166 walker->level = mmu->root_level;
167 pte = mmu->get_cr3(vcpu);
170 if (walker->level == PT32E_ROOT_LEVEL) {
171 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
172 trace_kvm_mmu_paging_element(pte, walker->level);
173 if (!is_present_gpte(pte))
178 walker->max_level = walker->level;
179 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
180 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
182 accessed_dirty = PT_ACCESSED_MASK;
183 pt_access = pte_access = ACC_ALL;
188 unsigned long host_addr;
190 pt_access &= pte_access;
193 index = PT_INDEX(addr, walker->level);
195 table_gfn = gpte_to_gfn(pte);
196 offset = index * sizeof(pt_element_t);
197 pte_gpa = gfn_to_gpa(table_gfn) + offset;
198 walker->table_gfn[walker->level - 1] = table_gfn;
199 walker->pte_gpa[walker->level - 1] = pte_gpa;
201 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
202 PFERR_USER_MASK|PFERR_WRITE_MASK);
203 if (unlikely(real_gfn == UNMAPPED_GVA))
205 real_gfn = gpa_to_gfn(real_gfn);
207 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
208 if (unlikely(kvm_is_error_hva(host_addr)))
211 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
212 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
214 walker->ptep_user[walker->level - 1] = ptep_user;
216 trace_kvm_mmu_paging_element(pte, walker->level);
218 if (unlikely(!is_present_gpte(pte)))
221 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
222 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
226 accessed_dirty &= pte;
227 pte_access = pt_access & gpte_access(vcpu, pte);
229 walker->ptes[walker->level - 1] = pte;
230 } while (!is_last_gpte(mmu, walker->level, pte));
232 if (unlikely(permission_fault(mmu, pte_access, access))) {
233 errcode |= PFERR_PRESENT_MASK;
237 gfn = gpte_to_gfn_lvl(pte, walker->level);
238 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
240 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
241 gfn += pse36_gfn_delta(pte);
243 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access);
244 if (real_gpa == UNMAPPED_GVA)
247 walker->gfn = real_gpa >> PAGE_SHIFT;
250 protect_clean_gpte(&pte_access, pte);
253 * On a write fault, fold the dirty bit into accessed_dirty by
254 * shifting it one place right.
256 accessed_dirty &= pte >> (PT_DIRTY_SHIFT - PT_ACCESSED_SHIFT);
258 if (unlikely(!accessed_dirty)) {
259 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
260 if (unlikely(ret < 0))
266 walker->pt_access = pt_access;
267 walker->pte_access = pte_access;
268 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
269 __func__, (u64)pte, pte_access, pt_access);
273 errcode |= write_fault | user_fault;
274 if (fetch_fault && (mmu->nx ||
275 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
276 errcode |= PFERR_FETCH_MASK;
278 walker->fault.vector = PF_VECTOR;
279 walker->fault.error_code_valid = true;
280 walker->fault.error_code = errcode;
281 walker->fault.address = addr;
282 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
284 trace_kvm_mmu_walker_error(walker->fault.error_code);
288 static int FNAME(walk_addr)(struct guest_walker *walker,
289 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
291 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
295 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
296 struct kvm_vcpu *vcpu, gva_t addr,
299 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
304 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
305 u64 *spte, pt_element_t gpte, bool no_dirty_log)
311 if (prefetch_invalid_gpte(vcpu, sp, spte, gpte))
314 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
316 gfn = gpte_to_gfn(gpte);
317 pte_access = sp->role.access & gpte_access(vcpu, gpte);
318 protect_clean_gpte(&pte_access, gpte);
319 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
320 no_dirty_log && (pte_access & ACC_WRITE_MASK));
321 if (is_error_pfn(pfn))
325 * we call mmu_set_spte() with host_writable = true because
326 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
328 mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL,
329 gfn, pfn, true, true);
334 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
335 u64 *spte, const void *pte)
337 pt_element_t gpte = *(const pt_element_t *)pte;
339 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
342 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
343 struct guest_walker *gw, int level)
345 pt_element_t curr_pte;
346 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
350 if (level == PT_PAGE_TABLE_LEVEL) {
351 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
352 base_gpa = pte_gpa & ~mask;
353 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
355 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
356 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
357 curr_pte = gw->prefetch_ptes[index];
359 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
360 &curr_pte, sizeof(curr_pte));
362 return r || curr_pte != gw->ptes[level - 1];
365 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
368 struct kvm_mmu_page *sp;
369 pt_element_t *gptep = gw->prefetch_ptes;
373 sp = page_header(__pa(sptep));
375 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
379 return __direct_pte_prefetch(vcpu, sp, sptep);
381 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
384 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
388 if (is_shadow_present_pte(*spte))
391 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
397 * Fetch a shadow pte for a specific level in the paging hierarchy.
398 * If the guest tries to write a write-protected page, we need to
399 * emulate this operation, return 1 to indicate this case.
401 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
402 struct guest_walker *gw,
403 int write_fault, int hlevel,
404 pfn_t pfn, bool map_writable, bool prefault)
406 struct kvm_mmu_page *sp = NULL;
407 struct kvm_shadow_walk_iterator it;
408 unsigned direct_access, access = gw->pt_access;
409 int top_level, emulate = 0;
411 direct_access = gw->pte_access;
413 top_level = vcpu->arch.mmu.root_level;
414 if (top_level == PT32E_ROOT_LEVEL)
415 top_level = PT32_ROOT_LEVEL;
417 * Verify that the top-level gpte is still there. Since the page
418 * is a root page, it is either write protected (and cannot be
419 * changed from now on) or it is invalid (in which case, we don't
420 * really care if it changes underneath us after this point).
422 if (FNAME(gpte_changed)(vcpu, gw, top_level))
423 goto out_gpte_changed;
425 for (shadow_walk_init(&it, vcpu, addr);
426 shadow_walk_okay(&it) && it.level > gw->level;
427 shadow_walk_next(&it)) {
430 clear_sp_write_flooding_count(it.sptep);
431 drop_large_spte(vcpu, it.sptep);
434 if (!is_shadow_present_pte(*it.sptep)) {
435 table_gfn = gw->table_gfn[it.level - 2];
436 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
437 false, access, it.sptep);
441 * Verify that the gpte in the page we've just write
442 * protected is still there.
444 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
445 goto out_gpte_changed;
448 link_shadow_page(it.sptep, sp);
452 shadow_walk_okay(&it) && it.level > hlevel;
453 shadow_walk_next(&it)) {
456 clear_sp_write_flooding_count(it.sptep);
457 validate_direct_spte(vcpu, it.sptep, direct_access);
459 drop_large_spte(vcpu, it.sptep);
461 if (is_shadow_present_pte(*it.sptep))
464 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
466 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
467 true, direct_access, it.sptep);
468 link_shadow_page(it.sptep, sp);
471 clear_sp_write_flooding_count(it.sptep);
472 mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate,
473 it.level, gw->gfn, pfn, prefault, map_writable);
474 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
480 kvm_mmu_put_page(sp, it.sptep);
481 kvm_release_pfn_clean(pfn);
486 * To see whether the mapped gfn can write its page table in the current
489 * It is the helper function of FNAME(page_fault). When guest uses large page
490 * size to map the writable gfn which is used as current page table, we should
491 * force kvm to use small page size to map it because new shadow page will be
492 * created when kvm establishes shadow page table that stop kvm using large
493 * page size. Do it early can avoid unnecessary #PF and emulation.
495 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
496 * currently used as its page table.
498 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
499 * since the PDPT is always shadowed, that means, we can not use large page
500 * size to map the gfn which is used as PDPT.
503 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
504 struct guest_walker *walker, int user_fault,
505 bool *write_fault_to_shadow_pgtable)
508 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
509 bool self_changed = false;
511 if (!(walker->pte_access & ACC_WRITE_MASK ||
512 (!is_write_protection(vcpu) && !user_fault)))
515 for (level = walker->level; level <= walker->max_level; level++) {
516 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
518 self_changed |= !(gfn & mask);
519 *write_fault_to_shadow_pgtable |= !gfn;
526 * Page fault handler. There are several causes for a page fault:
527 * - there is no shadow pte for the guest pte
528 * - write access through a shadow pte marked read only so that we can set
530 * - write access to a shadow pte marked read only so we can update the page
531 * dirty bitmap, when userspace requests it
532 * - mmio access; in this case we will never install a present shadow pte
533 * - normal guest page fault due to the guest pte marked not present, not
534 * writable, or not executable
536 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
537 * a negative value on error.
539 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
542 int write_fault = error_code & PFERR_WRITE_MASK;
543 int user_fault = error_code & PFERR_USER_MASK;
544 struct guest_walker walker;
547 int level = PT_PAGE_TABLE_LEVEL;
549 unsigned long mmu_seq;
550 bool map_writable, is_self_change_mapping;
552 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
554 if (unlikely(error_code & PFERR_RSVD_MASK)) {
555 r = handle_mmio_page_fault(vcpu, addr, error_code,
556 mmu_is_nested(vcpu));
557 if (likely(r != RET_MMIO_PF_INVALID))
561 r = mmu_topup_memory_caches(vcpu);
566 * Look up the guest pte for the faulting address.
568 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
571 * The page is not mapped by the guest. Let the guest handle it.
574 pgprintk("%s: guest page fault\n", __func__);
576 inject_page_fault(vcpu, &walker.fault);
581 vcpu->arch.write_fault_to_shadow_pgtable = false;
583 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
584 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
586 if (walker.level >= PT_DIRECTORY_LEVEL)
587 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn)
588 || is_self_change_mapping;
591 if (!force_pt_level) {
592 level = min(walker.level, mapping_level(vcpu, walker.gfn));
593 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
596 mmu_seq = vcpu->kvm->mmu_notifier_seq;
599 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
603 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
604 walker.gfn, pfn, walker.pte_access, &r))
608 * Do not change pte_access if the pfn is a mmio page, otherwise
609 * we will cache the incorrect access into mmio spte.
611 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
612 !is_write_protection(vcpu) && !user_fault &&
613 !is_noslot_pfn(pfn)) {
614 walker.pte_access |= ACC_WRITE_MASK;
615 walker.pte_access &= ~ACC_USER_MASK;
618 * If we converted a user page to a kernel page,
619 * so that the kernel can write to it when cr0.wp=0,
620 * then we should prevent the kernel from executing it
621 * if SMEP is enabled.
623 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
624 walker.pte_access &= ~ACC_EXEC_MASK;
627 spin_lock(&vcpu->kvm->mmu_lock);
628 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
631 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
632 make_mmu_pages_available(vcpu);
634 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
635 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
636 level, pfn, map_writable, prefault);
637 ++vcpu->stat.pf_fixed;
638 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
639 spin_unlock(&vcpu->kvm->mmu_lock);
644 spin_unlock(&vcpu->kvm->mmu_lock);
645 kvm_release_pfn_clean(pfn);
649 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
653 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
656 offset = sp->role.quadrant << PT64_LEVEL_BITS;
658 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
661 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
663 struct kvm_shadow_walk_iterator iterator;
664 struct kvm_mmu_page *sp;
668 vcpu_clear_mmio_info(vcpu, gva);
671 * No need to check return value here, rmap_can_add() can
672 * help us to skip pte prefetch later.
674 mmu_topup_memory_caches(vcpu);
676 spin_lock(&vcpu->kvm->mmu_lock);
677 for_each_shadow_entry(vcpu, gva, iterator) {
678 level = iterator.level;
679 sptep = iterator.sptep;
681 sp = page_header(__pa(sptep));
682 if (is_last_spte(*sptep, level)) {
689 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
690 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
692 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
693 kvm_flush_remote_tlbs(vcpu->kvm);
695 if (!rmap_can_add(vcpu))
698 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
699 sizeof(pt_element_t)))
702 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
705 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
708 spin_unlock(&vcpu->kvm->mmu_lock);
711 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
712 struct x86_exception *exception)
714 struct guest_walker walker;
715 gpa_t gpa = UNMAPPED_GVA;
718 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
721 gpa = gfn_to_gpa(walker.gfn);
722 gpa |= vaddr & ~PAGE_MASK;
723 } else if (exception)
724 *exception = walker.fault;
729 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
731 struct x86_exception *exception)
733 struct guest_walker walker;
734 gpa_t gpa = UNMAPPED_GVA;
737 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
740 gpa = gfn_to_gpa(walker.gfn);
741 gpa |= vaddr & ~PAGE_MASK;
742 } else if (exception)
743 *exception = walker.fault;
749 * Using the cached information from sp->gfns is safe because:
750 * - The spte has a reference to the struct page, so the pfn for a given gfn
751 * can't change unless all sptes pointing to it are nuked first.
754 * We should flush all tlbs if spte is dropped even though guest is
755 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
756 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
757 * used by guest then tlbs are not flushed, so guest is allowed to access the
759 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
761 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
763 int i, nr_present = 0;
767 /* direct kvm_mmu_page can not be unsync. */
768 BUG_ON(sp->role.direct);
770 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
772 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
781 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
783 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
784 sizeof(pt_element_t)))
787 if (prefetch_invalid_gpte(vcpu, sp, &sp->spt[i], gpte)) {
788 vcpu->kvm->tlbs_dirty++;
792 gfn = gpte_to_gfn(gpte);
793 pte_access = sp->role.access;
794 pte_access &= gpte_access(vcpu, gpte);
795 protect_clean_gpte(&pte_access, gpte);
797 if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access,
801 if (gfn != sp->gfns[i]) {
802 drop_spte(vcpu->kvm, &sp->spt[i]);
803 vcpu->kvm->tlbs_dirty++;
809 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
811 set_spte(vcpu, &sp->spt[i], pte_access,
812 PT_PAGE_TABLE_LEVEL, gfn,
813 spte_to_pfn(sp->spt[i]), true, false,
823 #undef PT_BASE_ADDR_MASK
825 #undef PT_LVL_ADDR_MASK
826 #undef PT_LVL_OFFSET_MASK
828 #undef PT_MAX_FULL_LEVELS
830 #undef gpte_to_gfn_lvl