2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
31 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
32 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
51 #define PT_LEVEL_BITS PT32_LEVEL_BITS
52 #define PT_MAX_FULL_LEVELS 2
53 #define CMPXCHG cmpxchg
55 #error Invalid PTTYPE value
58 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
59 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
62 * The guest_walker structure emulates the behavior of the hardware page
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
68 pt_element_t ptes[PT_MAX_FULL_LEVELS];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
81 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
82 gfn_t table_gfn, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
89 page = gfn_to_page(kvm, table_gfn);
91 table = kmap_atomic(page, KM_USER0);
92 ret = CMPXCHG(&table[index], orig_pte, new_pte);
93 kunmap_atomic(table, KM_USER0);
95 kvm_release_page_dirty(page);
97 return (ret != orig_pte);
100 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
104 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
107 access &= ~(gpte >> PT64_NX_SHIFT);
113 * Fetch a guest pte for a guest virtual address
115 static int FNAME(walk_addr)(struct guest_walker *walker,
116 struct kvm_vcpu *vcpu, gva_t addr,
117 int write_fault, int user_fault, int fetch_fault)
121 unsigned index, pt_access, pte_access;
125 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
128 walker->level = vcpu->arch.mmu.root_level;
129 pte = vcpu->arch.cr3;
131 if (!is_long_mode(vcpu)) {
132 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
133 trace_kvm_mmu_paging_element(pte, walker->level);
134 if (!is_present_gpte(pte))
139 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
140 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
145 index = PT_INDEX(addr, walker->level);
147 table_gfn = gpte_to_gfn(pte);
148 pte_gpa = gfn_to_gpa(table_gfn);
149 pte_gpa += index * sizeof(pt_element_t);
150 walker->table_gfn[walker->level - 1] = table_gfn;
151 walker->pte_gpa[walker->level - 1] = pte_gpa;
153 if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)))
156 trace_kvm_mmu_paging_element(pte, walker->level);
158 if (!is_present_gpte(pte))
161 rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
165 if (write_fault && !is_writable_pte(pte))
166 if (user_fault || is_write_protection(vcpu))
169 if (user_fault && !(pte & PT_USER_MASK))
173 if (fetch_fault && (pte & PT64_NX_MASK))
177 if (!(pte & PT_ACCESSED_MASK)) {
178 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
180 mark_page_dirty(vcpu->kvm, table_gfn);
181 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
182 index, pte, pte|PT_ACCESSED_MASK))
184 pte |= PT_ACCESSED_MASK;
187 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
189 walker->ptes[walker->level - 1] = pte;
191 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
192 ((walker->level == PT_DIRECTORY_LEVEL) &&
194 (PTTYPE == 64 || is_pse(vcpu))) ||
195 ((walker->level == PT_PDPE_LEVEL) &&
197 is_long_mode(vcpu))) {
198 int lvl = walker->level;
200 walker->gfn = gpte_to_gfn_lvl(pte, lvl);
201 walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
205 walker->level == PT_DIRECTORY_LEVEL &&
207 walker->gfn += pse36_gfn_delta(pte);
212 pt_access = pte_access;
216 if (write_fault && !is_dirty_gpte(pte)) {
219 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
220 mark_page_dirty(vcpu->kvm, table_gfn);
221 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
225 pte |= PT_DIRTY_MASK;
226 walker->ptes[walker->level - 1] = pte;
229 walker->pt_access = pt_access;
230 walker->pte_access = pte_access;
231 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
232 __func__, (u64)pte, pt_access, pte_access);
236 walker->error_code = 0;
240 walker->error_code = PFERR_PRESENT_MASK;
244 walker->error_code |= PFERR_WRITE_MASK;
246 walker->error_code |= PFERR_USER_MASK;
248 walker->error_code |= PFERR_FETCH_MASK;
250 walker->error_code |= PFERR_RSVD_MASK;
251 trace_kvm_mmu_walker_error(walker->error_code);
255 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
256 u64 *spte, const void *pte)
263 gpte = *(const pt_element_t *)pte;
264 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
265 if (!is_present_gpte(gpte)) {
267 new_spte = shadow_trap_nonpresent_pte;
269 new_spte = shadow_notrap_nonpresent_pte;
270 __set_spte(spte, new_spte);
274 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
275 pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
276 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
278 pfn = vcpu->arch.update_pte.pfn;
279 if (is_error_pfn(pfn))
281 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
285 * we call mmu_set_spte() with reset_host_protection = true beacuse that
286 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
288 mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
289 gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
290 gpte_to_gfn(gpte), pfn, true, true);
294 * Fetch a shadow pte for a specific level in the paging hierarchy.
296 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
297 struct guest_walker *gw,
298 int user_fault, int write_fault, int hlevel,
299 int *ptwrite, pfn_t pfn)
301 unsigned access = gw->pt_access;
302 struct kvm_mmu_page *shadow_page;
303 u64 spte, *sptep = NULL;
308 pt_element_t curr_pte;
309 struct kvm_shadow_walk_iterator iterator;
311 if (!is_present_gpte(gw->ptes[gw->level - 1]))
314 for_each_shadow_entry(vcpu, addr, iterator) {
315 level = iterator.level;
316 sptep = iterator.sptep;
317 if (iterator.level == hlevel) {
318 mmu_set_spte(vcpu, sptep, access,
319 gw->pte_access & access,
320 user_fault, write_fault,
321 gw->ptes[gw->level-1] & PT_DIRTY_MASK,
323 gw->gfn, pfn, false, true);
327 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
330 if (is_large_pte(*sptep)) {
331 rmap_remove(vcpu->kvm, sptep);
332 __set_spte(sptep, shadow_trap_nonpresent_pte);
333 kvm_flush_remote_tlbs(vcpu->kvm);
336 if (level <= gw->level) {
337 int delta = level - gw->level + 1;
339 if (!is_dirty_gpte(gw->ptes[level - delta]))
340 access &= ~ACC_WRITE_MASK;
341 table_gfn = gpte_to_gfn(gw->ptes[level - delta]);
342 /* advance table_gfn when emulating 1gb pages with 4k */
344 table_gfn += PT_INDEX(addr, level);
347 table_gfn = gw->table_gfn[level - 2];
349 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
350 direct, access, sptep);
352 r = kvm_read_guest_atomic(vcpu->kvm,
353 gw->pte_gpa[level - 2],
354 &curr_pte, sizeof(curr_pte));
355 if (r || curr_pte != gw->ptes[level - 2]) {
356 kvm_mmu_put_page(shadow_page, sptep);
357 kvm_release_pfn_clean(pfn);
363 spte = __pa(shadow_page->spt)
364 | PT_PRESENT_MASK | PT_ACCESSED_MASK
365 | PT_WRITABLE_MASK | PT_USER_MASK;
373 * Page fault handler. There are several causes for a page fault:
374 * - there is no shadow pte for the guest pte
375 * - write access through a shadow pte marked read only so that we can set
377 * - write access to a shadow pte marked read only so we can update the page
378 * dirty bitmap, when userspace requests it
379 * - mmio access; in this case we will never install a present shadow pte
380 * - normal guest page fault due to the guest pte marked not present, not
381 * writable, or not executable
383 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
384 * a negative value on error.
386 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
389 int write_fault = error_code & PFERR_WRITE_MASK;
390 int user_fault = error_code & PFERR_USER_MASK;
391 int fetch_fault = error_code & PFERR_FETCH_MASK;
392 struct guest_walker walker;
397 int level = PT_PAGE_TABLE_LEVEL;
398 unsigned long mmu_seq;
400 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
401 kvm_mmu_audit(vcpu, "pre page fault");
403 r = mmu_topup_memory_caches(vcpu);
408 * Look up the guest pte for the faulting address.
410 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
414 * The page is not mapped by the guest. Let the guest handle it.
417 pgprintk("%s: guest page fault\n", __func__);
418 inject_page_fault(vcpu, addr, walker.error_code);
419 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
423 if (walker.level >= PT_DIRECTORY_LEVEL) {
424 level = min(walker.level, mapping_level(vcpu, walker.gfn));
425 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
428 mmu_seq = vcpu->kvm->mmu_notifier_seq;
430 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
433 if (is_error_pfn(pfn)) {
434 pgprintk("gfn %lx is mmio\n", walker.gfn);
435 kvm_release_pfn_clean(pfn);
439 spin_lock(&vcpu->kvm->mmu_lock);
440 if (mmu_notifier_retry(vcpu, mmu_seq))
442 kvm_mmu_free_some_pages(vcpu);
443 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
444 level, &write_pt, pfn);
445 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
446 sptep, *sptep, write_pt);
449 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
451 ++vcpu->stat.pf_fixed;
452 kvm_mmu_audit(vcpu, "post page fault (fixed)");
453 spin_unlock(&vcpu->kvm->mmu_lock);
458 spin_unlock(&vcpu->kvm->mmu_lock);
459 kvm_release_pfn_clean(pfn);
463 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
465 struct kvm_shadow_walk_iterator iterator;
471 spin_lock(&vcpu->kvm->mmu_lock);
473 for_each_shadow_entry(vcpu, gva, iterator) {
474 level = iterator.level;
475 sptep = iterator.sptep;
477 if (is_last_spte(*sptep, level)) {
478 struct kvm_mmu_page *sp = page_header(__pa(sptep));
482 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
483 offset = sp->role.quadrant << shift;
485 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
486 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
488 if (is_shadow_present_pte(*sptep)) {
489 rmap_remove(vcpu->kvm, sptep);
490 if (is_large_pte(*sptep))
491 --vcpu->kvm->stat.lpages;
494 __set_spte(sptep, shadow_trap_nonpresent_pte);
498 if (!is_shadow_present_pte(*sptep))
503 kvm_flush_remote_tlbs(vcpu->kvm);
505 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
507 spin_unlock(&vcpu->kvm->mmu_lock);
512 if (mmu_topup_memory_caches(vcpu))
514 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
517 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
520 struct guest_walker walker;
521 gpa_t gpa = UNMAPPED_GVA;
524 r = FNAME(walk_addr)(&walker, vcpu, vaddr,
525 !!(access & PFERR_WRITE_MASK),
526 !!(access & PFERR_USER_MASK),
527 !!(access & PFERR_FETCH_MASK));
530 gpa = gfn_to_gpa(walker.gfn);
531 gpa |= vaddr & ~PAGE_MASK;
533 *error = walker.error_code;
538 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
539 struct kvm_mmu_page *sp)
542 pt_element_t pt[256 / sizeof(pt_element_t)];
546 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
547 nonpaging_prefetch_page(vcpu, sp);
551 pte_gpa = gfn_to_gpa(sp->gfn);
553 offset = sp->role.quadrant << PT64_LEVEL_BITS;
554 pte_gpa += offset * sizeof(pt_element_t);
557 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
558 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
559 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
560 for (j = 0; j < ARRAY_SIZE(pt); ++j)
561 if (r || is_present_gpte(pt[j]))
562 sp->spt[i+j] = shadow_trap_nonpresent_pte;
564 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
569 * Using the cached information from sp->gfns is safe because:
570 * - The spte has a reference to the struct page, so the pfn for a given gfn
571 * can't change unless all sptes pointing to it are nuked first.
572 * - Alias changes zap the entire shadow cache.
574 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
576 int i, offset, nr_present;
577 bool reset_host_protection;
580 offset = nr_present = 0;
583 offset = sp->role.quadrant << PT64_LEVEL_BITS;
585 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
587 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
591 gfn_t gfn = sp->gfns[i];
593 if (!is_shadow_present_pte(sp->spt[i]))
596 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
598 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
599 sizeof(pt_element_t)))
602 if (gpte_to_gfn(gpte) != gfn || !is_present_gpte(gpte) ||
603 !(gpte & PT_ACCESSED_MASK)) {
606 rmap_remove(vcpu->kvm, &sp->spt[i]);
607 if (is_present_gpte(gpte))
608 nonpresent = shadow_trap_nonpresent_pte;
610 nonpresent = shadow_notrap_nonpresent_pte;
611 __set_spte(&sp->spt[i], nonpresent);
616 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
617 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
618 pte_access &= ~ACC_WRITE_MASK;
619 reset_host_protection = 0;
621 reset_host_protection = 1;
623 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
624 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
625 spte_to_pfn(sp->spt[i]), true, false,
626 reset_host_protection);
635 #undef PT_BASE_ADDR_MASK
638 #undef PT_LVL_ADDR_MASK
639 #undef PT_LVL_OFFSET_MASK
641 #undef PT_MAX_FULL_LEVELS
643 #undef gpte_to_gfn_lvl