2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
28 * uses for EPT without A/D paging type.
30 extern u64 __pure __using_nonexistent_pte_bit(void)
31 __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
34 #define pt_element_t u64
35 #define guest_walker guest_walker64
36 #define FNAME(name) paging##64_##name
37 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
38 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
39 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
40 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
41 #define PT_LEVEL_BITS PT64_LEVEL_BITS
42 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
43 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
44 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
45 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
47 #define PT_MAX_FULL_LEVELS 4
48 #define CMPXCHG cmpxchg
50 #define CMPXCHG cmpxchg64
51 #define PT_MAX_FULL_LEVELS 2
54 #define pt_element_t u32
55 #define guest_walker guest_walker32
56 #define FNAME(name) paging##32_##name
57 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
58 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
59 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
60 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
61 #define PT_LEVEL_BITS PT32_LEVEL_BITS
62 #define PT_MAX_FULL_LEVELS 2
63 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
64 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
65 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
66 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
67 #define CMPXCHG cmpxchg
68 #elif PTTYPE == PTTYPE_EPT
69 #define pt_element_t u64
70 #define guest_walker guest_walkerEPT
71 #define FNAME(name) ept_##name
72 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
73 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
74 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
75 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
76 #define PT_LEVEL_BITS PT64_LEVEL_BITS
77 #define PT_GUEST_ACCESSED_MASK 0
78 #define PT_GUEST_DIRTY_MASK 0
79 #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
80 #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
81 #define CMPXCHG cmpxchg64
82 #define PT_MAX_FULL_LEVELS 4
84 #error Invalid PTTYPE value
87 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
88 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
91 * The guest_walker structure emulates the behavior of the hardware page
97 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
98 pt_element_t ptes[PT_MAX_FULL_LEVELS];
99 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
100 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
101 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
105 struct x86_exception fault;
108 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
110 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
113 static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
117 /* dirty bit is not supported, so no need to track it */
118 if (!PT_GUEST_DIRTY_MASK)
121 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
123 mask = (unsigned)~ACC_WRITE_MASK;
124 /* Allow write access to dirty gptes */
125 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
130 static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
132 int bit7 = (gpte >> 7) & 1, low6 = gpte & 0x3f;
134 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) |
135 ((mmu->bad_mt_xwr & (1ull << low6)) != 0);
138 static inline int FNAME(is_present_gpte)(unsigned long pte)
140 #if PTTYPE != PTTYPE_EPT
141 return is_present_gpte(pte);
147 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
148 pt_element_t __user *ptep_user, unsigned index,
149 pt_element_t orig_pte, pt_element_t new_pte)
156 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
157 /* Check if the user is doing something meaningless. */
158 if (unlikely(npages != 1))
161 table = kmap_atomic(page);
162 ret = CMPXCHG(&table[index], orig_pte, new_pte);
163 kunmap_atomic(table);
165 kvm_release_page_dirty(page);
167 return (ret != orig_pte);
170 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
171 struct kvm_mmu_page *sp, u64 *spte,
174 if (FNAME(is_rsvd_bits_set)(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
177 if (!FNAME(is_present_gpte)(gpte))
180 /* if accessed bit is not supported prefetch non accessed gpte */
181 if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK))
187 drop_spte(vcpu->kvm, spte);
191 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
194 #if PTTYPE == PTTYPE_EPT
195 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
196 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
199 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
200 access &= ~(gpte >> PT64_NX_SHIFT);
206 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
208 struct guest_walker *walker,
211 unsigned level, index;
212 pt_element_t pte, orig_pte;
213 pt_element_t __user *ptep_user;
217 /* dirty/accessed bits are not supported, so no need to update them */
218 if (!PT_GUEST_DIRTY_MASK)
221 for (level = walker->max_level; level >= walker->level; --level) {
222 pte = orig_pte = walker->ptes[level - 1];
223 table_gfn = walker->table_gfn[level - 1];
224 ptep_user = walker->ptep_user[level - 1];
225 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
226 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
227 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
228 pte |= PT_GUEST_ACCESSED_MASK;
230 if (level == walker->level && write_fault &&
231 !(pte & PT_GUEST_DIRTY_MASK)) {
232 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
233 pte |= PT_GUEST_DIRTY_MASK;
238 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
242 mark_page_dirty(vcpu->kvm, table_gfn);
243 walker->ptes[level] = pte;
249 * Fetch a guest pte for a guest virtual address
251 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
252 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
253 gva_t addr, u32 access)
257 pt_element_t __user *uninitialized_var(ptep_user);
259 unsigned index, pt_access, pte_access, accessed_dirty;
262 const int write_fault = access & PFERR_WRITE_MASK;
263 const int user_fault = access & PFERR_USER_MASK;
264 const int fetch_fault = access & PFERR_FETCH_MASK;
269 trace_kvm_mmu_pagetable_walk(addr, access);
271 walker->level = mmu->root_level;
272 pte = mmu->get_cr3(vcpu);
275 if (walker->level == PT32E_ROOT_LEVEL) {
276 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
277 trace_kvm_mmu_paging_element(pte, walker->level);
278 if (!FNAME(is_present_gpte)(pte))
283 walker->max_level = walker->level;
284 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
285 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
287 accessed_dirty = PT_GUEST_ACCESSED_MASK;
288 pt_access = pte_access = ACC_ALL;
293 unsigned long host_addr;
295 pt_access &= pte_access;
298 index = PT_INDEX(addr, walker->level);
300 table_gfn = gpte_to_gfn(pte);
301 offset = index * sizeof(pt_element_t);
302 pte_gpa = gfn_to_gpa(table_gfn) + offset;
303 walker->table_gfn[walker->level - 1] = table_gfn;
304 walker->pte_gpa[walker->level - 1] = pte_gpa;
306 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
307 PFERR_USER_MASK|PFERR_WRITE_MASK);
308 if (unlikely(real_gfn == UNMAPPED_GVA))
310 real_gfn = gpa_to_gfn(real_gfn);
312 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
313 if (unlikely(kvm_is_error_hva(host_addr)))
316 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
317 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
319 walker->ptep_user[walker->level - 1] = ptep_user;
321 trace_kvm_mmu_paging_element(pte, walker->level);
323 if (unlikely(!FNAME(is_present_gpte)(pte)))
326 if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte,
328 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
332 accessed_dirty &= pte;
333 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
335 walker->ptes[walker->level - 1] = pte;
336 } while (!is_last_gpte(mmu, walker->level, pte));
338 if (unlikely(permission_fault(mmu, pte_access, access))) {
339 errcode |= PFERR_PRESENT_MASK;
343 gfn = gpte_to_gfn_lvl(pte, walker->level);
344 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
346 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
347 gfn += pse36_gfn_delta(pte);
349 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access);
350 if (real_gpa == UNMAPPED_GVA)
353 walker->gfn = real_gpa >> PAGE_SHIFT;
356 FNAME(protect_clean_gpte)(&pte_access, pte);
359 * On a write fault, fold the dirty bit into accessed_dirty.
360 * For modes without A/D bits support accessed_dirty will be
363 accessed_dirty &= pte >>
364 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
366 if (unlikely(!accessed_dirty)) {
367 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
368 if (unlikely(ret < 0))
374 walker->pt_access = pt_access;
375 walker->pte_access = pte_access;
376 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
377 __func__, (u64)pte, pte_access, pt_access);
381 errcode |= write_fault | user_fault;
382 if (fetch_fault && (mmu->nx ||
383 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
384 errcode |= PFERR_FETCH_MASK;
386 walker->fault.vector = PF_VECTOR;
387 walker->fault.error_code_valid = true;
388 walker->fault.error_code = errcode;
390 #if PTTYPE == PTTYPE_EPT
392 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
393 * misconfiguration requires to be injected. The detection is
394 * done by is_rsvd_bits_set() above.
396 * We set up the value of exit_qualification to inject:
397 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
398 * [5:3] - Calculated by the page walk of the guest EPT page tables
399 * [7:8] - Derived from [7:8] of real exit_qualification
401 * The other bits are set to 0.
403 if (!(errcode & PFERR_RSVD_MASK)) {
404 vcpu->arch.exit_qualification &= 0x187;
405 vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
408 walker->fault.address = addr;
409 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
411 trace_kvm_mmu_walker_error(walker->fault.error_code);
415 static int FNAME(walk_addr)(struct guest_walker *walker,
416 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
418 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
422 #if PTTYPE != PTTYPE_EPT
423 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
424 struct kvm_vcpu *vcpu, gva_t addr,
427 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
433 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
434 u64 *spte, pt_element_t gpte, bool no_dirty_log)
440 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
443 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
445 gfn = gpte_to_gfn(gpte);
446 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
447 FNAME(protect_clean_gpte)(&pte_access, gpte);
448 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
449 no_dirty_log && (pte_access & ACC_WRITE_MASK));
450 if (is_error_pfn(pfn))
454 * we call mmu_set_spte() with host_writable = true because
455 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
457 mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL,
458 gfn, pfn, true, true);
463 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
464 u64 *spte, const void *pte)
466 pt_element_t gpte = *(const pt_element_t *)pte;
468 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
471 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
472 struct guest_walker *gw, int level)
474 pt_element_t curr_pte;
475 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
479 if (level == PT_PAGE_TABLE_LEVEL) {
480 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
481 base_gpa = pte_gpa & ~mask;
482 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
484 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
485 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
486 curr_pte = gw->prefetch_ptes[index];
488 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
489 &curr_pte, sizeof(curr_pte));
491 return r || curr_pte != gw->ptes[level - 1];
494 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
497 struct kvm_mmu_page *sp;
498 pt_element_t *gptep = gw->prefetch_ptes;
502 sp = page_header(__pa(sptep));
504 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
508 return __direct_pte_prefetch(vcpu, sp, sptep);
510 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
513 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
517 if (is_shadow_present_pte(*spte))
520 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
526 * Fetch a shadow pte for a specific level in the paging hierarchy.
527 * If the guest tries to write a write-protected page, we need to
528 * emulate this operation, return 1 to indicate this case.
530 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
531 struct guest_walker *gw,
532 int write_fault, int hlevel,
533 pfn_t pfn, bool map_writable, bool prefault)
535 struct kvm_mmu_page *sp = NULL;
536 struct kvm_shadow_walk_iterator it;
537 unsigned direct_access, access = gw->pt_access;
538 int top_level, emulate = 0;
540 direct_access = gw->pte_access;
542 top_level = vcpu->arch.mmu.root_level;
543 if (top_level == PT32E_ROOT_LEVEL)
544 top_level = PT32_ROOT_LEVEL;
546 * Verify that the top-level gpte is still there. Since the page
547 * is a root page, it is either write protected (and cannot be
548 * changed from now on) or it is invalid (in which case, we don't
549 * really care if it changes underneath us after this point).
551 if (FNAME(gpte_changed)(vcpu, gw, top_level))
552 goto out_gpte_changed;
554 for (shadow_walk_init(&it, vcpu, addr);
555 shadow_walk_okay(&it) && it.level > gw->level;
556 shadow_walk_next(&it)) {
559 clear_sp_write_flooding_count(it.sptep);
560 drop_large_spte(vcpu, it.sptep);
563 if (!is_shadow_present_pte(*it.sptep)) {
564 table_gfn = gw->table_gfn[it.level - 2];
565 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
566 false, access, it.sptep);
570 * Verify that the gpte in the page we've just write
571 * protected is still there.
573 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
574 goto out_gpte_changed;
577 link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
581 shadow_walk_okay(&it) && it.level > hlevel;
582 shadow_walk_next(&it)) {
585 clear_sp_write_flooding_count(it.sptep);
586 validate_direct_spte(vcpu, it.sptep, direct_access);
588 drop_large_spte(vcpu, it.sptep);
590 if (is_shadow_present_pte(*it.sptep))
593 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
595 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
596 true, direct_access, it.sptep);
597 link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
600 clear_sp_write_flooding_count(it.sptep);
601 mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate,
602 it.level, gw->gfn, pfn, prefault, map_writable);
603 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
609 kvm_mmu_put_page(sp, it.sptep);
610 kvm_release_pfn_clean(pfn);
615 * To see whether the mapped gfn can write its page table in the current
618 * It is the helper function of FNAME(page_fault). When guest uses large page
619 * size to map the writable gfn which is used as current page table, we should
620 * force kvm to use small page size to map it because new shadow page will be
621 * created when kvm establishes shadow page table that stop kvm using large
622 * page size. Do it early can avoid unnecessary #PF and emulation.
624 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
625 * currently used as its page table.
627 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
628 * since the PDPT is always shadowed, that means, we can not use large page
629 * size to map the gfn which is used as PDPT.
632 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
633 struct guest_walker *walker, int user_fault,
634 bool *write_fault_to_shadow_pgtable)
637 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
638 bool self_changed = false;
640 if (!(walker->pte_access & ACC_WRITE_MASK ||
641 (!is_write_protection(vcpu) && !user_fault)))
644 for (level = walker->level; level <= walker->max_level; level++) {
645 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
647 self_changed |= !(gfn & mask);
648 *write_fault_to_shadow_pgtable |= !gfn;
655 * Page fault handler. There are several causes for a page fault:
656 * - there is no shadow pte for the guest pte
657 * - write access through a shadow pte marked read only so that we can set
659 * - write access to a shadow pte marked read only so we can update the page
660 * dirty bitmap, when userspace requests it
661 * - mmio access; in this case we will never install a present shadow pte
662 * - normal guest page fault due to the guest pte marked not present, not
663 * writable, or not executable
665 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
666 * a negative value on error.
668 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
671 int write_fault = error_code & PFERR_WRITE_MASK;
672 int user_fault = error_code & PFERR_USER_MASK;
673 struct guest_walker walker;
676 int level = PT_PAGE_TABLE_LEVEL;
678 unsigned long mmu_seq;
679 bool map_writable, is_self_change_mapping;
681 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
683 if (unlikely(error_code & PFERR_RSVD_MASK)) {
684 r = handle_mmio_page_fault(vcpu, addr, error_code,
685 mmu_is_nested(vcpu));
686 if (likely(r != RET_MMIO_PF_INVALID))
690 r = mmu_topup_memory_caches(vcpu);
695 * Look up the guest pte for the faulting address.
697 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
700 * The page is not mapped by the guest. Let the guest handle it.
703 pgprintk("%s: guest page fault\n", __func__);
705 inject_page_fault(vcpu, &walker.fault);
710 vcpu->arch.write_fault_to_shadow_pgtable = false;
712 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
713 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
715 if (walker.level >= PT_DIRECTORY_LEVEL)
716 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn)
717 || is_self_change_mapping;
720 if (!force_pt_level) {
721 level = min(walker.level, mapping_level(vcpu, walker.gfn));
722 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
725 mmu_seq = vcpu->kvm->mmu_notifier_seq;
728 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
732 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
733 walker.gfn, pfn, walker.pte_access, &r))
737 * Do not change pte_access if the pfn is a mmio page, otherwise
738 * we will cache the incorrect access into mmio spte.
740 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
741 !is_write_protection(vcpu) && !user_fault &&
742 !is_noslot_pfn(pfn)) {
743 walker.pte_access |= ACC_WRITE_MASK;
744 walker.pte_access &= ~ACC_USER_MASK;
747 * If we converted a user page to a kernel page,
748 * so that the kernel can write to it when cr0.wp=0,
749 * then we should prevent the kernel from executing it
750 * if SMEP is enabled.
752 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
753 walker.pte_access &= ~ACC_EXEC_MASK;
756 spin_lock(&vcpu->kvm->mmu_lock);
757 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
760 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
761 make_mmu_pages_available(vcpu);
763 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
764 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
765 level, pfn, map_writable, prefault);
766 ++vcpu->stat.pf_fixed;
767 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
768 spin_unlock(&vcpu->kvm->mmu_lock);
773 spin_unlock(&vcpu->kvm->mmu_lock);
774 kvm_release_pfn_clean(pfn);
778 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
782 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
785 offset = sp->role.quadrant << PT64_LEVEL_BITS;
787 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
790 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
792 struct kvm_shadow_walk_iterator iterator;
793 struct kvm_mmu_page *sp;
797 vcpu_clear_mmio_info(vcpu, gva);
800 * No need to check return value here, rmap_can_add() can
801 * help us to skip pte prefetch later.
803 mmu_topup_memory_caches(vcpu);
805 spin_lock(&vcpu->kvm->mmu_lock);
806 for_each_shadow_entry(vcpu, gva, iterator) {
807 level = iterator.level;
808 sptep = iterator.sptep;
810 sp = page_header(__pa(sptep));
811 if (is_last_spte(*sptep, level)) {
818 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
819 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
821 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
822 kvm_flush_remote_tlbs(vcpu->kvm);
824 if (!rmap_can_add(vcpu))
827 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
828 sizeof(pt_element_t)))
831 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
834 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
837 spin_unlock(&vcpu->kvm->mmu_lock);
840 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
841 struct x86_exception *exception)
843 struct guest_walker walker;
844 gpa_t gpa = UNMAPPED_GVA;
847 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
850 gpa = gfn_to_gpa(walker.gfn);
851 gpa |= vaddr & ~PAGE_MASK;
852 } else if (exception)
853 *exception = walker.fault;
858 #if PTTYPE != PTTYPE_EPT
859 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
861 struct x86_exception *exception)
863 struct guest_walker walker;
864 gpa_t gpa = UNMAPPED_GVA;
867 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
870 gpa = gfn_to_gpa(walker.gfn);
871 gpa |= vaddr & ~PAGE_MASK;
872 } else if (exception)
873 *exception = walker.fault;
880 * Using the cached information from sp->gfns is safe because:
881 * - The spte has a reference to the struct page, so the pfn for a given gfn
882 * can't change unless all sptes pointing to it are nuked first.
885 * We should flush all tlbs if spte is dropped even though guest is
886 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
887 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
888 * used by guest then tlbs are not flushed, so guest is allowed to access the
890 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
892 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
894 int i, nr_present = 0;
898 /* direct kvm_mmu_page can not be unsync. */
899 BUG_ON(sp->role.direct);
901 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
903 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
912 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
914 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
915 sizeof(pt_element_t)))
918 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
919 vcpu->kvm->tlbs_dirty++;
923 gfn = gpte_to_gfn(gpte);
924 pte_access = sp->role.access;
925 pte_access &= FNAME(gpte_access)(vcpu, gpte);
926 FNAME(protect_clean_gpte)(&pte_access, gpte);
928 if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access,
932 if (gfn != sp->gfns[i]) {
933 drop_spte(vcpu->kvm, &sp->spt[i]);
934 vcpu->kvm->tlbs_dirty++;
940 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
942 set_spte(vcpu, &sp->spt[i], pte_access,
943 PT_PAGE_TABLE_LEVEL, gfn,
944 spte_to_pfn(sp->spt[i]), true, false,
954 #undef PT_BASE_ADDR_MASK
956 #undef PT_LVL_ADDR_MASK
957 #undef PT_LVL_OFFSET_MASK
959 #undef PT_MAX_FULL_LEVELS
961 #undef gpte_to_gfn_lvl
963 #undef PT_GUEST_ACCESSED_MASK
964 #undef PT_GUEST_DIRTY_MASK
965 #undef PT_GUEST_DIRTY_SHIFT
966 #undef PT_GUEST_ACCESSED_SHIFT