2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
28 * uses for EPT without A/D paging type.
30 extern u64 __pure __using_nonexistent_pte_bit(void)
31 __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
34 #define pt_element_t u64
35 #define guest_walker guest_walker64
36 #define FNAME(name) paging##64_##name
37 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
38 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
39 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
40 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
41 #define PT_LEVEL_BITS PT64_LEVEL_BITS
42 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
43 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
44 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
45 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
47 #define PT_MAX_FULL_LEVELS 4
48 #define CMPXCHG cmpxchg
50 #define CMPXCHG cmpxchg64
51 #define PT_MAX_FULL_LEVELS 2
54 #define pt_element_t u32
55 #define guest_walker guest_walker32
56 #define FNAME(name) paging##32_##name
57 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
58 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
59 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
60 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
61 #define PT_LEVEL_BITS PT32_LEVEL_BITS
62 #define PT_MAX_FULL_LEVELS 2
63 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
64 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
65 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
66 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
67 #define CMPXCHG cmpxchg
68 #elif PTTYPE == PTTYPE_EPT
69 #define pt_element_t u64
70 #define guest_walker guest_walkerEPT
71 #define FNAME(name) ept_##name
72 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
73 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
74 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
75 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
76 #define PT_LEVEL_BITS PT64_LEVEL_BITS
77 #define PT_GUEST_ACCESSED_MASK 0
78 #define PT_GUEST_DIRTY_MASK 0
79 #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
80 #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
81 #define CMPXCHG cmpxchg64
82 #define PT_MAX_FULL_LEVELS 4
84 #error Invalid PTTYPE value
87 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
88 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
91 * The guest_walker structure emulates the behavior of the hardware page
97 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
98 pt_element_t ptes[PT_MAX_FULL_LEVELS];
99 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
100 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
101 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
102 bool pte_writable[PT_MAX_FULL_LEVELS];
106 struct x86_exception fault;
109 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
111 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
114 static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
118 /* dirty bit is not supported, so no need to track it */
119 if (!PT_GUEST_DIRTY_MASK)
122 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
124 mask = (unsigned)~ACC_WRITE_MASK;
125 /* Allow write access to dirty gptes */
126 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
131 static inline int FNAME(is_present_gpte)(unsigned long pte)
133 #if PTTYPE != PTTYPE_EPT
134 return is_present_gpte(pte);
140 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
141 pt_element_t __user *ptep_user, unsigned index,
142 pt_element_t orig_pte, pt_element_t new_pte)
149 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
150 /* Check if the user is doing something meaningless. */
151 if (unlikely(npages != 1))
154 table = kmap_atomic(page);
155 ret = CMPXCHG(&table[index], orig_pte, new_pte);
156 kunmap_atomic(table);
158 kvm_release_page_dirty(page);
160 return (ret != orig_pte);
163 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
164 struct kvm_mmu_page *sp, u64 *spte,
167 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
170 if (!FNAME(is_present_gpte)(gpte))
173 /* if accessed bit is not supported prefetch non accessed gpte */
174 if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK))
180 drop_spte(vcpu->kvm, spte);
184 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
187 #if PTTYPE == PTTYPE_EPT
188 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
189 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
192 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
193 access &= ~(gpte >> PT64_NX_SHIFT);
199 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
201 struct guest_walker *walker,
204 unsigned level, index;
205 pt_element_t pte, orig_pte;
206 pt_element_t __user *ptep_user;
210 /* dirty/accessed bits are not supported, so no need to update them */
211 if (!PT_GUEST_DIRTY_MASK)
214 for (level = walker->max_level; level >= walker->level; --level) {
215 pte = orig_pte = walker->ptes[level - 1];
216 table_gfn = walker->table_gfn[level - 1];
217 ptep_user = walker->ptep_user[level - 1];
218 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
219 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
220 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
221 pte |= PT_GUEST_ACCESSED_MASK;
223 if (level == walker->level && write_fault &&
224 !(pte & PT_GUEST_DIRTY_MASK)) {
225 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
226 pte |= PT_GUEST_DIRTY_MASK;
232 * If the slot is read-only, simply do not process the accessed
233 * and dirty bits. This is the correct thing to do if the slot
234 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
235 * are only supported if the accessed and dirty bits are already
236 * set in the ROM (so that MMIO writes are never needed).
238 * Note that NPT does not allow this at all and faults, since
239 * it always wants nested page table entries for the guest
240 * page tables to be writable. And EPT works but will simply
241 * overwrite the read-only memory to set the accessed and dirty
244 if (unlikely(!walker->pte_writable[level - 1]))
247 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
251 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
252 walker->ptes[level] = pte;
258 * Fetch a guest pte for a guest virtual address
260 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
261 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
262 gva_t addr, u32 access)
266 pt_element_t __user *uninitialized_var(ptep_user);
268 unsigned index, pt_access, pte_access, accessed_dirty;
271 const int write_fault = access & PFERR_WRITE_MASK;
272 const int user_fault = access & PFERR_USER_MASK;
273 const int fetch_fault = access & PFERR_FETCH_MASK;
278 trace_kvm_mmu_pagetable_walk(addr, access);
280 walker->level = mmu->root_level;
281 pte = mmu->get_cr3(vcpu);
284 if (walker->level == PT32E_ROOT_LEVEL) {
285 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
286 trace_kvm_mmu_paging_element(pte, walker->level);
287 if (!FNAME(is_present_gpte)(pte))
292 walker->max_level = walker->level;
293 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
295 accessed_dirty = PT_GUEST_ACCESSED_MASK;
296 pt_access = pte_access = ACC_ALL;
301 unsigned long host_addr;
303 pt_access &= pte_access;
306 index = PT_INDEX(addr, walker->level);
308 table_gfn = gpte_to_gfn(pte);
309 offset = index * sizeof(pt_element_t);
310 pte_gpa = gfn_to_gpa(table_gfn) + offset;
311 walker->table_gfn[walker->level - 1] = table_gfn;
312 walker->pte_gpa[walker->level - 1] = pte_gpa;
314 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
315 PFERR_USER_MASK|PFERR_WRITE_MASK,
319 * FIXME: This can happen if emulation (for of an INS/OUTS
320 * instruction) triggers a nested page fault. The exit
321 * qualification / exit info field will incorrectly have
322 * "guest page access" as the nested page fault's cause,
323 * instead of "guest page structure access". To fix this,
324 * the x86_exception struct should be augmented with enough
325 * information to fix the exit_qualification or exit_info_1
328 if (unlikely(real_gfn == UNMAPPED_GVA))
331 real_gfn = gpa_to_gfn(real_gfn);
333 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
334 &walker->pte_writable[walker->level - 1]);
335 if (unlikely(kvm_is_error_hva(host_addr)))
338 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
339 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
341 walker->ptep_user[walker->level - 1] = ptep_user;
343 trace_kvm_mmu_paging_element(pte, walker->level);
345 if (unlikely(!FNAME(is_present_gpte)(pte)))
348 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
349 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
353 accessed_dirty &= pte;
354 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
356 walker->ptes[walker->level - 1] = pte;
357 } while (!is_last_gpte(mmu, walker->level, pte));
359 if (unlikely(permission_fault(vcpu, mmu, pte_access, access))) {
360 errcode |= PFERR_PRESENT_MASK;
364 gfn = gpte_to_gfn_lvl(pte, walker->level);
365 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
367 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
368 gfn += pse36_gfn_delta(pte);
370 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
371 if (real_gpa == UNMAPPED_GVA)
374 walker->gfn = real_gpa >> PAGE_SHIFT;
377 FNAME(protect_clean_gpte)(&pte_access, pte);
380 * On a write fault, fold the dirty bit into accessed_dirty.
381 * For modes without A/D bits support accessed_dirty will be
384 accessed_dirty &= pte >>
385 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
387 if (unlikely(!accessed_dirty)) {
388 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
389 if (unlikely(ret < 0))
395 walker->pt_access = pt_access;
396 walker->pte_access = pte_access;
397 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
398 __func__, (u64)pte, pte_access, pt_access);
402 errcode |= write_fault | user_fault;
403 if (fetch_fault && (mmu->nx ||
404 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
405 errcode |= PFERR_FETCH_MASK;
407 walker->fault.vector = PF_VECTOR;
408 walker->fault.error_code_valid = true;
409 walker->fault.error_code = errcode;
411 #if PTTYPE == PTTYPE_EPT
413 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
414 * misconfiguration requires to be injected. The detection is
415 * done by is_rsvd_bits_set() above.
417 * We set up the value of exit_qualification to inject:
418 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
419 * [5:3] - Calculated by the page walk of the guest EPT page tables
420 * [7:8] - Derived from [7:8] of real exit_qualification
422 * The other bits are set to 0.
424 if (!(errcode & PFERR_RSVD_MASK)) {
425 vcpu->arch.exit_qualification &= 0x187;
426 vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
429 walker->fault.address = addr;
430 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
432 trace_kvm_mmu_walker_error(walker->fault.error_code);
436 static int FNAME(walk_addr)(struct guest_walker *walker,
437 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
439 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
443 #if PTTYPE != PTTYPE_EPT
444 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
445 struct kvm_vcpu *vcpu, gva_t addr,
448 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
454 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
455 u64 *spte, pt_element_t gpte, bool no_dirty_log)
461 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
464 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
466 gfn = gpte_to_gfn(gpte);
467 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
468 FNAME(protect_clean_gpte)(&pte_access, gpte);
469 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
470 no_dirty_log && (pte_access & ACC_WRITE_MASK));
471 if (is_error_pfn(pfn))
475 * we call mmu_set_spte() with host_writable = true because
476 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
478 mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL,
479 gfn, pfn, true, true);
484 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
485 u64 *spte, const void *pte)
487 pt_element_t gpte = *(const pt_element_t *)pte;
489 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
492 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
493 struct guest_walker *gw, int level)
495 pt_element_t curr_pte;
496 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
500 if (level == PT_PAGE_TABLE_LEVEL) {
501 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
502 base_gpa = pte_gpa & ~mask;
503 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
505 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
506 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
507 curr_pte = gw->prefetch_ptes[index];
509 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
510 &curr_pte, sizeof(curr_pte));
512 return r || curr_pte != gw->ptes[level - 1];
515 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
518 struct kvm_mmu_page *sp;
519 pt_element_t *gptep = gw->prefetch_ptes;
523 sp = page_header(__pa(sptep));
525 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
529 return __direct_pte_prefetch(vcpu, sp, sptep);
531 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
534 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
538 if (is_shadow_present_pte(*spte))
541 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
547 * Fetch a shadow pte for a specific level in the paging hierarchy.
548 * If the guest tries to write a write-protected page, we need to
549 * emulate this operation, return 1 to indicate this case.
551 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
552 struct guest_walker *gw,
553 int write_fault, int hlevel,
554 pfn_t pfn, bool map_writable, bool prefault)
556 struct kvm_mmu_page *sp = NULL;
557 struct kvm_shadow_walk_iterator it;
558 unsigned direct_access, access = gw->pt_access;
559 int top_level, emulate = 0;
561 direct_access = gw->pte_access;
563 top_level = vcpu->arch.mmu.root_level;
564 if (top_level == PT32E_ROOT_LEVEL)
565 top_level = PT32_ROOT_LEVEL;
567 * Verify that the top-level gpte is still there. Since the page
568 * is a root page, it is either write protected (and cannot be
569 * changed from now on) or it is invalid (in which case, we don't
570 * really care if it changes underneath us after this point).
572 if (FNAME(gpte_changed)(vcpu, gw, top_level))
573 goto out_gpte_changed;
575 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
576 goto out_gpte_changed;
578 for (shadow_walk_init(&it, vcpu, addr);
579 shadow_walk_okay(&it) && it.level > gw->level;
580 shadow_walk_next(&it)) {
583 clear_sp_write_flooding_count(it.sptep);
584 drop_large_spte(vcpu, it.sptep);
587 if (!is_shadow_present_pte(*it.sptep)) {
588 table_gfn = gw->table_gfn[it.level - 2];
589 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
590 false, access, it.sptep);
594 * Verify that the gpte in the page we've just write
595 * protected is still there.
597 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
598 goto out_gpte_changed;
601 link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
605 shadow_walk_okay(&it) && it.level > hlevel;
606 shadow_walk_next(&it)) {
609 clear_sp_write_flooding_count(it.sptep);
610 validate_direct_spte(vcpu, it.sptep, direct_access);
612 drop_large_spte(vcpu, it.sptep);
614 if (is_shadow_present_pte(*it.sptep))
617 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
619 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
620 true, direct_access, it.sptep);
621 link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
624 clear_sp_write_flooding_count(it.sptep);
625 mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate,
626 it.level, gw->gfn, pfn, prefault, map_writable);
627 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
633 kvm_mmu_put_page(sp, it.sptep);
634 kvm_release_pfn_clean(pfn);
639 * To see whether the mapped gfn can write its page table in the current
642 * It is the helper function of FNAME(page_fault). When guest uses large page
643 * size to map the writable gfn which is used as current page table, we should
644 * force kvm to use small page size to map it because new shadow page will be
645 * created when kvm establishes shadow page table that stop kvm using large
646 * page size. Do it early can avoid unnecessary #PF and emulation.
648 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
649 * currently used as its page table.
651 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
652 * since the PDPT is always shadowed, that means, we can not use large page
653 * size to map the gfn which is used as PDPT.
656 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
657 struct guest_walker *walker, int user_fault,
658 bool *write_fault_to_shadow_pgtable)
661 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
662 bool self_changed = false;
664 if (!(walker->pte_access & ACC_WRITE_MASK ||
665 (!is_write_protection(vcpu) && !user_fault)))
668 for (level = walker->level; level <= walker->max_level; level++) {
669 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
671 self_changed |= !(gfn & mask);
672 *write_fault_to_shadow_pgtable |= !gfn;
679 * Page fault handler. There are several causes for a page fault:
680 * - there is no shadow pte for the guest pte
681 * - write access through a shadow pte marked read only so that we can set
683 * - write access to a shadow pte marked read only so we can update the page
684 * dirty bitmap, when userspace requests it
685 * - mmio access; in this case we will never install a present shadow pte
686 * - normal guest page fault due to the guest pte marked not present, not
687 * writable, or not executable
689 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
690 * a negative value on error.
692 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
695 int write_fault = error_code & PFERR_WRITE_MASK;
696 int user_fault = error_code & PFERR_USER_MASK;
697 struct guest_walker walker;
700 int level = PT_PAGE_TABLE_LEVEL;
702 unsigned long mmu_seq;
703 bool map_writable, is_self_change_mapping;
705 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
707 if (unlikely(error_code & PFERR_RSVD_MASK)) {
708 r = handle_mmio_page_fault(vcpu, addr, error_code,
709 mmu_is_nested(vcpu));
710 if (likely(r != RET_MMIO_PF_INVALID))
714 * page fault with PFEC.RSVD = 1 is caused by shadow
715 * page fault, should not be used to walk guest page
718 error_code &= ~PFERR_RSVD_MASK;
721 r = mmu_topup_memory_caches(vcpu);
726 * Look up the guest pte for the faulting address.
728 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
731 * The page is not mapped by the guest. Let the guest handle it.
734 pgprintk("%s: guest page fault\n", __func__);
736 inject_page_fault(vcpu, &walker.fault);
741 vcpu->arch.write_fault_to_shadow_pgtable = false;
743 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
744 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
746 if (walker.level >= PT_DIRECTORY_LEVEL)
747 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn)
748 || is_self_change_mapping;
751 if (!force_pt_level) {
752 level = min(walker.level, mapping_level(vcpu, walker.gfn));
753 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
756 mmu_seq = vcpu->kvm->mmu_notifier_seq;
759 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
763 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
764 walker.gfn, pfn, walker.pte_access, &r))
768 * Do not change pte_access if the pfn is a mmio page, otherwise
769 * we will cache the incorrect access into mmio spte.
771 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
772 !is_write_protection(vcpu) && !user_fault &&
773 !is_noslot_pfn(pfn)) {
774 walker.pte_access |= ACC_WRITE_MASK;
775 walker.pte_access &= ~ACC_USER_MASK;
778 * If we converted a user page to a kernel page,
779 * so that the kernel can write to it when cr0.wp=0,
780 * then we should prevent the kernel from executing it
781 * if SMEP is enabled.
783 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
784 walker.pte_access &= ~ACC_EXEC_MASK;
787 spin_lock(&vcpu->kvm->mmu_lock);
788 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
791 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
792 make_mmu_pages_available(vcpu);
794 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
795 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
796 level, pfn, map_writable, prefault);
797 ++vcpu->stat.pf_fixed;
798 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
799 spin_unlock(&vcpu->kvm->mmu_lock);
804 spin_unlock(&vcpu->kvm->mmu_lock);
805 kvm_release_pfn_clean(pfn);
809 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
813 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
816 offset = sp->role.quadrant << PT64_LEVEL_BITS;
818 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
821 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
823 struct kvm_shadow_walk_iterator iterator;
824 struct kvm_mmu_page *sp;
828 vcpu_clear_mmio_info(vcpu, gva);
831 * No need to check return value here, rmap_can_add() can
832 * help us to skip pte prefetch later.
834 mmu_topup_memory_caches(vcpu);
836 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
841 spin_lock(&vcpu->kvm->mmu_lock);
842 for_each_shadow_entry(vcpu, gva, iterator) {
843 level = iterator.level;
844 sptep = iterator.sptep;
846 sp = page_header(__pa(sptep));
847 if (is_last_spte(*sptep, level)) {
854 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
855 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
857 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
858 kvm_flush_remote_tlbs(vcpu->kvm);
860 if (!rmap_can_add(vcpu))
863 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
864 sizeof(pt_element_t)))
867 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
870 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
873 spin_unlock(&vcpu->kvm->mmu_lock);
876 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
877 struct x86_exception *exception)
879 struct guest_walker walker;
880 gpa_t gpa = UNMAPPED_GVA;
883 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
886 gpa = gfn_to_gpa(walker.gfn);
887 gpa |= vaddr & ~PAGE_MASK;
888 } else if (exception)
889 *exception = walker.fault;
894 #if PTTYPE != PTTYPE_EPT
895 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
897 struct x86_exception *exception)
899 struct guest_walker walker;
900 gpa_t gpa = UNMAPPED_GVA;
903 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
906 gpa = gfn_to_gpa(walker.gfn);
907 gpa |= vaddr & ~PAGE_MASK;
908 } else if (exception)
909 *exception = walker.fault;
916 * Using the cached information from sp->gfns is safe because:
917 * - The spte has a reference to the struct page, so the pfn for a given gfn
918 * can't change unless all sptes pointing to it are nuked first.
921 * We should flush all tlbs if spte is dropped even though guest is
922 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
923 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
924 * used by guest then tlbs are not flushed, so guest is allowed to access the
926 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
928 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
930 int i, nr_present = 0;
934 /* direct kvm_mmu_page can not be unsync. */
935 BUG_ON(sp->role.direct);
937 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
939 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
948 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
950 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
951 sizeof(pt_element_t)))
954 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
955 vcpu->kvm->tlbs_dirty++;
959 gfn = gpte_to_gfn(gpte);
960 pte_access = sp->role.access;
961 pte_access &= FNAME(gpte_access)(vcpu, gpte);
962 FNAME(protect_clean_gpte)(&pte_access, gpte);
964 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
968 if (gfn != sp->gfns[i]) {
969 drop_spte(vcpu->kvm, &sp->spt[i]);
970 vcpu->kvm->tlbs_dirty++;
976 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
978 set_spte(vcpu, &sp->spt[i], pte_access,
979 PT_PAGE_TABLE_LEVEL, gfn,
980 spte_to_pfn(sp->spt[i]), true, false,
990 #undef PT_BASE_ADDR_MASK
992 #undef PT_LVL_ADDR_MASK
993 #undef PT_LVL_OFFSET_MASK
995 #undef PT_MAX_FULL_LEVELS
997 #undef gpte_to_gfn_lvl
999 #undef PT_GUEST_ACCESSED_MASK
1000 #undef PT_GUEST_DIRTY_MASK
1001 #undef PT_GUEST_DIRTY_SHIFT
1002 #undef PT_GUEST_ACCESSED_SHIFT