2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
33 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 #define IOPM_ALLOC_ORDER 2
42 #define MSRPM_ALLOC_ORDER 1
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
50 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
52 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
53 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
54 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58 static const u32 host_save_user_msrs[] = {
60 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
63 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
66 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
75 /* These are the merged vectors */
78 /* gpa pointers to the real vectors */
81 /* A VMEXIT is required but not yet emulated */
84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
110 struct nested_state nested;
115 /* enable NPT for AMD64 and X86 with PAE */
116 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
117 static bool npt_enabled = true;
119 static bool npt_enabled = false;
123 module_param(npt, int, S_IRUGO);
125 static int nested = 1;
126 module_param(nested, int, S_IRUGO);
128 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
129 static void svm_complete_interrupts(struct vcpu_svm *svm);
131 static int nested_svm_exit_handled(struct vcpu_svm *svm);
132 static int nested_svm_intercept(struct vcpu_svm *svm);
133 static int nested_svm_vmexit(struct vcpu_svm *svm);
134 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
135 bool has_error_code, u32 error_code);
137 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
139 return container_of(vcpu, struct vcpu_svm, vcpu);
142 static inline bool is_nested(struct vcpu_svm *svm)
144 return svm->nested.vmcb;
147 static inline void enable_gif(struct vcpu_svm *svm)
149 svm->vcpu.arch.hflags |= HF_GIF_MASK;
152 static inline void disable_gif(struct vcpu_svm *svm)
154 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
157 static inline bool gif_set(struct vcpu_svm *svm)
159 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
162 static unsigned long iopm_base;
164 struct kvm_ldttss_desc {
167 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
168 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
171 } __attribute__((packed));
173 struct svm_cpu_data {
179 struct kvm_ldttss_desc *tss_desc;
181 struct page *save_area;
184 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
185 static uint32_t svm_features;
187 struct svm_init_data {
192 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
194 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
195 #define MSRS_RANGE_SIZE 2048
196 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
198 #define MAX_INST_SIZE 15
200 static inline u32 svm_has(u32 feat)
202 return svm_features & feat;
205 static inline void clgi(void)
207 asm volatile (__ex(SVM_CLGI));
210 static inline void stgi(void)
212 asm volatile (__ex(SVM_STGI));
215 static inline void invlpga(unsigned long addr, u32 asid)
217 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
220 static inline void force_new_asid(struct kvm_vcpu *vcpu)
222 to_svm(vcpu)->asid_generation--;
225 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
227 force_new_asid(vcpu);
230 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
232 if (!npt_enabled && !(efer & EFER_LMA))
235 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
236 vcpu->arch.efer = efer;
239 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
240 bool has_error_code, u32 error_code)
242 struct vcpu_svm *svm = to_svm(vcpu);
244 /* If we are within a nested VM we'd better #VMEXIT and let the
245 guest handle the exception */
246 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
249 svm->vmcb->control.event_inj = nr
251 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
252 | SVM_EVTINJ_TYPE_EXEPT;
253 svm->vmcb->control.event_inj_err = error_code;
256 static int is_external_interrupt(u32 info)
258 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
259 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
262 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
264 struct vcpu_svm *svm = to_svm(vcpu);
267 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
268 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
272 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
274 struct vcpu_svm *svm = to_svm(vcpu);
277 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
279 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
283 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
285 struct vcpu_svm *svm = to_svm(vcpu);
287 if (!svm->next_rip) {
288 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
290 printk(KERN_DEBUG "%s: NOP\n", __func__);
293 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
294 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
295 __func__, kvm_rip_read(vcpu), svm->next_rip);
297 kvm_rip_write(vcpu, svm->next_rip);
298 svm_set_interrupt_shadow(vcpu, 0);
301 static int has_svm(void)
305 if (!cpu_has_svm(&msg)) {
306 printk(KERN_INFO "has_svm: %s\n", msg);
313 static void svm_hardware_disable(void *garbage)
318 static int svm_hardware_enable(void *garbage)
321 struct svm_cpu_data *sd;
323 struct desc_ptr gdt_descr;
324 struct desc_struct *gdt;
325 int me = raw_smp_processor_id();
327 rdmsrl(MSR_EFER, efer);
328 if (efer & EFER_SVME)
332 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
336 sd = per_cpu(svm_data, me);
339 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
344 sd->asid_generation = 1;
345 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
346 sd->next_asid = sd->max_asid + 1;
348 kvm_get_gdt(&gdt_descr);
349 gdt = (struct desc_struct *)gdt_descr.address;
350 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
352 wrmsrl(MSR_EFER, efer | EFER_SVME);
354 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
359 static void svm_cpu_uninit(int cpu)
361 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
366 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
367 __free_page(sd->save_area);
371 static int svm_cpu_init(int cpu)
373 struct svm_cpu_data *sd;
376 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
380 sd->save_area = alloc_page(GFP_KERNEL);
385 per_cpu(svm_data, cpu) = sd;
395 static void set_msr_interception(u32 *msrpm, unsigned msr,
400 for (i = 0; i < NUM_MSR_MAPS; i++) {
401 if (msr >= msrpm_ranges[i] &&
402 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
403 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
404 msrpm_ranges[i]) * 2;
406 u32 *base = msrpm + (msr_offset / 32);
407 u32 msr_shift = msr_offset % 32;
408 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
409 *base = (*base & ~(0x3 << msr_shift)) |
417 static void svm_vcpu_init_msrpm(u32 *msrpm)
419 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
422 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
424 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
425 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
426 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
427 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
429 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
430 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
433 static void svm_enable_lbrv(struct vcpu_svm *svm)
435 u32 *msrpm = svm->msrpm;
437 svm->vmcb->control.lbr_ctl = 1;
438 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
440 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
441 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
444 static void svm_disable_lbrv(struct vcpu_svm *svm)
446 u32 *msrpm = svm->msrpm;
448 svm->vmcb->control.lbr_ctl = 0;
449 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
451 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
452 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
455 static __init int svm_hardware_setup(void)
458 struct page *iopm_pages;
462 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
467 iopm_va = page_address(iopm_pages);
468 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
469 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
471 if (boot_cpu_has(X86_FEATURE_NX))
472 kvm_enable_efer_bits(EFER_NX);
474 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
475 kvm_enable_efer_bits(EFER_FFXSR);
478 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
479 kvm_enable_efer_bits(EFER_SVME);
482 for_each_possible_cpu(cpu) {
483 r = svm_cpu_init(cpu);
488 svm_features = cpuid_edx(SVM_CPUID_FUNC);
490 if (!svm_has(SVM_FEATURE_NPT))
493 if (npt_enabled && !npt) {
494 printk(KERN_INFO "kvm: Nested Paging disabled\n");
499 printk(KERN_INFO "kvm: Nested Paging enabled\n");
507 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
512 static __exit void svm_hardware_unsetup(void)
516 for_each_possible_cpu(cpu)
519 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
523 static void init_seg(struct vmcb_seg *seg)
526 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
527 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
532 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
535 seg->attrib = SVM_SELECTOR_P_MASK | type;
540 static void init_vmcb(struct vcpu_svm *svm)
542 struct vmcb_control_area *control = &svm->vmcb->control;
543 struct vmcb_save_area *save = &svm->vmcb->save;
545 svm->vcpu.fpu_active = 1;
547 control->intercept_cr_read = INTERCEPT_CR0_MASK |
551 control->intercept_cr_write = INTERCEPT_CR0_MASK |
556 control->intercept_dr_read = INTERCEPT_DR0_MASK |
565 control->intercept_dr_write = INTERCEPT_DR0_MASK |
574 control->intercept_exceptions = (1 << PF_VECTOR) |
579 control->intercept = (1ULL << INTERCEPT_INTR) |
580 (1ULL << INTERCEPT_NMI) |
581 (1ULL << INTERCEPT_SMI) |
582 (1ULL << INTERCEPT_SELECTIVE_CR0) |
583 (1ULL << INTERCEPT_CPUID) |
584 (1ULL << INTERCEPT_INVD) |
585 (1ULL << INTERCEPT_HLT) |
586 (1ULL << INTERCEPT_INVLPG) |
587 (1ULL << INTERCEPT_INVLPGA) |
588 (1ULL << INTERCEPT_IOIO_PROT) |
589 (1ULL << INTERCEPT_MSR_PROT) |
590 (1ULL << INTERCEPT_TASK_SWITCH) |
591 (1ULL << INTERCEPT_SHUTDOWN) |
592 (1ULL << INTERCEPT_VMRUN) |
593 (1ULL << INTERCEPT_VMMCALL) |
594 (1ULL << INTERCEPT_VMLOAD) |
595 (1ULL << INTERCEPT_VMSAVE) |
596 (1ULL << INTERCEPT_STGI) |
597 (1ULL << INTERCEPT_CLGI) |
598 (1ULL << INTERCEPT_SKINIT) |
599 (1ULL << INTERCEPT_WBINVD) |
600 (1ULL << INTERCEPT_MONITOR) |
601 (1ULL << INTERCEPT_MWAIT);
603 control->iopm_base_pa = iopm_base;
604 control->msrpm_base_pa = __pa(svm->msrpm);
605 control->tsc_offset = 0;
606 control->int_ctl = V_INTR_MASKING_MASK;
614 save->cs.selector = 0xf000;
615 /* Executable/Readable Code Segment */
616 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
617 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
618 save->cs.limit = 0xffff;
620 * cs.base should really be 0xffff0000, but vmx can't handle that, so
621 * be consistent with it.
623 * Replace when we have real mode working for vmx.
625 save->cs.base = 0xf0000;
627 save->gdtr.limit = 0xffff;
628 save->idtr.limit = 0xffff;
630 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
631 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
633 save->efer = EFER_SVME;
634 save->dr6 = 0xffff0ff0;
637 save->rip = 0x0000fff0;
638 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
640 /* This is the guest-visible cr0 value.
641 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
643 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
644 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
646 save->cr4 = X86_CR4_PAE;
650 /* Setup VMCB for Nested Paging */
651 control->nested_ctl = 1;
652 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
653 (1ULL << INTERCEPT_INVLPG));
654 control->intercept_exceptions &= ~(1 << PF_VECTOR);
655 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
656 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
657 save->g_pat = 0x0007040600070406ULL;
661 force_new_asid(&svm->vcpu);
663 svm->nested.vmcb = 0;
664 svm->vcpu.arch.hflags = 0;
666 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
667 control->pause_filter_count = 3000;
668 control->intercept |= (1ULL << INTERCEPT_PAUSE);
674 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
676 struct vcpu_svm *svm = to_svm(vcpu);
680 if (!kvm_vcpu_is_bsp(vcpu)) {
681 kvm_rip_write(vcpu, 0);
682 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
683 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
685 vcpu->arch.regs_avail = ~0;
686 vcpu->arch.regs_dirty = ~0;
691 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
693 struct vcpu_svm *svm;
695 struct page *msrpm_pages;
696 struct page *hsave_page;
697 struct page *nested_msrpm_pages;
700 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
706 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
711 page = alloc_page(GFP_KERNEL);
715 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
719 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
720 if (!nested_msrpm_pages)
723 hsave_page = alloc_page(GFP_KERNEL);
727 svm->nested.hsave = page_address(hsave_page);
729 svm->msrpm = page_address(msrpm_pages);
730 svm_vcpu_init_msrpm(svm->msrpm);
732 svm->nested.msrpm = page_address(nested_msrpm_pages);
734 svm->vmcb = page_address(page);
735 clear_page(svm->vmcb);
736 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
737 svm->asid_generation = 0;
741 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
742 if (kvm_vcpu_is_bsp(&svm->vcpu))
743 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
748 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
750 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
754 kvm_vcpu_uninit(&svm->vcpu);
756 kmem_cache_free(kvm_vcpu_cache, svm);
761 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
763 struct vcpu_svm *svm = to_svm(vcpu);
765 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
766 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
767 __free_page(virt_to_page(svm->nested.hsave));
768 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
769 kvm_vcpu_uninit(vcpu);
770 kmem_cache_free(kvm_vcpu_cache, svm);
773 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
775 struct vcpu_svm *svm = to_svm(vcpu);
778 if (unlikely(cpu != vcpu->cpu)) {
781 if (check_tsc_unstable()) {
783 * Make sure that the guest sees a monotonically
786 delta = vcpu->arch.host_tsc - native_read_tsc();
787 svm->vmcb->control.tsc_offset += delta;
789 svm->nested.hsave->control.tsc_offset += delta;
792 kvm_migrate_timers(vcpu);
793 svm->asid_generation = 0;
796 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
797 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
800 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
802 struct vcpu_svm *svm = to_svm(vcpu);
805 ++vcpu->stat.host_state_reload;
806 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
807 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
809 vcpu->arch.host_tsc = native_read_tsc();
812 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
814 return to_svm(vcpu)->vmcb->save.rflags;
817 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
819 to_svm(vcpu)->vmcb->save.rflags = rflags;
822 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
825 case VCPU_EXREG_PDPTR:
826 BUG_ON(!npt_enabled);
827 load_pdptrs(vcpu, vcpu->arch.cr3);
834 static void svm_set_vintr(struct vcpu_svm *svm)
836 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
839 static void svm_clear_vintr(struct vcpu_svm *svm)
841 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
844 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
846 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
849 case VCPU_SREG_CS: return &save->cs;
850 case VCPU_SREG_DS: return &save->ds;
851 case VCPU_SREG_ES: return &save->es;
852 case VCPU_SREG_FS: return &save->fs;
853 case VCPU_SREG_GS: return &save->gs;
854 case VCPU_SREG_SS: return &save->ss;
855 case VCPU_SREG_TR: return &save->tr;
856 case VCPU_SREG_LDTR: return &save->ldtr;
862 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
864 struct vmcb_seg *s = svm_seg(vcpu, seg);
869 static void svm_get_segment(struct kvm_vcpu *vcpu,
870 struct kvm_segment *var, int seg)
872 struct vmcb_seg *s = svm_seg(vcpu, seg);
875 var->limit = s->limit;
876 var->selector = s->selector;
877 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
878 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
879 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
880 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
881 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
882 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
883 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
884 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
886 /* AMD's VMCB does not have an explicit unusable field, so emulate it
887 * for cross vendor migration purposes by "not present"
889 var->unusable = !var->present || (var->type == 0);
894 * SVM always stores 0 for the 'G' bit in the CS selector in
895 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
896 * Intel's VMENTRY has a check on the 'G' bit.
898 var->g = s->limit > 0xfffff;
902 * Work around a bug where the busy flag in the tr selector
912 * The accessed bit must always be set in the segment
913 * descriptor cache, although it can be cleared in the
914 * descriptor, the cached bit always remains at 1. Since
915 * Intel has a check on this, set it here to support
916 * cross-vendor migration.
922 /* On AMD CPUs sometimes the DB bit in the segment
923 * descriptor is left as 1, although the whole segment has
924 * been made unusable. Clear it here to pass an Intel VMX
925 * entry check when cross vendor migrating.
933 static int svm_get_cpl(struct kvm_vcpu *vcpu)
935 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
940 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
942 struct vcpu_svm *svm = to_svm(vcpu);
944 dt->size = svm->vmcb->save.idtr.limit;
945 dt->address = svm->vmcb->save.idtr.base;
948 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
950 struct vcpu_svm *svm = to_svm(vcpu);
952 svm->vmcb->save.idtr.limit = dt->size;
953 svm->vmcb->save.idtr.base = dt->address ;
956 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
958 struct vcpu_svm *svm = to_svm(vcpu);
960 dt->size = svm->vmcb->save.gdtr.limit;
961 dt->address = svm->vmcb->save.gdtr.base;
964 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
966 struct vcpu_svm *svm = to_svm(vcpu);
968 svm->vmcb->save.gdtr.limit = dt->size;
969 svm->vmcb->save.gdtr.base = dt->address ;
972 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
976 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
980 static void update_cr0_intercept(struct vcpu_svm *svm)
982 struct vmcb *vmcb = svm->vmcb;
983 ulong gcr0 = svm->vcpu.arch.cr0;
984 u64 *hcr0 = &svm->vmcb->save.cr0;
986 if (!svm->vcpu.fpu_active)
987 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
989 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
990 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
993 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
994 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
995 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
996 if (is_nested(svm)) {
997 struct vmcb *hsave = svm->nested.hsave;
999 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1000 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1001 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1002 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1005 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1006 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1007 if (is_nested(svm)) {
1008 struct vmcb *hsave = svm->nested.hsave;
1010 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1011 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1016 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1018 struct vcpu_svm *svm = to_svm(vcpu);
1020 #ifdef CONFIG_X86_64
1021 if (vcpu->arch.efer & EFER_LME) {
1022 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1023 vcpu->arch.efer |= EFER_LMA;
1024 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1027 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1028 vcpu->arch.efer &= ~EFER_LMA;
1029 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1033 vcpu->arch.cr0 = cr0;
1036 cr0 |= X86_CR0_PG | X86_CR0_WP;
1038 if (!vcpu->fpu_active)
1041 * re-enable caching here because the QEMU bios
1042 * does not do it - this results in some delay at
1045 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1046 svm->vmcb->save.cr0 = cr0;
1047 update_cr0_intercept(svm);
1050 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1052 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1053 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1055 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1056 force_new_asid(vcpu);
1058 vcpu->arch.cr4 = cr4;
1061 cr4 |= host_cr4_mce;
1062 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1065 static void svm_set_segment(struct kvm_vcpu *vcpu,
1066 struct kvm_segment *var, int seg)
1068 struct vcpu_svm *svm = to_svm(vcpu);
1069 struct vmcb_seg *s = svm_seg(vcpu, seg);
1071 s->base = var->base;
1072 s->limit = var->limit;
1073 s->selector = var->selector;
1077 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1078 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1079 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1080 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1081 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1082 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1083 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1084 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1086 if (seg == VCPU_SREG_CS)
1088 = (svm->vmcb->save.cs.attrib
1089 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1093 static void update_db_intercept(struct kvm_vcpu *vcpu)
1095 struct vcpu_svm *svm = to_svm(vcpu);
1097 svm->vmcb->control.intercept_exceptions &=
1098 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1100 if (svm->nmi_singlestep)
1101 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1103 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1104 if (vcpu->guest_debug &
1105 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1106 svm->vmcb->control.intercept_exceptions |=
1108 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1109 svm->vmcb->control.intercept_exceptions |=
1112 vcpu->guest_debug = 0;
1115 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1117 struct vcpu_svm *svm = to_svm(vcpu);
1119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1120 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1122 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1124 update_db_intercept(vcpu);
1127 static void load_host_msrs(struct kvm_vcpu *vcpu)
1129 #ifdef CONFIG_X86_64
1130 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1134 static void save_host_msrs(struct kvm_vcpu *vcpu)
1136 #ifdef CONFIG_X86_64
1137 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1141 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1143 if (sd->next_asid > sd->max_asid) {
1144 ++sd->asid_generation;
1146 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1149 svm->asid_generation = sd->asid_generation;
1150 svm->vmcb->control.asid = sd->next_asid++;
1153 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1155 struct vcpu_svm *svm = to_svm(vcpu);
1159 *dest = vcpu->arch.db[dr];
1162 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1163 return EMULATE_FAIL; /* will re-inject UD */
1166 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1167 *dest = vcpu->arch.dr6;
1169 *dest = svm->vmcb->save.dr6;
1172 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1173 return EMULATE_FAIL; /* will re-inject UD */
1176 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1177 *dest = vcpu->arch.dr7;
1179 *dest = svm->vmcb->save.dr7;
1183 return EMULATE_DONE;
1186 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1188 struct vcpu_svm *svm = to_svm(vcpu);
1192 vcpu->arch.db[dr] = value;
1193 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1194 vcpu->arch.eff_db[dr] = value;
1197 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1198 return EMULATE_FAIL; /* will re-inject UD */
1201 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1204 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1205 return EMULATE_FAIL; /* will re-inject UD */
1208 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1209 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1210 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1211 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1216 return EMULATE_DONE;
1219 static int pf_interception(struct vcpu_svm *svm)
1224 fault_address = svm->vmcb->control.exit_info_2;
1225 error_code = svm->vmcb->control.exit_info_1;
1227 trace_kvm_page_fault(fault_address, error_code);
1228 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1229 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1230 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1233 static int db_interception(struct vcpu_svm *svm)
1235 struct kvm_run *kvm_run = svm->vcpu.run;
1237 if (!(svm->vcpu.guest_debug &
1238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1239 !svm->nmi_singlestep) {
1240 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1244 if (svm->nmi_singlestep) {
1245 svm->nmi_singlestep = false;
1246 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1247 svm->vmcb->save.rflags &=
1248 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1249 update_db_intercept(&svm->vcpu);
1252 if (svm->vcpu.guest_debug &
1253 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1254 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1255 kvm_run->debug.arch.pc =
1256 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1257 kvm_run->debug.arch.exception = DB_VECTOR;
1264 static int bp_interception(struct vcpu_svm *svm)
1266 struct kvm_run *kvm_run = svm->vcpu.run;
1268 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1269 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1270 kvm_run->debug.arch.exception = BP_VECTOR;
1274 static int ud_interception(struct vcpu_svm *svm)
1278 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1279 if (er != EMULATE_DONE)
1280 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1284 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1286 struct vcpu_svm *svm = to_svm(vcpu);
1289 if (is_nested(svm)) {
1292 h_excp = svm->nested.hsave->control.intercept_exceptions;
1293 n_excp = svm->nested.intercept_exceptions;
1294 h_excp &= ~(1 << NM_VECTOR);
1295 excp = h_excp | n_excp;
1297 excp = svm->vmcb->control.intercept_exceptions;
1298 excp &= ~(1 << NM_VECTOR);
1301 svm->vmcb->control.intercept_exceptions = excp;
1303 svm->vcpu.fpu_active = 1;
1304 update_cr0_intercept(svm);
1307 static int nm_interception(struct vcpu_svm *svm)
1309 svm_fpu_activate(&svm->vcpu);
1313 static int mc_interception(struct vcpu_svm *svm)
1316 * On an #MC intercept the MCE handler is not called automatically in
1317 * the host. So do it by hand here.
1321 /* not sure if we ever come back to this point */
1326 static int shutdown_interception(struct vcpu_svm *svm)
1328 struct kvm_run *kvm_run = svm->vcpu.run;
1331 * VMCB is undefined after a SHUTDOWN intercept
1332 * so reinitialize it.
1334 clear_page(svm->vmcb);
1337 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1341 static int io_interception(struct vcpu_svm *svm)
1343 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1344 int size, in, string;
1347 ++svm->vcpu.stat.io_exits;
1349 svm->next_rip = svm->vmcb->control.exit_info_2;
1351 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1354 if (emulate_instruction(&svm->vcpu,
1355 0, 0, 0) == EMULATE_DO_MMIO)
1360 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1361 port = io_info >> 16;
1362 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1364 skip_emulated_instruction(&svm->vcpu);
1365 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1368 static int nmi_interception(struct vcpu_svm *svm)
1373 static int intr_interception(struct vcpu_svm *svm)
1375 ++svm->vcpu.stat.irq_exits;
1379 static int nop_on_interception(struct vcpu_svm *svm)
1384 static int halt_interception(struct vcpu_svm *svm)
1386 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1387 skip_emulated_instruction(&svm->vcpu);
1388 return kvm_emulate_halt(&svm->vcpu);
1391 static int vmmcall_interception(struct vcpu_svm *svm)
1393 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1394 skip_emulated_instruction(&svm->vcpu);
1395 kvm_emulate_hypercall(&svm->vcpu);
1399 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1401 if (!(svm->vcpu.arch.efer & EFER_SVME)
1402 || !is_paging(&svm->vcpu)) {
1403 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1407 if (svm->vmcb->save.cpl) {
1408 kvm_inject_gp(&svm->vcpu, 0);
1415 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1416 bool has_error_code, u32 error_code)
1420 if (!is_nested(svm))
1423 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1424 svm->vmcb->control.exit_code_hi = 0;
1425 svm->vmcb->control.exit_info_1 = error_code;
1426 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1428 vmexit = nested_svm_intercept(svm);
1429 if (vmexit == NESTED_EXIT_DONE)
1430 svm->nested.exit_required = true;
1435 /* This function returns true if it is save to enable the irq window */
1436 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1438 if (!is_nested(svm))
1441 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1444 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1447 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1449 if (svm->nested.intercept & 1ULL) {
1451 * The #vmexit can't be emulated here directly because this
1452 * code path runs with irqs and preemtion disabled. A
1453 * #vmexit emulation might sleep. Only signal request for
1456 svm->nested.exit_required = true;
1457 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1464 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1470 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1471 if (is_error_page(page))
1479 kvm_release_page_clean(page);
1480 kvm_inject_gp(&svm->vcpu, 0);
1485 static void nested_svm_unmap(struct page *page)
1488 kvm_release_page_dirty(page);
1491 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1493 u32 param = svm->vmcb->control.exit_info_1 & 1;
1494 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1499 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1507 case 0xc0000000 ... 0xc0001fff:
1508 t0 = (8192 + msr - 0xc0000000) * 2;
1512 case 0xc0010000 ... 0xc0011fff:
1513 t0 = (16384 + msr - 0xc0010000) * 2;
1522 if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1523 ret = val & ((1 << param) << t0);
1529 static int nested_svm_exit_special(struct vcpu_svm *svm)
1531 u32 exit_code = svm->vmcb->control.exit_code;
1533 switch (exit_code) {
1536 return NESTED_EXIT_HOST;
1537 /* For now we are always handling NPFs when using them */
1540 return NESTED_EXIT_HOST;
1542 /* When we're shadowing, trap PFs */
1543 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1545 return NESTED_EXIT_HOST;
1547 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1548 nm_interception(svm);
1554 return NESTED_EXIT_CONTINUE;
1558 * If this function returns true, this #vmexit was already handled
1560 static int nested_svm_intercept(struct vcpu_svm *svm)
1562 u32 exit_code = svm->vmcb->control.exit_code;
1563 int vmexit = NESTED_EXIT_HOST;
1565 switch (exit_code) {
1567 vmexit = nested_svm_exit_handled_msr(svm);
1569 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1570 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1571 if (svm->nested.intercept_cr_read & cr_bits)
1572 vmexit = NESTED_EXIT_DONE;
1575 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1576 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1577 if (svm->nested.intercept_cr_write & cr_bits)
1578 vmexit = NESTED_EXIT_DONE;
1581 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1582 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1583 if (svm->nested.intercept_dr_read & dr_bits)
1584 vmexit = NESTED_EXIT_DONE;
1587 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1588 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1589 if (svm->nested.intercept_dr_write & dr_bits)
1590 vmexit = NESTED_EXIT_DONE;
1593 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1594 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1595 if (svm->nested.intercept_exceptions & excp_bits)
1596 vmexit = NESTED_EXIT_DONE;
1600 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1601 if (svm->nested.intercept & exit_bits)
1602 vmexit = NESTED_EXIT_DONE;
1609 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1613 vmexit = nested_svm_intercept(svm);
1615 if (vmexit == NESTED_EXIT_DONE)
1616 nested_svm_vmexit(svm);
1621 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1623 struct vmcb_control_area *dst = &dst_vmcb->control;
1624 struct vmcb_control_area *from = &from_vmcb->control;
1626 dst->intercept_cr_read = from->intercept_cr_read;
1627 dst->intercept_cr_write = from->intercept_cr_write;
1628 dst->intercept_dr_read = from->intercept_dr_read;
1629 dst->intercept_dr_write = from->intercept_dr_write;
1630 dst->intercept_exceptions = from->intercept_exceptions;
1631 dst->intercept = from->intercept;
1632 dst->iopm_base_pa = from->iopm_base_pa;
1633 dst->msrpm_base_pa = from->msrpm_base_pa;
1634 dst->tsc_offset = from->tsc_offset;
1635 dst->asid = from->asid;
1636 dst->tlb_ctl = from->tlb_ctl;
1637 dst->int_ctl = from->int_ctl;
1638 dst->int_vector = from->int_vector;
1639 dst->int_state = from->int_state;
1640 dst->exit_code = from->exit_code;
1641 dst->exit_code_hi = from->exit_code_hi;
1642 dst->exit_info_1 = from->exit_info_1;
1643 dst->exit_info_2 = from->exit_info_2;
1644 dst->exit_int_info = from->exit_int_info;
1645 dst->exit_int_info_err = from->exit_int_info_err;
1646 dst->nested_ctl = from->nested_ctl;
1647 dst->event_inj = from->event_inj;
1648 dst->event_inj_err = from->event_inj_err;
1649 dst->nested_cr3 = from->nested_cr3;
1650 dst->lbr_ctl = from->lbr_ctl;
1653 static int nested_svm_vmexit(struct vcpu_svm *svm)
1655 struct vmcb *nested_vmcb;
1656 struct vmcb *hsave = svm->nested.hsave;
1657 struct vmcb *vmcb = svm->vmcb;
1660 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1661 vmcb->control.exit_info_1,
1662 vmcb->control.exit_info_2,
1663 vmcb->control.exit_int_info,
1664 vmcb->control.exit_int_info_err);
1666 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1670 /* Exit nested SVM mode */
1671 svm->nested.vmcb = 0;
1673 /* Give the current vmcb to the guest */
1676 nested_vmcb->save.es = vmcb->save.es;
1677 nested_vmcb->save.cs = vmcb->save.cs;
1678 nested_vmcb->save.ss = vmcb->save.ss;
1679 nested_vmcb->save.ds = vmcb->save.ds;
1680 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1681 nested_vmcb->save.idtr = vmcb->save.idtr;
1682 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
1684 nested_vmcb->save.cr3 = vmcb->save.cr3;
1686 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
1687 nested_vmcb->save.cr2 = vmcb->save.cr2;
1688 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
1689 nested_vmcb->save.rflags = vmcb->save.rflags;
1690 nested_vmcb->save.rip = vmcb->save.rip;
1691 nested_vmcb->save.rsp = vmcb->save.rsp;
1692 nested_vmcb->save.rax = vmcb->save.rax;
1693 nested_vmcb->save.dr7 = vmcb->save.dr7;
1694 nested_vmcb->save.dr6 = vmcb->save.dr6;
1695 nested_vmcb->save.cpl = vmcb->save.cpl;
1697 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1698 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1699 nested_vmcb->control.int_state = vmcb->control.int_state;
1700 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1701 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1702 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1703 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1704 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1705 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1708 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1709 * to make sure that we do not lose injected events. So check event_inj
1710 * here and copy it to exit_int_info if it is valid.
1711 * Exit_int_info and event_inj can't be both valid because the case
1712 * below only happens on a VMRUN instruction intercept which has
1713 * no valid exit_int_info set.
1715 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1716 struct vmcb_control_area *nc = &nested_vmcb->control;
1718 nc->exit_int_info = vmcb->control.event_inj;
1719 nc->exit_int_info_err = vmcb->control.event_inj_err;
1722 nested_vmcb->control.tlb_ctl = 0;
1723 nested_vmcb->control.event_inj = 0;
1724 nested_vmcb->control.event_inj_err = 0;
1726 /* We always set V_INTR_MASKING and remember the old value in hflags */
1727 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1728 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1730 /* Restore the original control entries */
1731 copy_vmcb_control_area(vmcb, hsave);
1733 kvm_clear_exception_queue(&svm->vcpu);
1734 kvm_clear_interrupt_queue(&svm->vcpu);
1736 /* Restore selected save entries */
1737 svm->vmcb->save.es = hsave->save.es;
1738 svm->vmcb->save.cs = hsave->save.cs;
1739 svm->vmcb->save.ss = hsave->save.ss;
1740 svm->vmcb->save.ds = hsave->save.ds;
1741 svm->vmcb->save.gdtr = hsave->save.gdtr;
1742 svm->vmcb->save.idtr = hsave->save.idtr;
1743 svm->vmcb->save.rflags = hsave->save.rflags;
1744 svm_set_efer(&svm->vcpu, hsave->save.efer);
1745 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1746 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1748 svm->vmcb->save.cr3 = hsave->save.cr3;
1749 svm->vcpu.arch.cr3 = hsave->save.cr3;
1751 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1753 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1754 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1755 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1756 svm->vmcb->save.dr7 = 0;
1757 svm->vmcb->save.cpl = 0;
1758 svm->vmcb->control.exit_int_info = 0;
1760 nested_svm_unmap(page);
1762 kvm_mmu_reset_context(&svm->vcpu);
1763 kvm_mmu_load(&svm->vcpu);
1768 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1774 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
1778 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1779 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1781 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1783 nested_svm_unmap(page);
1788 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1790 struct vmcb *nested_vmcb;
1791 struct vmcb *hsave = svm->nested.hsave;
1792 struct vmcb *vmcb = svm->vmcb;
1796 vmcb_gpa = svm->vmcb->save.rax;
1798 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1802 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1803 nested_vmcb->save.rip,
1804 nested_vmcb->control.int_ctl,
1805 nested_vmcb->control.event_inj,
1806 nested_vmcb->control.nested_ctl);
1808 /* Clear internal status */
1809 kvm_clear_exception_queue(&svm->vcpu);
1810 kvm_clear_interrupt_queue(&svm->vcpu);
1812 /* Save the old vmcb, so we don't need to pick what we save, but
1813 can restore everything when a VMEXIT occurs */
1814 hsave->save.es = vmcb->save.es;
1815 hsave->save.cs = vmcb->save.cs;
1816 hsave->save.ss = vmcb->save.ss;
1817 hsave->save.ds = vmcb->save.ds;
1818 hsave->save.gdtr = vmcb->save.gdtr;
1819 hsave->save.idtr = vmcb->save.idtr;
1820 hsave->save.efer = svm->vcpu.arch.efer;
1821 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
1822 hsave->save.cr4 = svm->vcpu.arch.cr4;
1823 hsave->save.rflags = vmcb->save.rflags;
1824 hsave->save.rip = svm->next_rip;
1825 hsave->save.rsp = vmcb->save.rsp;
1826 hsave->save.rax = vmcb->save.rax;
1828 hsave->save.cr3 = vmcb->save.cr3;
1830 hsave->save.cr3 = svm->vcpu.arch.cr3;
1832 copy_vmcb_control_area(hsave, vmcb);
1834 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1835 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1837 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1839 /* Load the nested guest state */
1840 svm->vmcb->save.es = nested_vmcb->save.es;
1841 svm->vmcb->save.cs = nested_vmcb->save.cs;
1842 svm->vmcb->save.ss = nested_vmcb->save.ss;
1843 svm->vmcb->save.ds = nested_vmcb->save.ds;
1844 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1845 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1846 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1847 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1848 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1849 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1851 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1852 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1854 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1855 kvm_mmu_reset_context(&svm->vcpu);
1857 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1858 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1859 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1860 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1861 /* In case we don't even reach vcpu_run, the fields are not updated */
1862 svm->vmcb->save.rax = nested_vmcb->save.rax;
1863 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1864 svm->vmcb->save.rip = nested_vmcb->save.rip;
1865 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1866 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1867 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1869 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1871 /* cache intercepts */
1872 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1873 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1874 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1875 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1876 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1877 svm->nested.intercept = nested_vmcb->control.intercept;
1879 force_new_asid(&svm->vcpu);
1880 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1881 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1882 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1884 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1886 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1887 /* We only want the cr8 intercept bits of the guest */
1888 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1889 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1892 /* We don't want a nested guest to be more powerful than the guest,
1893 so all intercepts are ORed */
1894 svm->vmcb->control.intercept_cr_read |=
1895 nested_vmcb->control.intercept_cr_read;
1896 svm->vmcb->control.intercept_cr_write |=
1897 nested_vmcb->control.intercept_cr_write;
1898 svm->vmcb->control.intercept_dr_read |=
1899 nested_vmcb->control.intercept_dr_read;
1900 svm->vmcb->control.intercept_dr_write |=
1901 nested_vmcb->control.intercept_dr_write;
1902 svm->vmcb->control.intercept_exceptions |=
1903 nested_vmcb->control.intercept_exceptions;
1905 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1907 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
1908 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1909 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1910 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1911 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1912 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1914 nested_svm_unmap(page);
1916 /* nested_vmcb is our indicator if nested SVM is activated */
1917 svm->nested.vmcb = vmcb_gpa;
1924 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1926 to_vmcb->save.fs = from_vmcb->save.fs;
1927 to_vmcb->save.gs = from_vmcb->save.gs;
1928 to_vmcb->save.tr = from_vmcb->save.tr;
1929 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1930 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1931 to_vmcb->save.star = from_vmcb->save.star;
1932 to_vmcb->save.lstar = from_vmcb->save.lstar;
1933 to_vmcb->save.cstar = from_vmcb->save.cstar;
1934 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1935 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1936 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1937 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1940 static int vmload_interception(struct vcpu_svm *svm)
1942 struct vmcb *nested_vmcb;
1945 if (nested_svm_check_permissions(svm))
1948 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1949 skip_emulated_instruction(&svm->vcpu);
1951 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1955 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1956 nested_svm_unmap(page);
1961 static int vmsave_interception(struct vcpu_svm *svm)
1963 struct vmcb *nested_vmcb;
1966 if (nested_svm_check_permissions(svm))
1969 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1970 skip_emulated_instruction(&svm->vcpu);
1972 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1976 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1977 nested_svm_unmap(page);
1982 static int vmrun_interception(struct vcpu_svm *svm)
1984 if (nested_svm_check_permissions(svm))
1987 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1988 skip_emulated_instruction(&svm->vcpu);
1990 if (!nested_svm_vmrun(svm))
1993 if (!nested_svm_vmrun_msrpm(svm))
2000 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2001 svm->vmcb->control.exit_code_hi = 0;
2002 svm->vmcb->control.exit_info_1 = 0;
2003 svm->vmcb->control.exit_info_2 = 0;
2005 nested_svm_vmexit(svm);
2010 static int stgi_interception(struct vcpu_svm *svm)
2012 if (nested_svm_check_permissions(svm))
2015 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2016 skip_emulated_instruction(&svm->vcpu);
2023 static int clgi_interception(struct vcpu_svm *svm)
2025 if (nested_svm_check_permissions(svm))
2028 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2029 skip_emulated_instruction(&svm->vcpu);
2033 /* After a CLGI no interrupts should come */
2034 svm_clear_vintr(svm);
2035 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2040 static int invlpga_interception(struct vcpu_svm *svm)
2042 struct kvm_vcpu *vcpu = &svm->vcpu;
2044 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2045 vcpu->arch.regs[VCPU_REGS_RAX]);
2047 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2048 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2050 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2051 skip_emulated_instruction(&svm->vcpu);
2055 static int skinit_interception(struct vcpu_svm *svm)
2057 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2059 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2063 static int invalid_op_interception(struct vcpu_svm *svm)
2065 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2069 static int task_switch_interception(struct vcpu_svm *svm)
2073 int int_type = svm->vmcb->control.exit_int_info &
2074 SVM_EXITINTINFO_TYPE_MASK;
2075 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2077 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2079 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2081 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2083 if (svm->vmcb->control.exit_info_2 &
2084 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2085 reason = TASK_SWITCH_IRET;
2086 else if (svm->vmcb->control.exit_info_2 &
2087 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2088 reason = TASK_SWITCH_JMP;
2090 reason = TASK_SWITCH_GATE;
2092 reason = TASK_SWITCH_CALL;
2094 if (reason == TASK_SWITCH_GATE) {
2096 case SVM_EXITINTINFO_TYPE_NMI:
2097 svm->vcpu.arch.nmi_injected = false;
2099 case SVM_EXITINTINFO_TYPE_EXEPT:
2100 kvm_clear_exception_queue(&svm->vcpu);
2102 case SVM_EXITINTINFO_TYPE_INTR:
2103 kvm_clear_interrupt_queue(&svm->vcpu);
2110 if (reason != TASK_SWITCH_GATE ||
2111 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2112 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2113 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2114 skip_emulated_instruction(&svm->vcpu);
2116 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2119 static int cpuid_interception(struct vcpu_svm *svm)
2121 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2122 kvm_emulate_cpuid(&svm->vcpu);
2126 static int iret_interception(struct vcpu_svm *svm)
2128 ++svm->vcpu.stat.nmi_window_exits;
2129 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2130 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2134 static int invlpg_interception(struct vcpu_svm *svm)
2136 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2137 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2141 static int emulate_on_interception(struct vcpu_svm *svm)
2143 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2144 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2148 static int cr8_write_interception(struct vcpu_svm *svm)
2150 struct kvm_run *kvm_run = svm->vcpu.run;
2152 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2153 /* instruction emulation calls kvm_set_cr8() */
2154 emulate_instruction(&svm->vcpu, 0, 0, 0);
2155 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2156 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2159 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2161 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2165 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2167 struct vcpu_svm *svm = to_svm(vcpu);
2170 case MSR_IA32_TSC: {
2174 tsc_offset = svm->nested.hsave->control.tsc_offset;
2176 tsc_offset = svm->vmcb->control.tsc_offset;
2178 *data = tsc_offset + native_read_tsc();
2182 *data = svm->vmcb->save.star;
2184 #ifdef CONFIG_X86_64
2186 *data = svm->vmcb->save.lstar;
2189 *data = svm->vmcb->save.cstar;
2191 case MSR_KERNEL_GS_BASE:
2192 *data = svm->vmcb->save.kernel_gs_base;
2194 case MSR_SYSCALL_MASK:
2195 *data = svm->vmcb->save.sfmask;
2198 case MSR_IA32_SYSENTER_CS:
2199 *data = svm->vmcb->save.sysenter_cs;
2201 case MSR_IA32_SYSENTER_EIP:
2202 *data = svm->sysenter_eip;
2204 case MSR_IA32_SYSENTER_ESP:
2205 *data = svm->sysenter_esp;
2207 /* Nobody will change the following 5 values in the VMCB so
2208 we can safely return them on rdmsr. They will always be 0
2209 until LBRV is implemented. */
2210 case MSR_IA32_DEBUGCTLMSR:
2211 *data = svm->vmcb->save.dbgctl;
2213 case MSR_IA32_LASTBRANCHFROMIP:
2214 *data = svm->vmcb->save.br_from;
2216 case MSR_IA32_LASTBRANCHTOIP:
2217 *data = svm->vmcb->save.br_to;
2219 case MSR_IA32_LASTINTFROMIP:
2220 *data = svm->vmcb->save.last_excp_from;
2222 case MSR_IA32_LASTINTTOIP:
2223 *data = svm->vmcb->save.last_excp_to;
2225 case MSR_VM_HSAVE_PA:
2226 *data = svm->nested.hsave_msr;
2231 case MSR_IA32_UCODE_REV:
2235 return kvm_get_msr_common(vcpu, ecx, data);
2240 static int rdmsr_interception(struct vcpu_svm *svm)
2242 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2245 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2246 trace_kvm_msr_read_ex(ecx);
2247 kvm_inject_gp(&svm->vcpu, 0);
2249 trace_kvm_msr_read(ecx, data);
2251 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2252 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2254 skip_emulated_instruction(&svm->vcpu);
2259 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2261 struct vcpu_svm *svm = to_svm(vcpu);
2264 case MSR_IA32_TSC: {
2265 u64 tsc_offset = data - native_read_tsc();
2266 u64 g_tsc_offset = 0;
2268 if (is_nested(svm)) {
2269 g_tsc_offset = svm->vmcb->control.tsc_offset -
2270 svm->nested.hsave->control.tsc_offset;
2271 svm->nested.hsave->control.tsc_offset = tsc_offset;
2274 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2279 svm->vmcb->save.star = data;
2281 #ifdef CONFIG_X86_64
2283 svm->vmcb->save.lstar = data;
2286 svm->vmcb->save.cstar = data;
2288 case MSR_KERNEL_GS_BASE:
2289 svm->vmcb->save.kernel_gs_base = data;
2291 case MSR_SYSCALL_MASK:
2292 svm->vmcb->save.sfmask = data;
2295 case MSR_IA32_SYSENTER_CS:
2296 svm->vmcb->save.sysenter_cs = data;
2298 case MSR_IA32_SYSENTER_EIP:
2299 svm->sysenter_eip = data;
2300 svm->vmcb->save.sysenter_eip = data;
2302 case MSR_IA32_SYSENTER_ESP:
2303 svm->sysenter_esp = data;
2304 svm->vmcb->save.sysenter_esp = data;
2306 case MSR_IA32_DEBUGCTLMSR:
2307 if (!svm_has(SVM_FEATURE_LBRV)) {
2308 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2312 if (data & DEBUGCTL_RESERVED_BITS)
2315 svm->vmcb->save.dbgctl = data;
2316 if (data & (1ULL<<0))
2317 svm_enable_lbrv(svm);
2319 svm_disable_lbrv(svm);
2321 case MSR_VM_HSAVE_PA:
2322 svm->nested.hsave_msr = data;
2326 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2329 return kvm_set_msr_common(vcpu, ecx, data);
2334 static int wrmsr_interception(struct vcpu_svm *svm)
2336 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2337 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2338 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2341 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2342 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2343 trace_kvm_msr_write_ex(ecx, data);
2344 kvm_inject_gp(&svm->vcpu, 0);
2346 trace_kvm_msr_write(ecx, data);
2347 skip_emulated_instruction(&svm->vcpu);
2352 static int msr_interception(struct vcpu_svm *svm)
2354 if (svm->vmcb->control.exit_info_1)
2355 return wrmsr_interception(svm);
2357 return rdmsr_interception(svm);
2360 static int interrupt_window_interception(struct vcpu_svm *svm)
2362 struct kvm_run *kvm_run = svm->vcpu.run;
2364 svm_clear_vintr(svm);
2365 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2367 * If the user space waits to inject interrupts, exit as soon as
2370 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2371 kvm_run->request_interrupt_window &&
2372 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2373 ++svm->vcpu.stat.irq_window_exits;
2374 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2381 static int pause_interception(struct vcpu_svm *svm)
2383 kvm_vcpu_on_spin(&(svm->vcpu));
2387 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2388 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2389 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2390 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2391 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2392 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2393 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2394 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2395 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2396 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2397 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2398 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2399 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2400 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2401 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2402 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2403 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2404 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2405 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2406 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2407 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2408 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2409 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2410 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2411 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2412 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2413 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2414 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2415 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2416 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2417 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2418 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2419 [SVM_EXIT_INTR] = intr_interception,
2420 [SVM_EXIT_NMI] = nmi_interception,
2421 [SVM_EXIT_SMI] = nop_on_interception,
2422 [SVM_EXIT_INIT] = nop_on_interception,
2423 [SVM_EXIT_VINTR] = interrupt_window_interception,
2424 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2425 [SVM_EXIT_CPUID] = cpuid_interception,
2426 [SVM_EXIT_IRET] = iret_interception,
2427 [SVM_EXIT_INVD] = emulate_on_interception,
2428 [SVM_EXIT_PAUSE] = pause_interception,
2429 [SVM_EXIT_HLT] = halt_interception,
2430 [SVM_EXIT_INVLPG] = invlpg_interception,
2431 [SVM_EXIT_INVLPGA] = invlpga_interception,
2432 [SVM_EXIT_IOIO] = io_interception,
2433 [SVM_EXIT_MSR] = msr_interception,
2434 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2435 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2436 [SVM_EXIT_VMRUN] = vmrun_interception,
2437 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2438 [SVM_EXIT_VMLOAD] = vmload_interception,
2439 [SVM_EXIT_VMSAVE] = vmsave_interception,
2440 [SVM_EXIT_STGI] = stgi_interception,
2441 [SVM_EXIT_CLGI] = clgi_interception,
2442 [SVM_EXIT_SKINIT] = skinit_interception,
2443 [SVM_EXIT_WBINVD] = emulate_on_interception,
2444 [SVM_EXIT_MONITOR] = invalid_op_interception,
2445 [SVM_EXIT_MWAIT] = invalid_op_interception,
2446 [SVM_EXIT_NPF] = pf_interception,
2449 static int handle_exit(struct kvm_vcpu *vcpu)
2451 struct vcpu_svm *svm = to_svm(vcpu);
2452 struct kvm_run *kvm_run = vcpu->run;
2453 u32 exit_code = svm->vmcb->control.exit_code;
2455 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2457 if (unlikely(svm->nested.exit_required)) {
2458 nested_svm_vmexit(svm);
2459 svm->nested.exit_required = false;
2464 if (is_nested(svm)) {
2467 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2468 svm->vmcb->control.exit_info_1,
2469 svm->vmcb->control.exit_info_2,
2470 svm->vmcb->control.exit_int_info,
2471 svm->vmcb->control.exit_int_info_err);
2473 vmexit = nested_svm_exit_special(svm);
2475 if (vmexit == NESTED_EXIT_CONTINUE)
2476 vmexit = nested_svm_exit_handled(svm);
2478 if (vmexit == NESTED_EXIT_DONE)
2482 svm_complete_interrupts(svm);
2484 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2485 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2487 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2489 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2490 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2491 kvm_run->fail_entry.hardware_entry_failure_reason
2492 = svm->vmcb->control.exit_code;
2496 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2497 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2498 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2499 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2501 __func__, svm->vmcb->control.exit_int_info,
2504 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2505 || !svm_exit_handlers[exit_code]) {
2506 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2507 kvm_run->hw.hardware_exit_reason = exit_code;
2511 return svm_exit_handlers[exit_code](svm);
2514 static void reload_tss(struct kvm_vcpu *vcpu)
2516 int cpu = raw_smp_processor_id();
2518 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2519 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2523 static void pre_svm_run(struct vcpu_svm *svm)
2525 int cpu = raw_smp_processor_id();
2527 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2529 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2530 /* FIXME: handle wraparound of asid_generation */
2531 if (svm->asid_generation != sd->asid_generation)
2535 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2537 struct vcpu_svm *svm = to_svm(vcpu);
2539 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2540 vcpu->arch.hflags |= HF_NMI_MASK;
2541 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2542 ++vcpu->stat.nmi_injections;
2545 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2547 struct vmcb_control_area *control;
2549 trace_kvm_inj_virq(irq);
2551 ++svm->vcpu.stat.irq_injections;
2552 control = &svm->vmcb->control;
2553 control->int_vector = irq;
2554 control->int_ctl &= ~V_INTR_PRIO_MASK;
2555 control->int_ctl |= V_IRQ_MASK |
2556 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2559 static void svm_set_irq(struct kvm_vcpu *vcpu)
2561 struct vcpu_svm *svm = to_svm(vcpu);
2563 BUG_ON(!(gif_set(svm)));
2565 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2566 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2569 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2571 struct vcpu_svm *svm = to_svm(vcpu);
2573 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2580 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2583 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2585 struct vcpu_svm *svm = to_svm(vcpu);
2586 struct vmcb *vmcb = svm->vmcb;
2587 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2588 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2591 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2593 struct vcpu_svm *svm = to_svm(vcpu);
2595 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2598 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2600 struct vcpu_svm *svm = to_svm(vcpu);
2603 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2604 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2606 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2607 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2611 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2613 struct vcpu_svm *svm = to_svm(vcpu);
2614 struct vmcb *vmcb = svm->vmcb;
2617 if (!gif_set(svm) ||
2618 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2621 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2624 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2629 static void enable_irq_window(struct kvm_vcpu *vcpu)
2631 struct vcpu_svm *svm = to_svm(vcpu);
2633 /* In case GIF=0 we can't rely on the CPU to tell us when
2634 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2635 * The next time we get that intercept, this function will be
2636 * called again though and we'll get the vintr intercept. */
2637 if (gif_set(svm) && nested_svm_intr(svm)) {
2639 svm_inject_irq(svm, 0x0);
2643 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2645 struct vcpu_svm *svm = to_svm(vcpu);
2647 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2649 return; /* IRET will cause a vm exit */
2651 /* Something prevents NMI from been injected. Single step over
2652 possible problem (IRET or exception injection or interrupt
2654 svm->nmi_singlestep = true;
2655 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2656 update_db_intercept(vcpu);
2659 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2664 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2666 force_new_asid(vcpu);
2669 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2673 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2675 struct vcpu_svm *svm = to_svm(vcpu);
2677 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2680 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2681 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2682 kvm_set_cr8(vcpu, cr8);
2686 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2688 struct vcpu_svm *svm = to_svm(vcpu);
2691 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2694 cr8 = kvm_get_cr8(vcpu);
2695 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2696 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2699 static void svm_complete_interrupts(struct vcpu_svm *svm)
2703 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2705 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2706 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2708 svm->vcpu.arch.nmi_injected = false;
2709 kvm_clear_exception_queue(&svm->vcpu);
2710 kvm_clear_interrupt_queue(&svm->vcpu);
2712 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2715 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2716 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2719 case SVM_EXITINTINFO_TYPE_NMI:
2720 svm->vcpu.arch.nmi_injected = true;
2722 case SVM_EXITINTINFO_TYPE_EXEPT:
2723 /* In case of software exception do not reinject an exception
2724 vector, but re-execute and instruction instead */
2727 if (kvm_exception_is_soft(vector))
2729 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2730 u32 err = svm->vmcb->control.exit_int_info_err;
2731 kvm_queue_exception_e(&svm->vcpu, vector, err);
2734 kvm_queue_exception(&svm->vcpu, vector);
2736 case SVM_EXITINTINFO_TYPE_INTR:
2737 kvm_queue_interrupt(&svm->vcpu, vector, false);
2744 #ifdef CONFIG_X86_64
2750 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2752 struct vcpu_svm *svm = to_svm(vcpu);
2758 * A vmexit emulation is required before the vcpu can be executed
2761 if (unlikely(svm->nested.exit_required))
2764 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2765 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2766 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2770 sync_lapic_to_cr8(vcpu);
2772 save_host_msrs(vcpu);
2773 fs_selector = kvm_read_fs();
2774 gs_selector = kvm_read_gs();
2775 ldt_selector = kvm_read_ldt();
2776 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2777 /* required for live migration with NPT */
2779 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2786 "push %%"R"bp; \n\t"
2787 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2788 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2789 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2790 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2791 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2792 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2793 #ifdef CONFIG_X86_64
2794 "mov %c[r8](%[svm]), %%r8 \n\t"
2795 "mov %c[r9](%[svm]), %%r9 \n\t"
2796 "mov %c[r10](%[svm]), %%r10 \n\t"
2797 "mov %c[r11](%[svm]), %%r11 \n\t"
2798 "mov %c[r12](%[svm]), %%r12 \n\t"
2799 "mov %c[r13](%[svm]), %%r13 \n\t"
2800 "mov %c[r14](%[svm]), %%r14 \n\t"
2801 "mov %c[r15](%[svm]), %%r15 \n\t"
2804 /* Enter guest mode */
2806 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2807 __ex(SVM_VMLOAD) "\n\t"
2808 __ex(SVM_VMRUN) "\n\t"
2809 __ex(SVM_VMSAVE) "\n\t"
2812 /* Save guest registers, load host registers */
2813 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2814 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2815 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2816 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2817 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2818 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2819 #ifdef CONFIG_X86_64
2820 "mov %%r8, %c[r8](%[svm]) \n\t"
2821 "mov %%r9, %c[r9](%[svm]) \n\t"
2822 "mov %%r10, %c[r10](%[svm]) \n\t"
2823 "mov %%r11, %c[r11](%[svm]) \n\t"
2824 "mov %%r12, %c[r12](%[svm]) \n\t"
2825 "mov %%r13, %c[r13](%[svm]) \n\t"
2826 "mov %%r14, %c[r14](%[svm]) \n\t"
2827 "mov %%r15, %c[r15](%[svm]) \n\t"
2832 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2833 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2834 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2835 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2836 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2837 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2838 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2839 #ifdef CONFIG_X86_64
2840 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2841 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2842 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2843 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2844 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2845 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2846 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2847 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2850 , R"bx", R"cx", R"dx", R"si", R"di"
2851 #ifdef CONFIG_X86_64
2852 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2856 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2857 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2858 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2859 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2861 kvm_load_fs(fs_selector);
2862 kvm_load_gs(gs_selector);
2863 kvm_load_ldt(ldt_selector);
2864 load_host_msrs(vcpu);
2868 local_irq_disable();
2872 sync_cr8_to_lapic(vcpu);
2877 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2878 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2884 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2886 struct vcpu_svm *svm = to_svm(vcpu);
2889 svm->vmcb->control.nested_cr3 = root;
2890 force_new_asid(vcpu);
2894 svm->vmcb->save.cr3 = root;
2895 force_new_asid(vcpu);
2898 static int is_disabled(void)
2902 rdmsrl(MSR_VM_CR, vm_cr);
2903 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2910 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2913 * Patch in the VMMCALL instruction:
2915 hypercall[0] = 0x0f;
2916 hypercall[1] = 0x01;
2917 hypercall[2] = 0xd9;
2920 static void svm_check_processor_compat(void *rtn)
2925 static bool svm_cpu_has_accelerated_tpr(void)
2930 static int get_npt_level(void)
2932 #ifdef CONFIG_X86_64
2933 return PT64_ROOT_LEVEL;
2935 return PT32E_ROOT_LEVEL;
2939 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2944 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2948 static const struct trace_print_flags svm_exit_reasons_str[] = {
2949 { SVM_EXIT_READ_CR0, "read_cr0" },
2950 { SVM_EXIT_READ_CR3, "read_cr3" },
2951 { SVM_EXIT_READ_CR4, "read_cr4" },
2952 { SVM_EXIT_READ_CR8, "read_cr8" },
2953 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2954 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2955 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2956 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2957 { SVM_EXIT_READ_DR0, "read_dr0" },
2958 { SVM_EXIT_READ_DR1, "read_dr1" },
2959 { SVM_EXIT_READ_DR2, "read_dr2" },
2960 { SVM_EXIT_READ_DR3, "read_dr3" },
2961 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2962 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2963 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2964 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2965 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2966 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2967 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2968 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2969 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2970 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2971 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2972 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2973 { SVM_EXIT_INTR, "interrupt" },
2974 { SVM_EXIT_NMI, "nmi" },
2975 { SVM_EXIT_SMI, "smi" },
2976 { SVM_EXIT_INIT, "init" },
2977 { SVM_EXIT_VINTR, "vintr" },
2978 { SVM_EXIT_CPUID, "cpuid" },
2979 { SVM_EXIT_INVD, "invd" },
2980 { SVM_EXIT_HLT, "hlt" },
2981 { SVM_EXIT_INVLPG, "invlpg" },
2982 { SVM_EXIT_INVLPGA, "invlpga" },
2983 { SVM_EXIT_IOIO, "io" },
2984 { SVM_EXIT_MSR, "msr" },
2985 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2986 { SVM_EXIT_SHUTDOWN, "shutdown" },
2987 { SVM_EXIT_VMRUN, "vmrun" },
2988 { SVM_EXIT_VMMCALL, "hypercall" },
2989 { SVM_EXIT_VMLOAD, "vmload" },
2990 { SVM_EXIT_VMSAVE, "vmsave" },
2991 { SVM_EXIT_STGI, "stgi" },
2992 { SVM_EXIT_CLGI, "clgi" },
2993 { SVM_EXIT_SKINIT, "skinit" },
2994 { SVM_EXIT_WBINVD, "wbinvd" },
2995 { SVM_EXIT_MONITOR, "monitor" },
2996 { SVM_EXIT_MWAIT, "mwait" },
2997 { SVM_EXIT_NPF, "npf" },
3001 static int svm_get_lpage_level(void)
3003 return PT_PDPE_LEVEL;
3006 static bool svm_rdtscp_supported(void)
3011 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3013 struct vcpu_svm *svm = to_svm(vcpu);
3015 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3017 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3018 update_cr0_intercept(svm);
3021 static struct kvm_x86_ops svm_x86_ops = {
3022 .cpu_has_kvm_support = has_svm,
3023 .disabled_by_bios = is_disabled,
3024 .hardware_setup = svm_hardware_setup,
3025 .hardware_unsetup = svm_hardware_unsetup,
3026 .check_processor_compatibility = svm_check_processor_compat,
3027 .hardware_enable = svm_hardware_enable,
3028 .hardware_disable = svm_hardware_disable,
3029 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3031 .vcpu_create = svm_create_vcpu,
3032 .vcpu_free = svm_free_vcpu,
3033 .vcpu_reset = svm_vcpu_reset,
3035 .prepare_guest_switch = svm_prepare_guest_switch,
3036 .vcpu_load = svm_vcpu_load,
3037 .vcpu_put = svm_vcpu_put,
3039 .set_guest_debug = svm_guest_debug,
3040 .get_msr = svm_get_msr,
3041 .set_msr = svm_set_msr,
3042 .get_segment_base = svm_get_segment_base,
3043 .get_segment = svm_get_segment,
3044 .set_segment = svm_set_segment,
3045 .get_cpl = svm_get_cpl,
3046 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3047 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3048 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3049 .set_cr0 = svm_set_cr0,
3050 .set_cr3 = svm_set_cr3,
3051 .set_cr4 = svm_set_cr4,
3052 .set_efer = svm_set_efer,
3053 .get_idt = svm_get_idt,
3054 .set_idt = svm_set_idt,
3055 .get_gdt = svm_get_gdt,
3056 .set_gdt = svm_set_gdt,
3057 .get_dr = svm_get_dr,
3058 .set_dr = svm_set_dr,
3059 .cache_reg = svm_cache_reg,
3060 .get_rflags = svm_get_rflags,
3061 .set_rflags = svm_set_rflags,
3062 .fpu_activate = svm_fpu_activate,
3063 .fpu_deactivate = svm_fpu_deactivate,
3065 .tlb_flush = svm_flush_tlb,
3067 .run = svm_vcpu_run,
3068 .handle_exit = handle_exit,
3069 .skip_emulated_instruction = skip_emulated_instruction,
3070 .set_interrupt_shadow = svm_set_interrupt_shadow,
3071 .get_interrupt_shadow = svm_get_interrupt_shadow,
3072 .patch_hypercall = svm_patch_hypercall,
3073 .set_irq = svm_set_irq,
3074 .set_nmi = svm_inject_nmi,
3075 .queue_exception = svm_queue_exception,
3076 .interrupt_allowed = svm_interrupt_allowed,
3077 .nmi_allowed = svm_nmi_allowed,
3078 .get_nmi_mask = svm_get_nmi_mask,
3079 .set_nmi_mask = svm_set_nmi_mask,
3080 .enable_nmi_window = enable_nmi_window,
3081 .enable_irq_window = enable_irq_window,
3082 .update_cr8_intercept = update_cr8_intercept,
3084 .set_tss_addr = svm_set_tss_addr,
3085 .get_tdp_level = get_npt_level,
3086 .get_mt_mask = svm_get_mt_mask,
3088 .exit_reasons_str = svm_exit_reasons_str,
3089 .get_lpage_level = svm_get_lpage_level,
3091 .cpuid_update = svm_cpuid_update,
3093 .rdtscp_supported = svm_rdtscp_supported,
3096 static int __init svm_init(void)
3098 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3102 static void __exit svm_exit(void)
3107 module_init(svm_init)
3108 module_exit(svm_exit)